fix(gicv5): align IWB_WDOMAINR to the EAC spec

The offset changed from 0x6000 to 0x8000.

Change-Id: I3a95e16c5379e2bb200a1ffaf40e3bae73288c5a
Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.com>

Merge changes Ib172b554,I9971fd47 into integration

* changes:
docs(per-cpu): clean up NUMA docs
fix(per-cpu): remove redundant casts

fix(smccc): ignore SCR_EEL2_BIT

Commit cbba59c41a99 ("enable SMCCC_ARCH_FEATURE_AVAILABILITY for RMM")
enables ARCH_FEATURE_AVAILABILITY by default when RME is enabled which
results into below asser

fix(smccc): ignore SCR_EEL2_BIT

Commit cbba59c41a99 ("enable SMCCC_ARCH_FEATURE_AVAILABILITY for RMM")
enables ARCH_FEATURE_AVAILABILITY by default when RME is enabled which
results into below assertion when RMM queries the features.

ERROR: Unexpected bits 0x40000 were set in register 1e1100!
ASSERT: services/arm_arch_svc/arm_arch_svc_setup.c:251

This happpens because SCR_EEL2_BIT is neither part of SCR_EL3_FEATS nor
part of SCR_EL3_IGNORED, as the SMCCC spec doesn't list SCR_EEL2_BIT as
reported, add it to SCR_EL3_IGNORED.

Change-Id: I0465744dc7f0ae589d6a8345c1cca63ac6f7f357
Signed-off-by: Jagdish Gediya <jagdish.gediya@arm.com>

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fix(per-cpu): remove redundant casts

The casts replaced in this change were redundant; they were initially
added after some consideration of pointer provenance, but in these
particular cases loss of

fix(per-cpu): remove redundant casts

The casts replaced in this change were redundant; they were initially
added after some consideration of pointer provenance, but in these
particular cases loss of provenance is deliberate.

Change-Id: I9971fd47155b4ec395b2d8d7991c215d0c6a06d3
Signed-off-by: Chris Kay <chris.kay@arm.com>

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Merge changes from topic "gr/cov_fixes" into integration

* changes:
fix(libc): fix coverity overflowed constant
fix(libc): fix coverity overflowed constant
fix(psci): fix coverity issue with o

Merge changes from topic "gr/cov_fixes" into integration

* changes:
fix(libc): fix coverity overflowed constant
fix(libc): fix coverity overflowed constant
fix(psci): fix coverity issue with out-of-bounds read
fix(fvp): fix coverity issue unsigned_compare

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feat(cpufeat): add support for FEAT_IDTE3

This patch adds support for FEAT_IDTE3, which introduces support
for handling the trapping of Group 3 and Group 5 (only GMID_EL1)
registers to EL3 (unless t

feat(cpufeat): add support for FEAT_IDTE3

This patch adds support for FEAT_IDTE3, which introduces support
for handling the trapping of Group 3 and Group 5 (only GMID_EL1)
registers to EL3 (unless trapped to EL2). IDTE3 allows EL3 to
modify the view of ID registers for lower ELs, and this capability
is used to disable fields of ID registers tied to disabled features.

The ID registers are initially read as-is and stored in context.
Then, based on the feature enablement status for each world, if a
particular feature is disabled, its corresponding field in the
cached ID register is set to Res0. When lower ELs attempt to read
an ID register, the cached ID register value is returned. This
allows EL3 to prevent lower ELs from accessing feature-specific
system registers that are disabled in EL3, even though the hardware
implements them.

The emulated ID register values are stored primarily in per-world
context, except for certain debug-related ID registers such as
ID_AA64DFR0_EL1 and ID_AA64DFR1_EL1, which are stored in the
cpu_data and are unique to each PE. This is done to support feature
asymmetry that is commonly seen in debug features.

FEAT_IDTE3 traps all Group 3 ID registers in the range
op0 == 3, op1 == 0, CRn == 0, CRm == {2–7}, op2 == {0–7} and the
Group 5 GMID_EL1 register. However, only a handful of ID registers
contain fields used to detect features enabled in EL3. Hence, we
only cache those ID registers, while the rest are transparently
returned as is to the lower EL.

This patch updates the CREATE_FEATURE_FUNCS macro to generate
update_feat_xyz_idreg_field() functions that disable ID register
fields on a per-feature basis. The enabled_worlds scope is used to
disable ID register fields for security states where the feature is
not enabled.

This EXPERIMENTAL feature is controlled by the ENABLE_FEAT_IDTE3
build flag and is currently disabled by default.

Signed-off-by: Arvind Ram Prakash <arvind.ramprakash@arm.com>
Change-Id: I5f998eeab81bb48c7595addc5595313a9ebb96d5

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feat(cpufeat): include enabled security state scope

This patch adds a security state scope to feature function creation.
The scope defines the set of worlds (Secure, Non-secure, and Realm)
for which

feat(cpufeat): include enabled security state scope

This patch adds a security state scope to feature function creation.
The scope defines the set of worlds (Secure, Non-secure, and Realm)
for which a given feature is enabled. This allows finer-grained
control of feature visibility and ensures that ID register are
updated based on feature's enablement status for that world.

Signed-off-by: Arvind Ram Prakash <arvind.ramprakash@arm.com>
Change-Id: Ia4ba4ea7c0b020a398785a28e7ce25b00ab1f4ec

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feat(cpufeat): add ID register defines and read helpers

Add system register encodings and read helper functions for
both AArch32 and AArch64 ID registers.

These additions complete the set of archit

feat(cpufeat): add ID register defines and read helpers

Add system register encodings and read helper functions for
both AArch32 and AArch64 ID registers.

These additions complete the set of architectural ID registers that
may be trapped as part of FEAT_IDTE3, which enables EL3 to intercept
ID register accesses from lower exception levels.

Signed-off-by: Arvind Ram Prakash <arvind.ramprakash@arm.com>
Change-Id: I5d73b78e80d56a0b78ce026dcf70373c8aabd857

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Merge changes from topic "NUMA_AWARE_PER_CPU" into integration

* changes:
docs(maintainers): add per-cpu framework into maintainers.rst
feat(per-cpu): add documentation for per-cpu framework
f

Merge changes from topic "NUMA_AWARE_PER_CPU" into integration

* changes:
docs(maintainers): add per-cpu framework into maintainers.rst
feat(per-cpu): add documentation for per-cpu framework
feat(rdv3): enable numa aware per-cpu for RD-V3-Cfg2
feat(per-cpu): migrate amu_ctx to per-cpu framework
feat(per-cpu): migrate spm_core_context to per-cpu framework
feat(per-cpu): migrate psci_ns_context to per-cpu framework
feat(per-cpu): migrate psci_cpu_pd_nodes to per-cpu framework
feat(per-cpu): migrate rmm_context to per-cpu framework
feat(per-cpu): integrate per-cpu framework into BL31/BL32
feat(per-cpu): introduce framework accessors/definers
feat(per-cpu): introduce linker changes for NUMA aware per-cpu framework
docs(changelog): add scope for per-cpu framework

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feat(per-cpu): integrate per-cpu framework into BL31/BL32

Integrate per-cpu support into BL31/BL32 by extending the following
areas:

Zero-initialization: Treats per-cpu sections like .bss and clear

feat(per-cpu): integrate per-cpu framework into BL31/BL32

Integrate per-cpu support into BL31/BL32 by extending the following
areas:

Zero-initialization: Treats per-cpu sections like .bss and clears them
during early C runtime initialization. For platforms that enable
NUMA_AWARE_PER_CPU, invokes a platform hook to zero-initialize
node-specific per-cpu regions.

Cache maintenance: Extends the BL31 exit path to clean dcache lines
covering the per-cpu region, ensuring data written by the primary core
is visible to secondary cores.

tpidr_el3 setup: Initializes tpidr_el3 with the base address of the
current CPU’s per-cpu section. This allows per-cpu framework to
resolve local cpu accesses efficiently.

The percpu_data object is currently stored in tpidr_el3. Since the
per-cpu framework will use tpidr_el3 for this-cpu access, percpu_data
must be migrated to avoid conflict. This commit moves percpu_data to
the per-cpu framework.

Signed-off-by: Sammit Joshi <sammit.joshi@arm.com>
Signed-off-by: Rohit Mathew <rohit.mathew@arm.com>
Change-Id: Iff0c2e1f8c0ebd25c4bb0b09bfe15dd4fbe20561

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feat(per-cpu): introduce framework accessors/definers

Introduce per-cpu framework definers and accessors for allocation and
access of per-cpu objects. The accessors support "per_cpu_cur" variants
fo

feat(per-cpu): introduce framework accessors/definers

Introduce per-cpu framework definers and accessors for allocation and
access of per-cpu objects. The accessors support "per_cpu_cur" variants
for access on the calling CPU as well as "per_cpu_by_index" variants for
access on any CPU. Additionally, the framework supports NUMA-aware
allocation, allowing the per-cpu data to be distributed across different
memory nodes. This enables the system to allocate per-cpu data on memory
nodes closest to the respective CPU, optimising memory access and
performance.

Signed-off-by: Sammit Joshi <sammit.joshi@arm.com>
Signed-off-by: Rohit Mathew <rohit.mathew@arm.com>
Change-Id: I8361602ff626dcfe9405e7e2a28c5d143aaac574

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feat(per-cpu): introduce linker changes for NUMA aware per-cpu framework

This commit introduces linker changes for NUMA aware per-cpu objects in
the BL31 and BL32 images. The per-cpu framework is de

feat(per-cpu): introduce linker changes for NUMA aware per-cpu framework

This commit introduces linker changes for NUMA aware per-cpu objects in
the BL31 and BL32 images. The per-cpu framework is designed to minimise
cache thrashing, and the linker layout ensures each CPU’s per-cpu data
is placed on a separate cache line. This isolation is expected to
improve performance when the per-cpu framework is enabled.

Signed-off-by: Sammit Joshi <sammit.joshi@arm.com>
Signed-off-by: Rohit Mathew <rohit.mathew@arm.com>
Change-Id: Ie4d8b4e444971adbd9dba0446d1ab8cafaca1556

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feat(el3-runtime): add flags argument to handle_sysreg_trap

Extend handle_sysreg_trap() to accept an additional flags
parameter indicating the caller’s security state.
The EL3 synchronous exception

feat(el3-runtime): add flags argument to handle_sysreg_trap

Extend handle_sysreg_trap() to accept an additional flags
parameter indicating the caller’s security state.
The EL3 synchronous exception handler now passes this value
when dispatching trapped system register accesses.
This allows handle_sysreg_trap() to handle traps based on
the originating security context.

Signed-off-by: Arvind Ram Prakash <arvind.ramprakash@arm.com>
Change-Id: Ic6e4a13297bf0b3afec3b83e1696c03286615560

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fix(cpufeat): remove unused FEAT_NV feature functions

The FEAT_NV feature functions were introduced in a8d5d3d54
but never used. This patch cleans up this dead code.

Signed-off-by: Arvind Ram Praka

fix(cpufeat): remove unused FEAT_NV feature functions

The FEAT_NV feature functions were introduced in a8d5d3d54
but never used. This patch cleans up this dead code.

Signed-off-by: Arvind Ram Prakash <arvind.ramprakash@arm.com>
Change-Id: I05fae1bd187782e5de6074a7b265fcdd4b473a68

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Merge changes I54152fbb,I9b70c3a2 into integration

* changes:
feat(cpufeat): introduce FEAT_RME_GDI support
feat(cpufeat): add support for FEAT_RME_GPC2

Merge changes from topic "lfa-prime-error-handling" into integration

* changes:
feat(lfa): introduce support for call_again for LFA_PRIME
feat(lfa): allow LFA_PRIME from one CPU at a time

feat(cpufeat): introduce FEAT_RME_GDI support

This patch adds a new build flag ENABLE_FEAT_RME_GDI to enable this
feature, along with defining various related register fields. At this
point, when en

feat(cpufeat): introduce FEAT_RME_GDI support

This patch adds a new build flag ENABLE_FEAT_RME_GDI to enable this
feature, along with defining various related register fields. At this
point, when enabled, this feature enables the SA and NSP GPI encodings
by setting the corresponding bits in GPCCR_EL3.

Change-Id: I54152fbb3d19b176264e5d16acbcc866725dc290
Signed-off-by: John Powell <john.powell@arm.com>
Signed-off-by: Timothy Hayes <timothy.hayes@arm.com>

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feat(cpufeat): add support for FEAT_RME_GPC2

This change adds support for FEAT_RME_GPC2 and Non-Secure-Only (NSO)
Physical Address Space.

Previously, all non-secure (NS) memory was accessible to th

feat(cpufeat): add support for FEAT_RME_GPC2

This change adds support for FEAT_RME_GPC2 and Non-Secure-Only (NSO)
Physical Address Space.

Previously, all non-secure (NS) memory was accessible to the secure
world and realm world. With GPC2 and the NSO bit in the GPT, memory
can now be restricted to the non-secure world only. This is enabled
automatically on supported systems when ENABLE_RME is true.

Change-Id: I9b70c3a23c5ec7d83bd787d0fb3edd55934f1d05
Signed-off-by: John Powell <john.powell@arm.com>
Signed-off-by: Girish Pathak <girish.pathak@arm.com>

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fix(psci): fix coverity issue with out-of-bounds read

Avoid OVERRUN on parent indices if accidental return negative value
from `get_pwr_lvl_state_idx`, so convert everything to use unsigned
int to a

fix(psci): fix coverity issue with out-of-bounds read

Avoid OVERRUN on parent indices if accidental return negative value
from `get_pwr_lvl_state_idx`, so convert everything to use unsigned
int to avoid Out-of-bounds read (OVERRUN)

Change-Id: Ie6d6fd34db9903e99b29e004fb46908aea8acd46
Signed-off-by: Govindraj Raja <govindraj.raja@arm.com>

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feat(lfa): introduce support for call_again for LFA_PRIME

LFA_PRIME is a single-threaded operation that is not pinned to
a specific CPU. The implementation must support calls being
issued from diffe

feat(lfa): introduce support for call_again for LFA_PRIME

LFA_PRIME is a single-threaded operation that is not pinned to
a specific CPU. The implementation must support calls being
issued from different CPUs, even for several calls to prime the
same component.

This patch checks if the plat_lfa_load_auth_image return -EAGAIN
indicating that the platform expects the LFA_PRIME call to be
issued again. This is done by returning LFA_SUCCESS and setting
flags[0] to 1, indicating that LFA_PRIME is incomplete and must
be called again.

Change-Id: Ia3046b5467c50c4c51392bac3fb9e9533f2438db
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>

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fix(tsp): add missing include

Depending on include order, u_register_t may be unknown in the file
platform_tsp.h. Include stdint.h to correct that.

Change-Id: I7aeb1d389048189e8ba1b5a48173d139dc29c

fix(tsp): add missing include

Depending on include order, u_register_t may be unknown in the file
platform_tsp.h. Include stdint.h to correct that.

Change-Id: I7aeb1d389048189e8ba1b5a48173d139dc29c0da
Signed-off-by: Yann Gautier <yann.gautier@st.com>

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Merge changes from topic "qti-rb3gen2" into integration

* changes:
docs(maintainers): update QTI platform maintainers
docs(qti): add RB3Gen2 platform documentation
docs(qti): move documentatio

Merge changes from topic "qti-rb3gen2" into integration

* changes:
docs(maintainers): update QTI platform maintainers
docs(qti): add RB3Gen2 platform documentation
docs(qti): move documentation under docs/plat/qti/
feat(kodiak): add support for RB3Gen2 platform
feat(qti): introduce basic XPU driver
refactor(qti): introduce SoC codename as Kodiak
feat(qti): add TF-A BL2 common platform framework
refactor(qti): refactor RNG as a proper driver
fix(qti): fix config PLAT_XLAT_TABLES_DYNAMIC
feat(qti): add BL32 support
refactor(qti): make UART config independent
refactor(qti): make CNTFRQ config independent
fix(qti): fix build without coreboot

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fix(cpufeat): extend FEAT_EBEP handling to delegate PMU control to EL2

Currently, the FEAT_EBEP feature presence check is only used for UNDEF
injection into lower ELs. However, this feature also aff

fix(cpufeat): extend FEAT_EBEP handling to delegate PMU control to EL2

Currently, the FEAT_EBEP feature presence check is only used for UNDEF
injection into lower ELs. However, this feature also affects the access
behavior of MDCR_EL2. Specifically, if the PMEE bits in MDCR_EL3 are not
set to 0b01, then the MDCR_EL2.PMEE bits cannot be configured by EL2.

This patch extends the use of FEAT_EBEP to delegate PMU IRQ and
profiling exception control to EL2 by setting MDCR_EL3.PMEE = 0b01.This
ensures that lower ELs can manage PMU configuration.

Signed-off-by: Manish Pandey <manish.pandey2@arm.com>
Change-Id: Ib7e1d5c72f017b8ffc2131fc57309dd9d811c973

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Merge changes from topic "ck/tf-a/tpip-updates" into integration

* changes:
chore(compiler-rt): update compiler-rt to v21.1.4
chore(zlib): update zlib to v1.3.1
chore(libfdt): update libfdt to

Merge changes from topic "ck/tf-a/tpip-updates" into integration

* changes:
chore(compiler-rt): update compiler-rt to v21.1.4
chore(zlib): update zlib to v1.3.1
chore(libfdt): update libfdt to v1.7.2

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Merge "fix(cpufeat): use of additional breakpoints" into integration