1 #ifndef __ODY_CSRS_PEM_H__
2 #define __ODY_CSRS_PEM_H__
3 /* This file is auto-generated. Do not edit */
4
5 /***********************license start***********************************
6 * Copyright (C) 2021-2026 Marvell.
7 * SPDX-License-Identifier: BSD-3-Clause
8 * https://spdx.org/licenses
9 ***********************license end**************************************/
10
11
12 /**
13 * @file
14 *
15 * Configuration and status register (CSR) address and type definitions for
16 * PEM.
17 *
18 * This file is auto generated. Do not edit.
19 *
20 */
21
22 /**
23 * Enumeration pem_bar_e
24 *
25 * PEM Base Address Register Enumeration
26 * Enumerates the base address registers.
27 */
28 #define ODY_PEM_BAR_E_PEMX_PF_BAR0(a) (0x8e0000000000ll + 0x1000000000ll * (a))
29 #define ODY_PEM_BAR_E_PEMX_PF_BAR0_SIZE 0x40000000ull
30 #define ODY_PEM_BAR_E_PEMX_PF_BAR4(a) (0x8e0f00000000ll + 0x1000000000ll * (a))
31 #define ODY_PEM_BAR_E_PEMX_PF_BAR4_SIZE 0x100000ull
32
33 /**
34 * Enumeration pem_int_vec_e
35 *
36 * PEM MSI-X Vector Enumeration
37 * Enumerates the MSI-X interrupt vectors.
38 */
39 #define ODY_PEM_INT_VEC_E_INTA (0)
40 #define ODY_PEM_INT_VEC_E_INTA_CLEAR (1)
41 #define ODY_PEM_INT_VEC_E_INTB (2)
42 #define ODY_PEM_INT_VEC_E_INTB_CLEAR (3)
43 #define ODY_PEM_INT_VEC_E_INTC (4)
44 #define ODY_PEM_INT_VEC_E_INTC_CLEAR (5)
45 #define ODY_PEM_INT_VEC_E_INTD (6)
46 #define ODY_PEM_INT_VEC_E_INTD_CLEAR (7)
47 #define ODY_PEM_INT_VEC_E_INT_SUM (8)
48 #define ODY_PEM_INT_VEC_E_PEMOOR_INT (0xa)
49 #define ODY_PEM_INT_VEC_E_RST_INT (9)
50 #define ODY_PEM_INT_VEC_E_VDMX_INT(a) (0xb + (a))
51
52 /**
53 * Enumeration pem_perf_bus_e
54 *
55 * PEM Performance Bus Enumeration
56 * Enumerates the internal bus associated with performance tracking registers.
57 */
58 #define ODY_PEM_PERF_BUS_E_PERF_EBUS (1)
59 #define ODY_PEM_PERF_BUS_E_PERF_NCB (0)
60
61 /**
62 * Enumeration pem_perf_tlp_type_e
63 *
64 * PEM Performance TLP Type Enumeration
65 * Enumerates the TLP type associated with performance tracking registers that are by type.
66 */
67 #define ODY_PEM_PERF_TLP_TYPE_E_PERF_CPL (2)
68 #define ODY_PEM_PERF_TLP_TYPE_E_PERF_NPR (0)
69 #define ODY_PEM_PERF_TLP_TYPE_E_PERF_PR (1)
70
71 /**
72 * Enumeration pem_rst_source_e
73 *
74 * PEM Reset Cause Enumeration
75 * Enumerates the reset sources for both reset domain mapping and cause of last reset,
76 * corresponding to the bit numbers of PEM()_RST_LBOOT.
77 */
78 #define ODY_PEM_RST_SOURCE_E_L2 (2)
79 #define ODY_PEM_RST_SOURCE_E_LINKDOWN (1)
80 #define ODY_PEM_RST_SOURCE_E_PEM_PFFLR (3)
81 #define ODY_PEM_RST_SOURCE_E_PEM_RSVD (4)
82 #define ODY_PEM_RST_SOURCE_E_PERST_PIN (0)
83
84 /**
85 * Structure pem_ncbo_norm_memio_s
86 *
87 * NCB to MAC Operation Structure
88 * Core initiated load and store operations that are initiating MAC transactions form an address
89 * with this structure through the PEM()_REG_NORM()_ACC table. 8-bit, 16-bit, 32-bit and 64-bit
90 * reads and writes, in addition to atomics are supported to this region.
91 */
92 union ody_pem_ncbo_norm_memio_s {
93 uint64_t u;
94 struct ody_pem_ncbo_norm_memio_s_s {
95 uint64_t addr : 31;
96 uint64_t region : 8;
97 uint64_t did_hi : 5;
98 uint64_t node : 2;
99 uint64_t reserved_46 : 1;
100 uint64_t io : 5;
101 uint64_t reserved_52_63 : 12;
102 } s;
103 /* struct ody_pem_ncbo_norm_memio_s_s cn; */
104 };
105
106 /**
107 * Register (NCB) pem#_ats_diag_status
108 *
109 * PEM ATS Diagnostic Status Register
110 * This register contains selection control for the ATS diagnostic bus.
111 */
112 union ody_pemx_ats_diag_status {
113 uint64_t u;
114 struct ody_pemx_ats_diag_status_s {
115 uint64_t unexpected_dti_sync : 1;
116 uint64_t invalidate_response_timeout : 1;
117 uint64_t unmatched_translation_id : 1;
118 uint64_t invalid_completion_count : 1;
119 uint64_t unmatched_itag : 1;
120 uint64_t reserved_5 : 1;
121 uint64_t malformed_prg_rsp : 1;
122 uint64_t malformed_ats_completion : 1;
123 uint64_t malformed_ats_req : 1;
124 uint64_t dropped_invalidate : 1;
125 uint64_t reserved_10_63 : 54;
126 } s;
127 /* struct ody_pemx_ats_diag_status_s cn; */
128 };
129 typedef union ody_pemx_ats_diag_status ody_pemx_ats_diag_status_t;
130
131 static inline uint64_t ODY_PEMX_ATS_DIAG_STATUS(uint64_t a) __attribute__ ((pure, always_inline));
ODY_PEMX_ATS_DIAG_STATUS(uint64_t a)132 static inline uint64_t ODY_PEMX_ATS_DIAG_STATUS(uint64_t a)
133 {
134 if (a <= 15)
135 return 0x8e0000007d08ll + 0x1000000000ll * ((a) & 0xf);
136 __ody_csr_fatal("PEMX_ATS_DIAG_STATUS", 1, a, 0, 0, 0, 0, 0);
137 }
138
139 #define typedef_ODY_PEMX_ATS_DIAG_STATUS(a) ody_pemx_ats_diag_status_t
140 #define bustype_ODY_PEMX_ATS_DIAG_STATUS(a) CSR_TYPE_NCB
141 #define basename_ODY_PEMX_ATS_DIAG_STATUS(a) "PEMX_ATS_DIAG_STATUS"
142 #define device_bar_ODY_PEMX_ATS_DIAG_STATUS(a) 0x0 /* PF_BAR0 */
143 #define busnum_ODY_PEMX_ATS_DIAG_STATUS(a) (a)
144 #define arguments_ODY_PEMX_ATS_DIAG_STATUS(a) (a), -1, -1, -1
145
146 /**
147 * Register (NCB) pem#_ats_inv_control
148 *
149 * PEM ATS Invalidation Control Register
150 */
151 union ody_pemx_ats_inv_control {
152 uint64_t u;
153 struct ody_pemx_ats_inv_control_s {
154 uint64_t limit : 6;
155 uint64_t outstanding_requests : 6;
156 uint64_t always_forward : 1;
157 uint64_t reserved_13_63 : 51;
158 } s;
159 /* struct ody_pemx_ats_inv_control_s cn; */
160 };
161 typedef union ody_pemx_ats_inv_control ody_pemx_ats_inv_control_t;
162
163 static inline uint64_t ODY_PEMX_ATS_INV_CONTROL(uint64_t a) __attribute__ ((pure, always_inline));
ODY_PEMX_ATS_INV_CONTROL(uint64_t a)164 static inline uint64_t ODY_PEMX_ATS_INV_CONTROL(uint64_t a)
165 {
166 if (a <= 15)
167 return 0x8e0000007d48ll + 0x1000000000ll * ((a) & 0xf);
168 __ody_csr_fatal("PEMX_ATS_INV_CONTROL", 1, a, 0, 0, 0, 0, 0);
169 }
170
171 #define typedef_ODY_PEMX_ATS_INV_CONTROL(a) ody_pemx_ats_inv_control_t
172 #define bustype_ODY_PEMX_ATS_INV_CONTROL(a) CSR_TYPE_NCB
173 #define basename_ODY_PEMX_ATS_INV_CONTROL(a) "PEMX_ATS_INV_CONTROL"
174 #define device_bar_ODY_PEMX_ATS_INV_CONTROL(a) 0x0 /* PF_BAR0 */
175 #define busnum_ODY_PEMX_ATS_INV_CONTROL(a) (a)
176 #define arguments_ODY_PEMX_ATS_INV_CONTROL(a) (a), -1, -1, -1
177
178 /**
179 * Register (NCB) pem#_ats_inv_latency_pc
180 *
181 * PEM ATS Invalidtion Latency Counter Register
182 */
183 union ody_pemx_ats_inv_latency_pc {
184 uint64_t u;
185 struct ody_pemx_ats_inv_latency_pc_s {
186 uint64_t count : 64;
187 } s;
188 /* struct ody_pemx_ats_inv_latency_pc_s cn; */
189 };
190 typedef union ody_pemx_ats_inv_latency_pc ody_pemx_ats_inv_latency_pc_t;
191
192 static inline uint64_t ODY_PEMX_ATS_INV_LATENCY_PC(uint64_t a) __attribute__ ((pure, always_inline));
ODY_PEMX_ATS_INV_LATENCY_PC(uint64_t a)193 static inline uint64_t ODY_PEMX_ATS_INV_LATENCY_PC(uint64_t a)
194 {
195 if (a <= 15)
196 return 0x8e0000007d40ll + 0x1000000000ll * ((a) & 0xf);
197 __ody_csr_fatal("PEMX_ATS_INV_LATENCY_PC", 1, a, 0, 0, 0, 0, 0);
198 }
199
200 #define typedef_ODY_PEMX_ATS_INV_LATENCY_PC(a) ody_pemx_ats_inv_latency_pc_t
201 #define bustype_ODY_PEMX_ATS_INV_LATENCY_PC(a) CSR_TYPE_NCB
202 #define basename_ODY_PEMX_ATS_INV_LATENCY_PC(a) "PEMX_ATS_INV_LATENCY_PC"
203 #define device_bar_ODY_PEMX_ATS_INV_LATENCY_PC(a) 0x0 /* PF_BAR0 */
204 #define busnum_ODY_PEMX_ATS_INV_LATENCY_PC(a) (a)
205 #define arguments_ODY_PEMX_ATS_INV_LATENCY_PC(a) (a), -1, -1, -1
206
207 /**
208 * Register (NCB) pem#_ats_inv_pc
209 *
210 * PEM ATS Invalidation Performance Counter Register
211 */
212 union ody_pemx_ats_inv_pc {
213 uint64_t u;
214 struct ody_pemx_ats_inv_pc_s {
215 uint64_t count : 64;
216 } s;
217 /* struct ody_pemx_ats_inv_pc_s cn; */
218 };
219 typedef union ody_pemx_ats_inv_pc ody_pemx_ats_inv_pc_t;
220
221 static inline uint64_t ODY_PEMX_ATS_INV_PC(uint64_t a) __attribute__ ((pure, always_inline));
ODY_PEMX_ATS_INV_PC(uint64_t a)222 static inline uint64_t ODY_PEMX_ATS_INV_PC(uint64_t a)
223 {
224 if (a <= 15)
225 return 0x8e0000007d38ll + 0x1000000000ll * ((a) & 0xf);
226 __ody_csr_fatal("PEMX_ATS_INV_PC", 1, a, 0, 0, 0, 0, 0);
227 }
228
229 #define typedef_ODY_PEMX_ATS_INV_PC(a) ody_pemx_ats_inv_pc_t
230 #define bustype_ODY_PEMX_ATS_INV_PC(a) CSR_TYPE_NCB
231 #define basename_ODY_PEMX_ATS_INV_PC(a) "PEMX_ATS_INV_PC"
232 #define device_bar_ODY_PEMX_ATS_INV_PC(a) 0x0 /* PF_BAR0 */
233 #define busnum_ODY_PEMX_ATS_INV_PC(a) (a)
234 #define arguments_ODY_PEMX_ATS_INV_PC(a) (a), -1, -1, -1
235
236 /**
237 * Register (NCB) pem#_ats_inv_sync
238 *
239 * PEM ATS Invalidation Sync Register
240 * This register is used by PEM ATS on an ATC invalidation to synchronize outstanding
241 * posted transactions using that translation.
242 */
243 union ody_pemx_ats_inv_sync {
244 uint64_t u;
245 struct ody_pemx_ats_inv_sync_s {
246 uint64_t sync : 1;
247 uint64_t reserved_1_63 : 63;
248 } s;
249 /* struct ody_pemx_ats_inv_sync_s cn; */
250 };
251 typedef union ody_pemx_ats_inv_sync ody_pemx_ats_inv_sync_t;
252
253 static inline uint64_t ODY_PEMX_ATS_INV_SYNC(uint64_t a) __attribute__ ((pure, always_inline));
ODY_PEMX_ATS_INV_SYNC(uint64_t a)254 static inline uint64_t ODY_PEMX_ATS_INV_SYNC(uint64_t a)
255 {
256 if (a <= 15)
257 return 0x8e0000007d00ll + 0x1000000000ll * ((a) & 0xf);
258 __ody_csr_fatal("PEMX_ATS_INV_SYNC", 1, a, 0, 0, 0, 0, 0);
259 }
260
261 #define typedef_ODY_PEMX_ATS_INV_SYNC(a) ody_pemx_ats_inv_sync_t
262 #define bustype_ODY_PEMX_ATS_INV_SYNC(a) CSR_TYPE_NCB
263 #define basename_ODY_PEMX_ATS_INV_SYNC(a) "PEMX_ATS_INV_SYNC"
264 #define device_bar_ODY_PEMX_ATS_INV_SYNC(a) 0x0 /* PF_BAR0 */
265 #define busnum_ODY_PEMX_ATS_INV_SYNC(a) (a)
266 #define arguments_ODY_PEMX_ATS_INV_SYNC(a) (a), -1, -1, -1
267
268 /**
269 * Register (NCB) pem#_ats_pri_latency_pc
270 *
271 * PEM ATS Page Request Latency Counter Register
272 */
273 union ody_pemx_ats_pri_latency_pc {
274 uint64_t u;
275 struct ody_pemx_ats_pri_latency_pc_s {
276 uint64_t count : 64;
277 } s;
278 /* struct ody_pemx_ats_pri_latency_pc_s cn; */
279 };
280 typedef union ody_pemx_ats_pri_latency_pc ody_pemx_ats_pri_latency_pc_t;
281
282 static inline uint64_t ODY_PEMX_ATS_PRI_LATENCY_PC(uint64_t a) __attribute__ ((pure, always_inline));
ODY_PEMX_ATS_PRI_LATENCY_PC(uint64_t a)283 static inline uint64_t ODY_PEMX_ATS_PRI_LATENCY_PC(uint64_t a)
284 {
285 if (a <= 15)
286 return 0x8e0000007d30ll + 0x1000000000ll * ((a) & 0xf);
287 __ody_csr_fatal("PEMX_ATS_PRI_LATENCY_PC", 1, a, 0, 0, 0, 0, 0);
288 }
289
290 #define typedef_ODY_PEMX_ATS_PRI_LATENCY_PC(a) ody_pemx_ats_pri_latency_pc_t
291 #define bustype_ODY_PEMX_ATS_PRI_LATENCY_PC(a) CSR_TYPE_NCB
292 #define basename_ODY_PEMX_ATS_PRI_LATENCY_PC(a) "PEMX_ATS_PRI_LATENCY_PC"
293 #define device_bar_ODY_PEMX_ATS_PRI_LATENCY_PC(a) 0x0 /* PF_BAR0 */
294 #define busnum_ODY_PEMX_ATS_PRI_LATENCY_PC(a) (a)
295 #define arguments_ODY_PEMX_ATS_PRI_LATENCY_PC(a) (a), -1, -1, -1
296
297 /**
298 * Register (NCB) pem#_ats_pri_pc
299 *
300 * PEM ATS Page Request Performance Counter Register
301 */
302 union ody_pemx_ats_pri_pc {
303 uint64_t u;
304 struct ody_pemx_ats_pri_pc_s {
305 uint64_t count : 64;
306 } s;
307 /* struct ody_pemx_ats_pri_pc_s cn; */
308 };
309 typedef union ody_pemx_ats_pri_pc ody_pemx_ats_pri_pc_t;
310
311 static inline uint64_t ODY_PEMX_ATS_PRI_PC(uint64_t a) __attribute__ ((pure, always_inline));
ODY_PEMX_ATS_PRI_PC(uint64_t a)312 static inline uint64_t ODY_PEMX_ATS_PRI_PC(uint64_t a)
313 {
314 if (a <= 15)
315 return 0x8e0000007d28ll + 0x1000000000ll * ((a) & 0xf);
316 __ody_csr_fatal("PEMX_ATS_PRI_PC", 1, a, 0, 0, 0, 0, 0);
317 }
318
319 #define typedef_ODY_PEMX_ATS_PRI_PC(a) ody_pemx_ats_pri_pc_t
320 #define bustype_ODY_PEMX_ATS_PRI_PC(a) CSR_TYPE_NCB
321 #define basename_ODY_PEMX_ATS_PRI_PC(a) "PEMX_ATS_PRI_PC"
322 #define device_bar_ODY_PEMX_ATS_PRI_PC(a) 0x0 /* PF_BAR0 */
323 #define busnum_ODY_PEMX_ATS_PRI_PC(a) (a)
324 #define arguments_ODY_PEMX_ATS_PRI_PC(a) (a), -1, -1, -1
325
326 /**
327 * Register (NCB) pem#_ats_tid_sts#
328 *
329 * PEM ATS Translation ID Status Register
330 */
331 union ody_pemx_ats_tid_stsx {
332 uint64_t u;
333 struct ody_pemx_ats_tid_stsx_s {
334 uint64_t busy : 64;
335 } s;
336 /* struct ody_pemx_ats_tid_stsx_s cn; */
337 };
338 typedef union ody_pemx_ats_tid_stsx ody_pemx_ats_tid_stsx_t;
339
340 static inline uint64_t ODY_PEMX_ATS_TID_STSX(uint64_t a, uint64_t b) __attribute__ ((pure, always_inline));
ODY_PEMX_ATS_TID_STSX(uint64_t a,uint64_t b)341 static inline uint64_t ODY_PEMX_ATS_TID_STSX(uint64_t a, uint64_t b)
342 {
343 if ((a <= 15) && (b <= 3))
344 return 0x8e0000007d60ll + 0x1000000000ll * ((a) & 0xf) + 8ll * ((b) & 0x3);
345 __ody_csr_fatal("PEMX_ATS_TID_STSX", 2, a, b, 0, 0, 0, 0);
346 }
347
348 #define typedef_ODY_PEMX_ATS_TID_STSX(a, b) ody_pemx_ats_tid_stsx_t
349 #define bustype_ODY_PEMX_ATS_TID_STSX(a, b) CSR_TYPE_NCB
350 #define basename_ODY_PEMX_ATS_TID_STSX(a, b) "PEMX_ATS_TID_STSX"
351 #define device_bar_ODY_PEMX_ATS_TID_STSX(a, b) 0x0 /* PF_BAR0 */
352 #define busnum_ODY_PEMX_ATS_TID_STSX(a, b) (a)
353 #define arguments_ODY_PEMX_ATS_TID_STSX(a, b) (a), (b), -1, -1
354
355 /**
356 * Register (NCB) pem#_ats_tlp_credits
357 *
358 * PEM ATS Inbound TLP Credits Register
359 * This register specifies the number of credits for use in moving TLPs. When this register is
360 * written, the credit values are reset to the register value. This register is for diagnostic
361 * use only, and should only be written when PEM()_CTL_STATUS[LNK_ENB] is clear.
362 *
363 * This register is accessible through ROM scripts; see SCR_WRITE32_S[ADDR].
364 *
365 * This register is reset on MAC reset.
366 */
367 union ody_pemx_ats_tlp_credits {
368 uint64_t u;
369 struct ody_pemx_ats_tlp_credits_s {
370 uint64_t ats_p : 11;
371 uint64_t ats_np : 10;
372 uint64_t reserved_21_63 : 43;
373 } s;
374 /* struct ody_pemx_ats_tlp_credits_s cn; */
375 };
376 typedef union ody_pemx_ats_tlp_credits ody_pemx_ats_tlp_credits_t;
377
378 static inline uint64_t ODY_PEMX_ATS_TLP_CREDITS(uint64_t a) __attribute__ ((pure, always_inline));
ODY_PEMX_ATS_TLP_CREDITS(uint64_t a)379 static inline uint64_t ODY_PEMX_ATS_TLP_CREDITS(uint64_t a)
380 {
381 if (a <= 15)
382 return 0x8e0000000090ll + 0x1000000000ll * ((a) & 0xf);
383 __ody_csr_fatal("PEMX_ATS_TLP_CREDITS", 1, a, 0, 0, 0, 0, 0);
384 }
385
386 #define typedef_ODY_PEMX_ATS_TLP_CREDITS(a) ody_pemx_ats_tlp_credits_t
387 #define bustype_ODY_PEMX_ATS_TLP_CREDITS(a) CSR_TYPE_NCB
388 #define basename_ODY_PEMX_ATS_TLP_CREDITS(a) "PEMX_ATS_TLP_CREDITS"
389 #define device_bar_ODY_PEMX_ATS_TLP_CREDITS(a) 0x0 /* PF_BAR0 */
390 #define busnum_ODY_PEMX_ATS_TLP_CREDITS(a) (a)
391 #define arguments_ODY_PEMX_ATS_TLP_CREDITS(a) (a), -1, -1, -1
392
393 /**
394 * Register (NCB) pem#_ats_trans_latency_pc
395 *
396 * PEM ATS Translation Latency Counter Register
397 */
398 union ody_pemx_ats_trans_latency_pc {
399 uint64_t u;
400 struct ody_pemx_ats_trans_latency_pc_s {
401 uint64_t count : 64;
402 } s;
403 /* struct ody_pemx_ats_trans_latency_pc_s cn; */
404 };
405 typedef union ody_pemx_ats_trans_latency_pc ody_pemx_ats_trans_latency_pc_t;
406
407 static inline uint64_t ODY_PEMX_ATS_TRANS_LATENCY_PC(uint64_t a) __attribute__ ((pure, always_inline));
ODY_PEMX_ATS_TRANS_LATENCY_PC(uint64_t a)408 static inline uint64_t ODY_PEMX_ATS_TRANS_LATENCY_PC(uint64_t a)
409 {
410 if (a <= 15)
411 return 0x8e0000007d20ll + 0x1000000000ll * ((a) & 0xf);
412 __ody_csr_fatal("PEMX_ATS_TRANS_LATENCY_PC", 1, a, 0, 0, 0, 0, 0);
413 }
414
415 #define typedef_ODY_PEMX_ATS_TRANS_LATENCY_PC(a) ody_pemx_ats_trans_latency_pc_t
416 #define bustype_ODY_PEMX_ATS_TRANS_LATENCY_PC(a) CSR_TYPE_NCB
417 #define basename_ODY_PEMX_ATS_TRANS_LATENCY_PC(a) "PEMX_ATS_TRANS_LATENCY_PC"
418 #define device_bar_ODY_PEMX_ATS_TRANS_LATENCY_PC(a) 0x0 /* PF_BAR0 */
419 #define busnum_ODY_PEMX_ATS_TRANS_LATENCY_PC(a) (a)
420 #define arguments_ODY_PEMX_ATS_TRANS_LATENCY_PC(a) (a), -1, -1, -1
421
422 /**
423 * Register (NCB) pem#_ats_trans_pc
424 *
425 * PEM ATS Translation Performance Counter Register
426 */
427 union ody_pemx_ats_trans_pc {
428 uint64_t u;
429 struct ody_pemx_ats_trans_pc_s {
430 uint64_t count : 64;
431 } s;
432 /* struct ody_pemx_ats_trans_pc_s cn; */
433 };
434 typedef union ody_pemx_ats_trans_pc ody_pemx_ats_trans_pc_t;
435
436 static inline uint64_t ODY_PEMX_ATS_TRANS_PC(uint64_t a) __attribute__ ((pure, always_inline));
ODY_PEMX_ATS_TRANS_PC(uint64_t a)437 static inline uint64_t ODY_PEMX_ATS_TRANS_PC(uint64_t a)
438 {
439 if (a <= 15)
440 return 0x8e0000007d18ll + 0x1000000000ll * ((a) & 0xf);
441 __ody_csr_fatal("PEMX_ATS_TRANS_PC", 1, a, 0, 0, 0, 0, 0);
442 }
443
444 #define typedef_ODY_PEMX_ATS_TRANS_PC(a) ody_pemx_ats_trans_pc_t
445 #define bustype_ODY_PEMX_ATS_TRANS_PC(a) CSR_TYPE_NCB
446 #define basename_ODY_PEMX_ATS_TRANS_PC(a) "PEMX_ATS_TRANS_PC"
447 #define device_bar_ODY_PEMX_ATS_TRANS_PC(a) 0x0 /* PF_BAR0 */
448 #define busnum_ODY_PEMX_ATS_TRANS_PC(a) (a)
449 #define arguments_ODY_PEMX_ATS_TRANS_PC(a) (a), -1, -1, -1
450
451 /**
452 * Register (NCB) pem#_bar2_mask
453 *
454 * PEM BAR2 Mask Register
455 * This register contains the mask pattern that is ANDed with the address from the PCIe core for
456 * inbound PF BAR2 hits in either RC or EP mode. This mask is only applied if
457 * the address hits in PEM()_P2N_BAR2_START / PEM()_BAR_CTL[BAR2_SIZ] registers.
458 *
459 * This register is not accessible through ROM scripts; see SCR_WRITE32_S[ADDR].
460 *
461 * This register is reset on core domain reset.
462 */
463 union ody_pemx_bar2_mask {
464 uint64_t u;
465 struct ody_pemx_bar2_mask_s {
466 uint64_t reserved_0_3 : 4;
467 uint64_t mask : 49;
468 uint64_t reserved_53_63 : 11;
469 } s;
470 /* struct ody_pemx_bar2_mask_s cn; */
471 };
472 typedef union ody_pemx_bar2_mask ody_pemx_bar2_mask_t;
473
474 static inline uint64_t ODY_PEMX_BAR2_MASK(uint64_t a) __attribute__ ((pure, always_inline));
ODY_PEMX_BAR2_MASK(uint64_t a)475 static inline uint64_t ODY_PEMX_BAR2_MASK(uint64_t a)
476 {
477 if (a <= 15)
478 return 0x8e0000000048ll + 0x1000000000ll * ((a) & 0xf);
479 __ody_csr_fatal("PEMX_BAR2_MASK", 1, a, 0, 0, 0, 0, 0);
480 }
481
482 #define typedef_ODY_PEMX_BAR2_MASK(a) ody_pemx_bar2_mask_t
483 #define bustype_ODY_PEMX_BAR2_MASK(a) CSR_TYPE_NCB
484 #define basename_ODY_PEMX_BAR2_MASK(a) "PEMX_BAR2_MASK"
485 #define device_bar_ODY_PEMX_BAR2_MASK(a) 0x0 /* PF_BAR0 */
486 #define busnum_ODY_PEMX_BAR2_MASK(a) (a)
487 #define arguments_ODY_PEMX_BAR2_MASK(a) (a), -1, -1, -1
488
489 /**
490 * Register (NCB) pem#_bar4_index#
491 *
492 * PEM BAR4 Index 0-15 Register
493 * This register contains the address index and control bits for access to memory ranges of BAR4.
494 * The index is built from the PCI inbound address \<25:22\>.
495 *
496 * This register is not accessible through ROM scripts; see SCR_WRITE32_S[ADDR].
497 *
498 * This register is reset on core domain reset.
499 */
500 union ody_pemx_bar4_indexx {
501 uint64_t u;
502 struct ody_pemx_bar4_indexx_s {
503 uint64_t addr_v : 1;
504 uint64_t reserved_1_2 : 2;
505 uint64_t ca : 1;
506 uint64_t addr_idx : 31;
507 uint64_t reserved_35_63 : 29;
508 } s;
509 /* struct ody_pemx_bar4_indexx_s cn; */
510 };
511 typedef union ody_pemx_bar4_indexx ody_pemx_bar4_indexx_t;
512
513 static inline uint64_t ODY_PEMX_BAR4_INDEXX(uint64_t a, uint64_t b) __attribute__ ((pure, always_inline));
ODY_PEMX_BAR4_INDEXX(uint64_t a,uint64_t b)514 static inline uint64_t ODY_PEMX_BAR4_INDEXX(uint64_t a, uint64_t b)
515 {
516 if ((a <= 15) && (b <= 15))
517 return 0x8e0000000700ll + 0x1000000000ll * ((a) & 0xf) + 8ll * ((b) & 0xf);
518 __ody_csr_fatal("PEMX_BAR4_INDEXX", 2, a, b, 0, 0, 0, 0);
519 }
520
521 #define typedef_ODY_PEMX_BAR4_INDEXX(a, b) ody_pemx_bar4_indexx_t
522 #define bustype_ODY_PEMX_BAR4_INDEXX(a, b) CSR_TYPE_NCB
523 #define basename_ODY_PEMX_BAR4_INDEXX(a, b) "PEMX_BAR4_INDEXX"
524 #define device_bar_ODY_PEMX_BAR4_INDEXX(a, b) 0x0 /* PF_BAR0 */
525 #define busnum_ODY_PEMX_BAR4_INDEXX(a, b) (a)
526 #define arguments_ODY_PEMX_BAR4_INDEXX(a, b) (a), (b), -1, -1
527
528 /**
529 * Register (NCB) pem#_bar_ctl
530 *
531 * PEM BAR Control Register
532 * This register contains control for BAR accesses. This control always
533 * applies to memory accesses targeting the NCBI bus. Some of the fields also
534 * apply to accesses targeting EBUS in RC mode only, see the individual field
535 * descriptions for more detail.
536 *
537 * This register is not accessible through ROM scripts; see SCR_WRITE32_S[ADDR].
538 *
539 * This register is reset on core domain reset.
540 */
541 union ody_pemx_bar_ctl {
542 uint64_t u;
543 struct ody_pemx_bar_ctl_s {
544 uint64_t bar2_cax : 1;
545 uint64_t reserved_1_2 : 2;
546 uint64_t bar2_enb : 1;
547 uint64_t bar4_siz : 3;
548 uint64_t bar2_siz : 6;
549 uint64_t bar2_cbit : 6;
550 uint64_t reserved_19_24 : 6;
551 uint64_t bar0_enb : 1;
552 uint64_t bar0_siz : 5;
553 uint64_t bar4_enb : 1;
554 uint64_t at_enb : 1;
555 uint64_t reserved_33_34 : 2;
556 uint64_t vf_bar0_enb : 1;
557 uint64_t stream_bits : 5;
558 uint64_t reserved_41_63 : 23;
559 } s;
560 /* struct ody_pemx_bar_ctl_s cn; */
561 };
562 typedef union ody_pemx_bar_ctl ody_pemx_bar_ctl_t;
563
564 static inline uint64_t ODY_PEMX_BAR_CTL(uint64_t a) __attribute__ ((pure, always_inline));
ODY_PEMX_BAR_CTL(uint64_t a)565 static inline uint64_t ODY_PEMX_BAR_CTL(uint64_t a)
566 {
567 if (a <= 15)
568 return 0x8e0000000168ll + 0x1000000000ll * ((a) & 0xf);
569 __ody_csr_fatal("PEMX_BAR_CTL", 1, a, 0, 0, 0, 0, 0);
570 }
571
572 #define typedef_ODY_PEMX_BAR_CTL(a) ody_pemx_bar_ctl_t
573 #define bustype_ODY_PEMX_BAR_CTL(a) CSR_TYPE_NCB
574 #define basename_ODY_PEMX_BAR_CTL(a) "PEMX_BAR_CTL"
575 #define device_bar_ODY_PEMX_BAR_CTL(a) 0x0 /* PF_BAR0 */
576 #define busnum_ODY_PEMX_BAR_CTL(a) (a)
577 #define arguments_ODY_PEMX_BAR_CTL(a) (a), -1, -1, -1
578
579 /**
580 * Register (NCB) pem#_cfg
581 *
582 * PEM Application Configuration Register
583 * This register configures the PCIe application.
584 *
585 * This register is accessible through ROM scripts; see SCR_WRITE32_S[ADDR].
586 *
587 * This register is reset on cold reset.
588 */
589 union ody_pemx_cfg {
590 uint64_t u;
591 struct ody_pemx_cfg_s {
592 uint64_t hostmd : 1;
593 uint64_t lanes : 3;
594 uint64_t pipe : 2;
595 uint64_t reserved_6_7 : 2;
596 uint64_t auto_dp_clr : 1;
597 uint64_t reserved_9_63 : 55;
598 } s;
599 /* struct ody_pemx_cfg_s cn; */
600 };
601 typedef union ody_pemx_cfg ody_pemx_cfg_t;
602
603 static inline uint64_t ODY_PEMX_CFG(uint64_t a) __attribute__ ((pure, always_inline));
ODY_PEMX_CFG(uint64_t a)604 static inline uint64_t ODY_PEMX_CFG(uint64_t a)
605 {
606 if (a <= 15)
607 return 0x8e00000000d8ll + 0x1000000000ll * ((a) & 0xf);
608 __ody_csr_fatal("PEMX_CFG", 1, a, 0, 0, 0, 0, 0);
609 }
610
611 #define typedef_ODY_PEMX_CFG(a) ody_pemx_cfg_t
612 #define bustype_ODY_PEMX_CFG(a) CSR_TYPE_NCB
613 #define basename_ODY_PEMX_CFG(a) "PEMX_CFG"
614 #define device_bar_ODY_PEMX_CFG(a) 0x0 /* PF_BAR0 */
615 #define busnum_ODY_PEMX_CFG(a) (a)
616 #define arguments_ODY_PEMX_CFG(a) (a), -1, -1, -1
617
618 /**
619 * Register (NCB) pem#_cfg_tbl#
620 *
621 * PEM Configuration Table Registers
622 * Software managed table with list of config registers to update when
623 * PEM()_CTL_STATUS[LNK_ENB] is written with a 1. Typically the last
624 * table action should be to set PEM()_CTL_STATUS[SCR_DONE].
625 *
626 * This register is accessible through ROM scripts; see SCR_WRITE32_S[ADDR].
627 *
628 * This register is reset on cold reset.
629 */
630 union ody_pemx_cfg_tblx {
631 uint64_t u;
632 struct ody_pemx_cfg_tblx_s {
633 uint64_t offset : 12;
634 uint64_t wmask : 4;
635 uint64_t shadow : 1;
636 uint64_t vf_active : 1;
637 uint64_t pf : 1;
638 uint64_t reserved_19_21 : 3;
639 uint64_t vf : 6;
640 uint64_t reserved_28_30 : 3;
641 uint64_t broadcast : 1;
642 uint64_t data : 32;
643 } s;
644 /* struct ody_pemx_cfg_tblx_s cn; */
645 };
646 typedef union ody_pemx_cfg_tblx ody_pemx_cfg_tblx_t;
647
648 static inline uint64_t ODY_PEMX_CFG_TBLX(uint64_t a, uint64_t b) __attribute__ ((pure, always_inline));
ODY_PEMX_CFG_TBLX(uint64_t a,uint64_t b)649 static inline uint64_t ODY_PEMX_CFG_TBLX(uint64_t a, uint64_t b)
650 {
651 if ((a <= 15) && (b <= 1023))
652 return 0x8e0000002000ll + 0x1000000000ll * ((a) & 0xf) + 8ll * ((b) & 0x3ff);
653 __ody_csr_fatal("PEMX_CFG_TBLX", 2, a, b, 0, 0, 0, 0);
654 }
655
656 #define typedef_ODY_PEMX_CFG_TBLX(a, b) ody_pemx_cfg_tblx_t
657 #define bustype_ODY_PEMX_CFG_TBLX(a, b) CSR_TYPE_NCB
658 #define basename_ODY_PEMX_CFG_TBLX(a, b) "PEMX_CFG_TBLX"
659 #define device_bar_ODY_PEMX_CFG_TBLX(a, b) 0x0 /* PF_BAR0 */
660 #define busnum_ODY_PEMX_CFG_TBLX(a, b) (a)
661 #define arguments_ODY_PEMX_CFG_TBLX(a, b) (a), (b), -1, -1
662
663 /**
664 * Register (NCB) pem#_cfg_tbl_size
665 *
666 * PEM Configuration Table Size Register
667 * This register is accessible through ROM scripts; see SCR_WRITE32_S[ADDR].
668 *
669 * This register is reset on cold reset.
670 */
671 union ody_pemx_cfg_tbl_size {
672 uint64_t u;
673 struct ody_pemx_cfg_tbl_size_s {
674 uint64_t size : 11;
675 uint64_t reserved_11_63 : 53;
676 } s;
677 /* struct ody_pemx_cfg_tbl_size_s cn; */
678 };
679 typedef union ody_pemx_cfg_tbl_size ody_pemx_cfg_tbl_size_t;
680
681 static inline uint64_t ODY_PEMX_CFG_TBL_SIZE(uint64_t a) __attribute__ ((pure, always_inline));
ODY_PEMX_CFG_TBL_SIZE(uint64_t a)682 static inline uint64_t ODY_PEMX_CFG_TBL_SIZE(uint64_t a)
683 {
684 if (a <= 15)
685 return 0x8e0000000220ll + 0x1000000000ll * ((a) & 0xf);
686 __ody_csr_fatal("PEMX_CFG_TBL_SIZE", 1, a, 0, 0, 0, 0, 0);
687 }
688
689 #define typedef_ODY_PEMX_CFG_TBL_SIZE(a) ody_pemx_cfg_tbl_size_t
690 #define bustype_ODY_PEMX_CFG_TBL_SIZE(a) CSR_TYPE_NCB
691 #define basename_ODY_PEMX_CFG_TBL_SIZE(a) "PEMX_CFG_TBL_SIZE"
692 #define device_bar_ODY_PEMX_CFG_TBL_SIZE(a) 0x0 /* PF_BAR0 */
693 #define busnum_ODY_PEMX_CFG_TBL_SIZE(a) (a)
694 #define arguments_ODY_PEMX_CFG_TBL_SIZE(a) (a), -1, -1, -1
695
696 /**
697 * Register (NCB) pem#_clk_en
698 *
699 * PEM Clock Enable Register
700 * This register contains the clock enable for CPCLK and PCE_CLK.
701 *
702 * This register is accessible through ROM scripts; see SCR_WRITE32_S[ADDR].
703 *
704 * This register is reset on cold reset.
705 */
706 union ody_pemx_clk_en {
707 uint64_t u;
708 struct ody_pemx_clk_en_s {
709 uint64_t pemm_cpclk_force : 1;
710 uint64_t pemc_cpclk_gate : 1;
711 uint64_t pceclk_gate : 1;
712 uint64_t pemc_macclk_force : 1;
713 uint64_t pem_mdh_dis : 1;
714 uint64_t reserved_5_63 : 59;
715 } s;
716 /* struct ody_pemx_clk_en_s cn; */
717 };
718 typedef union ody_pemx_clk_en ody_pemx_clk_en_t;
719
720 static inline uint64_t ODY_PEMX_CLK_EN(uint64_t a) __attribute__ ((pure, always_inline));
ODY_PEMX_CLK_EN(uint64_t a)721 static inline uint64_t ODY_PEMX_CLK_EN(uint64_t a)
722 {
723 if (a <= 15)
724 return 0x8e00000000c8ll + 0x1000000000ll * ((a) & 0xf);
725 __ody_csr_fatal("PEMX_CLK_EN", 1, a, 0, 0, 0, 0, 0);
726 }
727
728 #define typedef_ODY_PEMX_CLK_EN(a) ody_pemx_clk_en_t
729 #define bustype_ODY_PEMX_CLK_EN(a) CSR_TYPE_NCB
730 #define basename_ODY_PEMX_CLK_EN(a) "PEMX_CLK_EN"
731 #define device_bar_ODY_PEMX_CLK_EN(a) 0x0 /* PF_BAR0 */
732 #define busnum_ODY_PEMX_CLK_EN(a) (a)
733 #define arguments_ODY_PEMX_CLK_EN(a) (a), -1, -1, -1
734
735 /**
736 * Register (NCB) pem#_const_acc
737 *
738 * PEM Constant ACC Register
739 * Contains constant attributes related to the PEM ACC tables.
740 */
741 union ody_pemx_const_acc {
742 uint64_t u;
743 struct ody_pemx_const_acc_s {
744 uint64_t num_norm : 16;
745 uint64_t bits_norm : 16;
746 uint64_t reserved_32_63 : 32;
747 } s;
748 /* struct ody_pemx_const_acc_s cn; */
749 };
750 typedef union ody_pemx_const_acc ody_pemx_const_acc_t;
751
752 static inline uint64_t ODY_PEMX_CONST_ACC(uint64_t a) __attribute__ ((pure, always_inline));
ODY_PEMX_CONST_ACC(uint64_t a)753 static inline uint64_t ODY_PEMX_CONST_ACC(uint64_t a)
754 {
755 if (a <= 15)
756 return 0x8e0000000218ll + 0x1000000000ll * ((a) & 0xf);
757 __ody_csr_fatal("PEMX_CONST_ACC", 1, a, 0, 0, 0, 0, 0);
758 }
759
760 #define typedef_ODY_PEMX_CONST_ACC(a) ody_pemx_const_acc_t
761 #define bustype_ODY_PEMX_CONST_ACC(a) CSR_TYPE_NCB
762 #define basename_ODY_PEMX_CONST_ACC(a) "PEMX_CONST_ACC"
763 #define device_bar_ODY_PEMX_CONST_ACC(a) 0x0 /* PF_BAR0 */
764 #define busnum_ODY_PEMX_CONST_ACC(a) (a)
765 #define arguments_ODY_PEMX_CONST_ACC(a) (a), -1, -1, -1
766
767 /**
768 * Register (NCB) pem#_cpclk_active_pc
769 *
770 * PEM Conditional Coprocessor Clock Counter Register
771 * This register counts conditional clocks for power management.
772 *
773 * This register is not accessible through ROM scripts; see SCR_WRITE32_S[ADDR].
774 *
775 * This register is reset on core domain reset.
776 */
777 union ody_pemx_cpclk_active_pc {
778 uint64_t u;
779 struct ody_pemx_cpclk_active_pc_s {
780 uint64_t count : 64;
781 } s;
782 /* struct ody_pemx_cpclk_active_pc_s cn; */
783 };
784 typedef union ody_pemx_cpclk_active_pc ody_pemx_cpclk_active_pc_t;
785
786 static inline uint64_t ODY_PEMX_CPCLK_ACTIVE_PC(uint64_t a) __attribute__ ((pure, always_inline));
ODY_PEMX_CPCLK_ACTIVE_PC(uint64_t a)787 static inline uint64_t ODY_PEMX_CPCLK_ACTIVE_PC(uint64_t a)
788 {
789 if (a <= 15)
790 return 0x8e0000000058ll + 0x1000000000ll * ((a) & 0xf);
791 __ody_csr_fatal("PEMX_CPCLK_ACTIVE_PC", 1, a, 0, 0, 0, 0, 0);
792 }
793
794 #define typedef_ODY_PEMX_CPCLK_ACTIVE_PC(a) ody_pemx_cpclk_active_pc_t
795 #define bustype_ODY_PEMX_CPCLK_ACTIVE_PC(a) CSR_TYPE_NCB
796 #define basename_ODY_PEMX_CPCLK_ACTIVE_PC(a) "PEMX_CPCLK_ACTIVE_PC"
797 #define device_bar_ODY_PEMX_CPCLK_ACTIVE_PC(a) 0x0 /* PF_BAR0 */
798 #define busnum_ODY_PEMX_CPCLK_ACTIVE_PC(a) (a)
799 #define arguments_ODY_PEMX_CPCLK_ACTIVE_PC(a) (a), -1, -1, -1
800
801 /**
802 * Register (NCB) pem#_cpl_lut_valid
803 *
804 * PEM Completion Lookup Table Valid Register
805 * This register specifies how many tags are outstanding for reads.
806 *
807 * This register is not accessible through ROM scripts; see SCR_WRITE32_S[ADDR].
808 *
809 * This register is reset on MAC reset.
810 */
811 union ody_pemx_cpl_lut_valid {
812 uint64_t u;
813 struct ody_pemx_cpl_lut_valid_s {
814 uint64_t tag : 10;
815 uint64_t reserved_10_63 : 54;
816 } s;
817 /* struct ody_pemx_cpl_lut_valid_s cn; */
818 };
819 typedef union ody_pemx_cpl_lut_valid ody_pemx_cpl_lut_valid_t;
820
821 static inline uint64_t ODY_PEMX_CPL_LUT_VALID(uint64_t a) __attribute__ ((pure, always_inline));
ODY_PEMX_CPL_LUT_VALID(uint64_t a)822 static inline uint64_t ODY_PEMX_CPL_LUT_VALID(uint64_t a)
823 {
824 if (a <= 15)
825 return 0x8e0000000040ll + 0x1000000000ll * ((a) & 0xf);
826 __ody_csr_fatal("PEMX_CPL_LUT_VALID", 1, a, 0, 0, 0, 0, 0);
827 }
828
829 #define typedef_ODY_PEMX_CPL_LUT_VALID(a) ody_pemx_cpl_lut_valid_t
830 #define bustype_ODY_PEMX_CPL_LUT_VALID(a) CSR_TYPE_NCB
831 #define basename_ODY_PEMX_CPL_LUT_VALID(a) "PEMX_CPL_LUT_VALID"
832 #define device_bar_ODY_PEMX_CPL_LUT_VALID(a) 0x0 /* PF_BAR0 */
833 #define busnum_ODY_PEMX_CPL_LUT_VALID(a) (a)
834 #define arguments_ODY_PEMX_CPL_LUT_VALID(a) (a), -1, -1, -1
835
836 /**
837 * Register (NCB) pem#_ctl_status
838 *
839 * PEM Control Status Register
840 * This is a general control and status register of the PEM.
841 *
842 * This register is accessible through ROM scripts; see SCR_WRITE32_S[ADDR].
843 *
844 * This register is reset on cold reset. Note this differs from PEM()_CTL_STATUS2's reset.
845 */
846 union ody_pemx_ctl_status {
847 uint64_t u;
848 struct ody_pemx_ctl_status_s {
849 uint64_t inv_lcrc : 1;
850 uint64_t inv_ecrc : 1;
851 uint64_t fast_lm : 1;
852 uint64_t l1_exit : 1;
853 uint64_t lnk_enb : 1;
854 uint64_t frc_retry : 1;
855 uint64_t margin_rdy : 1;
856 uint64_t rdy_entr_l23 : 1;
857 uint64_t clk_req_n : 1;
858 uint64_t ccrs : 1;
859 uint64_t play : 1;
860 uint64_t auto_mode : 1;
861 uint64_t pm_xtoff : 1;
862 uint64_t scr_done : 1;
863 uint64_t spares : 2;
864 uint64_t reserved_16_31 : 16;
865 uint64_t pbus : 8;
866 uint64_t dnum : 5;
867 uint64_t auto_sd : 1;
868 uint64_t reserved_46_63 : 18;
869 } s;
870 /* struct ody_pemx_ctl_status_s cn; */
871 };
872 typedef union ody_pemx_ctl_status ody_pemx_ctl_status_t;
873
874 static inline uint64_t ODY_PEMX_CTL_STATUS(uint64_t a) __attribute__ ((pure, always_inline));
ODY_PEMX_CTL_STATUS(uint64_t a)875 static inline uint64_t ODY_PEMX_CTL_STATUS(uint64_t a)
876 {
877 if (a <= 15)
878 return 0x8e0000000000ll + 0x1000000000ll * ((a) & 0xf);
879 __ody_csr_fatal("PEMX_CTL_STATUS", 1, a, 0, 0, 0, 0, 0);
880 }
881
882 #define typedef_ODY_PEMX_CTL_STATUS(a) ody_pemx_ctl_status_t
883 #define bustype_ODY_PEMX_CTL_STATUS(a) CSR_TYPE_NCB
884 #define basename_ODY_PEMX_CTL_STATUS(a) "PEMX_CTL_STATUS"
885 #define device_bar_ODY_PEMX_CTL_STATUS(a) 0x0 /* PF_BAR0 */
886 #define busnum_ODY_PEMX_CTL_STATUS(a) (a)
887 #define arguments_ODY_PEMX_CTL_STATUS(a) (a), -1, -1, -1
888
889 /**
890 * Register (NCB) pem#_ctl_status2
891 *
892 * PEM Control Status 2 Register
893 * This register contains additional general control and status of the PEM.
894 *
895 * This register is accessible through ROM scripts; see SCR_WRITE32_S[ADDR].
896 *
897 * This register is reset on core domain reset. Note this differs from PEM()_CTL_STATUS's reset.
898 */
899 union ody_pemx_ctl_status2 {
900 uint64_t u;
901 struct ody_pemx_ctl_status2_s {
902 uint64_t no_fwd_prg : 16;
903 uint64_t cfg_rtry : 16;
904 uint64_t trgt1_ecc_cor_dis : 1;
905 uint64_t perf_latency_en : 1;
906 uint64_t reserved_34_63 : 30;
907 } s;
908 /* struct ody_pemx_ctl_status2_s cn; */
909 };
910 typedef union ody_pemx_ctl_status2 ody_pemx_ctl_status2_t;
911
912 static inline uint64_t ODY_PEMX_CTL_STATUS2(uint64_t a) __attribute__ ((pure, always_inline));
ODY_PEMX_CTL_STATUS2(uint64_t a)913 static inline uint64_t ODY_PEMX_CTL_STATUS2(uint64_t a)
914 {
915 if (a <= 15)
916 return 0x8e0000000130ll + 0x1000000000ll * ((a) & 0xf);
917 __ody_csr_fatal("PEMX_CTL_STATUS2", 1, a, 0, 0, 0, 0, 0);
918 }
919
920 #define typedef_ODY_PEMX_CTL_STATUS2(a) ody_pemx_ctl_status2_t
921 #define bustype_ODY_PEMX_CTL_STATUS2(a) CSR_TYPE_NCB
922 #define basename_ODY_PEMX_CTL_STATUS2(a) "PEMX_CTL_STATUS2"
923 #define device_bar_ODY_PEMX_CTL_STATUS2(a) 0x0 /* PF_BAR0 */
924 #define busnum_ODY_PEMX_CTL_STATUS2(a) (a)
925 #define arguments_ODY_PEMX_CTL_STATUS2(a) (a), -1, -1, -1
926
927 /**
928 * Register (NCB) pem#_dbg_info
929 *
930 * PEM Debug Information Register
931 * This is a debug information register of the PEM.
932 *
933 * This register is accessible through ROM scripts; see SCR_WRITE32_S[ADDR].
934 *
935 * This register is reset on core domain reset.
936 */
937 union ody_pemx_dbg_info {
938 uint64_t u;
939 struct ody_pemx_dbg_info_s {
940 uint64_t spoison : 1;
941 uint64_t rtlpmal : 1;
942 uint64_t rtlplle : 1;
943 uint64_t recrce : 1;
944 uint64_t rpoison : 1;
945 uint64_t rcemrc : 1;
946 uint64_t rnfemrc : 1;
947 uint64_t rfemrc : 1;
948 uint64_t rpmerc : 1;
949 uint64_t rptamrc : 1;
950 uint64_t rumep : 1;
951 uint64_t rvdm : 1;
952 uint64_t acto : 1;
953 uint64_t rte : 1;
954 uint64_t mre : 1;
955 uint64_t rdwdle : 1;
956 uint64_t rtwdle : 1;
957 uint64_t dpeoosd : 1;
958 uint64_t fcpvwt : 1;
959 uint64_t rpe : 1;
960 uint64_t fcuv : 1;
961 uint64_t rqo : 1;
962 uint64_t rauc : 1;
963 uint64_t racur : 1;
964 uint64_t racca : 1;
965 uint64_t caar : 1;
966 uint64_t rarwdns : 1;
967 uint64_t ramtlp : 1;
968 uint64_t racpp : 1;
969 uint64_t rawwpp : 1;
970 uint64_t ecrc_e : 1;
971 uint64_t lofp : 1;
972 uint64_t bmd_e : 1;
973 uint64_t rasdp : 1;
974 uint64_t in_flr : 1;
975 uint64_t vf_en_off : 1;
976 uint64_t non_mem_load : 1;
977 uint64_t atomic_non_mem : 1;
978 uint64_t n_ecam_store : 1;
979 uint64_t p_ecam_store : 1;
980 uint64_t ecam_load : 1;
981 uint64_t n_csr_store : 1;
982 uint64_t p_csr_store : 1;
983 uint64_t csr_load : 1;
984 uint64_t atomic_to_csr : 1;
985 uint64_t n_store : 1;
986 uint64_t p_maps_to_n : 1;
987 uint64_t n_store_zero_byte : 1;
988 uint64_t p_store_zero_byte : 1;
989 uint64_t n_lswst : 1;
990 uint64_t p_lswst : 1;
991 uint64_t bad_zero : 1;
992 uint64_t reserved_52_63 : 12;
993 } s;
994 /* struct ody_pemx_dbg_info_s cn; */
995 };
996 typedef union ody_pemx_dbg_info ody_pemx_dbg_info_t;
997
998 static inline uint64_t ODY_PEMX_DBG_INFO(uint64_t a) __attribute__ ((pure, always_inline));
ODY_PEMX_DBG_INFO(uint64_t a)999 static inline uint64_t ODY_PEMX_DBG_INFO(uint64_t a)
1000 {
1001 if (a <= 15)
1002 return 0x8e0000000108ll + 0x1000000000ll * ((a) & 0xf);
1003 __ody_csr_fatal("PEMX_DBG_INFO", 1, a, 0, 0, 0, 0, 0);
1004 }
1005
1006 #define typedef_ODY_PEMX_DBG_INFO(a) ody_pemx_dbg_info_t
1007 #define bustype_ODY_PEMX_DBG_INFO(a) CSR_TYPE_NCB
1008 #define basename_ODY_PEMX_DBG_INFO(a) "PEMX_DBG_INFO"
1009 #define device_bar_ODY_PEMX_DBG_INFO(a) 0x0 /* PF_BAR0 */
1010 #define busnum_ODY_PEMX_DBG_INFO(a) (a)
1011 #define arguments_ODY_PEMX_DBG_INFO(a) (a), -1, -1, -1
1012
1013 /**
1014 * Register (NCB) pem#_debug
1015 *
1016 * PEM Debug Register
1017 * This register contains status of level interrupts for debugging purposes.
1018 *
1019 * This register is not accessible through ROM scripts; see SCR_WRITE32_S[ADDR].
1020 *
1021 * This register is reset on cold reset.
1022 */
1023 union ody_pemx_debug {
1024 uint64_t u;
1025 struct ody_pemx_debug_s {
1026 uint64_t intval : 6;
1027 uint64_t reserved_6_31 : 26;
1028 uint64_t ib_drop_why : 32;
1029 } s;
1030 /* struct ody_pemx_debug_s cn; */
1031 };
1032 typedef union ody_pemx_debug ody_pemx_debug_t;
1033
1034 static inline uint64_t ODY_PEMX_DEBUG(uint64_t a) __attribute__ ((pure, always_inline));
ODY_PEMX_DEBUG(uint64_t a)1035 static inline uint64_t ODY_PEMX_DEBUG(uint64_t a)
1036 {
1037 if (a <= 15)
1038 return 0x8e0000000110ll + 0x1000000000ll * ((a) & 0xf);
1039 __ody_csr_fatal("PEMX_DEBUG", 1, a, 0, 0, 0, 0, 0);
1040 }
1041
1042 #define typedef_ODY_PEMX_DEBUG(a) ody_pemx_debug_t
1043 #define bustype_ODY_PEMX_DEBUG(a) CSR_TYPE_NCB
1044 #define basename_ODY_PEMX_DEBUG(a) "PEMX_DEBUG"
1045 #define device_bar_ODY_PEMX_DEBUG(a) 0x0 /* PF_BAR0 */
1046 #define busnum_ODY_PEMX_DEBUG(a) (a)
1047 #define arguments_ODY_PEMX_DEBUG(a) (a), -1, -1, -1
1048
1049 /**
1050 * Register (NCB) pem#_diag_status
1051 *
1052 * PEM Diagnostic Status Register
1053 * This register contains selection control for the core diagnostic bus.
1054 *
1055 * This register is accessible through ROM scripts; see SCR_WRITE32_S[ADDR].
1056 *
1057 * This register is reset on MAC reset.
1058 */
1059 union ody_pemx_diag_status {
1060 uint64_t u;
1061 struct ody_pemx_diag_status_s {
1062 uint64_t pwrdwn : 4;
1063 uint64_t ltssm : 6;
1064 uint64_t pclk_rate : 3;
1065 uint64_t lnkst_l2_exit : 1;
1066 uint64_t lnkst_l2 : 1;
1067 uint64_t reserved_15 : 1;
1068 uint64_t lnkst_l1 : 1;
1069 uint64_t lnk_up : 1;
1070 uint64_t sel_aux_clk : 1;
1071 uint64_t l1_entry_inprogress : 1;
1072 uint64_t pclkreqn : 1;
1073 uint64_t l1_aspm_enter_ready : 1;
1074 uint64_t reserved_22_23 : 2;
1075 uint64_t pm_mst_fsm : 5;
1076 uint64_t reserved_29_31 : 3;
1077 uint64_t pm_slv_fsm : 5;
1078 uint64_t reserved_37_63 : 27;
1079 } s;
1080 struct ody_pemx_diag_status_cn {
1081 uint64_t pwrdwn : 4;
1082 uint64_t ltssm : 6;
1083 uint64_t pclk_rate : 3;
1084 uint64_t lnkst_l2_exit : 1;
1085 uint64_t lnkst_l2 : 1;
1086 uint64_t reserved_15 : 1;
1087 uint64_t lnkst_l1 : 1;
1088 uint64_t lnk_up : 1;
1089 uint64_t sel_aux_clk : 1;
1090 uint64_t l1_entry_inprogress : 1;
1091 uint64_t pclkreqn : 1;
1092 uint64_t l1_aspm_enter_ready : 1;
1093 uint64_t reserved_22_23 : 2;
1094 uint64_t pm_mst_fsm : 5;
1095 uint64_t reserved_29_31 : 3;
1096 uint64_t pm_slv_fsm : 5;
1097 uint64_t reserved_37_39 : 3;
1098 uint64_t reserved_40_63 : 24;
1099 } cn;
1100 };
1101 typedef union ody_pemx_diag_status ody_pemx_diag_status_t;
1102
1103 static inline uint64_t ODY_PEMX_DIAG_STATUS(uint64_t a) __attribute__ ((pure, always_inline));
ODY_PEMX_DIAG_STATUS(uint64_t a)1104 static inline uint64_t ODY_PEMX_DIAG_STATUS(uint64_t a)
1105 {
1106 if (a <= 15)
1107 return 0x8e0000000010ll + 0x1000000000ll * ((a) & 0xf);
1108 __ody_csr_fatal("PEMX_DIAG_STATUS", 1, a, 0, 0, 0, 0, 0);
1109 }
1110
1111 #define typedef_ODY_PEMX_DIAG_STATUS(a) ody_pemx_diag_status_t
1112 #define bustype_ODY_PEMX_DIAG_STATUS(a) CSR_TYPE_NCB
1113 #define basename_ODY_PEMX_DIAG_STATUS(a) "PEMX_DIAG_STATUS"
1114 #define device_bar_ODY_PEMX_DIAG_STATUS(a) 0x0 /* PF_BAR0 */
1115 #define busnum_ODY_PEMX_DIAG_STATUS(a) (a)
1116 #define arguments_ODY_PEMX_DIAG_STATUS(a) (a), -1, -1, -1
1117
1118 /**
1119 * Register (NCB) pem#_dis_port
1120 *
1121 * PEM Disable Port Register
1122 * This register controls whether traffic is allowed to be sent out the PCIe link.
1123 *
1124 * This register is accessible through ROM scripts; see SCR_WRITE32_S[ADDR].
1125 *
1126 * This register is reset on core domain reset.
1127 */
1128 union ody_pemx_dis_port {
1129 uint64_t u;
1130 struct ody_pemx_dis_port_s {
1131 uint64_t dis_port : 1;
1132 uint64_t reserved_1_63 : 63;
1133 } s;
1134 /* struct ody_pemx_dis_port_s cn; */
1135 };
1136 typedef union ody_pemx_dis_port ody_pemx_dis_port_t;
1137
1138 static inline uint64_t ODY_PEMX_DIS_PORT(uint64_t a) __attribute__ ((pure, always_inline));
ODY_PEMX_DIS_PORT(uint64_t a)1139 static inline uint64_t ODY_PEMX_DIS_PORT(uint64_t a)
1140 {
1141 if (a <= 15)
1142 return 0x8e0000000050ll + 0x1000000000ll * ((a) & 0xf);
1143 __ody_csr_fatal("PEMX_DIS_PORT", 1, a, 0, 0, 0, 0, 0);
1144 }
1145
1146 #define typedef_ODY_PEMX_DIS_PORT(a) ody_pemx_dis_port_t
1147 #define bustype_ODY_PEMX_DIS_PORT(a) CSR_TYPE_NCB
1148 #define basename_ODY_PEMX_DIS_PORT(a) "PEMX_DIS_PORT"
1149 #define device_bar_ODY_PEMX_DIS_PORT(a) 0x0 /* PF_BAR0 */
1150 #define busnum_ODY_PEMX_DIS_PORT(a) (a)
1151 #define arguments_ODY_PEMX_DIS_PORT(a) (a), -1, -1, -1
1152
1153 /**
1154 * Register (NCB) pem#_ebi_tlp_credits
1155 *
1156 * PEM EBUS TLP Credits Register
1157 * This register specifies the number of credits for use in moving TLPs. When this register is
1158 * written, the credit values are reset to the register value. This register is for diagnostic
1159 * use only, and should only be written when PEM()_CTL_STATUS[LNK_ENB] is clear.
1160 *
1161 * This register is accessible through ROM scripts; see SCR_WRITE32_S[ADDR].
1162 *
1163 * This register is reset on MAC reset.
1164 */
1165 union ody_pemx_ebi_tlp_credits {
1166 uint64_t u;
1167 struct ody_pemx_ebi_tlp_credits_s {
1168 uint64_t ebi_p : 11;
1169 uint64_t ebi_np : 10;
1170 uint64_t ebi_cpl : 11;
1171 uint64_t reserved_32_63 : 32;
1172 } s;
1173 /* struct ody_pemx_ebi_tlp_credits_s cn; */
1174 };
1175 typedef union ody_pemx_ebi_tlp_credits ody_pemx_ebi_tlp_credits_t;
1176
1177 static inline uint64_t ODY_PEMX_EBI_TLP_CREDITS(uint64_t a) __attribute__ ((pure, always_inline));
ODY_PEMX_EBI_TLP_CREDITS(uint64_t a)1178 static inline uint64_t ODY_PEMX_EBI_TLP_CREDITS(uint64_t a)
1179 {
1180 if (a <= 15)
1181 return 0x8e0000000028ll + 0x1000000000ll * ((a) & 0xf);
1182 __ody_csr_fatal("PEMX_EBI_TLP_CREDITS", 1, a, 0, 0, 0, 0, 0);
1183 }
1184
1185 #define typedef_ODY_PEMX_EBI_TLP_CREDITS(a) ody_pemx_ebi_tlp_credits_t
1186 #define bustype_ODY_PEMX_EBI_TLP_CREDITS(a) CSR_TYPE_NCB
1187 #define basename_ODY_PEMX_EBI_TLP_CREDITS(a) "PEMX_EBI_TLP_CREDITS"
1188 #define device_bar_ODY_PEMX_EBI_TLP_CREDITS(a) 0x0 /* PF_BAR0 */
1189 #define busnum_ODY_PEMX_EBI_TLP_CREDITS(a) (a)
1190 #define arguments_ODY_PEMX_EBI_TLP_CREDITS(a) (a), -1, -1, -1
1191
1192 /**
1193 * Register (NCB) pem#_ebo_fifo_status
1194 *
1195 * PEM EBO Offloading FIFO Status Register
1196 * This register contains status about the PEM EBO offloading FIFOs.
1197 *
1198 * This register is not accessible through ROM scripts; see SCR_WRITE32_S[ADDR].
1199 *
1200 * This register is reset on core domain reset.
1201 */
1202 union ody_pemx_ebo_fifo_status {
1203 uint64_t u;
1204 struct ody_pemx_ebo_fifo_status_s {
1205 uint64_t p_data_volume : 8;
1206 uint64_t reserved_8_11 : 4;
1207 uint64_t n_data_volume : 8;
1208 uint64_t reserved_20_23 : 4;
1209 uint64_t c_data_volume : 8;
1210 uint64_t p_cmd_volume : 6;
1211 uint64_t reserved_38_39 : 2;
1212 uint64_t n_cmd_volume : 6;
1213 uint64_t reserved_46_47 : 2;
1214 uint64_t c_cmd_volume : 6;
1215 uint64_t reserved_54_63 : 10;
1216 } s;
1217 /* struct ody_pemx_ebo_fifo_status_s cn; */
1218 };
1219 typedef union ody_pemx_ebo_fifo_status ody_pemx_ebo_fifo_status_t;
1220
1221 static inline uint64_t ODY_PEMX_EBO_FIFO_STATUS(uint64_t a) __attribute__ ((pure, always_inline));
ODY_PEMX_EBO_FIFO_STATUS(uint64_t a)1222 static inline uint64_t ODY_PEMX_EBO_FIFO_STATUS(uint64_t a)
1223 {
1224 if (a <= 15)
1225 return 0x8e0000000140ll + 0x1000000000ll * ((a) & 0xf);
1226 __ody_csr_fatal("PEMX_EBO_FIFO_STATUS", 1, a, 0, 0, 0, 0, 0);
1227 }
1228
1229 #define typedef_ODY_PEMX_EBO_FIFO_STATUS(a) ody_pemx_ebo_fifo_status_t
1230 #define bustype_ODY_PEMX_EBO_FIFO_STATUS(a) CSR_TYPE_NCB
1231 #define basename_ODY_PEMX_EBO_FIFO_STATUS(a) "PEMX_EBO_FIFO_STATUS"
1232 #define device_bar_ODY_PEMX_EBO_FIFO_STATUS(a) 0x0 /* PF_BAR0 */
1233 #define busnum_ODY_PEMX_EBO_FIFO_STATUS(a) (a)
1234 #define arguments_ODY_PEMX_EBO_FIFO_STATUS(a) (a), -1, -1, -1
1235
1236 /**
1237 * Register (NCB) pem#_end_merge
1238 *
1239 * PEM End Merge Register
1240 * Any access (read or write) to this register over NCBO will create a merging barrier
1241 * for both the write and read streams within PEM outbound merging stations used by AP
1242 * traffic such that no NCBO reads or writes received from AP as the source after this
1243 * register's access will merge with any NCBO accesses received from AP as the source
1244 * that occurred prior to this register's access. Note that RSL accesses to this register
1245 * will have no effect on merging.
1246 *
1247 * This register is not accessible through ROM scripts; see SCR_WRITE32_S[ADDR].
1248 *
1249 * This register is reset on core domain reset.
1250 */
1251 union ody_pemx_end_merge {
1252 uint64_t u;
1253 struct ody_pemx_end_merge_s {
1254 uint64_t reserved_0_63 : 64;
1255 } s;
1256 /* struct ody_pemx_end_merge_s cn; */
1257 };
1258 typedef union ody_pemx_end_merge ody_pemx_end_merge_t;
1259
1260 static inline uint64_t ODY_PEMX_END_MERGE(uint64_t a) __attribute__ ((pure, always_inline));
ODY_PEMX_END_MERGE(uint64_t a)1261 static inline uint64_t ODY_PEMX_END_MERGE(uint64_t a)
1262 {
1263 if (a <= 15)
1264 return 0x8e0000000188ll + 0x1000000000ll * ((a) & 0xf);
1265 __ody_csr_fatal("PEMX_END_MERGE", 1, a, 0, 0, 0, 0, 0);
1266 }
1267
1268 #define typedef_ODY_PEMX_END_MERGE(a) ody_pemx_end_merge_t
1269 #define bustype_ODY_PEMX_END_MERGE(a) CSR_TYPE_NCB
1270 #define basename_ODY_PEMX_END_MERGE(a) "PEMX_END_MERGE"
1271 #define device_bar_ODY_PEMX_END_MERGE(a) 0x0 /* PF_BAR0 */
1272 #define busnum_ODY_PEMX_END_MERGE(a) (a)
1273 #define arguments_ODY_PEMX_END_MERGE(a) (a), -1, -1, -1
1274
1275 /**
1276 * Register (NCB) pem#_ib_latency#_pc#
1277 *
1278 * PEM Inbound Latency Time Registers
1279 * This register resets on core domain reset. It measures the time portion
1280 * of the information set needed by software to calculate average inbound
1281 * read latency to the target bus.
1282 * Index {a} represents the internal target bus and is enumerated by PEM_PERF_BUS_E.
1283 * Index {b} represents a set of registers mapped by using PEM_MPAM_ASSOC_PC, however
1284 * the MPAM value is not used for these registers and accumulated latency will reflect
1285 * all inbound TLPs. All 8 registers will read the same.
1286 *
1287 * This register is not accessible through ROM scripts; see SCR_WRITE32_S[ADDR].
1288 */
1289 union ody_pemx_ib_latencyx_pcx {
1290 uint64_t u;
1291 struct ody_pemx_ib_latencyx_pcx_s {
1292 uint64_t latency : 64;
1293 } s;
1294 /* struct ody_pemx_ib_latencyx_pcx_s cn; */
1295 };
1296 typedef union ody_pemx_ib_latencyx_pcx ody_pemx_ib_latencyx_pcx_t;
1297
1298 static inline uint64_t ODY_PEMX_IB_LATENCYX_PCX(uint64_t a, uint64_t b, uint64_t c) __attribute__ ((pure, always_inline));
ODY_PEMX_IB_LATENCYX_PCX(uint64_t a,uint64_t b,uint64_t c)1299 static inline uint64_t ODY_PEMX_IB_LATENCYX_PCX(uint64_t a, uint64_t b, uint64_t c)
1300 {
1301 if ((a <= 15) && (b == 0) && (c <= 7))
1302 return 0x8e0000005200ll + 0x1000000000ll * ((a) & 0xf) + 0x20ll * ((c) & 0x7);
1303 __ody_csr_fatal("PEMX_IB_LATENCYX_PCX", 3, a, b, c, 0, 0, 0);
1304 }
1305
1306 #define typedef_ODY_PEMX_IB_LATENCYX_PCX(a, b, c) ody_pemx_ib_latencyx_pcx_t
1307 #define bustype_ODY_PEMX_IB_LATENCYX_PCX(a, b, c) CSR_TYPE_NCB
1308 #define basename_ODY_PEMX_IB_LATENCYX_PCX(a, b, c) "PEMX_IB_LATENCYX_PCX"
1309 #define device_bar_ODY_PEMX_IB_LATENCYX_PCX(a, b, c) 0x0 /* PF_BAR0 */
1310 #define busnum_ODY_PEMX_IB_LATENCYX_PCX(a, b, c) (a)
1311 #define arguments_ODY_PEMX_IB_LATENCYX_PCX(a, b, c) (a), (b), (c), -1
1312
1313 /**
1314 * Register (NCB) pem#_ib_reads#_pc#
1315 *
1316 * PEM Inbound Read Count Registers
1317 * This register resets on core domain reset. It measures the count portion
1318 * of the information set needed by software to calculate average inbound
1319 * read latency to the target bus.
1320 * Index {a} represents the internal target bus and is enumerated by PEM_PERF_BUS_E.
1321 * Index {b} represents a set of registers mapped by using PEM_MPAM_ASSOC_PC, however
1322 * the MPAM value is not used for these registers and accumulated value will reflect
1323 * all inbound TLPs. All 8 registers will read the same.
1324 *
1325 * When PEM_CTL_STATUS2.PERF_LATENCY_EN is clear, this register is clock gated.
1326 *
1327 * This register is not accessible through ROM scripts; see SCR_WRITE32_S[ADDR].
1328 */
1329 union ody_pemx_ib_readsx_pcx {
1330 uint64_t u;
1331 struct ody_pemx_ib_readsx_pcx_s {
1332 uint64_t reads : 64;
1333 } s;
1334 /* struct ody_pemx_ib_readsx_pcx_s cn; */
1335 };
1336 typedef union ody_pemx_ib_readsx_pcx ody_pemx_ib_readsx_pcx_t;
1337
1338 static inline uint64_t ODY_PEMX_IB_READSX_PCX(uint64_t a, uint64_t b, uint64_t c) __attribute__ ((pure, always_inline));
ODY_PEMX_IB_READSX_PCX(uint64_t a,uint64_t b,uint64_t c)1339 static inline uint64_t ODY_PEMX_IB_READSX_PCX(uint64_t a, uint64_t b, uint64_t c)
1340 {
1341 if ((a <= 15) && (b == 0) && (c <= 7))
1342 return 0x8e0000005300ll + 0x1000000000ll * ((a) & 0xf) + 0x20ll * ((c) & 0x7);
1343 __ody_csr_fatal("PEMX_IB_READSX_PCX", 3, a, b, c, 0, 0, 0);
1344 }
1345
1346 #define typedef_ODY_PEMX_IB_READSX_PCX(a, b, c) ody_pemx_ib_readsx_pcx_t
1347 #define bustype_ODY_PEMX_IB_READSX_PCX(a, b, c) CSR_TYPE_NCB
1348 #define basename_ODY_PEMX_IB_READSX_PCX(a, b, c) "PEMX_IB_READSX_PCX"
1349 #define device_bar_ODY_PEMX_IB_READSX_PCX(a, b, c) 0x0 /* PF_BAR0 */
1350 #define busnum_ODY_PEMX_IB_READSX_PCX(a, b, c) (a)
1351 #define arguments_ODY_PEMX_IB_READSX_PCX(a, b, c) (a), (b), (c), -1
1352
1353 /**
1354 * Register (NCB) pem#_ib_req#_no_ro_pc#
1355 *
1356 * PEM Inbound No Relaxed Ordering Registers
1357 * This register resets on core domain reset. It measures the number of inbound requests
1358 * (non-posted/posted) directed to the target bus with the RO attribute not set.
1359 * Index {a} represents the internal target bus and is enumerated by PEM_PERF_BUS_E.
1360 * Index {b} represents a set of registers mapped by using PEM_MPAM_ASSOC_PC,
1361 * however the mapping is not used for these registers; instead, all 8 registers are
1362 * updated for all MPAM values.
1363 *
1364 * This register is not accessible through ROM scripts; see SCR_WRITE32_S[ADDR].
1365 */
1366 union ody_pemx_ib_reqx_no_ro_pcx {
1367 uint64_t u;
1368 struct ody_pemx_ib_reqx_no_ro_pcx_s {
1369 uint64_t count : 64;
1370 } s;
1371 /* struct ody_pemx_ib_reqx_no_ro_pcx_s cn; */
1372 };
1373 typedef union ody_pemx_ib_reqx_no_ro_pcx ody_pemx_ib_reqx_no_ro_pcx_t;
1374
1375 static inline uint64_t ODY_PEMX_IB_REQX_NO_RO_PCX(uint64_t a, uint64_t b, uint64_t c) __attribute__ ((pure, always_inline));
ODY_PEMX_IB_REQX_NO_RO_PCX(uint64_t a,uint64_t b,uint64_t c)1376 static inline uint64_t ODY_PEMX_IB_REQX_NO_RO_PCX(uint64_t a, uint64_t b, uint64_t c)
1377 {
1378 if ((a <= 15) && (b <= 1) && (c <= 7))
1379 return 0x8e0000005400ll + 0x1000000000ll * ((a) & 0xf) + 8ll * ((b) & 0x1) + 0x20ll * ((c) & 0x7);
1380 __ody_csr_fatal("PEMX_IB_REQX_NO_RO_PCX", 3, a, b, c, 0, 0, 0);
1381 }
1382
1383 #define typedef_ODY_PEMX_IB_REQX_NO_RO_PCX(a, b, c) ody_pemx_ib_reqx_no_ro_pcx_t
1384 #define bustype_ODY_PEMX_IB_REQX_NO_RO_PCX(a, b, c) CSR_TYPE_NCB
1385 #define basename_ODY_PEMX_IB_REQX_NO_RO_PCX(a, b, c) "PEMX_IB_REQX_NO_RO_PCX"
1386 #define device_bar_ODY_PEMX_IB_REQX_NO_RO_PCX(a, b, c) 0x0 /* PF_BAR0 */
1387 #define busnum_ODY_PEMX_IB_REQX_NO_RO_PCX(a, b, c) (a)
1388 #define arguments_ODY_PEMX_IB_REQX_NO_RO_PCX(a, b, c) (a), (b), (c), -1
1389
1390 /**
1391 * Register (NCB) pem#_ib_tlp#_dwords_pc#
1392 *
1393 * PEM Inbound TLP DWORDS Registers
1394 * This register resets on core domain reset. Otherwise, it continuously accumulates
1395 * the number of DWORDS (including header overhead) in every inbound TLP received
1396 * from PCIe and headed to the target bus.
1397 * Index {a} represents the TLP type and is enumerated by PEM_PERF_TLP_TYPE_E.
1398 * Index {b} represents a set of registers mapped by using PEM_MPAM_ASSOC_PC,
1399 * however the mapping only occurs when Index {a} indicates PERF_CPL; for other
1400 * types, all 8 registers are incremented for all MPAM values.
1401 *
1402 * This register is not accessible through ROM scripts; see SCR_WRITE32_S[ADDR].
1403 */
1404 union ody_pemx_ib_tlpx_dwords_pcx {
1405 uint64_t u;
1406 struct ody_pemx_ib_tlpx_dwords_pcx_s {
1407 uint64_t tlp_dwords : 64;
1408 } s;
1409 /* struct ody_pemx_ib_tlpx_dwords_pcx_s cn; */
1410 };
1411 typedef union ody_pemx_ib_tlpx_dwords_pcx ody_pemx_ib_tlpx_dwords_pcx_t;
1412
1413 static inline uint64_t ODY_PEMX_IB_TLPX_DWORDS_PCX(uint64_t a, uint64_t b, uint64_t c) __attribute__ ((pure, always_inline));
ODY_PEMX_IB_TLPX_DWORDS_PCX(uint64_t a,uint64_t b,uint64_t c)1414 static inline uint64_t ODY_PEMX_IB_TLPX_DWORDS_PCX(uint64_t a, uint64_t b, uint64_t c)
1415 {
1416 if ((a <= 15) && (b <= 2) && (c <= 7))
1417 return 0x8e0000005100ll + 0x1000000000ll * ((a) & 0xf) + 8ll * ((b) & 0x3) + 0x20ll * ((c) & 0x7);
1418 __ody_csr_fatal("PEMX_IB_TLPX_DWORDS_PCX", 3, a, b, c, 0, 0, 0);
1419 }
1420
1421 #define typedef_ODY_PEMX_IB_TLPX_DWORDS_PCX(a, b, c) ody_pemx_ib_tlpx_dwords_pcx_t
1422 #define bustype_ODY_PEMX_IB_TLPX_DWORDS_PCX(a, b, c) CSR_TYPE_NCB
1423 #define basename_ODY_PEMX_IB_TLPX_DWORDS_PCX(a, b, c) "PEMX_IB_TLPX_DWORDS_PCX"
1424 #define device_bar_ODY_PEMX_IB_TLPX_DWORDS_PCX(a, b, c) 0x0 /* PF_BAR0 */
1425 #define busnum_ODY_PEMX_IB_TLPX_DWORDS_PCX(a, b, c) (a)
1426 #define arguments_ODY_PEMX_IB_TLPX_DWORDS_PCX(a, b, c) (a), (b), (c), -1
1427
1428 /**
1429 * Register (NCB) pem#_ib_tlp#_pc#
1430 *
1431 * PEM Inbound TLP Count Registers
1432 * This register resets on core domain reset. Otherwise, it continuously increments
1433 * on every inbound TLP received from PCIe and headed to the target bus.
1434 * Index {a} represents the TLP type and is enumerated by PEM_PERF_TLP_TYPE_E.
1435 * Index {b} represents a set of registers mapped by using PEM_MPAM_ASSOC_PC,
1436 * however the mapping only occurs when Index {a} indicates PERF_CPL; for other
1437 * types, all 8 registers are incremented for all MPAM values.
1438 *
1439 * This register is not accessible through ROM scripts; see SCR_WRITE32_S[ADDR].
1440 */
1441 union ody_pemx_ib_tlpx_pcx {
1442 uint64_t u;
1443 struct ody_pemx_ib_tlpx_pcx_s {
1444 uint64_t count : 64;
1445 } s;
1446 /* struct ody_pemx_ib_tlpx_pcx_s cn; */
1447 };
1448 typedef union ody_pemx_ib_tlpx_pcx ody_pemx_ib_tlpx_pcx_t;
1449
1450 static inline uint64_t ODY_PEMX_IB_TLPX_PCX(uint64_t a, uint64_t b, uint64_t c) __attribute__ ((pure, always_inline));
ODY_PEMX_IB_TLPX_PCX(uint64_t a,uint64_t b,uint64_t c)1451 static inline uint64_t ODY_PEMX_IB_TLPX_PCX(uint64_t a, uint64_t b, uint64_t c)
1452 {
1453 if ((a <= 15) && (b <= 2) && (c <= 7))
1454 return 0x8e0000005000ll + 0x1000000000ll * ((a) & 0xf) + 8ll * ((b) & 0x3) + 0x20ll * ((c) & 0x7);
1455 __ody_csr_fatal("PEMX_IB_TLPX_PCX", 3, a, b, c, 0, 0, 0);
1456 }
1457
1458 #define typedef_ODY_PEMX_IB_TLPX_PCX(a, b, c) ody_pemx_ib_tlpx_pcx_t
1459 #define bustype_ODY_PEMX_IB_TLPX_PCX(a, b, c) CSR_TYPE_NCB
1460 #define basename_ODY_PEMX_IB_TLPX_PCX(a, b, c) "PEMX_IB_TLPX_PCX"
1461 #define device_bar_ODY_PEMX_IB_TLPX_PCX(a, b, c) 0x0 /* PF_BAR0 */
1462 #define busnum_ODY_PEMX_IB_TLPX_PCX(a, b, c) (a)
1463 #define arguments_ODY_PEMX_IB_TLPX_PCX(a, b, c) (a), (b), (c), -1
1464
1465 /**
1466 * Register (NCB) pem#_int_ena_w1c
1467 *
1468 * PEM Interrupt Enable Clear Register
1469 * This register clears interrupt enable bits.
1470 */
1471 union ody_pemx_int_ena_w1c {
1472 uint64_t u;
1473 struct ody_pemx_int_ena_w1c_s {
1474 uint64_t se : 1;
1475 uint64_t up_b3 : 1;
1476 uint64_t up_b4 : 1;
1477 uint64_t up_b2 : 1;
1478 uint64_t up_bx : 1;
1479 uint64_t un_b4 : 1;
1480 uint64_t un_b2 : 1;
1481 uint64_t un_bx : 1;
1482 uint64_t rdlk : 1;
1483 uint64_t crs_er : 1;
1484 uint64_t crs_dr : 1;
1485 uint64_t cfg_inf : 1;
1486 uint64_t surp_down : 1;
1487 uint64_t up_b0 : 1;
1488 uint64_t un_b0 : 1;
1489 uint64_t ptm_rdy_val : 1;
1490 uint64_t reserved_16_17 : 2;
1491 uint64_t up_vf_b0 : 1;
1492 uint64_t reserved_19_20 : 2;
1493 uint64_t un_vf_b0 : 1;
1494 uint64_t ptm_rq_replaytx : 1;
1495 uint64_t ptm_rq_duprx : 1;
1496 uint64_t ptm_rq_unexp_rto : 1;
1497 uint64_t un_at : 1;
1498 uint64_t up_at : 1;
1499 uint64_t ats_itag_er : 1;
1500 uint64_t reserved_28_63 : 36;
1501 } s;
1502 /* struct ody_pemx_int_ena_w1c_s cn; */
1503 };
1504 typedef union ody_pemx_int_ena_w1c ody_pemx_int_ena_w1c_t;
1505
1506 static inline uint64_t ODY_PEMX_INT_ENA_W1C(uint64_t a) __attribute__ ((pure, always_inline));
ODY_PEMX_INT_ENA_W1C(uint64_t a)1507 static inline uint64_t ODY_PEMX_INT_ENA_W1C(uint64_t a)
1508 {
1509 if (a <= 15)
1510 return 0x8e00000000f8ll + 0x1000000000ll * ((a) & 0xf);
1511 __ody_csr_fatal("PEMX_INT_ENA_W1C", 1, a, 0, 0, 0, 0, 0);
1512 }
1513
1514 #define typedef_ODY_PEMX_INT_ENA_W1C(a) ody_pemx_int_ena_w1c_t
1515 #define bustype_ODY_PEMX_INT_ENA_W1C(a) CSR_TYPE_NCB
1516 #define basename_ODY_PEMX_INT_ENA_W1C(a) "PEMX_INT_ENA_W1C"
1517 #define device_bar_ODY_PEMX_INT_ENA_W1C(a) 0x0 /* PF_BAR0 */
1518 #define busnum_ODY_PEMX_INT_ENA_W1C(a) (a)
1519 #define arguments_ODY_PEMX_INT_ENA_W1C(a) (a), -1, -1, -1
1520
1521 /**
1522 * Register (NCB) pem#_int_ena_w1s
1523 *
1524 * PEM Interrupt Enable Set Register
1525 * This register sets interrupt enable bits.
1526 */
1527 union ody_pemx_int_ena_w1s {
1528 uint64_t u;
1529 struct ody_pemx_int_ena_w1s_s {
1530 uint64_t se : 1;
1531 uint64_t up_b3 : 1;
1532 uint64_t up_b4 : 1;
1533 uint64_t up_b2 : 1;
1534 uint64_t up_bx : 1;
1535 uint64_t un_b4 : 1;
1536 uint64_t un_b2 : 1;
1537 uint64_t un_bx : 1;
1538 uint64_t rdlk : 1;
1539 uint64_t crs_er : 1;
1540 uint64_t crs_dr : 1;
1541 uint64_t cfg_inf : 1;
1542 uint64_t surp_down : 1;
1543 uint64_t up_b0 : 1;
1544 uint64_t un_b0 : 1;
1545 uint64_t ptm_rdy_val : 1;
1546 uint64_t reserved_16_17 : 2;
1547 uint64_t up_vf_b0 : 1;
1548 uint64_t reserved_19_20 : 2;
1549 uint64_t un_vf_b0 : 1;
1550 uint64_t ptm_rq_replaytx : 1;
1551 uint64_t ptm_rq_duprx : 1;
1552 uint64_t ptm_rq_unexp_rto : 1;
1553 uint64_t un_at : 1;
1554 uint64_t up_at : 1;
1555 uint64_t ats_itag_er : 1;
1556 uint64_t reserved_28_63 : 36;
1557 } s;
1558 /* struct ody_pemx_int_ena_w1s_s cn; */
1559 };
1560 typedef union ody_pemx_int_ena_w1s ody_pemx_int_ena_w1s_t;
1561
1562 static inline uint64_t ODY_PEMX_INT_ENA_W1S(uint64_t a) __attribute__ ((pure, always_inline));
ODY_PEMX_INT_ENA_W1S(uint64_t a)1563 static inline uint64_t ODY_PEMX_INT_ENA_W1S(uint64_t a)
1564 {
1565 if (a <= 15)
1566 return 0x8e0000000100ll + 0x1000000000ll * ((a) & 0xf);
1567 __ody_csr_fatal("PEMX_INT_ENA_W1S", 1, a, 0, 0, 0, 0, 0);
1568 }
1569
1570 #define typedef_ODY_PEMX_INT_ENA_W1S(a) ody_pemx_int_ena_w1s_t
1571 #define bustype_ODY_PEMX_INT_ENA_W1S(a) CSR_TYPE_NCB
1572 #define basename_ODY_PEMX_INT_ENA_W1S(a) "PEMX_INT_ENA_W1S"
1573 #define device_bar_ODY_PEMX_INT_ENA_W1S(a) 0x0 /* PF_BAR0 */
1574 #define busnum_ODY_PEMX_INT_ENA_W1S(a) (a)
1575 #define arguments_ODY_PEMX_INT_ENA_W1S(a) (a), -1, -1, -1
1576
1577 /**
1578 * Register (NCB) pem#_int_sum
1579 *
1580 * PEM Interrupt Summary Register
1581 * This register contains the different interrupt summary bits of the PEM.
1582 *
1583 * This register is not accessible through ROM scripts; see SCR_WRITE32_S[ADDR].
1584 *
1585 * This register is reset on core domain reset.
1586 */
1587 union ody_pemx_int_sum {
1588 uint64_t u;
1589 struct ody_pemx_int_sum_s {
1590 uint64_t se : 1;
1591 uint64_t up_b3 : 1;
1592 uint64_t up_b4 : 1;
1593 uint64_t up_b2 : 1;
1594 uint64_t up_bx : 1;
1595 uint64_t un_b4 : 1;
1596 uint64_t un_b2 : 1;
1597 uint64_t un_bx : 1;
1598 uint64_t rdlk : 1;
1599 uint64_t crs_er : 1;
1600 uint64_t crs_dr : 1;
1601 uint64_t cfg_inf : 1;
1602 uint64_t surp_down : 1;
1603 uint64_t up_b0 : 1;
1604 uint64_t un_b0 : 1;
1605 uint64_t ptm_rdy_val : 1;
1606 uint64_t reserved_16_17 : 2;
1607 uint64_t up_vf_b0 : 1;
1608 uint64_t reserved_19_20 : 2;
1609 uint64_t un_vf_b0 : 1;
1610 uint64_t ptm_rq_replaytx : 1;
1611 uint64_t ptm_rq_duprx : 1;
1612 uint64_t ptm_rq_unexp_rto : 1;
1613 uint64_t un_at : 1;
1614 uint64_t up_at : 1;
1615 uint64_t ats_itag_er : 1;
1616 uint64_t reserved_28_63 : 36;
1617 } s;
1618 /* struct ody_pemx_int_sum_s cn; */
1619 };
1620 typedef union ody_pemx_int_sum ody_pemx_int_sum_t;
1621
1622 static inline uint64_t ODY_PEMX_INT_SUM(uint64_t a) __attribute__ ((pure, always_inline));
ODY_PEMX_INT_SUM(uint64_t a)1623 static inline uint64_t ODY_PEMX_INT_SUM(uint64_t a)
1624 {
1625 if (a <= 15)
1626 return 0x8e00000000e8ll + 0x1000000000ll * ((a) & 0xf);
1627 __ody_csr_fatal("PEMX_INT_SUM", 1, a, 0, 0, 0, 0, 0);
1628 }
1629
1630 #define typedef_ODY_PEMX_INT_SUM(a) ody_pemx_int_sum_t
1631 #define bustype_ODY_PEMX_INT_SUM(a) CSR_TYPE_NCB
1632 #define basename_ODY_PEMX_INT_SUM(a) "PEMX_INT_SUM"
1633 #define device_bar_ODY_PEMX_INT_SUM(a) 0x0 /* PF_BAR0 */
1634 #define busnum_ODY_PEMX_INT_SUM(a) (a)
1635 #define arguments_ODY_PEMX_INT_SUM(a) (a), -1, -1, -1
1636
1637 /**
1638 * Register (NCB) pem#_int_sum_w1s
1639 *
1640 * PEM Interrupt Summary Register
1641 * This register sets interrupt bits.
1642 */
1643 union ody_pemx_int_sum_w1s {
1644 uint64_t u;
1645 struct ody_pemx_int_sum_w1s_s {
1646 uint64_t se : 1;
1647 uint64_t up_b3 : 1;
1648 uint64_t up_b4 : 1;
1649 uint64_t up_b2 : 1;
1650 uint64_t up_bx : 1;
1651 uint64_t un_b4 : 1;
1652 uint64_t un_b2 : 1;
1653 uint64_t un_bx : 1;
1654 uint64_t rdlk : 1;
1655 uint64_t crs_er : 1;
1656 uint64_t crs_dr : 1;
1657 uint64_t cfg_inf : 1;
1658 uint64_t surp_down : 1;
1659 uint64_t up_b0 : 1;
1660 uint64_t un_b0 : 1;
1661 uint64_t ptm_rdy_val : 1;
1662 uint64_t reserved_16_17 : 2;
1663 uint64_t up_vf_b0 : 1;
1664 uint64_t reserved_19_20 : 2;
1665 uint64_t un_vf_b0 : 1;
1666 uint64_t ptm_rq_replaytx : 1;
1667 uint64_t ptm_rq_duprx : 1;
1668 uint64_t ptm_rq_unexp_rto : 1;
1669 uint64_t un_at : 1;
1670 uint64_t up_at : 1;
1671 uint64_t ats_itag_er : 1;
1672 uint64_t reserved_28_63 : 36;
1673 } s;
1674 /* struct ody_pemx_int_sum_w1s_s cn; */
1675 };
1676 typedef union ody_pemx_int_sum_w1s ody_pemx_int_sum_w1s_t;
1677
1678 static inline uint64_t ODY_PEMX_INT_SUM_W1S(uint64_t a) __attribute__ ((pure, always_inline));
ODY_PEMX_INT_SUM_W1S(uint64_t a)1679 static inline uint64_t ODY_PEMX_INT_SUM_W1S(uint64_t a)
1680 {
1681 if (a <= 15)
1682 return 0x8e00000000f0ll + 0x1000000000ll * ((a) & 0xf);
1683 __ody_csr_fatal("PEMX_INT_SUM_W1S", 1, a, 0, 0, 0, 0, 0);
1684 }
1685
1686 #define typedef_ODY_PEMX_INT_SUM_W1S(a) ody_pemx_int_sum_w1s_t
1687 #define bustype_ODY_PEMX_INT_SUM_W1S(a) CSR_TYPE_NCB
1688 #define basename_ODY_PEMX_INT_SUM_W1S(a) "PEMX_INT_SUM_W1S"
1689 #define device_bar_ODY_PEMX_INT_SUM_W1S(a) 0x0 /* PF_BAR0 */
1690 #define busnum_ODY_PEMX_INT_SUM_W1S(a) (a)
1691 #define arguments_ODY_PEMX_INT_SUM_W1S(a) (a), -1, -1, -1
1692
1693 /**
1694 * Register (NCB) pem#_merge_timer_ctl
1695 *
1696 * PEM Merge Timer Control Register
1697 * This register controls merging timers and overrides for maximum merging size
1698 * for outbound reads, writes, and completions. The TIMER fields in this
1699 * register reset to values that will allow merging and therefore improved
1700 * bandwidth across all PEM configurations. If a system is more sensitive to
1701 * reducing latency, then these fields can be written to smaller values to
1702 * ensure transactions do not wait too long to merge before being sent to PCIe.
1703 *
1704 * This register is not accessible through ROM scripts; see SCR_WRITE32_S[ADDR].
1705 *
1706 * This register is reset on core domain reset.
1707 */
1708 union ody_pemx_merge_timer_ctl {
1709 uint64_t u;
1710 struct ody_pemx_merge_timer_ctl_s {
1711 uint64_t rmerge_segment_timer : 10;
1712 uint64_t rmerge_total_timer : 10;
1713 uint64_t rmerge_mrrs_limit : 3;
1714 uint64_t wmerge_segment_timer : 10;
1715 uint64_t wmerge_total_timer : 10;
1716 uint64_t wmerge_mps_limit : 3;
1717 uint64_t cmerge_segment_timer : 7;
1718 uint64_t cmerge_total_timer : 7;
1719 uint64_t cmerge_mps_limit : 3;
1720 uint64_t cmerge_dis : 1;
1721 } s;
1722 /* struct ody_pemx_merge_timer_ctl_s cn; */
1723 };
1724 typedef union ody_pemx_merge_timer_ctl ody_pemx_merge_timer_ctl_t;
1725
1726 static inline uint64_t ODY_PEMX_MERGE_TIMER_CTL(uint64_t a) __attribute__ ((pure, always_inline));
ODY_PEMX_MERGE_TIMER_CTL(uint64_t a)1727 static inline uint64_t ODY_PEMX_MERGE_TIMER_CTL(uint64_t a)
1728 {
1729 if (a <= 15)
1730 return 0x8e0000000180ll + 0x1000000000ll * ((a) & 0xf);
1731 __ody_csr_fatal("PEMX_MERGE_TIMER_CTL", 1, a, 0, 0, 0, 0, 0);
1732 }
1733
1734 #define typedef_ODY_PEMX_MERGE_TIMER_CTL(a) ody_pemx_merge_timer_ctl_t
1735 #define bustype_ODY_PEMX_MERGE_TIMER_CTL(a) CSR_TYPE_NCB
1736 #define basename_ODY_PEMX_MERGE_TIMER_CTL(a) "PEMX_MERGE_TIMER_CTL"
1737 #define device_bar_ODY_PEMX_MERGE_TIMER_CTL(a) 0x0 /* PF_BAR0 */
1738 #define busnum_ODY_PEMX_MERGE_TIMER_CTL(a) (a)
1739 #define arguments_ODY_PEMX_MERGE_TIMER_CTL(a) (a), -1, -1, -1
1740
1741 /**
1742 * Register (NCB) pem#_mpam_assoc_pc#
1743 *
1744 * PEM NCB Outbound Merge Count Register
1745 * This register is used to create a mapping of MPAM ID to one of eight sets of
1746 * hardware performance counters.
1747 *
1748 * This register is not accessible through ROM scripts; see SCR_WRITE32_S[ADDR].
1749 */
1750 union ody_pemx_mpam_assoc_pcx {
1751 uint64_t u;
1752 struct ody_pemx_mpam_assoc_pcx_s {
1753 uint64_t id : 3;
1754 uint64_t reserved_3_63 : 61;
1755 } s;
1756 /* struct ody_pemx_mpam_assoc_pcx_s cn; */
1757 };
1758 typedef union ody_pemx_mpam_assoc_pcx ody_pemx_mpam_assoc_pcx_t;
1759
1760 static inline uint64_t ODY_PEMX_MPAM_ASSOC_PCX(uint64_t a, uint64_t b) __attribute__ ((pure, always_inline));
ODY_PEMX_MPAM_ASSOC_PCX(uint64_t a,uint64_t b)1761 static inline uint64_t ODY_PEMX_MPAM_ASSOC_PCX(uint64_t a, uint64_t b)
1762 {
1763 if ((a <= 15) && (b <= 255))
1764 return 0x8e0000006000ll + 0x1000000000ll * ((a) & 0xf) + 8ll * ((b) & 0xff);
1765 __ody_csr_fatal("PEMX_MPAM_ASSOC_PCX", 2, a, b, 0, 0, 0, 0);
1766 }
1767
1768 #define typedef_ODY_PEMX_MPAM_ASSOC_PCX(a, b) ody_pemx_mpam_assoc_pcx_t
1769 #define bustype_ODY_PEMX_MPAM_ASSOC_PCX(a, b) CSR_TYPE_NCB
1770 #define basename_ODY_PEMX_MPAM_ASSOC_PCX(a, b) "PEMX_MPAM_ASSOC_PCX"
1771 #define device_bar_ODY_PEMX_MPAM_ASSOC_PCX(a, b) 0x0 /* PF_BAR0 */
1772 #define busnum_ODY_PEMX_MPAM_ASSOC_PCX(a, b) (a)
1773 #define arguments_ODY_PEMX_MPAM_ASSOC_PCX(a, b) (a), (b), -1, -1
1774
1775 /**
1776 * Register (NCB) pem#_msix_pba#
1777 *
1778 * PEM MSI-X Pending Bit Array Registers
1779 * This register is the MSI-X PBA table, the bit number is indexed by the PEM_INT_VEC_E enumeration.
1780 *
1781 * This register is not accessible through ROM scripts; see SCR_WRITE32_S[ADDR].
1782 *
1783 * This register is reset on core domain reset.
1784 */
1785 union ody_pemx_msix_pbax {
1786 uint64_t u;
1787 struct ody_pemx_msix_pbax_s {
1788 uint64_t pend : 64;
1789 } s;
1790 /* struct ody_pemx_msix_pbax_s cn; */
1791 };
1792 typedef union ody_pemx_msix_pbax ody_pemx_msix_pbax_t;
1793
1794 static inline uint64_t ODY_PEMX_MSIX_PBAX(uint64_t a, uint64_t b) __attribute__ ((pure, always_inline));
ODY_PEMX_MSIX_PBAX(uint64_t a,uint64_t b)1795 static inline uint64_t ODY_PEMX_MSIX_PBAX(uint64_t a, uint64_t b)
1796 {
1797 if ((a <= 15) && (b == 0))
1798 return 0x8e0f000f0000ll + 0x1000000000ll * ((a) & 0xf);
1799 __ody_csr_fatal("PEMX_MSIX_PBAX", 2, a, b, 0, 0, 0, 0);
1800 }
1801
1802 #define typedef_ODY_PEMX_MSIX_PBAX(a, b) ody_pemx_msix_pbax_t
1803 #define bustype_ODY_PEMX_MSIX_PBAX(a, b) CSR_TYPE_NCB
1804 #define basename_ODY_PEMX_MSIX_PBAX(a, b) "PEMX_MSIX_PBAX"
1805 #define device_bar_ODY_PEMX_MSIX_PBAX(a, b) 0x4 /* PF_BAR4 */
1806 #define busnum_ODY_PEMX_MSIX_PBAX(a, b) (a)
1807 #define arguments_ODY_PEMX_MSIX_PBAX(a, b) (a), (b), -1, -1
1808
1809 /**
1810 * Register (NCB) pem#_msix_vec#_addr
1811 *
1812 * PEM MSI-X Vector Table Address Registers
1813 * This register is the MSI-X vector table, indexed by the PEM_INT_VEC_E enumeration.
1814 *
1815 * This register is not accessible through ROM scripts; see SCR_WRITE32_S[ADDR].
1816 *
1817 * This register is reset on core domain reset.
1818 */
1819 union ody_pemx_msix_vecx_addr {
1820 uint64_t u;
1821 struct ody_pemx_msix_vecx_addr_s {
1822 uint64_t secvec : 1;
1823 uint64_t reserved_1 : 1;
1824 uint64_t addr : 51;
1825 uint64_t reserved_53_63 : 11;
1826 } s;
1827 /* struct ody_pemx_msix_vecx_addr_s cn; */
1828 };
1829 typedef union ody_pemx_msix_vecx_addr ody_pemx_msix_vecx_addr_t;
1830
1831 static inline uint64_t ODY_PEMX_MSIX_VECX_ADDR(uint64_t a, uint64_t b) __attribute__ ((pure, always_inline));
ODY_PEMX_MSIX_VECX_ADDR(uint64_t a,uint64_t b)1832 static inline uint64_t ODY_PEMX_MSIX_VECX_ADDR(uint64_t a, uint64_t b)
1833 {
1834 if ((a <= 15) && (b <= 11))
1835 return 0x8e0f00000000ll + 0x1000000000ll * ((a) & 0xf) + 0x10ll * ((b) & 0xf);
1836 __ody_csr_fatal("PEMX_MSIX_VECX_ADDR", 2, a, b, 0, 0, 0, 0);
1837 }
1838
1839 #define typedef_ODY_PEMX_MSIX_VECX_ADDR(a, b) ody_pemx_msix_vecx_addr_t
1840 #define bustype_ODY_PEMX_MSIX_VECX_ADDR(a, b) CSR_TYPE_NCB
1841 #define basename_ODY_PEMX_MSIX_VECX_ADDR(a, b) "PEMX_MSIX_VECX_ADDR"
1842 #define device_bar_ODY_PEMX_MSIX_VECX_ADDR(a, b) 0x4 /* PF_BAR4 */
1843 #define busnum_ODY_PEMX_MSIX_VECX_ADDR(a, b) (a)
1844 #define arguments_ODY_PEMX_MSIX_VECX_ADDR(a, b) (a), (b), -1, -1
1845
1846 /**
1847 * Register (NCB) pem#_msix_vec#_ctl
1848 *
1849 * PEM MSI-X Vector Table Control and Data Registers
1850 * This register is the MSI-X vector table, indexed by the PEM_INT_VEC_E enumeration.
1851 *
1852 * This register is not accessible through ROM scripts; see SCR_WRITE32_S[ADDR].
1853 *
1854 * This register is reset on core domain reset.
1855 */
1856 union ody_pemx_msix_vecx_ctl {
1857 uint64_t u;
1858 struct ody_pemx_msix_vecx_ctl_s {
1859 uint64_t data : 32;
1860 uint64_t mask : 1;
1861 uint64_t reserved_33_63 : 31;
1862 } s;
1863 /* struct ody_pemx_msix_vecx_ctl_s cn; */
1864 };
1865 typedef union ody_pemx_msix_vecx_ctl ody_pemx_msix_vecx_ctl_t;
1866
1867 static inline uint64_t ODY_PEMX_MSIX_VECX_CTL(uint64_t a, uint64_t b) __attribute__ ((pure, always_inline));
ODY_PEMX_MSIX_VECX_CTL(uint64_t a,uint64_t b)1868 static inline uint64_t ODY_PEMX_MSIX_VECX_CTL(uint64_t a, uint64_t b)
1869 {
1870 if ((a <= 15) && (b <= 11))
1871 return 0x8e0f00000008ll + 0x1000000000ll * ((a) & 0xf) + 0x10ll * ((b) & 0xf);
1872 __ody_csr_fatal("PEMX_MSIX_VECX_CTL", 2, a, b, 0, 0, 0, 0);
1873 }
1874
1875 #define typedef_ODY_PEMX_MSIX_VECX_CTL(a, b) ody_pemx_msix_vecx_ctl_t
1876 #define bustype_ODY_PEMX_MSIX_VECX_CTL(a, b) CSR_TYPE_NCB
1877 #define basename_ODY_PEMX_MSIX_VECX_CTL(a, b) "PEMX_MSIX_VECX_CTL"
1878 #define device_bar_ODY_PEMX_MSIX_VECX_CTL(a, b) 0x4 /* PF_BAR4 */
1879 #define busnum_ODY_PEMX_MSIX_VECX_CTL(a, b) (a)
1880 #define arguments_ODY_PEMX_MSIX_VECX_CTL(a, b) (a), (b), -1, -1
1881
1882 /**
1883 * Register (NCB) pem#_ncbi_ctl
1884 *
1885 * PEM Inbound NCBI Control Register
1886 * This register contains control bits for memory accesses targeting the NCBI bus.
1887 *
1888 * This register is not accessible through ROM scripts; see SCR_WRITE32_S[ADDR].
1889 *
1890 * This register is reset on core domain reset.
1891 */
1892 union ody_pemx_ncbi_ctl {
1893 uint64_t u;
1894 struct ody_pemx_ncbi_ctl_s {
1895 uint64_t reserved_0 : 1;
1896 uint64_t ld_cmd : 2;
1897 uint64_t reserved_3_6 : 4;
1898 uint64_t ptlp_ro_dis : 1;
1899 uint64_t ctlp_ro_dis : 1;
1900 uint64_t ntlp_ro_dis : 1;
1901 uint64_t clken_force : 1;
1902 uint64_t reserved_11_19 : 9;
1903 uint64_t bige : 1;
1904 uint64_t reserved_21_63 : 43;
1905 } s;
1906 struct ody_pemx_ncbi_ctl_cn {
1907 uint64_t reserved_0 : 1;
1908 uint64_t ld_cmd : 2;
1909 uint64_t reserved_3 : 1;
1910 uint64_t reserved_4 : 1;
1911 uint64_t reserved_5_6 : 2;
1912 uint64_t ptlp_ro_dis : 1;
1913 uint64_t ctlp_ro_dis : 1;
1914 uint64_t ntlp_ro_dis : 1;
1915 uint64_t clken_force : 1;
1916 uint64_t reserved_11_19 : 9;
1917 uint64_t bige : 1;
1918 uint64_t reserved_21_63 : 43;
1919 } cn;
1920 };
1921 typedef union ody_pemx_ncbi_ctl ody_pemx_ncbi_ctl_t;
1922
1923 static inline uint64_t ODY_PEMX_NCBI_CTL(uint64_t a) __attribute__ ((pure, always_inline));
ODY_PEMX_NCBI_CTL(uint64_t a)1924 static inline uint64_t ODY_PEMX_NCBI_CTL(uint64_t a)
1925 {
1926 if (a <= 15)
1927 return 0x8e0000000178ll + 0x1000000000ll * ((a) & 0xf);
1928 __ody_csr_fatal("PEMX_NCBI_CTL", 1, a, 0, 0, 0, 0, 0);
1929 }
1930
1931 #define typedef_ODY_PEMX_NCBI_CTL(a) ody_pemx_ncbi_ctl_t
1932 #define bustype_ODY_PEMX_NCBI_CTL(a) CSR_TYPE_NCB
1933 #define basename_ODY_PEMX_NCBI_CTL(a) "PEMX_NCBI_CTL"
1934 #define device_bar_ODY_PEMX_NCBI_CTL(a) 0x0 /* PF_BAR0 */
1935 #define busnum_ODY_PEMX_NCBI_CTL(a) (a)
1936 #define arguments_ODY_PEMX_NCBI_CTL(a) (a), -1, -1, -1
1937
1938 /**
1939 * Register (NCB) pem#_ncbi_tlp_credits
1940 *
1941 * PEM NCB Inbound TLP Credits Register
1942 * This register specifies the number of credits for use in moving TLPs. When this register is
1943 * written, the credit values are reset to the register value. This register is for diagnostic
1944 * use only, and should only be written when PEM()_CTL_STATUS[LNK_ENB] is clear.
1945 *
1946 * This register is accessible through ROM scripts; see SCR_WRITE32_S[ADDR].
1947 *
1948 * This register is reset on MAC reset.
1949 */
1950 union ody_pemx_ncbi_tlp_credits {
1951 uint64_t u;
1952 struct ody_pemx_ncbi_tlp_credits_s {
1953 uint64_t ncbi_p : 11;
1954 uint64_t ncbi_np : 10;
1955 uint64_t ncbi_cpl : 11;
1956 uint64_t reserved_32_63 : 32;
1957 } s;
1958 /* struct ody_pemx_ncbi_tlp_credits_s cn; */
1959 };
1960 typedef union ody_pemx_ncbi_tlp_credits ody_pemx_ncbi_tlp_credits_t;
1961
1962 static inline uint64_t ODY_PEMX_NCBI_TLP_CREDITS(uint64_t a) __attribute__ ((pure, always_inline));
ODY_PEMX_NCBI_TLP_CREDITS(uint64_t a)1963 static inline uint64_t ODY_PEMX_NCBI_TLP_CREDITS(uint64_t a)
1964 {
1965 if (a <= 15)
1966 return 0x8e0000000030ll + 0x1000000000ll * ((a) & 0xf);
1967 __ody_csr_fatal("PEMX_NCBI_TLP_CREDITS", 1, a, 0, 0, 0, 0, 0);
1968 }
1969
1970 #define typedef_ODY_PEMX_NCBI_TLP_CREDITS(a) ody_pemx_ncbi_tlp_credits_t
1971 #define bustype_ODY_PEMX_NCBI_TLP_CREDITS(a) CSR_TYPE_NCB
1972 #define basename_ODY_PEMX_NCBI_TLP_CREDITS(a) "PEMX_NCBI_TLP_CREDITS"
1973 #define device_bar_ODY_PEMX_NCBI_TLP_CREDITS(a) 0x0 /* PF_BAR0 */
1974 #define busnum_ODY_PEMX_NCBI_TLP_CREDITS(a) (a)
1975 #define arguments_ODY_PEMX_NCBI_TLP_CREDITS(a) (a), -1, -1, -1
1976
1977 /**
1978 * Register (NCB) pem#_ncbo_fifo_status
1979 *
1980 * PEM NCBO Offloading FIFO Status Register
1981 * This register contains status about the PEM NCBO offloading FIFOs.
1982 *
1983 * This register is not accessible through ROM scripts; see SCR_WRITE32_S[ADDR].
1984 *
1985 * This register is reset on core domain reset.
1986 */
1987 union ody_pemx_ncbo_fifo_status {
1988 uint64_t u;
1989 struct ody_pemx_ncbo_fifo_status_s {
1990 uint64_t p_volume : 8;
1991 uint64_t n_volume : 8;
1992 uint64_t csr_volume : 8;
1993 uint64_t reserved_24_63 : 40;
1994 } s;
1995 /* struct ody_pemx_ncbo_fifo_status_s cn; */
1996 };
1997 typedef union ody_pemx_ncbo_fifo_status ody_pemx_ncbo_fifo_status_t;
1998
1999 static inline uint64_t ODY_PEMX_NCBO_FIFO_STATUS(uint64_t a) __attribute__ ((pure, always_inline));
ODY_PEMX_NCBO_FIFO_STATUS(uint64_t a)2000 static inline uint64_t ODY_PEMX_NCBO_FIFO_STATUS(uint64_t a)
2001 {
2002 if (a <= 15)
2003 return 0x8e0000000138ll + 0x1000000000ll * ((a) & 0xf);
2004 __ody_csr_fatal("PEMX_NCBO_FIFO_STATUS", 1, a, 0, 0, 0, 0, 0);
2005 }
2006
2007 #define typedef_ODY_PEMX_NCBO_FIFO_STATUS(a) ody_pemx_ncbo_fifo_status_t
2008 #define bustype_ODY_PEMX_NCBO_FIFO_STATUS(a) CSR_TYPE_NCB
2009 #define basename_ODY_PEMX_NCBO_FIFO_STATUS(a) "PEMX_NCBO_FIFO_STATUS"
2010 #define device_bar_ODY_PEMX_NCBO_FIFO_STATUS(a) 0x0 /* PF_BAR0 */
2011 #define busnum_ODY_PEMX_NCBO_FIFO_STATUS(a) (a)
2012 #define arguments_ODY_PEMX_NCBO_FIFO_STATUS(a) (a), -1, -1, -1
2013
2014 /**
2015 * Register (NCB) pem#_ob_cmerge_limit
2016 *
2017 * PEM Outbound Completion Merge Limit Register
2018 * This register provides a mechanism to artificially limit the number of active
2019 * outbound completion merging stations to assist in code coverage.
2020 *
2021 * This register is not accessible through ROM scripts; see SCR_WRITE32_S[ADDR].
2022 *
2023 * This register is reset on core domain reset.
2024 */
2025 union ody_pemx_ob_cmerge_limit {
2026 uint64_t u;
2027 struct ody_pemx_ob_cmerge_limit_s {
2028 uint64_t limit : 4;
2029 uint64_t reserved_4_63 : 60;
2030 } s;
2031 /* struct ody_pemx_ob_cmerge_limit_s cn; */
2032 };
2033 typedef union ody_pemx_ob_cmerge_limit ody_pemx_ob_cmerge_limit_t;
2034
2035 static inline uint64_t ODY_PEMX_OB_CMERGE_LIMIT(uint64_t a) __attribute__ ((pure, always_inline));
ODY_PEMX_OB_CMERGE_LIMIT(uint64_t a)2036 static inline uint64_t ODY_PEMX_OB_CMERGE_LIMIT(uint64_t a)
2037 {
2038 if (a <= 15)
2039 return 0x8e0000000330ll + 0x1000000000ll * ((a) & 0xf);
2040 __ody_csr_fatal("PEMX_OB_CMERGE_LIMIT", 1, a, 0, 0, 0, 0, 0);
2041 }
2042
2043 #define typedef_ODY_PEMX_OB_CMERGE_LIMIT(a) ody_pemx_ob_cmerge_limit_t
2044 #define bustype_ODY_PEMX_OB_CMERGE_LIMIT(a) CSR_TYPE_NCB
2045 #define basename_ODY_PEMX_OB_CMERGE_LIMIT(a) "PEMX_OB_CMERGE_LIMIT"
2046 #define device_bar_ODY_PEMX_OB_CMERGE_LIMIT(a) 0x0 /* PF_BAR0 */
2047 #define busnum_ODY_PEMX_OB_CMERGE_LIMIT(a) (a)
2048 #define arguments_ODY_PEMX_OB_CMERGE_LIMIT(a) (a), -1, -1, -1
2049
2050 /**
2051 * Register (NCB) pem#_ob_cpl_fifo_status
2052 *
2053 * PEM Outbound Completion FIFO Status Register
2054 * This register contains status about the PEM Outbound Completion FIFOs.
2055 *
2056 * This register is not accessible through ROM scripts; see SCR_WRITE32_S[ADDR].
2057 *
2058 * This register is reset on core domain reset.
2059 */
2060 union ody_pemx_ob_cpl_fifo_status {
2061 uint64_t u;
2062 struct ody_pemx_ob_cpl_fifo_status_s {
2063 uint64_t pspi_c_volume : 8;
2064 uint64_t ebo_c_volume : 8;
2065 uint64_t ncbo_c_volume : 10;
2066 uint64_t reserved_26_63 : 38;
2067 } s;
2068 /* struct ody_pemx_ob_cpl_fifo_status_s cn; */
2069 };
2070 typedef union ody_pemx_ob_cpl_fifo_status ody_pemx_ob_cpl_fifo_status_t;
2071
2072 static inline uint64_t ODY_PEMX_OB_CPL_FIFO_STATUS(uint64_t a) __attribute__ ((pure, always_inline));
ODY_PEMX_OB_CPL_FIFO_STATUS(uint64_t a)2073 static inline uint64_t ODY_PEMX_OB_CPL_FIFO_STATUS(uint64_t a)
2074 {
2075 if (a <= 15)
2076 return 0x8e0000000170ll + 0x1000000000ll * ((a) & 0xf);
2077 __ody_csr_fatal("PEMX_OB_CPL_FIFO_STATUS", 1, a, 0, 0, 0, 0, 0);
2078 }
2079
2080 #define typedef_ODY_PEMX_OB_CPL_FIFO_STATUS(a) ody_pemx_ob_cpl_fifo_status_t
2081 #define bustype_ODY_PEMX_OB_CPL_FIFO_STATUS(a) CSR_TYPE_NCB
2082 #define basename_ODY_PEMX_OB_CPL_FIFO_STATUS(a) "PEMX_OB_CPL_FIFO_STATUS"
2083 #define device_bar_ODY_PEMX_OB_CPL_FIFO_STATUS(a) 0x0 /* PF_BAR0 */
2084 #define busnum_ODY_PEMX_OB_CPL_FIFO_STATUS(a) (a)
2085 #define arguments_ODY_PEMX_OB_CPL_FIFO_STATUS(a) (a), -1, -1, -1
2086
2087 /**
2088 * Register (NCB) pem#_ob_latency#_pc#
2089 *
2090 * PEM Outbound Latency Time Registers
2091 * This register resets on core domain reset. It measures the time portion
2092 * of the information set needed by software to calculate average outbound
2093 * read latency originating from the target bus.
2094 * Index {a} represents the TLP type and is enumerated by PEM_PERF_TLP_TYPE_E.
2095 * Index {b} represents a set of registers mapped by using PEM_MPAM_ASSOC_PC.
2096 *
2097 * When PEM_CTL_STATUS2.PERF_LATENCY_EN is clear, this register is clock gated.
2098 *
2099 * This register is not accessible through ROM scripts; see SCR_WRITE32_S[ADDR].
2100 */
2101 union ody_pemx_ob_latencyx_pcx {
2102 uint64_t u;
2103 struct ody_pemx_ob_latencyx_pcx_s {
2104 uint64_t latency : 64;
2105 } s;
2106 /* struct ody_pemx_ob_latencyx_pcx_s cn; */
2107 };
2108 typedef union ody_pemx_ob_latencyx_pcx ody_pemx_ob_latencyx_pcx_t;
2109
2110 static inline uint64_t ODY_PEMX_OB_LATENCYX_PCX(uint64_t a, uint64_t b, uint64_t c) __attribute__ ((pure, always_inline));
ODY_PEMX_OB_LATENCYX_PCX(uint64_t a,uint64_t b,uint64_t c)2111 static inline uint64_t ODY_PEMX_OB_LATENCYX_PCX(uint64_t a, uint64_t b, uint64_t c)
2112 {
2113 if ((a <= 15) && (b == 0) && (c <= 7))
2114 return 0x8e0000005700ll + 0x1000000000ll * ((a) & 0xf) + 0x20ll * ((c) & 0x7);
2115 __ody_csr_fatal("PEMX_OB_LATENCYX_PCX", 3, a, b, c, 0, 0, 0);
2116 }
2117
2118 #define typedef_ODY_PEMX_OB_LATENCYX_PCX(a, b, c) ody_pemx_ob_latencyx_pcx_t
2119 #define bustype_ODY_PEMX_OB_LATENCYX_PCX(a, b, c) CSR_TYPE_NCB
2120 #define basename_ODY_PEMX_OB_LATENCYX_PCX(a, b, c) "PEMX_OB_LATENCYX_PCX"
2121 #define device_bar_ODY_PEMX_OB_LATENCYX_PCX(a, b, c) 0x0 /* PF_BAR0 */
2122 #define busnum_ODY_PEMX_OB_LATENCYX_PCX(a, b, c) (a)
2123 #define arguments_ODY_PEMX_OB_LATENCYX_PCX(a, b, c) (a), (b), (c), -1
2124
2125 /**
2126 * Register (NCB) pem#_ob_reads#_pc#
2127 *
2128 * PEM Outbound Read Count Registers
2129 * This register resets on core domain reset. It measures the count portion
2130 * of the information set needed by software to calculate average outbound
2131 * read latency originating from the target bus.
2132 * Index {a} represents the TLP type and is enumerated by PEM_PERF_TLP_TYPE_E.
2133 * Index {b} represents a set of registers mapped by using PEM_MPAM_ASSOC_PC.
2134 *
2135 * This register is not accessible through ROM scripts; see SCR_WRITE32_S[ADDR].
2136 */
2137 union ody_pemx_ob_readsx_pcx {
2138 uint64_t u;
2139 struct ody_pemx_ob_readsx_pcx_s {
2140 uint64_t reads : 64;
2141 } s;
2142 /* struct ody_pemx_ob_readsx_pcx_s cn; */
2143 };
2144 typedef union ody_pemx_ob_readsx_pcx ody_pemx_ob_readsx_pcx_t;
2145
2146 static inline uint64_t ODY_PEMX_OB_READSX_PCX(uint64_t a, uint64_t b, uint64_t c) __attribute__ ((pure, always_inline));
ODY_PEMX_OB_READSX_PCX(uint64_t a,uint64_t b,uint64_t c)2147 static inline uint64_t ODY_PEMX_OB_READSX_PCX(uint64_t a, uint64_t b, uint64_t c)
2148 {
2149 if ((a <= 15) && (b == 0) && (c <= 7))
2150 return 0x8e0000005800ll + 0x1000000000ll * ((a) & 0xf) + 0x20ll * ((c) & 0x7);
2151 __ody_csr_fatal("PEMX_OB_READSX_PCX", 3, a, b, c, 0, 0, 0);
2152 }
2153
2154 #define typedef_ODY_PEMX_OB_READSX_PCX(a, b, c) ody_pemx_ob_readsx_pcx_t
2155 #define bustype_ODY_PEMX_OB_READSX_PCX(a, b, c) CSR_TYPE_NCB
2156 #define basename_ODY_PEMX_OB_READSX_PCX(a, b, c) "PEMX_OB_READSX_PCX"
2157 #define device_bar_ODY_PEMX_OB_READSX_PCX(a, b, c) 0x0 /* PF_BAR0 */
2158 #define busnum_ODY_PEMX_OB_READSX_PCX(a, b, c) (a)
2159 #define arguments_ODY_PEMX_OB_READSX_PCX(a, b, c) (a), (b), (c), -1
2160
2161 /**
2162 * Register (NCB) pem#_ob_tlp#_dwords_pc#
2163 *
2164 * PEM Outbound TLP DWORDS Registers
2165 * This register resets on core domain reset. Otherwise, it continuously accumulates
2166 * the number of DWORDS (including header overhead) in every outbound TLP received
2167 * from the target bus and headed to PCIe.
2168 * Index {a} represents the TLP type and is enumerated by PEM_PERF_TLP_TYPE_E.
2169 * Index {b} represents a set of registers mapped by using PEM_MPAM_ASSOC_PC.
2170 *
2171 * This register is not accessible through ROM scripts; see SCR_WRITE32_S[ADDR].
2172 */
2173 union ody_pemx_ob_tlpx_dwords_pcx {
2174 uint64_t u;
2175 struct ody_pemx_ob_tlpx_dwords_pcx_s {
2176 uint64_t tlp_dwords : 64;
2177 } s;
2178 /* struct ody_pemx_ob_tlpx_dwords_pcx_s cn; */
2179 };
2180 typedef union ody_pemx_ob_tlpx_dwords_pcx ody_pemx_ob_tlpx_dwords_pcx_t;
2181
2182 static inline uint64_t ODY_PEMX_OB_TLPX_DWORDS_PCX(uint64_t a, uint64_t b, uint64_t c) __attribute__ ((pure, always_inline));
ODY_PEMX_OB_TLPX_DWORDS_PCX(uint64_t a,uint64_t b,uint64_t c)2183 static inline uint64_t ODY_PEMX_OB_TLPX_DWORDS_PCX(uint64_t a, uint64_t b, uint64_t c)
2184 {
2185 if ((a <= 15) && (b <= 2) && (c <= 7))
2186 return 0x8e0000005600ll + 0x1000000000ll * ((a) & 0xf) + 8ll * ((b) & 0x3) + 0x20ll * ((c) & 0x7);
2187 __ody_csr_fatal("PEMX_OB_TLPX_DWORDS_PCX", 3, a, b, c, 0, 0, 0);
2188 }
2189
2190 #define typedef_ODY_PEMX_OB_TLPX_DWORDS_PCX(a, b, c) ody_pemx_ob_tlpx_dwords_pcx_t
2191 #define bustype_ODY_PEMX_OB_TLPX_DWORDS_PCX(a, b, c) CSR_TYPE_NCB
2192 #define basename_ODY_PEMX_OB_TLPX_DWORDS_PCX(a, b, c) "PEMX_OB_TLPX_DWORDS_PCX"
2193 #define device_bar_ODY_PEMX_OB_TLPX_DWORDS_PCX(a, b, c) 0x0 /* PF_BAR0 */
2194 #define busnum_ODY_PEMX_OB_TLPX_DWORDS_PCX(a, b, c) (a)
2195 #define arguments_ODY_PEMX_OB_TLPX_DWORDS_PCX(a, b, c) (a), (b), (c), -1
2196
2197 /**
2198 * Register (NCB) pem#_ob_tlp#_merges_pc#
2199 *
2200 * PEM NCB Outbound Merge Count Register
2201 * This register resets on core domain reset. Otherwise, it continuously tracks the
2202 * number of outbound transactions from NCBO that are part of a merging sequence.
2203 * Currently only NCBO transactions can be merged.
2204 * Index {a} represents the TLP type and is enumerated by PEM_PERF_TLP_TYPE_E.
2205 * Index {b} represents a set of registers mapped by using PEM_MPAM_ASSOC_PC.
2206 *
2207 * This register is not accessible through ROM scripts; see SCR_WRITE32_S[ADDR].
2208 */
2209 union ody_pemx_ob_tlpx_merges_pcx {
2210 uint64_t u;
2211 struct ody_pemx_ob_tlpx_merges_pcx_s {
2212 uint64_t count : 64;
2213 } s;
2214 /* struct ody_pemx_ob_tlpx_merges_pcx_s cn; */
2215 };
2216 typedef union ody_pemx_ob_tlpx_merges_pcx ody_pemx_ob_tlpx_merges_pcx_t;
2217
2218 static inline uint64_t ODY_PEMX_OB_TLPX_MERGES_PCX(uint64_t a, uint64_t b, uint64_t c) __attribute__ ((pure, always_inline));
ODY_PEMX_OB_TLPX_MERGES_PCX(uint64_t a,uint64_t b,uint64_t c)2219 static inline uint64_t ODY_PEMX_OB_TLPX_MERGES_PCX(uint64_t a, uint64_t b, uint64_t c)
2220 {
2221 if ((a <= 15) && (b <= 2) && (c <= 7))
2222 return 0x8e0000005900ll + 0x1000000000ll * ((a) & 0xf) + 8ll * ((b) & 0x3) + 0x20ll * ((c) & 0x7);
2223 __ody_csr_fatal("PEMX_OB_TLPX_MERGES_PCX", 3, a, b, c, 0, 0, 0);
2224 }
2225
2226 #define typedef_ODY_PEMX_OB_TLPX_MERGES_PCX(a, b, c) ody_pemx_ob_tlpx_merges_pcx_t
2227 #define bustype_ODY_PEMX_OB_TLPX_MERGES_PCX(a, b, c) CSR_TYPE_NCB
2228 #define basename_ODY_PEMX_OB_TLPX_MERGES_PCX(a, b, c) "PEMX_OB_TLPX_MERGES_PCX"
2229 #define device_bar_ODY_PEMX_OB_TLPX_MERGES_PCX(a, b, c) 0x0 /* PF_BAR0 */
2230 #define busnum_ODY_PEMX_OB_TLPX_MERGES_PCX(a, b, c) (a)
2231 #define arguments_ODY_PEMX_OB_TLPX_MERGES_PCX(a, b, c) (a), (b), (c), -1
2232
2233 /**
2234 * Register (NCB) pem#_ob_tlp#_pc#
2235 *
2236 * PEM Outbound TLP Count Registers
2237 * This register resets on core domain reset. Otherwise, it continuously increments
2238 * on every outbound TLP received from the target bus and headed to PCIe.
2239 * Index {a} represents the TLP type and is enumerated by PEM_PERF_TLP_TYPE_E.
2240 * Index {b} represents a set of registers mapped by using PEM_MPAM_ASSOC_PC.
2241 *
2242 * This register is not accessible through ROM scripts; see SCR_WRITE32_S[ADDR].
2243 */
2244 union ody_pemx_ob_tlpx_pcx {
2245 uint64_t u;
2246 struct ody_pemx_ob_tlpx_pcx_s {
2247 uint64_t count : 64;
2248 } s;
2249 /* struct ody_pemx_ob_tlpx_pcx_s cn; */
2250 };
2251 typedef union ody_pemx_ob_tlpx_pcx ody_pemx_ob_tlpx_pcx_t;
2252
2253 static inline uint64_t ODY_PEMX_OB_TLPX_PCX(uint64_t a, uint64_t b, uint64_t c) __attribute__ ((pure, always_inline));
ODY_PEMX_OB_TLPX_PCX(uint64_t a,uint64_t b,uint64_t c)2254 static inline uint64_t ODY_PEMX_OB_TLPX_PCX(uint64_t a, uint64_t b, uint64_t c)
2255 {
2256 if ((a <= 15) && (b <= 2) && (c <= 7))
2257 return 0x8e0000005500ll + 0x1000000000ll * ((a) & 0xf) + 8ll * ((b) & 0x3) + 0x20ll * ((c) & 0x7);
2258 __ody_csr_fatal("PEMX_OB_TLPX_PCX", 3, a, b, c, 0, 0, 0);
2259 }
2260
2261 #define typedef_ODY_PEMX_OB_TLPX_PCX(a, b, c) ody_pemx_ob_tlpx_pcx_t
2262 #define bustype_ODY_PEMX_OB_TLPX_PCX(a, b, c) CSR_TYPE_NCB
2263 #define basename_ODY_PEMX_OB_TLPX_PCX(a, b, c) "PEMX_OB_TLPX_PCX"
2264 #define device_bar_ODY_PEMX_OB_TLPX_PCX(a, b, c) 0x0 /* PF_BAR0 */
2265 #define busnum_ODY_PEMX_OB_TLPX_PCX(a, b, c) (a)
2266 #define arguments_ODY_PEMX_OB_TLPX_PCX(a, b, c) (a), (b), (c), -1
2267
2268 /**
2269 * Register (NCB) pem#_on
2270 *
2271 * PEM On Status Register
2272 * This register indicates that PEM is configured and ready.
2273 *
2274 * This register is accessible through ROM scripts; see SCR_WRITE32_S[ADDR].
2275 *
2276 * This register is reset on cold reset.
2277 */
2278 union ody_pemx_on {
2279 uint64_t u;
2280 struct ody_pemx_on_s {
2281 uint64_t pemon : 1;
2282 uint64_t pemoor : 1;
2283 uint64_t aclr : 1;
2284 uint64_t reserved_3_63 : 61;
2285 } s;
2286 /* struct ody_pemx_on_s cn; */
2287 };
2288 typedef union ody_pemx_on ody_pemx_on_t;
2289
2290 static inline uint64_t ODY_PEMX_ON(uint64_t a) __attribute__ ((pure, always_inline));
ODY_PEMX_ON(uint64_t a)2291 static inline uint64_t ODY_PEMX_ON(uint64_t a)
2292 {
2293 if (a <= 15)
2294 return 0x8e00000000e0ll + 0x1000000000ll * ((a) & 0xf);
2295 __ody_csr_fatal("PEMX_ON", 1, a, 0, 0, 0, 0, 0);
2296 }
2297
2298 #define typedef_ODY_PEMX_ON(a) ody_pemx_on_t
2299 #define bustype_ODY_PEMX_ON(a) CSR_TYPE_NCB
2300 #define basename_ODY_PEMX_ON(a) "PEMX_ON"
2301 #define device_bar_ODY_PEMX_ON(a) 0x0 /* PF_BAR0 */
2302 #define busnum_ODY_PEMX_ON(a) (a)
2303 #define arguments_ODY_PEMX_ON(a) (a), -1, -1, -1
2304
2305 /**
2306 * Register (NCB) pem#_override_pclk_rate
2307 *
2308 * PEM Reset Mac Register
2309 * This register provides a mechanism to override the divide ratio pemx__div_max_pclk_ratio
2310 * to modify the PCLK rate
2311 *
2312 * This register is accessible through ROM scripts; see SCR_WRITE32_S[ADDR].
2313 *
2314 * This register is reset on cold reset.
2315 */
2316 union ody_pemx_override_pclk_rate {
2317 uint64_t u;
2318 struct ody_pemx_override_pclk_rate_s {
2319 uint64_t override_div_pclk_val : 7;
2320 uint64_t override_div_pclk_en : 1;
2321 uint64_t reserved_8_63 : 56;
2322 } s;
2323 /* struct ody_pemx_override_pclk_rate_s cn; */
2324 };
2325 typedef union ody_pemx_override_pclk_rate ody_pemx_override_pclk_rate_t;
2326
2327 static inline uint64_t ODY_PEMX_OVERRIDE_PCLK_RATE(uint64_t a) __attribute__ ((pure, always_inline));
ODY_PEMX_OVERRIDE_PCLK_RATE(uint64_t a)2328 static inline uint64_t ODY_PEMX_OVERRIDE_PCLK_RATE(uint64_t a)
2329 {
2330 if (a <= 15)
2331 return 0x8e00000002a0ll + 0x1000000000ll * ((a) & 0xf);
2332 __ody_csr_fatal("PEMX_OVERRIDE_PCLK_RATE", 1, a, 0, 0, 0, 0, 0);
2333 }
2334
2335 #define typedef_ODY_PEMX_OVERRIDE_PCLK_RATE(a) ody_pemx_override_pclk_rate_t
2336 #define bustype_ODY_PEMX_OVERRIDE_PCLK_RATE(a) CSR_TYPE_NCB
2337 #define basename_ODY_PEMX_OVERRIDE_PCLK_RATE(a) "PEMX_OVERRIDE_PCLK_RATE"
2338 #define device_bar_ODY_PEMX_OVERRIDE_PCLK_RATE(a) 0x0 /* PF_BAR0 */
2339 #define busnum_ODY_PEMX_OVERRIDE_PCLK_RATE(a) (a)
2340 #define arguments_ODY_PEMX_OVERRIDE_PCLK_RATE(a) (a), -1, -1, -1
2341
2342 /**
2343 * Register (NCB) pem#_p2n_bar2_start
2344 *
2345 * PEM PCIe RC BAR2 Start Register
2346 * This register specifies the starting address for memory requests that are to be forwarded to
2347 * NCB/EBUS in RC mode. In EP mode, the standard PCIe config space BAR registers are used, and
2348 * this register is ignored.
2349 *
2350 * This register is not accessible through ROM scripts; see SCR_WRITE32_S[ADDR].
2351 *
2352 * This register is reset on core domain reset.
2353 */
2354 union ody_pemx_p2n_bar2_start {
2355 uint64_t u;
2356 struct ody_pemx_p2n_bar2_start_s {
2357 uint64_t reserved_0_19 : 20;
2358 uint64_t addr : 44;
2359 } s;
2360 /* struct ody_pemx_p2n_bar2_start_s cn; */
2361 };
2362 typedef union ody_pemx_p2n_bar2_start ody_pemx_p2n_bar2_start_t;
2363
2364 static inline uint64_t ODY_PEMX_P2N_BAR2_START(uint64_t a) __attribute__ ((pure, always_inline));
ODY_PEMX_P2N_BAR2_START(uint64_t a)2365 static inline uint64_t ODY_PEMX_P2N_BAR2_START(uint64_t a)
2366 {
2367 if (a <= 15)
2368 return 0x8e0000000150ll + 0x1000000000ll * ((a) & 0xf);
2369 __ody_csr_fatal("PEMX_P2N_BAR2_START", 1, a, 0, 0, 0, 0, 0);
2370 }
2371
2372 #define typedef_ODY_PEMX_P2N_BAR2_START(a) ody_pemx_p2n_bar2_start_t
2373 #define bustype_ODY_PEMX_P2N_BAR2_START(a) CSR_TYPE_NCB
2374 #define basename_ODY_PEMX_P2N_BAR2_START(a) "PEMX_P2N_BAR2_START"
2375 #define device_bar_ODY_PEMX_P2N_BAR2_START(a) 0x0 /* PF_BAR0 */
2376 #define busnum_ODY_PEMX_P2N_BAR2_START(a) (a)
2377 #define arguments_ODY_PEMX_P2N_BAR2_START(a) (a), -1, -1, -1
2378
2379 /**
2380 * Register (NCB) pem#_p2n_bar4_start
2381 *
2382 * PEM PCIe RC BAR4 Start Register
2383 * This register specifies the starting address for memory requests that are to be forwarded to
2384 * NCB/EBUS in RC mode. In EP mode, the standard PCIe config space BAR registers are used, and
2385 * this register is ignored.
2386 *
2387 * This register is not accessible through ROM scripts; see SCR_WRITE32_S[ADDR].
2388 *
2389 * This register is reset on core domain reset.
2390 */
2391 union ody_pemx_p2n_bar4_start {
2392 uint64_t u;
2393 struct ody_pemx_p2n_bar4_start_s {
2394 uint64_t reserved_0_25 : 26;
2395 uint64_t addr : 38;
2396 } s;
2397 /* struct ody_pemx_p2n_bar4_start_s cn; */
2398 };
2399 typedef union ody_pemx_p2n_bar4_start ody_pemx_p2n_bar4_start_t;
2400
2401 static inline uint64_t ODY_PEMX_P2N_BAR4_START(uint64_t a) __attribute__ ((pure, always_inline));
ODY_PEMX_P2N_BAR4_START(uint64_t a)2402 static inline uint64_t ODY_PEMX_P2N_BAR4_START(uint64_t a)
2403 {
2404 if (a <= 15)
2405 return 0x8e0000000148ll + 0x1000000000ll * ((a) & 0xf);
2406 __ody_csr_fatal("PEMX_P2N_BAR4_START", 1, a, 0, 0, 0, 0, 0);
2407 }
2408
2409 #define typedef_ODY_PEMX_P2N_BAR4_START(a) ody_pemx_p2n_bar4_start_t
2410 #define bustype_ODY_PEMX_P2N_BAR4_START(a) CSR_TYPE_NCB
2411 #define basename_ODY_PEMX_P2N_BAR4_START(a) "PEMX_P2N_BAR4_START"
2412 #define device_bar_ODY_PEMX_P2N_BAR4_START(a) 0x0 /* PF_BAR0 */
2413 #define busnum_ODY_PEMX_P2N_BAR4_START(a) (a)
2414 #define arguments_ODY_PEMX_P2N_BAR4_START(a) (a), -1, -1, -1
2415
2416 /**
2417 * Register (NCB) pem#_pemoor_int
2418 *
2419 * PEM PEMOOR Interrupt Register
2420 * This register contains the interrupt bits for PEMOOR.
2421 *
2422 * This register is not accessible through ROM scripts; see SCR_WRITE32_S[ADDR].
2423 *
2424 * This register is reset on core domain reset.
2425 */
2426 union ody_pemx_pemoor_int {
2427 uint64_t u;
2428 struct ody_pemx_pemoor_int_s {
2429 uint64_t pemoor : 1;
2430 uint64_t reserved_1_63 : 63;
2431 } s;
2432 /* struct ody_pemx_pemoor_int_s cn; */
2433 };
2434 typedef union ody_pemx_pemoor_int ody_pemx_pemoor_int_t;
2435
2436 static inline uint64_t ODY_PEMX_PEMOOR_INT(uint64_t a) __attribute__ ((pure, always_inline));
ODY_PEMX_PEMOOR_INT(uint64_t a)2437 static inline uint64_t ODY_PEMX_PEMOOR_INT(uint64_t a)
2438 {
2439 if (a <= 15)
2440 return 0x8e0000000350ll + 0x1000000000ll * ((a) & 0xf);
2441 __ody_csr_fatal("PEMX_PEMOOR_INT", 1, a, 0, 0, 0, 0, 0);
2442 }
2443
2444 #define typedef_ODY_PEMX_PEMOOR_INT(a) ody_pemx_pemoor_int_t
2445 #define bustype_ODY_PEMX_PEMOOR_INT(a) CSR_TYPE_NCB
2446 #define basename_ODY_PEMX_PEMOOR_INT(a) "PEMX_PEMOOR_INT"
2447 #define device_bar_ODY_PEMX_PEMOOR_INT(a) 0x0 /* PF_BAR0 */
2448 #define busnum_ODY_PEMX_PEMOOR_INT(a) (a)
2449 #define arguments_ODY_PEMX_PEMOOR_INT(a) (a), -1, -1, -1
2450
2451 /**
2452 * Register (NCB) pem#_pemoor_int_ena_w1c
2453 *
2454 * PEM PEMOOR Interrupt Enable Clear Register
2455 * This register clears interrupt enable bits.
2456 */
2457 union ody_pemx_pemoor_int_ena_w1c {
2458 uint64_t u;
2459 struct ody_pemx_pemoor_int_ena_w1c_s {
2460 uint64_t pemoor : 1;
2461 uint64_t reserved_1_63 : 63;
2462 } s;
2463 /* struct ody_pemx_pemoor_int_ena_w1c_s cn; */
2464 };
2465 typedef union ody_pemx_pemoor_int_ena_w1c ody_pemx_pemoor_int_ena_w1c_t;
2466
2467 static inline uint64_t ODY_PEMX_PEMOOR_INT_ENA_W1C(uint64_t a) __attribute__ ((pure, always_inline));
ODY_PEMX_PEMOOR_INT_ENA_W1C(uint64_t a)2468 static inline uint64_t ODY_PEMX_PEMOOR_INT_ENA_W1C(uint64_t a)
2469 {
2470 if (a <= 15)
2471 return 0x8e0000000360ll + 0x1000000000ll * ((a) & 0xf);
2472 __ody_csr_fatal("PEMX_PEMOOR_INT_ENA_W1C", 1, a, 0, 0, 0, 0, 0);
2473 }
2474
2475 #define typedef_ODY_PEMX_PEMOOR_INT_ENA_W1C(a) ody_pemx_pemoor_int_ena_w1c_t
2476 #define bustype_ODY_PEMX_PEMOOR_INT_ENA_W1C(a) CSR_TYPE_NCB
2477 #define basename_ODY_PEMX_PEMOOR_INT_ENA_W1C(a) "PEMX_PEMOOR_INT_ENA_W1C"
2478 #define device_bar_ODY_PEMX_PEMOOR_INT_ENA_W1C(a) 0x0 /* PF_BAR0 */
2479 #define busnum_ODY_PEMX_PEMOOR_INT_ENA_W1C(a) (a)
2480 #define arguments_ODY_PEMX_PEMOOR_INT_ENA_W1C(a) (a), -1, -1, -1
2481
2482 /**
2483 * Register (NCB) pem#_pemoor_int_ena_w1s
2484 *
2485 * PEM PEMOOR Interrupt Enable Set Register
2486 * This register sets interrupt enable bits.
2487 */
2488 union ody_pemx_pemoor_int_ena_w1s {
2489 uint64_t u;
2490 struct ody_pemx_pemoor_int_ena_w1s_s {
2491 uint64_t pemoor : 1;
2492 uint64_t reserved_1_63 : 63;
2493 } s;
2494 /* struct ody_pemx_pemoor_int_ena_w1s_s cn; */
2495 };
2496 typedef union ody_pemx_pemoor_int_ena_w1s ody_pemx_pemoor_int_ena_w1s_t;
2497
2498 static inline uint64_t ODY_PEMX_PEMOOR_INT_ENA_W1S(uint64_t a) __attribute__ ((pure, always_inline));
ODY_PEMX_PEMOOR_INT_ENA_W1S(uint64_t a)2499 static inline uint64_t ODY_PEMX_PEMOOR_INT_ENA_W1S(uint64_t a)
2500 {
2501 if (a <= 15)
2502 return 0x8e0000000368ll + 0x1000000000ll * ((a) & 0xf);
2503 __ody_csr_fatal("PEMX_PEMOOR_INT_ENA_W1S", 1, a, 0, 0, 0, 0, 0);
2504 }
2505
2506 #define typedef_ODY_PEMX_PEMOOR_INT_ENA_W1S(a) ody_pemx_pemoor_int_ena_w1s_t
2507 #define bustype_ODY_PEMX_PEMOOR_INT_ENA_W1S(a) CSR_TYPE_NCB
2508 #define basename_ODY_PEMX_PEMOOR_INT_ENA_W1S(a) "PEMX_PEMOOR_INT_ENA_W1S"
2509 #define device_bar_ODY_PEMX_PEMOOR_INT_ENA_W1S(a) 0x0 /* PF_BAR0 */
2510 #define busnum_ODY_PEMX_PEMOOR_INT_ENA_W1S(a) (a)
2511 #define arguments_ODY_PEMX_PEMOOR_INT_ENA_W1S(a) (a), -1, -1, -1
2512
2513 /**
2514 * Register (NCB) pem#_pemoor_int_w1s
2515 *
2516 * PEM PEMOOR Interrupt Set Register
2517 * This register sets interrupt bits.
2518 */
2519 union ody_pemx_pemoor_int_w1s {
2520 uint64_t u;
2521 struct ody_pemx_pemoor_int_w1s_s {
2522 uint64_t pemoor : 1;
2523 uint64_t reserved_1_63 : 63;
2524 } s;
2525 /* struct ody_pemx_pemoor_int_w1s_s cn; */
2526 };
2527 typedef union ody_pemx_pemoor_int_w1s ody_pemx_pemoor_int_w1s_t;
2528
2529 static inline uint64_t ODY_PEMX_PEMOOR_INT_W1S(uint64_t a) __attribute__ ((pure, always_inline));
ODY_PEMX_PEMOOR_INT_W1S(uint64_t a)2530 static inline uint64_t ODY_PEMX_PEMOOR_INT_W1S(uint64_t a)
2531 {
2532 if (a <= 15)
2533 return 0x8e0000000358ll + 0x1000000000ll * ((a) & 0xf);
2534 __ody_csr_fatal("PEMX_PEMOOR_INT_W1S", 1, a, 0, 0, 0, 0, 0);
2535 }
2536
2537 #define typedef_ODY_PEMX_PEMOOR_INT_W1S(a) ody_pemx_pemoor_int_w1s_t
2538 #define bustype_ODY_PEMX_PEMOOR_INT_W1S(a) CSR_TYPE_NCB
2539 #define basename_ODY_PEMX_PEMOOR_INT_W1S(a) "PEMX_PEMOOR_INT_W1S"
2540 #define device_bar_ODY_PEMX_PEMOOR_INT_W1S(a) 0x0 /* PF_BAR0 */
2541 #define busnum_ODY_PEMX_PEMOOR_INT_W1S(a) (a)
2542 #define arguments_ODY_PEMX_PEMOOR_INT_W1S(a) (a), -1, -1, -1
2543
2544 /**
2545 * Register (NCB) pem#_perr_status
2546 *
2547 * PEM Parity Error Status Register
2548 * This register contains indications of parity errors detected inside PEM.
2549 *
2550 * This register is not accessible through ROM scripts; see SCR_WRITE32_S[ADDR].
2551 *
2552 * This register is reset on core domain reset.
2553 */
2554 union ody_pemx_perr_status {
2555 uint64_t u;
2556 struct ody_pemx_perr_status_s {
2557 uint64_t tx_perr : 1;
2558 uint64_t rx_perr : 1;
2559 uint64_t dbe : 1;
2560 uint64_t rasdp : 1;
2561 uint64_t mac_txfe_perr : 1;
2562 uint64_t mac_txbe_perr : 1;
2563 uint64_t mac_rx_perr : 1;
2564 uint64_t reserved_7_63 : 57;
2565 } s;
2566 /* struct ody_pemx_perr_status_s cn; */
2567 };
2568 typedef union ody_pemx_perr_status ody_pemx_perr_status_t;
2569
2570 static inline uint64_t ODY_PEMX_PERR_STATUS(uint64_t a) __attribute__ ((pure, always_inline));
ODY_PEMX_PERR_STATUS(uint64_t a)2571 static inline uint64_t ODY_PEMX_PERR_STATUS(uint64_t a)
2572 {
2573 if (a <= 15)
2574 return 0x8e00000001d8ll + 0x1000000000ll * ((a) & 0xf);
2575 __ody_csr_fatal("PEMX_PERR_STATUS", 1, a, 0, 0, 0, 0, 0);
2576 }
2577
2578 #define typedef_ODY_PEMX_PERR_STATUS(a) ody_pemx_perr_status_t
2579 #define bustype_ODY_PEMX_PERR_STATUS(a) CSR_TYPE_NCB
2580 #define basename_ODY_PEMX_PERR_STATUS(a) "PEMX_PERR_STATUS"
2581 #define device_bar_ODY_PEMX_PERR_STATUS(a) 0x0 /* PF_BAR0 */
2582 #define busnum_ODY_PEMX_PERR_STATUS(a) (a)
2583 #define arguments_ODY_PEMX_PERR_STATUS(a) (a), -1, -1, -1
2584
2585 /**
2586 * Register (NCB) pem#_pf#_cs#_pfcfg#
2587 *
2588 * PEM PCIe Direct Config PF Registers
2589 * This register is used to modify PF configuration space. It can only be accessed
2590 * using 32-bit instructions (either [DATA_LO] or [DATA_HI] but not both
2591 * simultaneously.) Although an unsupported 64-bit access attempt will have
2592 * unpredictable results, it will not cause a hang situation.
2593 *
2594 * Index {c} is the register number, which is the configuration offset divided by 0x2;
2595 * e.g. index 0 is either for PCIERC_CMD/PCIEEP_CMD (DATA_HI) or PCIERC_ID/PCIEEP_ID (DATA_LO).
2596 *
2597 * This register is accessible through ROM scripts; see SCR_WRITE32_S[ADDR].
2598 *
2599 * This register is reset on MAC reset.
2600 */
2601 union ody_pemx_pfx_csx_pfcfgx {
2602 uint64_t u;
2603 struct ody_pemx_pfx_csx_pfcfgx_s {
2604 uint64_t data_lo : 32;
2605 uint64_t data_hi : 32;
2606 } s;
2607 /* struct ody_pemx_pfx_csx_pfcfgx_s cn; */
2608 };
2609 typedef union ody_pemx_pfx_csx_pfcfgx ody_pemx_pfx_csx_pfcfgx_t;
2610
2611 static inline uint64_t ODY_PEMX_PFX_CSX_PFCFGX(uint64_t a, uint64_t b, uint64_t c, uint64_t d) __attribute__ ((pure, always_inline));
ODY_PEMX_PFX_CSX_PFCFGX(uint64_t a,uint64_t b,uint64_t c,uint64_t d)2612 static inline uint64_t ODY_PEMX_PFX_CSX_PFCFGX(uint64_t a, uint64_t b, uint64_t c, uint64_t d)
2613 {
2614 if ((a <= 15) && (b == 0) && (c <= 1) && (d <= 511))
2615 return 0x8e0000008000ll + 0x1000000000ll * ((a) & 0xf) + 0x10000ll * ((c) & 0x1) + 8ll * ((d) & 0x1ff);
2616 __ody_csr_fatal("PEMX_PFX_CSX_PFCFGX", 4, a, b, c, d, 0, 0);
2617 }
2618
2619 #define typedef_ODY_PEMX_PFX_CSX_PFCFGX(a, b, c, d) ody_pemx_pfx_csx_pfcfgx_t
2620 #define bustype_ODY_PEMX_PFX_CSX_PFCFGX(a, b, c, d) CSR_TYPE_NCB
2621 #define basename_ODY_PEMX_PFX_CSX_PFCFGX(a, b, c, d) "PEMX_PFX_CSX_PFCFGX"
2622 #define device_bar_ODY_PEMX_PFX_CSX_PFCFGX(a, b, c, d) 0x0 /* PF_BAR0 */
2623 #define busnum_ODY_PEMX_PFX_CSX_PFCFGX(a, b, c, d) (a)
2624 #define arguments_ODY_PEMX_PFX_CSX_PFCFGX(a, b, c, d) (a), (b), (c), (d)
2625
2626 /**
2627 * Register (NCB) pem#_pf#_ctl_status
2628 *
2629 * PEM PF Control Status Register
2630 * This is a general PF control and status register of the PEM.
2631 * There is a register for each PF.
2632 *
2633 * This register is accessible through ROM scripts; see SCR_WRITE32_S[ADDR].
2634 *
2635 * This register is reset on MAC reset.
2636 */
2637 union ody_pemx_pfx_ctl_status {
2638 uint64_t u;
2639 struct ody_pemx_pfx_ctl_status_s {
2640 uint64_t pm_dst : 3;
2641 uint64_t pf_flr_en : 1;
2642 uint64_t ob_p_cmd : 1;
2643 uint64_t reserved_5_63 : 59;
2644 } s;
2645 /* struct ody_pemx_pfx_ctl_status_s cn; */
2646 };
2647 typedef union ody_pemx_pfx_ctl_status ody_pemx_pfx_ctl_status_t;
2648
2649 static inline uint64_t ODY_PEMX_PFX_CTL_STATUS(uint64_t a, uint64_t b) __attribute__ ((pure, always_inline));
ODY_PEMX_PFX_CTL_STATUS(uint64_t a,uint64_t b)2650 static inline uint64_t ODY_PEMX_PFX_CTL_STATUS(uint64_t a, uint64_t b)
2651 {
2652 if ((a <= 15) && (b == 0))
2653 return 0x8e0000000800ll + 0x1000000000ll * ((a) & 0xf);
2654 __ody_csr_fatal("PEMX_PFX_CTL_STATUS", 2, a, b, 0, 0, 0, 0);
2655 }
2656
2657 #define typedef_ODY_PEMX_PFX_CTL_STATUS(a, b) ody_pemx_pfx_ctl_status_t
2658 #define bustype_ODY_PEMX_PFX_CTL_STATUS(a, b) CSR_TYPE_NCB
2659 #define basename_ODY_PEMX_PFX_CTL_STATUS(a, b) "PEMX_PFX_CTL_STATUS"
2660 #define device_bar_ODY_PEMX_PFX_CTL_STATUS(a, b) 0x0 /* PF_BAR0 */
2661 #define busnum_ODY_PEMX_PFX_CTL_STATUS(a, b) (a)
2662 #define arguments_ODY_PEMX_PFX_CTL_STATUS(a, b) (a), (b), -1, -1
2663
2664 /**
2665 * Register (NCB) pem#_pspi_tlp_credits
2666 *
2667 * PEM NCB Inbound TLP Credits Register
2668 * This register specifies the number of credits for use in moving TLPs. When this register is
2669 * written, the credit values are reset to the register value. This register is for diagnostic
2670 * use only, and should only be written when PEM()_CTL_STATUS[LNK_ENB] is clear.
2671 *
2672 * This register is accessible through ROM scripts; see SCR_WRITE32_S[ADDR].
2673 *
2674 * This register is reset on MAC reset.
2675 */
2676 union ody_pemx_pspi_tlp_credits {
2677 uint64_t u;
2678 struct ody_pemx_pspi_tlp_credits_s {
2679 uint64_t reserved_0_10 : 11;
2680 uint64_t pspi_np : 10;
2681 uint64_t reserved_21_63 : 43;
2682 } s;
2683 /* struct ody_pemx_pspi_tlp_credits_s cn; */
2684 };
2685 typedef union ody_pemx_pspi_tlp_credits ody_pemx_pspi_tlp_credits_t;
2686
2687 static inline uint64_t ODY_PEMX_PSPI_TLP_CREDITS(uint64_t a) __attribute__ ((pure, always_inline));
ODY_PEMX_PSPI_TLP_CREDITS(uint64_t a)2688 static inline uint64_t ODY_PEMX_PSPI_TLP_CREDITS(uint64_t a)
2689 {
2690 if (a <= 15)
2691 return 0x8e0000000038ll + 0x1000000000ll * ((a) & 0xf);
2692 __ody_csr_fatal("PEMX_PSPI_TLP_CREDITS", 1, a, 0, 0, 0, 0, 0);
2693 }
2694
2695 #define typedef_ODY_PEMX_PSPI_TLP_CREDITS(a) ody_pemx_pspi_tlp_credits_t
2696 #define bustype_ODY_PEMX_PSPI_TLP_CREDITS(a) CSR_TYPE_NCB
2697 #define basename_ODY_PEMX_PSPI_TLP_CREDITS(a) "PEMX_PSPI_TLP_CREDITS"
2698 #define device_bar_ODY_PEMX_PSPI_TLP_CREDITS(a) 0x0 /* PF_BAR0 */
2699 #define busnum_ODY_PEMX_PSPI_TLP_CREDITS(a) (a)
2700 #define arguments_ODY_PEMX_PSPI_TLP_CREDITS(a) (a), -1, -1, -1
2701
2702 /**
2703 * Register (NCB) pem#_ptm_ctl
2704 *
2705 * PEM Miscellaneous Control Register
2706 * This register contains precision timer control bits.
2707 *
2708 * This register is not accessible through ROM scripts; see SCR_WRITE32_S[ADDR].
2709 *
2710 * This register is reset on cold reset.
2711 */
2712 union ody_pemx_ptm_ctl {
2713 uint64_t u;
2714 struct ody_pemx_ptm_ctl_s {
2715 uint64_t ptm_mstr_adj : 8;
2716 uint64_t ptm_mstr_sel : 1;
2717 uint64_t ptm_auto_load : 1;
2718 uint64_t ptm_lcl_cap : 1;
2719 uint64_t ptm_auto_update : 1;
2720 uint64_t reserved_12_63 : 52;
2721 } s;
2722 /* struct ody_pemx_ptm_ctl_s cn; */
2723 };
2724 typedef union ody_pemx_ptm_ctl ody_pemx_ptm_ctl_t;
2725
2726 static inline uint64_t ODY_PEMX_PTM_CTL(uint64_t a) __attribute__ ((pure, always_inline));
ODY_PEMX_PTM_CTL(uint64_t a)2727 static inline uint64_t ODY_PEMX_PTM_CTL(uint64_t a)
2728 {
2729 if (a <= 15)
2730 return 0x8e0000000098ll + 0x1000000000ll * ((a) & 0xf);
2731 __ody_csr_fatal("PEMX_PTM_CTL", 1, a, 0, 0, 0, 0, 0);
2732 }
2733
2734 #define typedef_ODY_PEMX_PTM_CTL(a) ody_pemx_ptm_ctl_t
2735 #define bustype_ODY_PEMX_PTM_CTL(a) CSR_TYPE_NCB
2736 #define basename_ODY_PEMX_PTM_CTL(a) "PEMX_PTM_CTL"
2737 #define device_bar_ODY_PEMX_PTM_CTL(a) 0x0 /* PF_BAR0 */
2738 #define busnum_ODY_PEMX_PTM_CTL(a) (a)
2739 #define arguments_ODY_PEMX_PTM_CTL(a) (a), -1, -1, -1
2740
2741 /**
2742 * Register (NCB) pem#_ptm_lcl_time
2743 *
2744 * PEM PTM Time Register
2745 * This register contains the PTM synchronized local time value.
2746 *
2747 * This register is not accessible through ROM scripts; see SCR_WRITE32_S[ADDR].
2748 *
2749 * This register is reset on MAC reset.
2750 */
2751 union ody_pemx_ptm_lcl_time {
2752 uint64_t u;
2753 struct ody_pemx_ptm_lcl_time_s {
2754 uint64_t val : 64;
2755 } s;
2756 /* struct ody_pemx_ptm_lcl_time_s cn; */
2757 };
2758 typedef union ody_pemx_ptm_lcl_time ody_pemx_ptm_lcl_time_t;
2759
2760 static inline uint64_t ODY_PEMX_PTM_LCL_TIME(uint64_t a) __attribute__ ((pure, always_inline));
ODY_PEMX_PTM_LCL_TIME(uint64_t a)2761 static inline uint64_t ODY_PEMX_PTM_LCL_TIME(uint64_t a)
2762 {
2763 if (a <= 15)
2764 return 0x8e00000000a0ll + 0x1000000000ll * ((a) & 0xf);
2765 __ody_csr_fatal("PEMX_PTM_LCL_TIME", 1, a, 0, 0, 0, 0, 0);
2766 }
2767
2768 #define typedef_ODY_PEMX_PTM_LCL_TIME(a) ody_pemx_ptm_lcl_time_t
2769 #define bustype_ODY_PEMX_PTM_LCL_TIME(a) CSR_TYPE_NCB
2770 #define basename_ODY_PEMX_PTM_LCL_TIME(a) "PEMX_PTM_LCL_TIME"
2771 #define device_bar_ODY_PEMX_PTM_LCL_TIME(a) 0x0 /* PF_BAR0 */
2772 #define busnum_ODY_PEMX_PTM_LCL_TIME(a) (a)
2773 #define arguments_ODY_PEMX_PTM_LCL_TIME(a) (a), -1, -1, -1
2774
2775 /**
2776 * Register (NCB) pem#_ptm_mas_time
2777 *
2778 * PEM PTM Time Register
2779 * This register contains the PTM synchronized local time value.
2780 *
2781 * This register is not accessible through ROM scripts; see SCR_WRITE32_S[ADDR].
2782 *
2783 * This register is reset on MAC reset.
2784 */
2785 union ody_pemx_ptm_mas_time {
2786 uint64_t u;
2787 struct ody_pemx_ptm_mas_time_s {
2788 uint64_t val : 64;
2789 } s;
2790 /* struct ody_pemx_ptm_mas_time_s cn; */
2791 };
2792 typedef union ody_pemx_ptm_mas_time ody_pemx_ptm_mas_time_t;
2793
2794 static inline uint64_t ODY_PEMX_PTM_MAS_TIME(uint64_t a) __attribute__ ((pure, always_inline));
ODY_PEMX_PTM_MAS_TIME(uint64_t a)2795 static inline uint64_t ODY_PEMX_PTM_MAS_TIME(uint64_t a)
2796 {
2797 if (a <= 15)
2798 return 0x8e00000000a8ll + 0x1000000000ll * ((a) & 0xf);
2799 __ody_csr_fatal("PEMX_PTM_MAS_TIME", 1, a, 0, 0, 0, 0, 0);
2800 }
2801
2802 #define typedef_ODY_PEMX_PTM_MAS_TIME(a) ody_pemx_ptm_mas_time_t
2803 #define bustype_ODY_PEMX_PTM_MAS_TIME(a) CSR_TYPE_NCB
2804 #define basename_ODY_PEMX_PTM_MAS_TIME(a) "PEMX_PTM_MAS_TIME"
2805 #define device_bar_ODY_PEMX_PTM_MAS_TIME(a) 0x0 /* PF_BAR0 */
2806 #define busnum_ODY_PEMX_PTM_MAS_TIME(a) (a)
2807 #define arguments_ODY_PEMX_PTM_MAS_TIME(a) (a), -1, -1, -1
2808
2809 /**
2810 * Register (NCB) pem#_ras_tba_ctl
2811 *
2812 * PEM RAS Time Based Analysis Control Register
2813 * This register is not accessible through ROM scripts; see SCR_WRITE32_S[ADDR].
2814 *
2815 * This register is reset on MAC reset.
2816 */
2817 union ody_pemx_ras_tba_ctl {
2818 uint64_t u;
2819 struct ody_pemx_ras_tba_ctl_s {
2820 uint64_t tba_ctrl : 2;
2821 uint64_t reserved_2_63 : 62;
2822 } s;
2823 /* struct ody_pemx_ras_tba_ctl_s cn; */
2824 };
2825 typedef union ody_pemx_ras_tba_ctl ody_pemx_ras_tba_ctl_t;
2826
2827 static inline uint64_t ODY_PEMX_RAS_TBA_CTL(uint64_t a) __attribute__ ((pure, always_inline));
ODY_PEMX_RAS_TBA_CTL(uint64_t a)2828 static inline uint64_t ODY_PEMX_RAS_TBA_CTL(uint64_t a)
2829 {
2830 if (a <= 15)
2831 return 0x8e0000000068ll + 0x1000000000ll * ((a) & 0xf);
2832 __ody_csr_fatal("PEMX_RAS_TBA_CTL", 1, a, 0, 0, 0, 0, 0);
2833 }
2834
2835 #define typedef_ODY_PEMX_RAS_TBA_CTL(a) ody_pemx_ras_tba_ctl_t
2836 #define bustype_ODY_PEMX_RAS_TBA_CTL(a) CSR_TYPE_NCB
2837 #define basename_ODY_PEMX_RAS_TBA_CTL(a) "PEMX_RAS_TBA_CTL"
2838 #define device_bar_ODY_PEMX_RAS_TBA_CTL(a) 0x0 /* PF_BAR0 */
2839 #define busnum_ODY_PEMX_RAS_TBA_CTL(a) (a)
2840 #define arguments_ODY_PEMX_RAS_TBA_CTL(a) (a), -1, -1, -1
2841
2842 /**
2843 * Register (NCB) pem#_reg_ctl
2844 *
2845 * PEM CSR Control Register
2846 * This register contains control for register accesses.
2847 *
2848 * This register is not accessible through ROM scripts; see SCR_WRITE32_S[ADDR].
2849 *
2850 * This register is reset on core domain reset.
2851 */
2852 union ody_pemx_reg_ctl {
2853 uint64_t u;
2854 struct ody_pemx_reg_ctl_s {
2855 uint64_t gia_timeout : 6;
2856 uint64_t reserved_6_63 : 58;
2857 } s;
2858 /* struct ody_pemx_reg_ctl_s cn; */
2859 };
2860 typedef union ody_pemx_reg_ctl ody_pemx_reg_ctl_t;
2861
2862 static inline uint64_t ODY_PEMX_REG_CTL(uint64_t a) __attribute__ ((pure, always_inline));
ODY_PEMX_REG_CTL(uint64_t a)2863 static inline uint64_t ODY_PEMX_REG_CTL(uint64_t a)
2864 {
2865 if (a <= 15)
2866 return 0x8e0000000060ll + 0x1000000000ll * ((a) & 0xf);
2867 __ody_csr_fatal("PEMX_REG_CTL", 1, a, 0, 0, 0, 0, 0);
2868 }
2869
2870 #define typedef_ODY_PEMX_REG_CTL(a) ody_pemx_reg_ctl_t
2871 #define bustype_ODY_PEMX_REG_CTL(a) CSR_TYPE_NCB
2872 #define basename_ODY_PEMX_REG_CTL(a) "PEMX_REG_CTL"
2873 #define device_bar_ODY_PEMX_REG_CTL(a) 0x0 /* PF_BAR0 */
2874 #define busnum_ODY_PEMX_REG_CTL(a) (a)
2875 #define arguments_ODY_PEMX_REG_CTL(a) (a), -1, -1, -1
2876
2877 /**
2878 * Register (NCB) pem#_reg_norm#_acc
2879 *
2880 * PEM Normal Region Access Registers
2881 * These registers contains address index and control bits for access to memory from cores.
2882 * Indexed using NCBO address\<38:31\>.
2883 *
2884 * See PEM()_CONST_ACC.
2885 *
2886 * This register is not accessible through ROM scripts; see SCR_WRITE32_S[ADDR].
2887 */
2888 union ody_pemx_reg_normx_acc {
2889 uint64_t u;
2890 struct ody_pemx_reg_normx_acc_s {
2891 uint64_t ba : 33;
2892 uint64_t reserved_33_34 : 2;
2893 uint64_t rtype : 3;
2894 uint64_t wtype : 3;
2895 uint64_t rnmerge : 1;
2896 uint64_t wnmerge : 1;
2897 uint64_t zero : 1;
2898 uint64_t ctype : 2;
2899 uint64_t pf : 1;
2900 uint64_t reserved_47_52 : 6;
2901 uint64_t vf_active : 1;
2902 uint64_t vf : 6;
2903 uint64_t reserved_60_63 : 4;
2904 } s;
2905 /* struct ody_pemx_reg_normx_acc_s cn; */
2906 };
2907 typedef union ody_pemx_reg_normx_acc ody_pemx_reg_normx_acc_t;
2908
2909 static inline uint64_t ODY_PEMX_REG_NORMX_ACC(uint64_t a, uint64_t b) __attribute__ ((pure, always_inline));
ODY_PEMX_REG_NORMX_ACC(uint64_t a,uint64_t b)2910 static inline uint64_t ODY_PEMX_REG_NORMX_ACC(uint64_t a, uint64_t b)
2911 {
2912 if ((a <= 15) && (b <= 255))
2913 return 0x8e0000004000ll + 0x1000000000ll * ((a) & 0xf) + 0x10ll * ((b) & 0xff);
2914 __ody_csr_fatal("PEMX_REG_NORMX_ACC", 2, a, b, 0, 0, 0, 0);
2915 }
2916
2917 #define typedef_ODY_PEMX_REG_NORMX_ACC(a, b) ody_pemx_reg_normx_acc_t
2918 #define bustype_ODY_PEMX_REG_NORMX_ACC(a, b) CSR_TYPE_NCB
2919 #define basename_ODY_PEMX_REG_NORMX_ACC(a, b) "PEMX_REG_NORMX_ACC"
2920 #define device_bar_ODY_PEMX_REG_NORMX_ACC(a, b) 0x0 /* PF_BAR0 */
2921 #define busnum_ODY_PEMX_REG_NORMX_ACC(a, b) (a)
2922 #define arguments_ODY_PEMX_REG_NORMX_ACC(a, b) (a), (b), -1, -1
2923
2924 /**
2925 * Register (NCB) pem#_reg_norm#_acc2
2926 *
2927 * PEM Normal Region Access 2 Registers
2928 * See PEM()_CONST_ACC.
2929 *
2930 * This register is not accessible through ROM scripts; see SCR_WRITE32_S[ADDR].
2931 */
2932 union ody_pemx_reg_normx_acc2 {
2933 uint64_t u;
2934 struct ody_pemx_reg_normx_acc2_s {
2935 uint64_t reserved_0_63 : 64;
2936 } s;
2937 /* struct ody_pemx_reg_normx_acc2_s cn; */
2938 };
2939 typedef union ody_pemx_reg_normx_acc2 ody_pemx_reg_normx_acc2_t;
2940
2941 static inline uint64_t ODY_PEMX_REG_NORMX_ACC2(uint64_t a, uint64_t b) __attribute__ ((pure, always_inline));
ODY_PEMX_REG_NORMX_ACC2(uint64_t a,uint64_t b)2942 static inline uint64_t ODY_PEMX_REG_NORMX_ACC2(uint64_t a, uint64_t b)
2943 {
2944 if ((a <= 15) && (b <= 255))
2945 return 0x8e0000004008ll + 0x1000000000ll * ((a) & 0xf) + 0x10ll * ((b) & 0xff);
2946 __ody_csr_fatal("PEMX_REG_NORMX_ACC2", 2, a, b, 0, 0, 0, 0);
2947 }
2948
2949 #define typedef_ODY_PEMX_REG_NORMX_ACC2(a, b) ody_pemx_reg_normx_acc2_t
2950 #define bustype_ODY_PEMX_REG_NORMX_ACC2(a, b) CSR_TYPE_NCB
2951 #define basename_ODY_PEMX_REG_NORMX_ACC2(a, b) "PEMX_REG_NORMX_ACC2"
2952 #define device_bar_ODY_PEMX_REG_NORMX_ACC2(a, b) 0x0 /* PF_BAR0 */
2953 #define busnum_ODY_PEMX_REG_NORMX_ACC2(a, b) (a)
2954 #define arguments_ODY_PEMX_REG_NORMX_ACC2(a, b) (a), (b), -1, -1
2955
2956 /**
2957 * Register (NCB) pem#_rst_cold_state_w1c
2958 *
2959 * PEM Interrupt Summary Register
2960 * This register contains the state of PEM()_RST_INT through core domain reset.
2961 *
2962 * This register is not accessible through ROM scripts; see SCR_WRITE32_S[ADDR].
2963 *
2964 * This register is reset on cold reset.
2965 */
2966 union ody_pemx_rst_cold_state_w1c {
2967 uint64_t u;
2968 struct ody_pemx_rst_cold_state_w1c_s {
2969 uint64_t perst : 1;
2970 uint64_t linkdown : 1;
2971 uint64_t l2 : 1;
2972 uint64_t reserved_3_63 : 61;
2973 } s;
2974 /* struct ody_pemx_rst_cold_state_w1c_s cn; */
2975 };
2976 typedef union ody_pemx_rst_cold_state_w1c ody_pemx_rst_cold_state_w1c_t;
2977
2978 static inline uint64_t ODY_PEMX_RST_COLD_STATE_W1C(uint64_t a) __attribute__ ((pure, always_inline));
ODY_PEMX_RST_COLD_STATE_W1C(uint64_t a)2979 static inline uint64_t ODY_PEMX_RST_COLD_STATE_W1C(uint64_t a)
2980 {
2981 if (a <= 15)
2982 return 0x8e0000000320ll + 0x1000000000ll * ((a) & 0xf);
2983 __ody_csr_fatal("PEMX_RST_COLD_STATE_W1C", 1, a, 0, 0, 0, 0, 0);
2984 }
2985
2986 #define typedef_ODY_PEMX_RST_COLD_STATE_W1C(a) ody_pemx_rst_cold_state_w1c_t
2987 #define bustype_ODY_PEMX_RST_COLD_STATE_W1C(a) CSR_TYPE_NCB
2988 #define basename_ODY_PEMX_RST_COLD_STATE_W1C(a) "PEMX_RST_COLD_STATE_W1C"
2989 #define device_bar_ODY_PEMX_RST_COLD_STATE_W1C(a) 0x0 /* PF_BAR0 */
2990 #define busnum_ODY_PEMX_RST_COLD_STATE_W1C(a) (a)
2991 #define arguments_ODY_PEMX_RST_COLD_STATE_W1C(a) (a), -1, -1, -1
2992
2993 /**
2994 * Register (NCB) pem#_rst_cold_state_w1s
2995 *
2996 * PEM Reset Cold State Interrupt Summary Register
2997 */
2998 union ody_pemx_rst_cold_state_w1s {
2999 uint64_t u;
3000 struct ody_pemx_rst_cold_state_w1s_s {
3001 uint64_t perst : 1;
3002 uint64_t linkdown : 1;
3003 uint64_t l2 : 1;
3004 uint64_t reserved_3_63 : 61;
3005 } s;
3006 /* struct ody_pemx_rst_cold_state_w1s_s cn; */
3007 };
3008 typedef union ody_pemx_rst_cold_state_w1s ody_pemx_rst_cold_state_w1s_t;
3009
3010 static inline uint64_t ODY_PEMX_RST_COLD_STATE_W1S(uint64_t a) __attribute__ ((pure, always_inline));
ODY_PEMX_RST_COLD_STATE_W1S(uint64_t a)3011 static inline uint64_t ODY_PEMX_RST_COLD_STATE_W1S(uint64_t a)
3012 {
3013 if (a <= 15)
3014 return 0x8e0000000328ll + 0x1000000000ll * ((a) & 0xf);
3015 __ody_csr_fatal("PEMX_RST_COLD_STATE_W1S", 1, a, 0, 0, 0, 0, 0);
3016 }
3017
3018 #define typedef_ODY_PEMX_RST_COLD_STATE_W1S(a) ody_pemx_rst_cold_state_w1s_t
3019 #define bustype_ODY_PEMX_RST_COLD_STATE_W1S(a) CSR_TYPE_NCB
3020 #define basename_ODY_PEMX_RST_COLD_STATE_W1S(a) "PEMX_RST_COLD_STATE_W1S"
3021 #define device_bar_ODY_PEMX_RST_COLD_STATE_W1S(a) 0x0 /* PF_BAR0 */
3022 #define busnum_ODY_PEMX_RST_COLD_STATE_W1S(a) (a)
3023 #define arguments_ODY_PEMX_RST_COLD_STATE_W1S(a) (a), -1, -1, -1
3024
3025 /**
3026 * Register (NCB) pem#_rst_int
3027 *
3028 * PEM Interrupt Summary Register
3029 * This register contains the different interrupt summary bits of the PEM.
3030 *
3031 * This register is not accessible through ROM scripts; see SCR_WRITE32_S[ADDR].
3032 *
3033 * This register is reset on core domain reset.
3034 */
3035 union ody_pemx_rst_int {
3036 uint64_t u;
3037 struct ody_pemx_rst_int_s {
3038 uint64_t perst : 1;
3039 uint64_t linkdown : 1;
3040 uint64_t l2 : 1;
3041 uint64_t reserved_3_63 : 61;
3042 } s;
3043 /* struct ody_pemx_rst_int_s cn; */
3044 };
3045 typedef union ody_pemx_rst_int ody_pemx_rst_int_t;
3046
3047 static inline uint64_t ODY_PEMX_RST_INT(uint64_t a) __attribute__ ((pure, always_inline));
ODY_PEMX_RST_INT(uint64_t a)3048 static inline uint64_t ODY_PEMX_RST_INT(uint64_t a)
3049 {
3050 if (a <= 15)
3051 return 0x8e0000000300ll + 0x1000000000ll * ((a) & 0xf);
3052 __ody_csr_fatal("PEMX_RST_INT", 1, a, 0, 0, 0, 0, 0);
3053 }
3054
3055 #define typedef_ODY_PEMX_RST_INT(a) ody_pemx_rst_int_t
3056 #define bustype_ODY_PEMX_RST_INT(a) CSR_TYPE_NCB
3057 #define basename_ODY_PEMX_RST_INT(a) "PEMX_RST_INT"
3058 #define device_bar_ODY_PEMX_RST_INT(a) 0x0 /* PF_BAR0 */
3059 #define busnum_ODY_PEMX_RST_INT(a) (a)
3060 #define arguments_ODY_PEMX_RST_INT(a) (a), -1, -1, -1
3061
3062 /**
3063 * Register (NCB) pem#_rst_int_ena_w1c
3064 *
3065 * PEM Interrupt Enable Clear Register
3066 * This register clears interrupt enable bits.
3067 */
3068 union ody_pemx_rst_int_ena_w1c {
3069 uint64_t u;
3070 struct ody_pemx_rst_int_ena_w1c_s {
3071 uint64_t perst : 1;
3072 uint64_t linkdown : 1;
3073 uint64_t l2 : 1;
3074 uint64_t reserved_3_63 : 61;
3075 } s;
3076 /* struct ody_pemx_rst_int_ena_w1c_s cn; */
3077 };
3078 typedef union ody_pemx_rst_int_ena_w1c ody_pemx_rst_int_ena_w1c_t;
3079
3080 static inline uint64_t ODY_PEMX_RST_INT_ENA_W1C(uint64_t a) __attribute__ ((pure, always_inline));
ODY_PEMX_RST_INT_ENA_W1C(uint64_t a)3081 static inline uint64_t ODY_PEMX_RST_INT_ENA_W1C(uint64_t a)
3082 {
3083 if (a <= 15)
3084 return 0x8e0000000310ll + 0x1000000000ll * ((a) & 0xf);
3085 __ody_csr_fatal("PEMX_RST_INT_ENA_W1C", 1, a, 0, 0, 0, 0, 0);
3086 }
3087
3088 #define typedef_ODY_PEMX_RST_INT_ENA_W1C(a) ody_pemx_rst_int_ena_w1c_t
3089 #define bustype_ODY_PEMX_RST_INT_ENA_W1C(a) CSR_TYPE_NCB
3090 #define basename_ODY_PEMX_RST_INT_ENA_W1C(a) "PEMX_RST_INT_ENA_W1C"
3091 #define device_bar_ODY_PEMX_RST_INT_ENA_W1C(a) 0x0 /* PF_BAR0 */
3092 #define busnum_ODY_PEMX_RST_INT_ENA_W1C(a) (a)
3093 #define arguments_ODY_PEMX_RST_INT_ENA_W1C(a) (a), -1, -1, -1
3094
3095 /**
3096 * Register (NCB) pem#_rst_int_ena_w1s
3097 *
3098 * PEM Interrupt Enable Set Register
3099 * This register sets interrupt enable bits.
3100 */
3101 union ody_pemx_rst_int_ena_w1s {
3102 uint64_t u;
3103 struct ody_pemx_rst_int_ena_w1s_s {
3104 uint64_t perst : 1;
3105 uint64_t linkdown : 1;
3106 uint64_t l2 : 1;
3107 uint64_t reserved_3_63 : 61;
3108 } s;
3109 /* struct ody_pemx_rst_int_ena_w1s_s cn; */
3110 };
3111 typedef union ody_pemx_rst_int_ena_w1s ody_pemx_rst_int_ena_w1s_t;
3112
3113 static inline uint64_t ODY_PEMX_RST_INT_ENA_W1S(uint64_t a) __attribute__ ((pure, always_inline));
ODY_PEMX_RST_INT_ENA_W1S(uint64_t a)3114 static inline uint64_t ODY_PEMX_RST_INT_ENA_W1S(uint64_t a)
3115 {
3116 if (a <= 15)
3117 return 0x8e0000000318ll + 0x1000000000ll * ((a) & 0xf);
3118 __ody_csr_fatal("PEMX_RST_INT_ENA_W1S", 1, a, 0, 0, 0, 0, 0);
3119 }
3120
3121 #define typedef_ODY_PEMX_RST_INT_ENA_W1S(a) ody_pemx_rst_int_ena_w1s_t
3122 #define bustype_ODY_PEMX_RST_INT_ENA_W1S(a) CSR_TYPE_NCB
3123 #define basename_ODY_PEMX_RST_INT_ENA_W1S(a) "PEMX_RST_INT_ENA_W1S"
3124 #define device_bar_ODY_PEMX_RST_INT_ENA_W1S(a) 0x0 /* PF_BAR0 */
3125 #define busnum_ODY_PEMX_RST_INT_ENA_W1S(a) (a)
3126 #define arguments_ODY_PEMX_RST_INT_ENA_W1S(a) (a), -1, -1, -1
3127
3128 /**
3129 * Register (NCB) pem#_rst_int_w1s
3130 *
3131 * PEM Interrupt Summary Register
3132 * This register sets interrupt bits.
3133 */
3134 union ody_pemx_rst_int_w1s {
3135 uint64_t u;
3136 struct ody_pemx_rst_int_w1s_s {
3137 uint64_t perst : 1;
3138 uint64_t linkdown : 1;
3139 uint64_t l2 : 1;
3140 uint64_t reserved_3_63 : 61;
3141 } s;
3142 /* struct ody_pemx_rst_int_w1s_s cn; */
3143 };
3144 typedef union ody_pemx_rst_int_w1s ody_pemx_rst_int_w1s_t;
3145
3146 static inline uint64_t ODY_PEMX_RST_INT_W1S(uint64_t a) __attribute__ ((pure, always_inline));
ODY_PEMX_RST_INT_W1S(uint64_t a)3147 static inline uint64_t ODY_PEMX_RST_INT_W1S(uint64_t a)
3148 {
3149 if (a <= 15)
3150 return 0x8e0000000308ll + 0x1000000000ll * ((a) & 0xf);
3151 __ody_csr_fatal("PEMX_RST_INT_W1S", 1, a, 0, 0, 0, 0, 0);
3152 }
3153
3154 #define typedef_ODY_PEMX_RST_INT_W1S(a) ody_pemx_rst_int_w1s_t
3155 #define bustype_ODY_PEMX_RST_INT_W1S(a) CSR_TYPE_NCB
3156 #define basename_ODY_PEMX_RST_INT_W1S(a) "PEMX_RST_INT_W1S"
3157 #define device_bar_ODY_PEMX_RST_INT_W1S(a) 0x0 /* PF_BAR0 */
3158 #define busnum_ODY_PEMX_RST_INT_W1S(a) (a)
3159 #define arguments_ODY_PEMX_RST_INT_W1S(a) (a), -1, -1, -1
3160
3161 /**
3162 * Register (NCB) pem#_rst_lboot
3163 *
3164 * PEM Reset Last Boot Register
3165 * This register contains status last reset cause.
3166 *
3167 * This register is not accessible through ROM scripts; see SCR_WRITE32_S[ADDR].
3168 *
3169 * This register is reset on cold reset.
3170 */
3171 union ody_pemx_rst_lboot {
3172 uint64_t u;
3173 struct ody_pemx_rst_lboot_s {
3174 uint64_t lboot : 5;
3175 uint64_t reserved_5_63 : 59;
3176 } s;
3177 /* struct ody_pemx_rst_lboot_s cn; */
3178 };
3179 typedef union ody_pemx_rst_lboot ody_pemx_rst_lboot_t;
3180
3181 static inline uint64_t ODY_PEMX_RST_LBOOT(uint64_t a) __attribute__ ((pure, always_inline));
ODY_PEMX_RST_LBOOT(uint64_t a)3182 static inline uint64_t ODY_PEMX_RST_LBOOT(uint64_t a)
3183 {
3184 if (a <= 15)
3185 return 0x8e0000000280ll + 0x1000000000ll * ((a) & 0xf);
3186 __ody_csr_fatal("PEMX_RST_LBOOT", 1, a, 0, 0, 0, 0, 0);
3187 }
3188
3189 #define typedef_ODY_PEMX_RST_LBOOT(a) ody_pemx_rst_lboot_t
3190 #define bustype_ODY_PEMX_RST_LBOOT(a) CSR_TYPE_NCB
3191 #define basename_ODY_PEMX_RST_LBOOT(a) "PEMX_RST_LBOOT"
3192 #define device_bar_ODY_PEMX_RST_LBOOT(a) 0x0 /* PF_BAR0 */
3193 #define busnum_ODY_PEMX_RST_LBOOT(a) (a)
3194 #define arguments_ODY_PEMX_RST_LBOOT(a) (a), -1, -1, -1
3195
3196 /**
3197 * Register (NCB) pem#_rst_mac
3198 *
3199 * PEM Reset Mac Register
3200 * This register provides controls and modes related to resets to the MAC.
3201 *
3202 * This register is accessible through ROM scripts; see SCR_WRITE32_S[ADDR].
3203 *
3204 * This register is reset on cold reset.
3205 */
3206 union ody_pemx_rst_mac {
3207 uint64_t u;
3208 struct ody_pemx_rst_mac_s {
3209 uint64_t mac_rst : 1;
3210 uint64_t pipe_rst : 1;
3211 uint64_t pipe_rst_ovrd_en : 1;
3212 uint64_t diag_clr_phystatus : 1;
3213 uint64_t dis_pipe_rst : 1;
3214 uint64_t ns_mode : 1;
3215 uint64_t ns_rst : 1;
3216 uint64_t mac_perst : 1;
3217 uint64_t insecure_mode : 1;
3218 uint64_t reserved_9_63 : 55;
3219 } s;
3220 /* struct ody_pemx_rst_mac_s cn; */
3221 };
3222 typedef union ody_pemx_rst_mac ody_pemx_rst_mac_t;
3223
3224 static inline uint64_t ODY_PEMX_RST_MAC(uint64_t a) __attribute__ ((pure, always_inline));
ODY_PEMX_RST_MAC(uint64_t a)3225 static inline uint64_t ODY_PEMX_RST_MAC(uint64_t a)
3226 {
3227 if (a <= 15)
3228 return 0x8e0000000290ll + 0x1000000000ll * ((a) & 0xf);
3229 __ody_csr_fatal("PEMX_RST_MAC", 1, a, 0, 0, 0, 0, 0);
3230 }
3231
3232 #define typedef_ODY_PEMX_RST_MAC(a) ody_pemx_rst_mac_t
3233 #define bustype_ODY_PEMX_RST_MAC(a) CSR_TYPE_NCB
3234 #define basename_ODY_PEMX_RST_MAC(a) "PEMX_RST_MAC"
3235 #define device_bar_ODY_PEMX_RST_MAC(a) 0x0 /* PF_BAR0 */
3236 #define busnum_ODY_PEMX_RST_MAC(a) (a)
3237 #define arguments_ODY_PEMX_RST_MAC(a) (a), -1, -1, -1
3238
3239 /**
3240 * Register (NCB) pem#_rst_soft_perst
3241 *
3242 * PEM Reset Software PERST Register
3243 * This register provides a mechanism to drive the PCIe PERSTN pin.
3244 *
3245 * This register is accessible through ROM scripts; see SCR_WRITE32_S[ADDR].
3246 */
3247 union ody_pemx_rst_soft_perst {
3248 uint64_t u;
3249 struct ody_pemx_rst_soft_perst_s {
3250 uint64_t soft_perst : 1;
3251 uint64_t reserved_1_63 : 63;
3252 } s;
3253 /* struct ody_pemx_rst_soft_perst_s cn; */
3254 };
3255 typedef union ody_pemx_rst_soft_perst ody_pemx_rst_soft_perst_t;
3256
3257 static inline uint64_t ODY_PEMX_RST_SOFT_PERST(uint64_t a) __attribute__ ((pure, always_inline));
ODY_PEMX_RST_SOFT_PERST(uint64_t a)3258 static inline uint64_t ODY_PEMX_RST_SOFT_PERST(uint64_t a)
3259 {
3260 if (a <= 15)
3261 return 0x8e0000000298ll + 0x1000000000ll * ((a) & 0xf);
3262 __ody_csr_fatal("PEMX_RST_SOFT_PERST", 1, a, 0, 0, 0, 0, 0);
3263 }
3264
3265 #define typedef_ODY_PEMX_RST_SOFT_PERST(a) ody_pemx_rst_soft_perst_t
3266 #define bustype_ODY_PEMX_RST_SOFT_PERST(a) CSR_TYPE_NCB
3267 #define basename_ODY_PEMX_RST_SOFT_PERST(a) "PEMX_RST_SOFT_PERST"
3268 #define device_bar_ODY_PEMX_RST_SOFT_PERST(a) 0x0 /* PF_BAR0 */
3269 #define busnum_ODY_PEMX_RST_SOFT_PERST(a) (a)
3270 #define arguments_ODY_PEMX_RST_SOFT_PERST(a) (a), -1, -1, -1
3271
3272 /**
3273 * Register (NCB) pem#_s_rst_ctl
3274 *
3275 * PEM Secure Reset Controllers Register
3276 * This register is accessible through ROM scripts; see SCR_WRITE32_S[ADDR].
3277 */
3278 union ody_pemx_s_rst_ctl {
3279 uint64_t u;
3280 struct ody_pemx_s_rst_ctl_s {
3281 uint64_t perst_pin : 1;
3282 uint64_t en_perst_rcv : 1;
3283 uint64_t en_perst_drv : 1;
3284 uint64_t reserved_3_6 : 4;
3285 uint64_t rst_perst : 1;
3286 uint64_t prst_lnkdwn : 1;
3287 uint64_t rst_lnkdwn : 1;
3288 uint64_t rst_pfflr : 1;
3289 uint64_t prst_l2 : 1;
3290 uint64_t rst_l2 : 1;
3291 uint64_t reset_type : 1;
3292 uint64_t reserved_14_63 : 50;
3293 } s;
3294 /* struct ody_pemx_s_rst_ctl_s cn; */
3295 };
3296 typedef union ody_pemx_s_rst_ctl ody_pemx_s_rst_ctl_t;
3297
3298 static inline uint64_t ODY_PEMX_S_RST_CTL(uint64_t a) __attribute__ ((pure, always_inline));
ODY_PEMX_S_RST_CTL(uint64_t a)3299 static inline uint64_t ODY_PEMX_S_RST_CTL(uint64_t a)
3300 {
3301 if (a <= 15)
3302 return 0x8e0000000288ll + 0x1000000000ll * ((a) & 0xf);
3303 __ody_csr_fatal("PEMX_S_RST_CTL", 1, a, 0, 0, 0, 0, 0);
3304 }
3305
3306 #define typedef_ODY_PEMX_S_RST_CTL(a) ody_pemx_s_rst_ctl_t
3307 #define bustype_ODY_PEMX_S_RST_CTL(a) CSR_TYPE_NCB
3308 #define basename_ODY_PEMX_S_RST_CTL(a) "PEMX_S_RST_CTL"
3309 #define device_bar_ODY_PEMX_S_RST_CTL(a) 0x0 /* PF_BAR0 */
3310 #define busnum_ODY_PEMX_S_RST_CTL(a) (a)
3311 #define arguments_ODY_PEMX_S_RST_CTL(a) (a), -1, -1, -1
3312
3313 /**
3314 * Register (NCB) pem#_strap
3315 *
3316 * PEM Pin Strapping Register
3317 * This register is accessible through ROM scripts; see SCR_WRITE32_S[ADDR].
3318 *
3319 * This register is reset on cold reset.
3320 */
3321 union ody_pemx_strap {
3322 uint64_t u;
3323 struct ody_pemx_strap_s {
3324 uint64_t pirc : 1;
3325 uint64_t reserved_1_63 : 63;
3326 } s;
3327 /* struct ody_pemx_strap_s cn; */
3328 };
3329 typedef union ody_pemx_strap ody_pemx_strap_t;
3330
3331 static inline uint64_t ODY_PEMX_STRAP(uint64_t a) __attribute__ ((pure, always_inline));
ODY_PEMX_STRAP(uint64_t a)3332 static inline uint64_t ODY_PEMX_STRAP(uint64_t a)
3333 {
3334 if (a <= 15)
3335 return 0x8e00000000d0ll + 0x1000000000ll * ((a) & 0xf);
3336 __ody_csr_fatal("PEMX_STRAP", 1, a, 0, 0, 0, 0, 0);
3337 }
3338
3339 #define typedef_ODY_PEMX_STRAP(a) ody_pemx_strap_t
3340 #define bustype_ODY_PEMX_STRAP(a) CSR_TYPE_NCB
3341 #define basename_ODY_PEMX_STRAP(a) "PEMX_STRAP"
3342 #define device_bar_ODY_PEMX_STRAP(a) 0x0 /* PF_BAR0 */
3343 #define busnum_ODY_PEMX_STRAP(a) (a)
3344 #define arguments_ODY_PEMX_STRAP(a) (a), -1, -1, -1
3345
3346 /**
3347 * Register (NCB) pem#_vdm#_ctl
3348 *
3349 * PEM VDM Control Register
3350 * This register provides control of the Vendor Defined Message (VDM) inbound
3351 * and outbound message mailboxes. Type 1 PCIe VDM messages are received and sent
3352 * via the VDM message mailbox interface.
3353 *
3354 * This register is not accessible through ROM scripts; see SCR_WRITE32_S[ADDR].
3355 *
3356 * This register is reset on core domain reset.
3357 *
3358 * This register is restricted to 64-bit access. Unsupported 32-bit access will
3359 * have unpredictable results, however will not cause an access hang or timeout.
3360 *
3361 * The operation of this register is restricted if PEMSEC()_VDM()_CFG[VDM_SEC_MODE]
3362 * is set to 1. Refer to the PEMSEC()_VDM()_CFG register description.
3363 */
3364 union ody_pemx_vdmx_ctl {
3365 uint64_t u;
3366 struct ody_pemx_vdmx_ctl_s {
3367 uint64_t ib_mbx_rst : 1;
3368 uint64_t ob_mbx_rst : 1;
3369 uint64_t reserved_2 : 1;
3370 uint64_t mbx_cfg : 1;
3371 uint64_t reserved_4_30 : 27;
3372 uint64_t ob_mbx_snd : 1;
3373 uint64_t reserved_32_63 : 32;
3374 } s;
3375 /* struct ody_pemx_vdmx_ctl_s cn; */
3376 };
3377 typedef union ody_pemx_vdmx_ctl ody_pemx_vdmx_ctl_t;
3378
3379 static inline uint64_t ODY_PEMX_VDMX_CTL(uint64_t a, uint64_t b) __attribute__ ((pure, always_inline));
ODY_PEMX_VDMX_CTL(uint64_t a,uint64_t b)3380 static inline uint64_t ODY_PEMX_VDMX_CTL(uint64_t a, uint64_t b)
3381 {
3382 if ((a <= 15) && (b == 0))
3383 return 0x8e0000007f00ll + 0x1000000000ll * ((a) & 0xf);
3384 __ody_csr_fatal("PEMX_VDMX_CTL", 2, a, b, 0, 0, 0, 0);
3385 }
3386
3387 #define typedef_ODY_PEMX_VDMX_CTL(a, b) ody_pemx_vdmx_ctl_t
3388 #define bustype_ODY_PEMX_VDMX_CTL(a, b) CSR_TYPE_NCB
3389 #define basename_ODY_PEMX_VDMX_CTL(a, b) "PEMX_VDMX_CTL"
3390 #define device_bar_ODY_PEMX_VDMX_CTL(a, b) 0x0 /* PF_BAR0 */
3391 #define busnum_ODY_PEMX_VDMX_CTL(a, b) (a)
3392 #define arguments_ODY_PEMX_VDMX_CTL(a, b) (a), (b), -1, -1
3393
3394 /**
3395 * Register (NCB) pem#_vdm#_ib_hdr
3396 *
3397 * PEM VDM Inbound Message Header Register
3398 * Vendor Defined Message Inbound Message Header Register.
3399 *
3400 * This register is not accessible through ROM scripts; see SCR_WRITE32_S[ADDR].
3401 *
3402 * This register is reset on core domain reset.
3403 *
3404 * This register is restricted to 64-bit access. Unsupported 32-bit access will
3405 * have unpredictable results, however will not cause an access hang or timeout.
3406 *
3407 * The operation of this register is restricted if PEMSEC()_VDM()_CFG[VDM_SEC_MODE]
3408 * is set to 1. Refer to the PEMSEC()_VDM()_CFG register description.
3409 */
3410 union ody_pemx_vdmx_ib_hdr {
3411 uint64_t u;
3412 struct ody_pemx_vdmx_ib_hdr_s {
3413 uint64_t ib_msg_hdr : 64;
3414 } s;
3415 /* struct ody_pemx_vdmx_ib_hdr_s cn; */
3416 };
3417 typedef union ody_pemx_vdmx_ib_hdr ody_pemx_vdmx_ib_hdr_t;
3418
3419 static inline uint64_t ODY_PEMX_VDMX_IB_HDR(uint64_t a, uint64_t b) __attribute__ ((pure, always_inline));
ODY_PEMX_VDMX_IB_HDR(uint64_t a,uint64_t b)3420 static inline uint64_t ODY_PEMX_VDMX_IB_HDR(uint64_t a, uint64_t b)
3421 {
3422 if ((a <= 15) && (b == 0))
3423 return 0x8e0000007f50ll + 0x1000000000ll * ((a) & 0xf);
3424 __ody_csr_fatal("PEMX_VDMX_IB_HDR", 2, a, b, 0, 0, 0, 0);
3425 }
3426
3427 #define typedef_ODY_PEMX_VDMX_IB_HDR(a, b) ody_pemx_vdmx_ib_hdr_t
3428 #define bustype_ODY_PEMX_VDMX_IB_HDR(a, b) CSR_TYPE_NCB
3429 #define basename_ODY_PEMX_VDMX_IB_HDR(a, b) "PEMX_VDMX_IB_HDR"
3430 #define device_bar_ODY_PEMX_VDMX_IB_HDR(a, b) 0x0 /* PF_BAR0 */
3431 #define busnum_ODY_PEMX_VDMX_IB_HDR(a, b) (a)
3432 #define arguments_ODY_PEMX_VDMX_IB_HDR(a, b) (a), (b), -1, -1
3433
3434 /**
3435 * Register (NCB) pem#_vdm#_ib_pld
3436 *
3437 * PEM VDM Inbound Message Payload Register
3438 * Vendor Defined Message Inbound Message Payload Register.
3439 *
3440 * This register is not accessible through ROM scripts; see SCR_WRITE32_S[ADDR].
3441 *
3442 * This register is reset on core domain reset.
3443 *
3444 * This register is restricted to 64-bit access. Unsupported 32-bit access will
3445 * have unpredictable results, however will not cause an access hang or timeout.
3446 *
3447 * The operation of this register is restricted if PEMSEC()_VDM()_CFG[VDM_SEC_MODE]
3448 * is set to 1. Refer to the PEMSEC()_VDM()_CFG register description.
3449 */
3450 union ody_pemx_vdmx_ib_pld {
3451 uint64_t u;
3452 struct ody_pemx_vdmx_ib_pld_s {
3453 uint64_t ib_msg_pld : 64;
3454 } s;
3455 /* struct ody_pemx_vdmx_ib_pld_s cn; */
3456 };
3457 typedef union ody_pemx_vdmx_ib_pld ody_pemx_vdmx_ib_pld_t;
3458
3459 static inline uint64_t ODY_PEMX_VDMX_IB_PLD(uint64_t a, uint64_t b) __attribute__ ((pure, always_inline));
ODY_PEMX_VDMX_IB_PLD(uint64_t a,uint64_t b)3460 static inline uint64_t ODY_PEMX_VDMX_IB_PLD(uint64_t a, uint64_t b)
3461 {
3462 if ((a <= 15) && (b == 0))
3463 return 0x8e0000007f60ll + 0x1000000000ll * ((a) & 0xf);
3464 __ody_csr_fatal("PEMX_VDMX_IB_PLD", 2, a, b, 0, 0, 0, 0);
3465 }
3466
3467 #define typedef_ODY_PEMX_VDMX_IB_PLD(a, b) ody_pemx_vdmx_ib_pld_t
3468 #define bustype_ODY_PEMX_VDMX_IB_PLD(a, b) CSR_TYPE_NCB
3469 #define basename_ODY_PEMX_VDMX_IB_PLD(a, b) "PEMX_VDMX_IB_PLD"
3470 #define device_bar_ODY_PEMX_VDMX_IB_PLD(a, b) 0x0 /* PF_BAR0 */
3471 #define busnum_ODY_PEMX_VDMX_IB_PLD(a, b) (a)
3472 #define arguments_ODY_PEMX_VDMX_IB_PLD(a, b) (a), (b), -1, -1
3473
3474 /**
3475 * Register (NCB) pem#_vdm#_ib_vid#
3476 *
3477 * PEM VDM Inbound Message VID Match Register
3478 * Vendor Defined Message Inbound Message VID Match Register.
3479 *
3480 * This register is not accessible through ROM scripts; see SCR_WRITE32_S[ADDR].
3481 *
3482 * This register is reset on core domain reset.
3483 *
3484 * This register is restricted to 64-bit access. Unsupported 32-bit access will
3485 * have unpredictable results, however will not cause an access hang or timeout.
3486 *
3487 * The operation of this register is restricted if PEMSEC()_VDM()_CFG[VDM_SEC_MODE]
3488 * is set to 1. Refer to the PEMSEC()_VDM()_CFG register description.
3489 */
3490 union ody_pemx_vdmx_ib_vidx {
3491 uint64_t u;
3492 struct ody_pemx_vdmx_ib_vidx_s {
3493 uint64_t vid : 16;
3494 uint64_t reserved_16_30 : 15;
3495 uint64_t valid : 1;
3496 uint64_t reserved_32_63 : 32;
3497 } s;
3498 /* struct ody_pemx_vdmx_ib_vidx_s cn; */
3499 };
3500 typedef union ody_pemx_vdmx_ib_vidx ody_pemx_vdmx_ib_vidx_t;
3501
3502 static inline uint64_t ODY_PEMX_VDMX_IB_VIDX(uint64_t a, uint64_t b, uint64_t c) __attribute__ ((pure, always_inline));
ODY_PEMX_VDMX_IB_VIDX(uint64_t a,uint64_t b,uint64_t c)3503 static inline uint64_t ODY_PEMX_VDMX_IB_VIDX(uint64_t a, uint64_t b, uint64_t c)
3504 {
3505 if ((a <= 15) && (b == 0) && (c <= 7))
3506 return 0x8e0000007f80ll + 0x1000000000ll * ((a) & 0xf) + 8ll * ((c) & 0x7);
3507 __ody_csr_fatal("PEMX_VDMX_IB_VIDX", 3, a, b, c, 0, 0, 0);
3508 }
3509
3510 #define typedef_ODY_PEMX_VDMX_IB_VIDX(a, b, c) ody_pemx_vdmx_ib_vidx_t
3511 #define bustype_ODY_PEMX_VDMX_IB_VIDX(a, b, c) CSR_TYPE_NCB
3512 #define basename_ODY_PEMX_VDMX_IB_VIDX(a, b, c) "PEMX_VDMX_IB_VIDX"
3513 #define device_bar_ODY_PEMX_VDMX_IB_VIDX(a, b, c) 0x0 /* PF_BAR0 */
3514 #define busnum_ODY_PEMX_VDMX_IB_VIDX(a, b, c) (a)
3515 #define arguments_ODY_PEMX_VDMX_IB_VIDX(a, b, c) (a), (b), (c), -1
3516
3517 /**
3518 * Register (NCB) pem#_vdm#_int
3519 *
3520 * PEM VDM Interrupt Register
3521 * This register contains the interrupt bits for VDM.
3522 *
3523 * This register is not accessible through ROM scripts; see SCR_WRITE32_S[ADDR].
3524 *
3525 * This register is reset on core domain reset.
3526 *
3527 * The operation of this register is restricted if PEMSEC()_VDM()_CFG[VDM_SEC_MODE]
3528 * is set to 1. Refer to the PEMSEC()_VDM()_CFG register description.
3529 */
3530 union ody_pemx_vdmx_int {
3531 uint64_t u;
3532 struct ody_pemx_vdmx_int_s {
3533 uint64_t rx_rcv : 1;
3534 uint64_t reserved_1_63 : 63;
3535 } s;
3536 /* struct ody_pemx_vdmx_int_s cn; */
3537 };
3538 typedef union ody_pemx_vdmx_int ody_pemx_vdmx_int_t;
3539
3540 static inline uint64_t ODY_PEMX_VDMX_INT(uint64_t a, uint64_t b) __attribute__ ((pure, always_inline));
ODY_PEMX_VDMX_INT(uint64_t a,uint64_t b)3541 static inline uint64_t ODY_PEMX_VDMX_INT(uint64_t a, uint64_t b)
3542 {
3543 if ((a <= 15) && (b == 0))
3544 return 0x8e0000007e00ll + 0x1000000000ll * ((a) & 0xf);
3545 __ody_csr_fatal("PEMX_VDMX_INT", 2, a, b, 0, 0, 0, 0);
3546 }
3547
3548 #define typedef_ODY_PEMX_VDMX_INT(a, b) ody_pemx_vdmx_int_t
3549 #define bustype_ODY_PEMX_VDMX_INT(a, b) CSR_TYPE_NCB
3550 #define basename_ODY_PEMX_VDMX_INT(a, b) "PEMX_VDMX_INT"
3551 #define device_bar_ODY_PEMX_VDMX_INT(a, b) 0x0 /* PF_BAR0 */
3552 #define busnum_ODY_PEMX_VDMX_INT(a, b) (a)
3553 #define arguments_ODY_PEMX_VDMX_INT(a, b) (a), (b), -1, -1
3554
3555 /**
3556 * Register (NCB) pem#_vdm#_int_ena_w1c
3557 *
3558 * PEM VDM Interrupt Enable Clear Register
3559 * This register clears interrupt enable bits.
3560 */
3561 union ody_pemx_vdmx_int_ena_w1c {
3562 uint64_t u;
3563 struct ody_pemx_vdmx_int_ena_w1c_s {
3564 uint64_t rx_rcv : 1;
3565 uint64_t reserved_1_63 : 63;
3566 } s;
3567 /* struct ody_pemx_vdmx_int_ena_w1c_s cn; */
3568 };
3569 typedef union ody_pemx_vdmx_int_ena_w1c ody_pemx_vdmx_int_ena_w1c_t;
3570
3571 static inline uint64_t ODY_PEMX_VDMX_INT_ENA_W1C(uint64_t a, uint64_t b) __attribute__ ((pure, always_inline));
ODY_PEMX_VDMX_INT_ENA_W1C(uint64_t a,uint64_t b)3572 static inline uint64_t ODY_PEMX_VDMX_INT_ENA_W1C(uint64_t a, uint64_t b)
3573 {
3574 if ((a <= 15) && (b == 0))
3575 return 0x8e0000007e20ll + 0x1000000000ll * ((a) & 0xf);
3576 __ody_csr_fatal("PEMX_VDMX_INT_ENA_W1C", 2, a, b, 0, 0, 0, 0);
3577 }
3578
3579 #define typedef_ODY_PEMX_VDMX_INT_ENA_W1C(a, b) ody_pemx_vdmx_int_ena_w1c_t
3580 #define bustype_ODY_PEMX_VDMX_INT_ENA_W1C(a, b) CSR_TYPE_NCB
3581 #define basename_ODY_PEMX_VDMX_INT_ENA_W1C(a, b) "PEMX_VDMX_INT_ENA_W1C"
3582 #define device_bar_ODY_PEMX_VDMX_INT_ENA_W1C(a, b) 0x0 /* PF_BAR0 */
3583 #define busnum_ODY_PEMX_VDMX_INT_ENA_W1C(a, b) (a)
3584 #define arguments_ODY_PEMX_VDMX_INT_ENA_W1C(a, b) (a), (b), -1, -1
3585
3586 /**
3587 * Register (NCB) pem#_vdm#_int_ena_w1s
3588 *
3589 * PEM VDM Interrupt Enable Set Register
3590 * This register sets interrupt enable bits.
3591 */
3592 union ody_pemx_vdmx_int_ena_w1s {
3593 uint64_t u;
3594 struct ody_pemx_vdmx_int_ena_w1s_s {
3595 uint64_t rx_rcv : 1;
3596 uint64_t reserved_1_63 : 63;
3597 } s;
3598 /* struct ody_pemx_vdmx_int_ena_w1s_s cn; */
3599 };
3600 typedef union ody_pemx_vdmx_int_ena_w1s ody_pemx_vdmx_int_ena_w1s_t;
3601
3602 static inline uint64_t ODY_PEMX_VDMX_INT_ENA_W1S(uint64_t a, uint64_t b) __attribute__ ((pure, always_inline));
ODY_PEMX_VDMX_INT_ENA_W1S(uint64_t a,uint64_t b)3603 static inline uint64_t ODY_PEMX_VDMX_INT_ENA_W1S(uint64_t a, uint64_t b)
3604 {
3605 if ((a <= 15) && (b == 0))
3606 return 0x8e0000007e30ll + 0x1000000000ll * ((a) & 0xf);
3607 __ody_csr_fatal("PEMX_VDMX_INT_ENA_W1S", 2, a, b, 0, 0, 0, 0);
3608 }
3609
3610 #define typedef_ODY_PEMX_VDMX_INT_ENA_W1S(a, b) ody_pemx_vdmx_int_ena_w1s_t
3611 #define bustype_ODY_PEMX_VDMX_INT_ENA_W1S(a, b) CSR_TYPE_NCB
3612 #define basename_ODY_PEMX_VDMX_INT_ENA_W1S(a, b) "PEMX_VDMX_INT_ENA_W1S"
3613 #define device_bar_ODY_PEMX_VDMX_INT_ENA_W1S(a, b) 0x0 /* PF_BAR0 */
3614 #define busnum_ODY_PEMX_VDMX_INT_ENA_W1S(a, b) (a)
3615 #define arguments_ODY_PEMX_VDMX_INT_ENA_W1S(a, b) (a), (b), -1, -1
3616
3617 /**
3618 * Register (NCB) pem#_vdm#_int_w1s
3619 *
3620 * PEM VDM Interrupt Set Register
3621 * This register sets interrupt bits.
3622 */
3623 union ody_pemx_vdmx_int_w1s {
3624 uint64_t u;
3625 struct ody_pemx_vdmx_int_w1s_s {
3626 uint64_t rx_rcv : 1;
3627 uint64_t reserved_1_63 : 63;
3628 } s;
3629 /* struct ody_pemx_vdmx_int_w1s_s cn; */
3630 };
3631 typedef union ody_pemx_vdmx_int_w1s ody_pemx_vdmx_int_w1s_t;
3632
3633 static inline uint64_t ODY_PEMX_VDMX_INT_W1S(uint64_t a, uint64_t b) __attribute__ ((pure, always_inline));
ODY_PEMX_VDMX_INT_W1S(uint64_t a,uint64_t b)3634 static inline uint64_t ODY_PEMX_VDMX_INT_W1S(uint64_t a, uint64_t b)
3635 {
3636 if ((a <= 15) && (b == 0))
3637 return 0x8e0000007e10ll + 0x1000000000ll * ((a) & 0xf);
3638 __ody_csr_fatal("PEMX_VDMX_INT_W1S", 2, a, b, 0, 0, 0, 0);
3639 }
3640
3641 #define typedef_ODY_PEMX_VDMX_INT_W1S(a, b) ody_pemx_vdmx_int_w1s_t
3642 #define bustype_ODY_PEMX_VDMX_INT_W1S(a, b) CSR_TYPE_NCB
3643 #define basename_ODY_PEMX_VDMX_INT_W1S(a, b) "PEMX_VDMX_INT_W1S"
3644 #define device_bar_ODY_PEMX_VDMX_INT_W1S(a, b) 0x0 /* PF_BAR0 */
3645 #define busnum_ODY_PEMX_VDMX_INT_W1S(a, b) (a)
3646 #define arguments_ODY_PEMX_VDMX_INT_W1S(a, b) (a), (b), -1, -1
3647
3648 /**
3649 * Register (NCB) pem#_vdm#_ob_hdrh
3650 *
3651 * PEM VDM Outbound Message Header Hi Register
3652 * Vendor Defined Message Outbound Message Header Hi Register.
3653 *
3654 * This register is not accessible through ROM scripts; see SCR_WRITE32_S[ADDR].
3655 *
3656 * This register is reset on core domain reset.
3657 *
3658 * This register is restricted to 64-bit access. Unsupported 32-bit access will
3659 * have unpredictable results, however will not cause an access hang or timeout.
3660 *
3661 * The operation of this register is restricted if PEMSEC()_VDM()_CFG[VDM_SEC_MODE]
3662 * is set to 1. Refer to the PEMSEC()_VDM()_CFG register description.
3663 */
3664 union ody_pemx_vdmx_ob_hdrh {
3665 uint64_t u;
3666 struct ody_pemx_vdmx_ob_hdrh_s {
3667 uint64_t msg_tlp_hdr12 : 8;
3668 uint64_t msg_tlp_hdr13 : 8;
3669 uint64_t msg_tlp_hdr14 : 8;
3670 uint64_t msg_tlp_hdr15 : 8;
3671 uint64_t msg_vid : 16;
3672 uint64_t reserved_48_63 : 16;
3673 } s;
3674 /* struct ody_pemx_vdmx_ob_hdrh_s cn; */
3675 };
3676 typedef union ody_pemx_vdmx_ob_hdrh ody_pemx_vdmx_ob_hdrh_t;
3677
3678 static inline uint64_t ODY_PEMX_VDMX_OB_HDRH(uint64_t a, uint64_t b) __attribute__ ((pure, always_inline));
ODY_PEMX_VDMX_OB_HDRH(uint64_t a,uint64_t b)3679 static inline uint64_t ODY_PEMX_VDMX_OB_HDRH(uint64_t a, uint64_t b)
3680 {
3681 if ((a <= 15) && (b == 0))
3682 return 0x8e0000007f30ll + 0x1000000000ll * ((a) & 0xf);
3683 __ody_csr_fatal("PEMX_VDMX_OB_HDRH", 2, a, b, 0, 0, 0, 0);
3684 }
3685
3686 #define typedef_ODY_PEMX_VDMX_OB_HDRH(a, b) ody_pemx_vdmx_ob_hdrh_t
3687 #define bustype_ODY_PEMX_VDMX_OB_HDRH(a, b) CSR_TYPE_NCB
3688 #define basename_ODY_PEMX_VDMX_OB_HDRH(a, b) "PEMX_VDMX_OB_HDRH"
3689 #define device_bar_ODY_PEMX_VDMX_OB_HDRH(a, b) 0x0 /* PF_BAR0 */
3690 #define busnum_ODY_PEMX_VDMX_OB_HDRH(a, b) (a)
3691 #define arguments_ODY_PEMX_VDMX_OB_HDRH(a, b) (a), (b), -1, -1
3692
3693 /**
3694 * Register (NCB) pem#_vdm#_ob_hdrl
3695 *
3696 * PEM VDM Outbound Message Header Low Register
3697 * Vendor Defined Message Outbound Message Header Low Register.
3698 *
3699 * This register is not accessible through ROM scripts; see SCR_WRITE32_S[ADDR].
3700 *
3701 * This register is reset on core domain reset.
3702 *
3703 * This register is restricted to 64-bit access. Unsupported 32-bit access will
3704 * have unpredictable results, however will not cause an access hang or timeout.
3705 *
3706 * The operation of this register is restricted if PEMSEC()_VDM()_CFG[VDM_SEC_MODE]
3707 * is set to 1. Refer to the PEMSEC()_VDM()_CFG register description.
3708 */
3709 union ody_pemx_vdmx_ob_hdrl {
3710 uint64_t u;
3711 struct ody_pemx_vdmx_ob_hdrl_s {
3712 uint64_t msg_len : 6;
3713 uint64_t reserved_6_7 : 2;
3714 uint64_t msg_tag : 8;
3715 uint64_t trgt_id : 16;
3716 uint64_t msg_err : 1;
3717 uint64_t reserved_33_47 : 15;
3718 uint64_t msg_rt : 3;
3719 uint64_t reserved_51_63 : 13;
3720 } s;
3721 /* struct ody_pemx_vdmx_ob_hdrl_s cn; */
3722 };
3723 typedef union ody_pemx_vdmx_ob_hdrl ody_pemx_vdmx_ob_hdrl_t;
3724
3725 static inline uint64_t ODY_PEMX_VDMX_OB_HDRL(uint64_t a, uint64_t b) __attribute__ ((pure, always_inline));
ODY_PEMX_VDMX_OB_HDRL(uint64_t a,uint64_t b)3726 static inline uint64_t ODY_PEMX_VDMX_OB_HDRL(uint64_t a, uint64_t b)
3727 {
3728 if ((a <= 15) && (b == 0))
3729 return 0x8e0000007f20ll + 0x1000000000ll * ((a) & 0xf);
3730 __ody_csr_fatal("PEMX_VDMX_OB_HDRL", 2, a, b, 0, 0, 0, 0);
3731 }
3732
3733 #define typedef_ODY_PEMX_VDMX_OB_HDRL(a, b) ody_pemx_vdmx_ob_hdrl_t
3734 #define bustype_ODY_PEMX_VDMX_OB_HDRL(a, b) CSR_TYPE_NCB
3735 #define basename_ODY_PEMX_VDMX_OB_HDRL(a, b) "PEMX_VDMX_OB_HDRL"
3736 #define device_bar_ODY_PEMX_VDMX_OB_HDRL(a, b) 0x0 /* PF_BAR0 */
3737 #define busnum_ODY_PEMX_VDMX_OB_HDRL(a, b) (a)
3738 #define arguments_ODY_PEMX_VDMX_OB_HDRL(a, b) (a), (b), -1, -1
3739
3740 /**
3741 * Register (NCB) pem#_vdm#_ob_pld
3742 *
3743 * PEM VDM Outbound Message Payload Register
3744 * Vendor Defined Message Outbound Message Payload Register.
3745 *
3746 * This register is not accessible through ROM scripts; see SCR_WRITE32_S[ADDR].
3747 *
3748 * This register is reset on core domain reset.
3749 *
3750 * This register is restricted to 64-bit access. Unsupported 32-bit access will
3751 * have unpredictable results, however will not cause an access hang or timeout.
3752 *
3753 * The operation of this register is restricted if PEMSEC()_VDM()_CFG[VDM_SEC_MODE]
3754 * is set to 1. Refer to the PEMSEC()_VDM()_CFG register description.
3755 */
3756 union ody_pemx_vdmx_ob_pld {
3757 uint64_t u;
3758 struct ody_pemx_vdmx_ob_pld_s {
3759 uint64_t ob_msg_pld : 64;
3760 } s;
3761 /* struct ody_pemx_vdmx_ob_pld_s cn; */
3762 };
3763 typedef union ody_pemx_vdmx_ob_pld ody_pemx_vdmx_ob_pld_t;
3764
3765 static inline uint64_t ODY_PEMX_VDMX_OB_PLD(uint64_t a, uint64_t b) __attribute__ ((pure, always_inline));
ODY_PEMX_VDMX_OB_PLD(uint64_t a,uint64_t b)3766 static inline uint64_t ODY_PEMX_VDMX_OB_PLD(uint64_t a, uint64_t b)
3767 {
3768 if ((a <= 15) && (b == 0))
3769 return 0x8e0000007f40ll + 0x1000000000ll * ((a) & 0xf);
3770 __ody_csr_fatal("PEMX_VDMX_OB_PLD", 2, a, b, 0, 0, 0, 0);
3771 }
3772
3773 #define typedef_ODY_PEMX_VDMX_OB_PLD(a, b) ody_pemx_vdmx_ob_pld_t
3774 #define bustype_ODY_PEMX_VDMX_OB_PLD(a, b) CSR_TYPE_NCB
3775 #define basename_ODY_PEMX_VDMX_OB_PLD(a, b) "PEMX_VDMX_OB_PLD"
3776 #define device_bar_ODY_PEMX_VDMX_OB_PLD(a, b) 0x0 /* PF_BAR0 */
3777 #define busnum_ODY_PEMX_VDMX_OB_PLD(a, b) (a)
3778 #define arguments_ODY_PEMX_VDMX_OB_PLD(a, b) (a), (b), -1, -1
3779
3780 /**
3781 * Register (NCB) pem#_vdm#_status
3782 *
3783 * PEM VDM Status Register
3784 * This register provides status of the Vendor Defined Message (VDM) inbound
3785 * and outbound message mailboxes.
3786 *
3787 * This register is not accessible through ROM scripts; see SCR_WRITE32_S[ADDR].
3788 *
3789 * This register is reset on core domain reset.
3790 *
3791 * This register is restricted to 64-bit access. Unsupported 32-bit access will
3792 * have unpredictable results, however will not cause an access hang or timeout.
3793 *
3794 * The operation of this register is restricted if PEMSEC()_VDM()_CFG[VDM_SEC_MODE]
3795 * is set to 1. Refer to the PEMSEC()_VDM()_CFG register description.
3796 */
3797 union ody_pemx_vdmx_status {
3798 uint64_t u;
3799 struct ody_pemx_vdmx_status_s {
3800 uint64_t ob_mbx_busy : 1;
3801 uint64_t reserved_1 : 1;
3802 uint64_t ib_mbx_err : 1;
3803 uint64_t ob_mbx_err : 1;
3804 uint64_t ob_mbx_sts : 14;
3805 uint64_t ib_mbx_sts : 13;
3806 uint64_t ib_mbx_rdy : 1;
3807 uint64_t reserved_32_63 : 32;
3808 } s;
3809 /* struct ody_pemx_vdmx_status_s cn; */
3810 };
3811 typedef union ody_pemx_vdmx_status ody_pemx_vdmx_status_t;
3812
3813 static inline uint64_t ODY_PEMX_VDMX_STATUS(uint64_t a, uint64_t b) __attribute__ ((pure, always_inline));
ODY_PEMX_VDMX_STATUS(uint64_t a,uint64_t b)3814 static inline uint64_t ODY_PEMX_VDMX_STATUS(uint64_t a, uint64_t b)
3815 {
3816 if ((a <= 15) && (b == 0))
3817 return 0x8e0000007f10ll + 0x1000000000ll * ((a) & 0xf);
3818 __ody_csr_fatal("PEMX_VDMX_STATUS", 2, a, b, 0, 0, 0, 0);
3819 }
3820
3821 #define typedef_ODY_PEMX_VDMX_STATUS(a, b) ody_pemx_vdmx_status_t
3822 #define bustype_ODY_PEMX_VDMX_STATUS(a, b) CSR_TYPE_NCB
3823 #define basename_ODY_PEMX_VDMX_STATUS(a, b) "PEMX_VDMX_STATUS"
3824 #define device_bar_ODY_PEMX_VDMX_STATUS(a, b) 0x0 /* PF_BAR0 */
3825 #define busnum_ODY_PEMX_VDMX_STATUS(a, b) (a)
3826 #define arguments_ODY_PEMX_VDMX_STATUS(a, b) (a), (b), -1, -1
3827
3828 #endif /* __ODY_CSRS_PEM_H__ */
3829