1 #ifndef __ODY_CSRS_RST_H__
2 #define __ODY_CSRS_RST_H__
3 /* This file is auto-generated. Do not edit */
4
5 /***********************license start***********************************
6 * Copyright (C) 2021-2026 Marvell.
7 * SPDX-License-Identifier: BSD-3-Clause
8 * https://spdx.org/licenses
9 ***********************license end**************************************/
10
11
12 /**
13 * @file
14 *
15 * Configuration and status register (CSR) address and type definitions for
16 * RST.
17 *
18 * This file is auto generated. Do not edit.
19 *
20 */
21
22 /**
23 * Enumeration rst_bar_e
24 *
25 * RST Base Address Register Enumeration
26 * Enumerates the base address registers.
27 */
28 #define ODY_RST_BAR_E_RST_PF_BAR0 (0x87e006000000ll)
29 #define ODY_RST_BAR_E_RST_PF_BAR0_SIZE 0x10000ull
30 #define ODY_RST_BAR_E_RST_PF_BAR2 (0x87e00a000000ll)
31 #define ODY_RST_BAR_E_RST_PF_BAR2_SIZE 0x10000ull
32 #define ODY_RST_BAR_E_RST_PF_BAR4 (0x87e006f00000ll)
33 #define ODY_RST_BAR_E_RST_PF_BAR4_SIZE 0x100000ull
34
35 /**
36 * Enumeration rst_boot_method_e
37 *
38 * RST Primary Boot-strap Method Enumeration
39 * Enumerates the primary (first choice) and secondary (second choice) boot
40 * device. Primary boot method is selected with the straps
41 * GPIO_STRAP_PIN_E::BOOT_METHOD2..0, and secondary is selected with the straps
42 * GPIO_STRAP_PIN_E::BOOT_METHOD5..3.
43 *
44 * To disable the secondary method, use ::REMOTE.
45 */
46 #define ODY_RST_BOOT_METHOD_E_I3C3 (0)
47 #define ODY_RST_BOOT_METHOD_E_I3C4 (1)
48 #define ODY_RST_BOOT_METHOD_E_REMOTE (7)
49 #define ODY_RST_BOOT_METHOD_E_SPI0_CS0 (2)
50 #define ODY_RST_BOOT_METHOD_E_SPI0_CS1 (3)
51 #define ODY_RST_BOOT_METHOD_E_SPI1_CS0 (4)
52 #define ODY_RST_BOOT_METHOD_E_SPI1_CS1 (5)
53 #define ODY_RST_BOOT_METHOD_E_UART (6)
54
55 /**
56 * Enumeration rst_dev_e
57 *
58 * Programmable Reset Device Enumeration
59 * Enumerates devices that have programmable reset domains, and index {a} of RST_DEV_MAP().
60 */
61 #define ODY_RST_DEV_E_AVS (1)
62 #define ODY_RST_DEV_E_EMMC (0x19)
63 #define ODY_RST_DEV_E_I3CX(a) (0x10 + (a))
64 #define ODY_RST_DEV_E_MPIX(a) (2 + (a))
65 #define ODY_RST_DEV_E_RFIFX(a) (0x28 + (a))
66 #define ODY_RST_DEV_E_ROC_OCLA (0x18)
67 #define ODY_RST_DEV_E_SGPIO (0x17)
68 #define ODY_RST_DEV_E_SMI (0x16)
69 #define ODY_RST_DEV_E_TWSX(a) (4 + (a))
70 #define ODY_RST_DEV_E_UAAX(a) (0x1a + (a))
71
72 /**
73 * Enumeration rst_domain_e
74 *
75 * RST Domain Enumeration
76 * This enumerates the values of RST_DEV_MAP()[DMN].
77 */
78 #define ODY_RST_DOMAIN_E_BPHY (5)
79 #define ODY_RST_DOMAIN_E_CHIP (0)
80 #define ODY_RST_DOMAIN_E_COLD (6)
81 #define ODY_RST_DOMAIN_E_CORE (1)
82 #define ODY_RST_DOMAIN_E_MCP (2)
83 #define ODY_RST_DOMAIN_E_OFF (7)
84 #define ODY_RST_DOMAIN_E_SCP (3)
85 #define ODY_RST_DOMAIN_E_XCP2 (4)
86
87 /**
88 * Enumeration rst_int_vec_e
89 *
90 * RST MSI-X Vector Enumeration
91 * Enumerates the MSI-X interrupt vectors.
92 */
93 #define ODY_RST_INT_VEC_E_INTS (0)
94
95 /**
96 * Enumeration rst_pll_e
97 *
98 * RST PLL Enumeration
99 * Enumerates the values of RST_PLL() and RST_MAN_PLL().
100 */
101 #define ODY_RST_PLL_E_BCLK (0xc)
102 #define ODY_RST_PLL_E_BCNCLK (0xd)
103 #define ODY_RST_PLL_E_CPTCLK (5)
104 #define ODY_RST_PLL_E_DFICLK (4)
105 #define ODY_RST_PLL_E_DSPCLK (0xe)
106 #define ODY_RST_PLL_E_IOCLK (3)
107 #define ODY_RST_PLL_E_JESDCLK (0xf)
108 #define ODY_RST_PLL_E_MESHCLK (1)
109 #define ODY_RST_PLL_E_NCLK (0xb)
110 #define ODY_RST_PLL_E_NETCLK (2)
111 #define ODY_RST_PLL_E_PCIE0CLK (6)
112 #define ODY_RST_PLL_E_PCIE1CLK (7)
113 #define ODY_RST_PLL_E_PCIE2CLK (8)
114 #define ODY_RST_PLL_E_PCIE3CLK (9)
115 #define ODY_RST_PLL_E_SCLK (0)
116
117 /**
118 * Enumeration rst_pll_sel_e
119 *
120 * RST PLL Selection Enumeration
121 * Enumerates the values of RST_PLL()[NEXT_PLL_SEL] and RST_PLL()[CUR_PLL_SEL].
122 */
123 #define ODY_RST_PLL_SEL_E_ARO (6)
124 #define ODY_RST_PLL_SEL_E_BYPASS (2)
125 #define ODY_RST_PLL_SEL_E_OFF (3)
126 #define ODY_RST_PLL_SEL_E_PLL0 (4)
127 #define ODY_RST_PLL_SEL_E_PLL1 (5)
128 #define ODY_RST_PLL_SEL_E_REFCLK (1)
129 #define ODY_RST_PLL_SEL_E_RSVD (7)
130 #define ODY_RST_PLL_SEL_E_RUNT (0)
131
132 /**
133 * Enumeration rst_pllro_cfg_status_mux_e
134 *
135 * RST PLLRO Status Mux Selection Enumeration
136 * This enumerates the values of RST_TEST_PLL_RSVD5_S[PLLRO_CFG_STATUS_MUX].
137 * All other bits are assumed to be 0.
138 */
139 #define ODY_RST_PLLRO_CFG_STATUS_MUX_E_RST_EROSEL_RESULT (0)
140 #define ODY_RST_PLLRO_CFG_STATUS_MUX_E_RST_PROFILE_ARO_CLK_CNT (4)
141 #define ODY_RST_PLLRO_CFG_STATUS_MUX_E_RST_PROFILE_DELTA (5)
142 #define ODY_RST_PLLRO_CFG_STATUS_MUX_E_RST_PROFILE_REF_CLK_CNT (1)
143 #define ODY_RST_PLLRO_CFG_STATUS_MUX_E_RST_PROFILE_VDROOP (6)
144 #define ODY_RST_PLLRO_CFG_STATUS_MUX_E_RST_PROFILE_VDROOP_SUM (7)
145 #define ODY_RST_PLLRO_CFG_STATUS_MUX_E_RST_PROFILE_VDROOP_TOTAL_CNT (2)
146 #define ODY_RST_PLLRO_CFG_STATUS_MUX_E_RST_ROU_ROS_TRGT (3)
147
148 /**
149 * Enumeration rst_source_e
150 *
151 * RST Cause Enumeration
152 * Enumerates the reset sources for both reset domain mapping and cause of last reset,
153 * corresponding to the bit numbers of RST_LBOOT.
154 */
155 #define ODY_RST_SOURCE_E_BPHY_RESET_PIN (0x30)
156 #define ODY_RST_SOURCE_E_BPHY_SOFT (0x33)
157 #define ODY_RST_SOURCE_E_CHIPKILL (4)
158 #define ODY_RST_SOURCE_E_CHIP_RESET_PIN (2)
159 #define ODY_RST_SOURCE_E_CHIP_SOFT (3)
160 #define ODY_RST_SOURCE_E_COLD_SOFT (1)
161 #define ODY_RST_SOURCE_E_CORE_RESET_PIN (0xb)
162 #define ODY_RST_SOURCE_E_CORE_SOFT (0xc)
163 #define ODY_RST_SOURCE_E_CORE_WDOG (0xd)
164 #define ODY_RST_SOURCE_E_DCOK_PIN (0)
165 #define ODY_RST_SOURCE_E_MCP_RESET_PIN (8)
166 #define ODY_RST_SOURCE_E_MCP_SOFT (9)
167 #define ODY_RST_SOURCE_E_MCP_SYSREQ (0x35)
168 #define ODY_RST_SOURCE_E_MCP_WDOG (0xa)
169 #define ODY_RST_SOURCE_E_PEM_CHIPX(a) (0x11 + 2 * (a))
170 #define ODY_RST_SOURCE_E_PEM_COREX(a) (0x10 + 2 * (a))
171 #define ODY_RST_SOURCE_E_RSVD_32 (0x32)
172 #define ODY_RST_SOURCE_E_RSVD_E (0xe)
173 #define ODY_RST_SOURCE_E_RSVD_F (0xf)
174 #define ODY_RST_SOURCE_E_SCP_RESET_PIN (5)
175 #define ODY_RST_SOURCE_E_SCP_SOFT (6)
176 #define ODY_RST_SOURCE_E_SCP_SYSREQ (0x36)
177 #define ODY_RST_SOURCE_E_SCP_WDOG (7)
178 #define ODY_RST_SOURCE_E_XCP2_SOFT (0x31)
179 #define ODY_RST_SOURCE_E_XCP2_SYSREQ (0x37)
180 #define ODY_RST_SOURCE_E_XCP2_WDOG (0x34)
181
182 /**
183 * Enumeration rst_test_pll_rsvd4_e
184 *
185 * RST TEST_PLL[TEST_RSVD]=4 Enumeration
186 * This enumerates the values of RST_TEST_PLL()[STOP_CNT\<\>] bits.
187 * All other bits are assumed to be 0.
188 */
189 #define ODY_RST_TEST_PLL_RSVD4_E_PLL0_VOLTAGE0 (0)
190 #define ODY_RST_TEST_PLL_RSVD4_E_PLL0_VOLTAGE1 (1)
191 #define ODY_RST_TEST_PLL_RSVD4_E_PLL0_VOLTAGE2 (2)
192 #define ODY_RST_TEST_PLL_RSVD4_E_PLL1_VOLTAGE0 (4)
193 #define ODY_RST_TEST_PLL_RSVD4_E_PLL1_VOLTAGE1 (5)
194 #define ODY_RST_TEST_PLL_RSVD4_E_PLL1_VOLTAGE2 (6)
195 #define ODY_RST_TEST_PLL_RSVD4_E_TEST_ID0 (7)
196 #define ODY_RST_TEST_PLL_RSVD4_E_TEST_ID1 (8)
197 #define ODY_RST_TEST_PLL_RSVD4_E_TEST_ID2 (9)
198 #define ODY_RST_TEST_PLL_RSVD4_E_TEST_ID3 (0xa)
199 #define ODY_RST_TEST_PLL_RSVD4_E_TEST_ID4 (0xb)
200
201 /**
202 * Structure rst_boot_stat_s
203 *
204 * BOOT_STATUS field Structure
205 * The ROM boot code stores this data in the RST_BOOT_STATUS register, once per each boot attempt.
206 * Bits 31:0 For Primary partition.
207 * Bits 63:32 For Secondary partition.
208 */
209 union ody_rst_boot_stat_s {
210 uint64_t u;
211 struct ody_rst_boot_stat_s_s {
212 uint64_t p_local_error_code : 16;
213 uint64_t p_error_module : 8;
214 uint64_t reserved_24_27 : 4;
215 uint64_t p_boot_method : 3;
216 uint64_t p_image_partition : 1;
217 uint64_t s_local_error_code : 16;
218 uint64_t s_error_module : 8;
219 uint64_t reserved_56_59 : 4;
220 uint64_t s_boot_method : 3;
221 uint64_t s_image_partition : 1;
222 } s;
223 /* struct ody_rst_boot_stat_s_s cn; */
224 };
225
226 /**
227 * Structure rst_erosel_result_s
228 *
229 * RST EROSEL STATUS Structure
230 * This structure describes the fields used in MRC_ARO_STATUS when a previous write to
231 * RST_TEST_PLL\<RST_PLL_E::MESHCLK\>[RSVD] = 5 with RST_TEST_RSVD5_S[PLLRO_CFG_STATUS_MUX] = 0.
232 * This structure describes the fields used in APA_ARO_STATUSn when a previous write to
233 * APA\<n\>_TEST_PLL[RSVD] = 5 with RST_TEST_PLL_RSVD5_S[PLLRO_CFG_STATUS_MUX] = 0.
234 * All other bits are assumed to be 0.
235 */
236 union ody_rst_erosel_result_s {
237 uint32_t u;
238 struct ody_rst_erosel_result_s_s {
239 uint32_t reserved_0_9 : 10;
240 uint32_t dd_cell_vdroop : 1;
241 uint32_t calib_lock_status : 1;
242 uint32_t ros_calib_min_status : 1;
243 uint32_t rou_calib_min_status : 1;
244 uint32_t reserved_14_19 : 6;
245 uint32_t dd_calib_error_code : 2;
246 uint32_t dd_calib_error : 1;
247 uint32_t dd_calib_done : 1;
248 uint32_t dd_calib_ecnt_erosel_result : 8;
249 } s;
250 /* struct ody_rst_erosel_result_s_s cn; */
251 };
252
253 /**
254 * Structure rst_profile_aro_clk_cnt_s
255 *
256 * RST PLLRO Profile ARO Clock Count Structure
257 * This structure describes the fields used in MRC_ARO_STATUS when a previous write to
258 * RST_TEST_PLL\<RST_PLL_E::MESHCLK\>[RSVD] = 5 with RST_TEST_RSVD5_S[PLLRO_CFG_STATUS_MUX] = 4.
259 * This structure describes the fields used in APA_ARO_STATUSn when a previous write to
260 * APA\<n\>_TEST_PLL[RSVD] = 5 with RST_TEST_PLL_RSVD5_S[PLLRO_CFG_STATUS_MUX] = 4.
261 * All other bits are assumed to be 0.
262 */
263 union ody_rst_profile_aro_clk_cnt_s {
264 uint32_t u;
265 struct ody_rst_profile_aro_clk_cnt_s_s {
266 uint32_t profile_aro_clk_cnt : 31;
267 uint32_t v : 1;
268 } s;
269 /* struct ody_rst_profile_aro_clk_cnt_s_s cn; */
270 };
271
272 /**
273 * Structure rst_profile_delta_s
274 *
275 * RST PLLRO Profile Delta Structure
276 * This structure describes the fields used in MRC_ARO_STATUS when a previous write to
277 * RST_TEST_PLL\<RST_PLL_E::MESHCLK\>[RSVD] = 5 with RST_TEST_RSVD5_S[PLLRO_CFG_STATUS_MUX] = 5.
278 * This structure describes the fields used in APA_ARO_STATUSn when a previous write to
279 * APA\<n\>_TEST_PLL[RSVD] = 5 with RST_TEST_PLL_RSVD5_S[PLLRO_CFG_STATUS_MUX] = 5.
280 * All other bits are assumed to be 0.
281 */
282 union ody_rst_profile_delta_s {
283 uint32_t u;
284 struct ody_rst_profile_delta_s_s {
285 uint32_t profile_max_pos_cpu_cnt_delta : 14;
286 uint32_t profile_max_neg_cpu_cnt_delta : 14;
287 uint32_t reserved_28_30 : 3;
288 uint32_t v : 1;
289 } s;
290 /* struct ody_rst_profile_delta_s_s cn; */
291 };
292
293 /**
294 * Structure rst_profile_ref_clk_cnt_s
295 *
296 * RST PLLRO Profile Refclk Count Structure
297 * This structure describes the fields used in MRC_ARO_STATUS when a previous write to
298 * RST_TEST_PLL\<RST_PLL_E::MESHCLK\>[RSVD] = 5 with RST_TEST_RSVD5_S[PLLRO_CFG_STATUS_MUX] = 1.
299 * This structure describes the fields used in APA_ARO_STATUSn when a previous write to
300 * APA\<n\>_TEST_PLL[RSVD] = 5 with RST_TEST_PLL_RSVD5_S[PLLRO_CFG_STATUS_MUX] = 1.
301 * All other bits are assumed to be 0.
302 */
303 union ody_rst_profile_ref_clk_cnt_s {
304 uint32_t u;
305 struct ody_rst_profile_ref_clk_cnt_s_s {
306 uint32_t profile_ref_clk_cnt : 31;
307 uint32_t v : 1;
308 } s;
309 /* struct ody_rst_profile_ref_clk_cnt_s_s cn; */
310 };
311
312 /**
313 * Structure rst_profile_vdroop_s
314 *
315 * RST PLLRO Profile Vdroop Structure
316 * This structure describes the fields used in MRC_ARO_STATUS when a previous write to
317 * RST_TEST_PLL\<RST_PLL_E::MESHCLK\>[RSVD] = 5 with RST_TEST_RSVD5_S[PLLRO_CFG_STATUS_MUX] = 6.
318 * This structure describes the fields used in APA_ARO_STATUSn when a previous write to
319 * APA\<n\>_TEST_PLL[RSVD] = 5 with RST_TEST_PLL_RSVD5_S[PLLRO_CFG_STATUS_MUX] = 6.
320 * All other bits are assumed to be 0.
321 */
322 union ody_rst_profile_vdroop_s {
323 uint32_t u;
324 struct ody_rst_profile_vdroop_s_s {
325 uint32_t profile_vdroop_max_duration : 21;
326 uint32_t profile_vdroop_edge_cnt : 10;
327 uint32_t v : 1;
328 } s;
329 /* struct ody_rst_profile_vdroop_s_s cn; */
330 };
331
332 /**
333 * Structure rst_profile_vdroop_sum_s
334 *
335 * RST PLLRO Profile ARO Clock Count Structure
336 * This structure describes the fields used in MRC_ARO_STATUS when a previous write to
337 * RST_TEST_PLL\<RST_PLL_E::MESHCLK\>[RSVD] = 5 with RST_TEST_RSVD5_S[PLLRO_CFG_STATUS_MUX] = 7.
338 * This structure describes the fields used in APA_ARO_STATUSn when a previous write to
339 * APA\<n\>_TEST_PLL[RSVD] = 5 with RST_TEST_PLL_RSVD5_S[PLLRO_CFG_STATUS_MUX] = 7.
340 * All other bits are assumed to be 0.
341 */
342 union ody_rst_profile_vdroop_sum_s {
343 uint32_t u;
344 struct ody_rst_profile_vdroop_sum_s_s {
345 uint32_t profile_vdroop_sum_duration : 31;
346 uint32_t v : 1;
347 } s;
348 /* struct ody_rst_profile_vdroop_sum_s_s cn; */
349 };
350
351 /**
352 * Structure rst_profile_vdroop_total_cnt_s
353 *
354 * RST PLLRO Profile Refclk Count Structure
355 * This structure describes the fields used in MRC_ARO_STATUS when a previous write to
356 * RST_TEST_PLL\<RST_PLL_E::MESHCLK\>[RSVD] = 5 with RST_TEST_RSVD5_S[PLLRO_CFG_STATUS_MUX] = 2.
357 * This structure describes the fields used in APA_ARO_STATUSn when a previous write to
358 * APA\<n\>_TEST_PLL[RSVD] = 5 with RST_TEST_PLL_RSVD5_S[PLLRO_CFG_STATUS_MUX] = 2.
359 * All other bits are assumed to be 0.
360 */
361 union ody_rst_profile_vdroop_total_cnt_s {
362 uint32_t u;
363 struct ody_rst_profile_vdroop_total_cnt_s_s {
364 uint32_t profile_vdroop_total_cnt : 31;
365 uint32_t v : 1;
366 } s;
367 /* struct ody_rst_profile_vdroop_total_cnt_s_s cn; */
368 };
369
370 /**
371 * Structure rst_rou_ros_trgt_s
372 *
373 * RST PLLRO ROU and ROS Target Structure
374 * This structure describes the fields used in MRC_ARO_STATUS when a previous write to
375 * RST_TEST_PLL\<RST_PLL_E::MESHCLK\>[RSVD] = 5 with RST_TEST_RSVD5_S[PLLRO_CFG_STATUS_MUX] = 3.
376 * This structure describes the fields used in APA_ARO_STATUSn when a previous write to
377 * APA\<n\>_TEST_PLL[RSVD] = 5 with RST_TEST_PLL_RSVD5_S[PLLRO_CFG_STATUS_MUX] = 3.
378 * All other bits are assumed to be 0.
379 */
380 union ody_rst_rou_ros_trgt_s {
381 uint32_t u;
382 struct ody_rst_rou_ros_trgt_s_s {
383 uint32_t ros_trgt_p1 : 8;
384 uint32_t ros_trgt_p2 : 8;
385 uint32_t rou_trgt_p1 : 8;
386 uint32_t rou_trgt_p2 : 8;
387 } s;
388 /* struct ody_rst_rou_ros_trgt_s_s cn; */
389 };
390
391 /**
392 * Structure rst_test_pll_rsvd4_s
393 *
394 * RST TEST_PLL[TEST_RSVD]=4 Structure
395 * This structure specifies the values of RST_TEST_PLL()[STOP_CNT\<\>] bits.
396 * All other bits are assumed to be 0.
397 */
398 union ody_rst_test_pll_rsvd4_s {
399 uint32_t u;
400 struct ody_rst_test_pll_rsvd4_s_s {
401 uint32_t pll0_voltage : 3;
402 uint32_t pll1_voltage : 4;
403 uint32_t test_id : 5;
404 uint32_t reserved_12_31 : 20;
405 } s;
406 /* struct ody_rst_test_pll_rsvd4_s_s cn; */
407 };
408
409 /**
410 * Structure rst_test_pll_rsvd5_s
411 *
412 * RST TEST_PLL[TEST_RSVD]=5 Structure
413 * This structure specifies the values of RST_TEST_PLL()[STOP_CNT\<\>] bits.
414 * All other bits are assumed to be 0.
415 */
416 union ody_rst_test_pll_rsvd5_s {
417 uint32_t u;
418 struct ody_rst_test_pll_rsvd5_s_s {
419 uint32_t pllro_cfg_usr_rst : 1;
420 uint32_t pllro_cfg_div_en : 1;
421 uint32_t pllro_cfg_clkout_en : 1;
422 uint32_t pllro_cfg_usr_sel_ro_trgt : 1;
423 uint32_t pllro_cfg_usr_cntrs_init_ld : 1;
424 uint32_t pllro_cfg_calib_mode : 1;
425 uint32_t pllro_cfg_ref_cnt_frq_grd : 2;
426 uint32_t pllro_cfg_locktime_opt_dis : 1;
427 uint32_t pllro_cfg_select_u : 1;
428 uint32_t pllro_cfg_select_s : 1;
429 uint32_t pllro_cfg_usr_update_ro_trgt : 1;
430 uint32_t pllro_cfg_ref_cnt_fctr : 4;
431 uint32_t aro_mux_disable : 1;
432 uint32_t pllro_cfg_status_mux : 3;
433 uint32_t droop_divider : 2;
434 uint32_t droop_recovery : 6;
435 uint32_t pll0_uses_droop : 1;
436 uint32_t pll1_uses_droop : 1;
437 uint32_t droop_test : 1;
438 uint32_t reserved_31 : 1;
439 } s;
440 /* struct ody_rst_test_pll_rsvd5_s_s cn; */
441 };
442
443 /**
444 * Structure rst_test_pll_rsvd6_s
445 *
446 * RST TEST_PLL[TEST_RSVD]=6 Structure
447 * This structure defines the values of RST_TEST_PLL()[STOP_CNT\<\>] bits.
448 * All other bits are assumed to be 0.
449 */
450 union ody_rst_test_pll_rsvd6_s {
451 uint32_t u;
452 struct ody_rst_test_pll_rsvd6_s_s {
453 uint32_t pllro_cfg_safe_ro_trgt : 8;
454 uint32_t pllro_cfg_rou_trgt_min_val : 8;
455 uint32_t pllro_cfg_ros_trgt_min_val : 8;
456 uint32_t reserved_24_31 : 8;
457 } s;
458 /* struct ody_rst_test_pll_rsvd6_s_s cn; */
459 };
460
461 /**
462 * Structure rst_test_pll_rsvd7_droop_s
463 *
464 * RST TEST_PLL[TEST_RSVD]=7 Droop Detector Structure
465 * This structure defines the values of RST_TEST_PLL()[STOP_CNT\<\>] bits.
466 * All other bits are assumed to be 0.
467 */
468 union ody_rst_test_pll_rsvd7_droop_s {
469 uint32_t u;
470 struct ody_rst_test_pll_rsvd7_droop_s_s {
471 uint32_t erosel : 4;
472 uint32_t ecnt : 4;
473 uint32_t srosel : 4;
474 uint32_t scnt : 2;
475 uint32_t dd_cell_enable : 1;
476 uint32_t dd_calb_go : 1;
477 uint32_t aro_slowdown : 4;
478 uint32_t dd_recovery_delay : 4;
479 uint32_t frequency_governer_disable : 1;
480 uint32_t dd_ctrl_enable : 1;
481 uint32_t profile_enable : 1;
482 uint32_t aro_target_find_go : 1;
483 uint32_t profile_window_size : 2;
484 uint32_t profile_win_start : 1;
485 uint32_t profile_one_shot : 1;
486 } s;
487 /* struct ody_rst_test_pll_rsvd7_droop_s_s cn; */
488 };
489
490 /**
491 * Structure rst_test_pll_rsvd7_s
492 *
493 * RST TEST_PLL[TEST_RSVD]=7 Structure
494 * This enumerates the values of RST_TEST_PLL()[STOP_CNT\<\>] bits.
495 * All other bits are assumed to be 0.
496 */
497 union ody_rst_test_pll_rsvd7_s {
498 uint32_t u;
499 struct ody_rst_test_pll_rsvd7_s_s {
500 uint32_t pllro_cfg_usr_rou_trgt_p2 : 8;
501 uint32_t pllro_cfg_usr_rou_trgt_p1 : 8;
502 uint32_t pllro_cfg_usr_ros_trgt_p2 : 8;
503 uint32_t pllro_cfg_usr_ros_trgt_p1 : 8;
504 } s;
505 /* struct ody_rst_test_pll_rsvd7_s_s cn; */
506 };
507
508 /**
509 * Register (RSL) rst_ap_available#
510 *
511 * RST Physical Core Availability Register
512 * This register is not accessible through ROM scripts; see SCR_WRITE32_S[ADDR].
513 */
514 union ody_rst_ap_availablex {
515 uint64_t u;
516 struct ody_rst_ap_availablex_s {
517 uint64_t present : 64;
518 } s;
519 /* struct ody_rst_ap_availablex_s cn; */
520 };
521 typedef union ody_rst_ap_availablex ody_rst_ap_availablex_t;
522
523 static inline uint64_t ODY_RST_AP_AVAILABLEX(uint64_t a) __attribute__ ((pure, always_inline));
ODY_RST_AP_AVAILABLEX(uint64_t a)524 static inline uint64_t ODY_RST_AP_AVAILABLEX(uint64_t a)
525 {
526 if (a <= 3)
527 return 0x87e006001730ll + 8ll * ((a) & 0x3);
528 __ody_csr_fatal("RST_AP_AVAILABLEX", 1, a, 0, 0, 0, 0, 0);
529 }
530
531 #define typedef_ODY_RST_AP_AVAILABLEX(a) ody_rst_ap_availablex_t
532 #define bustype_ODY_RST_AP_AVAILABLEX(a) CSR_TYPE_RSL
533 #define basename_ODY_RST_AP_AVAILABLEX(a) "RST_AP_AVAILABLEX"
534 #define device_bar_ODY_RST_AP_AVAILABLEX(a) 0x0 /* PF_BAR0 */
535 #define busnum_ODY_RST_AP_AVAILABLEX(a) (a)
536 #define arguments_ODY_RST_AP_AVAILABLEX(a) (a), -1, -1, -1
537
538 /**
539 * Register (RSL) rst_bist_active
540 *
541 * RST BIST Active Status Register
542 * This register is not accessible through ROM scripts; see SCR_WRITE32_S[ADDR].
543 */
544 union ody_rst_bist_active {
545 uint64_t u;
546 struct ody_rst_bist_active_s {
547 uint64_t chip : 1;
548 uint64_t core : 1;
549 uint64_t mcp : 1;
550 uint64_t scp : 1;
551 uint64_t bphy : 1;
552 uint64_t xcp2 : 1;
553 uint64_t csr : 1;
554 uint64_t reserved_7_63 : 57;
555 } s;
556 /* struct ody_rst_bist_active_s cn; */
557 };
558 typedef union ody_rst_bist_active ody_rst_bist_active_t;
559
560 #define ODY_RST_BIST_ACTIVE ODY_RST_BIST_ACTIVE_FUNC()
561 static inline uint64_t ODY_RST_BIST_ACTIVE_FUNC(void) __attribute__ ((pure, always_inline));
ODY_RST_BIST_ACTIVE_FUNC(void)562 static inline uint64_t ODY_RST_BIST_ACTIVE_FUNC(void)
563 {
564 return 0x87e006001890ll;
565 }
566
567 #define typedef_ODY_RST_BIST_ACTIVE ody_rst_bist_active_t
568 #define bustype_ODY_RST_BIST_ACTIVE CSR_TYPE_RSL
569 #define basename_ODY_RST_BIST_ACTIVE "RST_BIST_ACTIVE"
570 #define device_bar_ODY_RST_BIST_ACTIVE 0x0 /* PF_BAR0 */
571 #define busnum_ODY_RST_BIST_ACTIVE 0
572 #define arguments_ODY_RST_BIST_ACTIVE -1, -1, -1, -1
573
574 /**
575 * Register (RSL) rst_boot
576 *
577 * RST Boot Register
578 * This register is not accessible through ROM scripts; see SCR_WRITE32_S[ADDR].
579 */
580 union ody_rst_boot {
581 uint64_t u;
582 struct ody_rst_boot_s {
583 uint64_t rboot_pin : 1;
584 uint64_t rboot_scp : 1;
585 uint64_t rboot_mcp : 1;
586 uint64_t rboot_xcp2 : 1;
587 uint64_t reserved_4_62 : 59;
588 uint64_t chipkill : 1;
589 } s;
590 /* struct ody_rst_boot_s cn; */
591 };
592 typedef union ody_rst_boot ody_rst_boot_t;
593
594 #define ODY_RST_BOOT ODY_RST_BOOT_FUNC()
595 static inline uint64_t ODY_RST_BOOT_FUNC(void) __attribute__ ((pure, always_inline));
ODY_RST_BOOT_FUNC(void)596 static inline uint64_t ODY_RST_BOOT_FUNC(void)
597 {
598 return 0x87e006001600ll;
599 }
600
601 #define typedef_ODY_RST_BOOT ody_rst_boot_t
602 #define bustype_ODY_RST_BOOT CSR_TYPE_RSL
603 #define basename_ODY_RST_BOOT "RST_BOOT"
604 #define device_bar_ODY_RST_BOOT 0x0 /* PF_BAR0 */
605 #define busnum_ODY_RST_BOOT 0
606 #define arguments_ODY_RST_BOOT -1, -1, -1, -1
607
608 /**
609 * Register (RSL) rst_boot_status
610 *
611 * RST Boot Status Register
612 * This register is not accessible through ROM scripts; see SCR_WRITE32_S[ADDR].
613 */
614 union ody_rst_boot_status {
615 uint64_t u;
616 struct ody_rst_boot_status_s {
617 uint64_t stat0 : 16;
618 uint64_t stat1 : 16;
619 uint64_t stat2 : 16;
620 uint64_t stat3 : 16;
621 } s;
622 /* struct ody_rst_boot_status_s cn; */
623 };
624 typedef union ody_rst_boot_status ody_rst_boot_status_t;
625
626 #define ODY_RST_BOOT_STATUS ODY_RST_BOOT_STATUS_FUNC()
627 static inline uint64_t ODY_RST_BOOT_STATUS_FUNC(void) __attribute__ ((pure, always_inline));
ODY_RST_BOOT_STATUS_FUNC(void)628 static inline uint64_t ODY_RST_BOOT_STATUS_FUNC(void)
629 {
630 return 0x87e006001800ll;
631 }
632
633 #define typedef_ODY_RST_BOOT_STATUS ody_rst_boot_status_t
634 #define bustype_ODY_RST_BOOT_STATUS CSR_TYPE_RSL
635 #define basename_ODY_RST_BOOT_STATUS "RST_BOOT_STATUS"
636 #define device_bar_ODY_RST_BOOT_STATUS 0x0 /* PF_BAR0 */
637 #define busnum_ODY_RST_BOOT_STATUS 0
638 #define arguments_ODY_RST_BOOT_STATUS -1, -1, -1, -1
639
640 /**
641 * Register (RSL) rst_bphy_domain_w1c
642 *
643 * RST BPHY Domain Soft Reset Clear Register
644 * This register is not accessible through ROM scripts; see SCR_WRITE32_S[ADDR].
645 */
646 union ody_rst_bphy_domain_w1c {
647 uint64_t u;
648 struct ody_rst_bphy_domain_w1c_s {
649 uint64_t soft_rst : 1;
650 uint64_t reserved_1_63 : 63;
651 } s;
652 /* struct ody_rst_bphy_domain_w1c_s cn; */
653 };
654 typedef union ody_rst_bphy_domain_w1c ody_rst_bphy_domain_w1c_t;
655
656 #define ODY_RST_BPHY_DOMAIN_W1C ODY_RST_BPHY_DOMAIN_W1C_FUNC()
657 static inline uint64_t ODY_RST_BPHY_DOMAIN_W1C_FUNC(void) __attribute__ ((pure, always_inline));
ODY_RST_BPHY_DOMAIN_W1C_FUNC(void)658 static inline uint64_t ODY_RST_BPHY_DOMAIN_W1C_FUNC(void)
659 {
660 return 0x87e006001858ll;
661 }
662
663 #define typedef_ODY_RST_BPHY_DOMAIN_W1C ody_rst_bphy_domain_w1c_t
664 #define bustype_ODY_RST_BPHY_DOMAIN_W1C CSR_TYPE_RSL
665 #define basename_ODY_RST_BPHY_DOMAIN_W1C "RST_BPHY_DOMAIN_W1C"
666 #define device_bar_ODY_RST_BPHY_DOMAIN_W1C 0x0 /* PF_BAR0 */
667 #define busnum_ODY_RST_BPHY_DOMAIN_W1C 0
668 #define arguments_ODY_RST_BPHY_DOMAIN_W1C -1, -1, -1, -1
669
670 /**
671 * Register (RSL) rst_bphy_domain_w1s
672 *
673 * RST BPHY Domain Soft Reset Set Register
674 * This register is not accessible through ROM scripts; see SCR_WRITE32_S[ADDR].
675 */
676 union ody_rst_bphy_domain_w1s {
677 uint64_t u;
678 struct ody_rst_bphy_domain_w1s_s {
679 uint64_t soft_rst : 1;
680 uint64_t reserved_1_63 : 63;
681 } s;
682 /* struct ody_rst_bphy_domain_w1s_s cn; */
683 };
684 typedef union ody_rst_bphy_domain_w1s ody_rst_bphy_domain_w1s_t;
685
686 #define ODY_RST_BPHY_DOMAIN_W1S ODY_RST_BPHY_DOMAIN_W1S_FUNC()
687 static inline uint64_t ODY_RST_BPHY_DOMAIN_W1S_FUNC(void) __attribute__ ((pure, always_inline));
ODY_RST_BPHY_DOMAIN_W1S_FUNC(void)688 static inline uint64_t ODY_RST_BPHY_DOMAIN_W1S_FUNC(void)
689 {
690 return 0x87e006001850ll;
691 }
692
693 #define typedef_ODY_RST_BPHY_DOMAIN_W1S ody_rst_bphy_domain_w1s_t
694 #define bustype_ODY_RST_BPHY_DOMAIN_W1S CSR_TYPE_RSL
695 #define basename_ODY_RST_BPHY_DOMAIN_W1S "RST_BPHY_DOMAIN_W1S"
696 #define device_bar_ODY_RST_BPHY_DOMAIN_W1S 0x0 /* PF_BAR0 */
697 #define busnum_ODY_RST_BPHY_DOMAIN_W1S 0
698 #define arguments_ODY_RST_BPHY_DOMAIN_W1S -1, -1, -1, -1
699
700 /**
701 * Register (RSL) rst_cfg
702 *
703 * RST Configuration Register
704 * This register is not accessible through ROM scripts; see SCR_WRITE32_S[ADDR].
705 */
706 union ody_rst_cfg {
707 uint64_t u;
708 struct ody_rst_cfg_s {
709 uint64_t clr_bist : 1;
710 uint64_t reserved_1_63 : 63;
711 } s;
712 /* struct ody_rst_cfg_s cn; */
713 };
714 typedef union ody_rst_cfg ody_rst_cfg_t;
715
716 #define ODY_RST_CFG ODY_RST_CFG_FUNC()
717 static inline uint64_t ODY_RST_CFG_FUNC(void) __attribute__ ((pure, always_inline));
ODY_RST_CFG_FUNC(void)718 static inline uint64_t ODY_RST_CFG_FUNC(void)
719 {
720 return 0x87e006001610ll;
721 }
722
723 #define typedef_ODY_RST_CFG ody_rst_cfg_t
724 #define bustype_ODY_RST_CFG CSR_TYPE_RSL
725 #define basename_ODY_RST_CFG "RST_CFG"
726 #define device_bar_ODY_RST_CFG 0x0 /* PF_BAR0 */
727 #define busnum_ODY_RST_CFG 0
728 #define arguments_ODY_RST_CFG -1, -1, -1, -1
729
730 /**
731 * Register (RSL) rst_chip_domain_w1s
732 *
733 * RST Chip Domain Soft Pulse Reset Register
734 * This register is not accessible through ROM scripts; see SCR_WRITE32_S[ADDR].
735 */
736 union ody_rst_chip_domain_w1s {
737 uint64_t u;
738 struct ody_rst_chip_domain_w1s_s {
739 uint64_t soft_rst : 1;
740 uint64_t reserved_1_63 : 63;
741 } s;
742 /* struct ody_rst_chip_domain_w1s_s cn; */
743 };
744 typedef union ody_rst_chip_domain_w1s ody_rst_chip_domain_w1s_t;
745
746 #define ODY_RST_CHIP_DOMAIN_W1S ODY_RST_CHIP_DOMAIN_W1S_FUNC()
747 static inline uint64_t ODY_RST_CHIP_DOMAIN_W1S_FUNC(void) __attribute__ ((pure, always_inline));
ODY_RST_CHIP_DOMAIN_W1S_FUNC(void)748 static inline uint64_t ODY_RST_CHIP_DOMAIN_W1S_FUNC(void)
749 {
750 return 0x87e006001810ll;
751 }
752
753 #define typedef_ODY_RST_CHIP_DOMAIN_W1S ody_rst_chip_domain_w1s_t
754 #define bustype_ODY_RST_CHIP_DOMAIN_W1S CSR_TYPE_RSL
755 #define basename_ODY_RST_CHIP_DOMAIN_W1S "RST_CHIP_DOMAIN_W1S"
756 #define device_bar_ODY_RST_CHIP_DOMAIN_W1S 0x0 /* PF_BAR0 */
757 #define busnum_ODY_RST_CHIP_DOMAIN_W1S 0
758 #define arguments_ODY_RST_CHIP_DOMAIN_W1S -1, -1, -1, -1
759
760 /**
761 * Register (RSL) rst_ckill
762 *
763 * RST Chipkill Timer Register
764 * This register is not accessible through ROM scripts; see SCR_WRITE32_S[ADDR].
765 */
766 union ody_rst_ckill {
767 uint64_t u;
768 struct ody_rst_ckill_s {
769 uint64_t timer : 47;
770 uint64_t reserved_47_63 : 17;
771 } s;
772 /* struct ody_rst_ckill_s cn; */
773 };
774 typedef union ody_rst_ckill ody_rst_ckill_t;
775
776 #define ODY_RST_CKILL ODY_RST_CKILL_FUNC()
777 static inline uint64_t ODY_RST_CKILL_FUNC(void) __attribute__ ((pure, always_inline));
ODY_RST_CKILL_FUNC(void)778 static inline uint64_t ODY_RST_CKILL_FUNC(void)
779 {
780 return 0x87e006001638ll;
781 }
782
783 #define typedef_ODY_RST_CKILL ody_rst_ckill_t
784 #define bustype_ODY_RST_CKILL CSR_TYPE_RSL
785 #define basename_ODY_RST_CKILL "RST_CKILL"
786 #define device_bar_ODY_RST_CKILL 0x0 /* PF_BAR0 */
787 #define busnum_ODY_RST_CKILL 0
788 #define arguments_ODY_RST_CKILL -1, -1, -1, -1
789
790 /**
791 * Register (RSL) rst_clk_ctl
792 *
793 * RST Clock Control Register
794 * This register is accessible through ROM scripts; see SCR_WRITE32_S[ADDR].
795 */
796 union ody_rst_clk_ctl {
797 uint64_t u;
798 struct ody_rst_clk_ctl_s {
799 uint64_t refclk_src : 1;
800 uint64_t reserved_1_63 : 63;
801 } s;
802 /* struct ody_rst_clk_ctl_s cn; */
803 };
804 typedef union ody_rst_clk_ctl ody_rst_clk_ctl_t;
805
806 #define ODY_RST_CLK_CTL ODY_RST_CLK_CTL_FUNC()
807 static inline uint64_t ODY_RST_CLK_CTL_FUNC(void) __attribute__ ((pure, always_inline));
ODY_RST_CLK_CTL_FUNC(void)808 static inline uint64_t ODY_RST_CLK_CTL_FUNC(void)
809 {
810 return 0x87e0060018a0ll;
811 }
812
813 #define typedef_ODY_RST_CLK_CTL ody_rst_clk_ctl_t
814 #define bustype_ODY_RST_CLK_CTL CSR_TYPE_RSL
815 #define basename_ODY_RST_CLK_CTL "RST_CLK_CTL"
816 #define device_bar_ODY_RST_CLK_CTL 0x0 /* PF_BAR0 */
817 #define busnum_ODY_RST_CLK_CTL 0
818 #define arguments_ODY_RST_CLK_CTL -1, -1, -1, -1
819
820 /**
821 * Register (RSL) rst_clk_freq
822 *
823 * RST PLL Clock Frequency Register
824 * This register is not accessible through ROM scripts; see SCR_WRITE32_S[ADDR].
825 */
826 union ody_rst_clk_freq {
827 uint64_t u;
828 struct ody_rst_clk_freq_s {
829 uint64_t cnt : 37;
830 uint64_t reserved_37_63 : 27;
831 } s;
832 /* struct ody_rst_clk_freq_s cn; */
833 };
834 typedef union ody_rst_clk_freq ody_rst_clk_freq_t;
835
836 #define ODY_RST_CLK_FREQ ODY_RST_CLK_FREQ_FUNC()
837 static inline uint64_t ODY_RST_CLK_FREQ_FUNC(void) __attribute__ ((pure, always_inline));
ODY_RST_CLK_FREQ_FUNC(void)838 static inline uint64_t ODY_RST_CLK_FREQ_FUNC(void)
839 {
840 return 0x87e0060016b8ll;
841 }
842
843 #define typedef_ODY_RST_CLK_FREQ ody_rst_clk_freq_t
844 #define bustype_ODY_RST_CLK_FREQ CSR_TYPE_RSL
845 #define basename_ODY_RST_CLK_FREQ "RST_CLK_FREQ"
846 #define device_bar_ODY_RST_CLK_FREQ 0x0 /* PF_BAR0 */
847 #define busnum_ODY_RST_CLK_FREQ 0
848 #define arguments_ODY_RST_CLK_FREQ -1, -1, -1, -1
849
850 /**
851 * Register (RSL) rst_clk_sample
852 *
853 * RST PLL Clock Sample Period Register
854 * This register is not accessible through ROM scripts; see SCR_WRITE32_S[ADDR].
855 */
856 union ody_rst_clk_sample {
857 uint64_t u;
858 struct ody_rst_clk_sample_s {
859 uint64_t window : 32;
860 uint64_t reserved_32_62 : 31;
861 uint64_t not_done : 1;
862 } s;
863 /* struct ody_rst_clk_sample_s cn; */
864 };
865 typedef union ody_rst_clk_sample ody_rst_clk_sample_t;
866
867 #define ODY_RST_CLK_SAMPLE ODY_RST_CLK_SAMPLE_FUNC()
868 static inline uint64_t ODY_RST_CLK_SAMPLE_FUNC(void) __attribute__ ((pure, always_inline));
ODY_RST_CLK_SAMPLE_FUNC(void)869 static inline uint64_t ODY_RST_CLK_SAMPLE_FUNC(void)
870 {
871 return 0x87e0060016b0ll;
872 }
873
874 #define typedef_ODY_RST_CLK_SAMPLE ody_rst_clk_sample_t
875 #define bustype_ODY_RST_CLK_SAMPLE CSR_TYPE_RSL
876 #define basename_ODY_RST_CLK_SAMPLE "RST_CLK_SAMPLE"
877 #define device_bar_ODY_RST_CLK_SAMPLE 0x0 /* PF_BAR0 */
878 #define busnum_ODY_RST_CLK_SAMPLE 0
879 #define arguments_ODY_RST_CLK_SAMPLE -1, -1, -1, -1
880
881 /**
882 * Register (RSL) rst_cold_data#
883 *
884 * RST Cold Reset Data Registers
885 * This register is not accessible through ROM scripts; see SCR_WRITE32_S[ADDR].
886 */
887 union ody_rst_cold_datax {
888 uint64_t u;
889 struct ody_rst_cold_datax_s {
890 uint64_t data : 64;
891 } s;
892 /* struct ody_rst_cold_datax_s cn; */
893 };
894 typedef union ody_rst_cold_datax ody_rst_cold_datax_t;
895
896 static inline uint64_t ODY_RST_COLD_DATAX(uint64_t a) __attribute__ ((pure, always_inline));
ODY_RST_COLD_DATAX(uint64_t a)897 static inline uint64_t ODY_RST_COLD_DATAX(uint64_t a)
898 {
899 if (a <= 5)
900 return 0x87e0060017c0ll + 8ll * ((a) & 0x7);
901 __ody_csr_fatal("RST_COLD_DATAX", 1, a, 0, 0, 0, 0, 0);
902 }
903
904 #define typedef_ODY_RST_COLD_DATAX(a) ody_rst_cold_datax_t
905 #define bustype_ODY_RST_COLD_DATAX(a) CSR_TYPE_RSL
906 #define basename_ODY_RST_COLD_DATAX(a) "RST_COLD_DATAX"
907 #define device_bar_ODY_RST_COLD_DATAX(a) 0x0 /* PF_BAR0 */
908 #define busnum_ODY_RST_COLD_DATAX(a) (a)
909 #define arguments_ODY_RST_COLD_DATAX(a) (a), -1, -1, -1
910
911 /**
912 * Register (RSL) rst_cold_domain_w1s
913 *
914 * RST Cold Domain Pulse Reset Register
915 * This register is not accessible through ROM scripts; see SCR_WRITE32_S[ADDR].
916 */
917 union ody_rst_cold_domain_w1s {
918 uint64_t u;
919 struct ody_rst_cold_domain_w1s_s {
920 uint64_t soft_rst : 1;
921 uint64_t reserved_1_63 : 63;
922 } s;
923 /* struct ody_rst_cold_domain_w1s_s cn; */
924 };
925 typedef union ody_rst_cold_domain_w1s ody_rst_cold_domain_w1s_t;
926
927 #define ODY_RST_COLD_DOMAIN_W1S ODY_RST_COLD_DOMAIN_W1S_FUNC()
928 static inline uint64_t ODY_RST_COLD_DOMAIN_W1S_FUNC(void) __attribute__ ((pure, always_inline));
ODY_RST_COLD_DOMAIN_W1S_FUNC(void)929 static inline uint64_t ODY_RST_COLD_DOMAIN_W1S_FUNC(void)
930 {
931 return 0x87e006001808ll;
932 }
933
934 #define typedef_ODY_RST_COLD_DOMAIN_W1S ody_rst_cold_domain_w1s_t
935 #define bustype_ODY_RST_COLD_DOMAIN_W1S CSR_TYPE_RSL
936 #define basename_ODY_RST_COLD_DOMAIN_W1S "RST_COLD_DOMAIN_W1S"
937 #define device_bar_ODY_RST_COLD_DOMAIN_W1S 0x0 /* PF_BAR0 */
938 #define busnum_ODY_RST_COLD_DOMAIN_W1S 0
939 #define arguments_ODY_RST_COLD_DOMAIN_W1S -1, -1, -1, -1
940
941 /**
942 * Register (RSL) rst_const
943 *
944 * RST Constant Register
945 * This register is accessible through ROM scripts; see SCR_WRITE32_S[ADDR].
946 */
947 union ody_rst_const {
948 uint64_t u;
949 struct ody_rst_const_s {
950 uint64_t pems : 8;
951 uint64_t rst_devs : 8;
952 uint64_t plls : 16;
953 uint64_t reserved_32_63 : 32;
954 } s;
955 /* struct ody_rst_const_s cn; */
956 };
957 typedef union ody_rst_const ody_rst_const_t;
958
959 #define ODY_RST_CONST ODY_RST_CONST_FUNC()
960 static inline uint64_t ODY_RST_CONST_FUNC(void) __attribute__ ((pure, always_inline));
ODY_RST_CONST_FUNC(void)961 static inline uint64_t ODY_RST_CONST_FUNC(void)
962 {
963 return 0x87e0060018f8ll;
964 }
965
966 #define typedef_ODY_RST_CONST ody_rst_const_t
967 #define bustype_ODY_RST_CONST CSR_TYPE_RSL
968 #define basename_ODY_RST_CONST "RST_CONST"
969 #define device_bar_ODY_RST_CONST 0x0 /* PF_BAR0 */
970 #define busnum_ODY_RST_CONST 0
971 #define arguments_ODY_RST_CONST -1, -1, -1, -1
972
973 /**
974 * Register (RSL) rst_core_domain_w1c
975 *
976 * RST Core Domain Soft Reset Clear Register
977 * This register is not accessible through ROM scripts; see SCR_WRITE32_S[ADDR].
978 */
979 union ody_rst_core_domain_w1c {
980 uint64_t u;
981 struct ody_rst_core_domain_w1c_s {
982 uint64_t soft_rst : 1;
983 uint64_t reserved_1_63 : 63;
984 } s;
985 /* struct ody_rst_core_domain_w1c_s cn; */
986 };
987 typedef union ody_rst_core_domain_w1c ody_rst_core_domain_w1c_t;
988
989 #define ODY_RST_CORE_DOMAIN_W1C ODY_RST_CORE_DOMAIN_W1C_FUNC()
990 static inline uint64_t ODY_RST_CORE_DOMAIN_W1C_FUNC(void) __attribute__ ((pure, always_inline));
ODY_RST_CORE_DOMAIN_W1C_FUNC(void)991 static inline uint64_t ODY_RST_CORE_DOMAIN_W1C_FUNC(void)
992 {
993 return 0x87e006001828ll;
994 }
995
996 #define typedef_ODY_RST_CORE_DOMAIN_W1C ody_rst_core_domain_w1c_t
997 #define bustype_ODY_RST_CORE_DOMAIN_W1C CSR_TYPE_RSL
998 #define basename_ODY_RST_CORE_DOMAIN_W1C "RST_CORE_DOMAIN_W1C"
999 #define device_bar_ODY_RST_CORE_DOMAIN_W1C 0x0 /* PF_BAR0 */
1000 #define busnum_ODY_RST_CORE_DOMAIN_W1C 0
1001 #define arguments_ODY_RST_CORE_DOMAIN_W1C -1, -1, -1, -1
1002
1003 /**
1004 * Register (RSL) rst_core_domain_w1s
1005 *
1006 * RST Core Domain Soft Reset Set Register
1007 * This register is not accessible through ROM scripts; see SCR_WRITE32_S[ADDR].
1008 */
1009 union ody_rst_core_domain_w1s {
1010 uint64_t u;
1011 struct ody_rst_core_domain_w1s_s {
1012 uint64_t soft_rst : 1;
1013 uint64_t reserved_1_63 : 63;
1014 } s;
1015 /* struct ody_rst_core_domain_w1s_s cn; */
1016 };
1017 typedef union ody_rst_core_domain_w1s ody_rst_core_domain_w1s_t;
1018
1019 #define ODY_RST_CORE_DOMAIN_W1S ODY_RST_CORE_DOMAIN_W1S_FUNC()
1020 static inline uint64_t ODY_RST_CORE_DOMAIN_W1S_FUNC(void) __attribute__ ((pure, always_inline));
ODY_RST_CORE_DOMAIN_W1S_FUNC(void)1021 static inline uint64_t ODY_RST_CORE_DOMAIN_W1S_FUNC(void)
1022 {
1023 return 0x87e006001820ll;
1024 }
1025
1026 #define typedef_ODY_RST_CORE_DOMAIN_W1S ody_rst_core_domain_w1s_t
1027 #define bustype_ODY_RST_CORE_DOMAIN_W1S CSR_TYPE_RSL
1028 #define basename_ODY_RST_CORE_DOMAIN_W1S "RST_CORE_DOMAIN_W1S"
1029 #define device_bar_ODY_RST_CORE_DOMAIN_W1S 0x0 /* PF_BAR0 */
1030 #define busnum_ODY_RST_CORE_DOMAIN_W1S 0
1031 #define arguments_ODY_RST_CORE_DOMAIN_W1S -1, -1, -1, -1
1032
1033 /**
1034 * Register (RSL) rst_debug
1035 *
1036 * RST Debug Register
1037 * This register is not accessible through ROM scripts; see SCR_WRITE32_S[ADDR].
1038 */
1039 union ody_rst_debug {
1040 uint64_t u;
1041 struct ody_rst_debug_s {
1042 uint64_t clk_on : 1;
1043 uint64_t clk_cng : 1;
1044 uint64_t clkena_on : 1;
1045 uint64_t dll_csr_wakeup : 1;
1046 uint64_t div_clk_rst : 1;
1047 uint64_t reserved_5_63 : 59;
1048 } s;
1049 /* struct ody_rst_debug_s cn; */
1050 };
1051 typedef union ody_rst_debug ody_rst_debug_t;
1052
1053 #define ODY_RST_DEBUG ODY_RST_DEBUG_FUNC()
1054 static inline uint64_t ODY_RST_DEBUG_FUNC(void) __attribute__ ((pure, always_inline));
ODY_RST_DEBUG_FUNC(void)1055 static inline uint64_t ODY_RST_DEBUG_FUNC(void)
1056 {
1057 return 0x87e0060017b0ll;
1058 }
1059
1060 #define typedef_ODY_RST_DEBUG ody_rst_debug_t
1061 #define bustype_ODY_RST_DEBUG CSR_TYPE_RSL
1062 #define basename_ODY_RST_DEBUG "RST_DEBUG"
1063 #define device_bar_ODY_RST_DEBUG 0x0 /* PF_BAR0 */
1064 #define busnum_ODY_RST_DEBUG 0
1065 #define arguments_ODY_RST_DEBUG -1, -1, -1, -1
1066
1067 /**
1068 * Register (RSL) rst_delay
1069 *
1070 * RST Delay Register
1071 * This register is not accessible through ROM scripts; see SCR_WRITE32_S[ADDR].
1072 */
1073 union ody_rst_delay {
1074 uint64_t u;
1075 struct ody_rst_delay_s {
1076 uint64_t rst_dly : 16;
1077 uint64_t reserved_16_63 : 48;
1078 } s;
1079 /* struct ody_rst_delay_s cn; */
1080 };
1081 typedef union ody_rst_delay ody_rst_delay_t;
1082
1083 #define ODY_RST_DELAY ODY_RST_DELAY_FUNC()
1084 static inline uint64_t ODY_RST_DELAY_FUNC(void) __attribute__ ((pure, always_inline));
ODY_RST_DELAY_FUNC(void)1085 static inline uint64_t ODY_RST_DELAY_FUNC(void)
1086 {
1087 return 0x87e006001608ll;
1088 }
1089
1090 #define typedef_ODY_RST_DELAY ody_rst_delay_t
1091 #define bustype_ODY_RST_DELAY CSR_TYPE_RSL
1092 #define basename_ODY_RST_DELAY "RST_DELAY"
1093 #define device_bar_ODY_RST_DELAY 0x0 /* PF_BAR0 */
1094 #define busnum_ODY_RST_DELAY 0
1095 #define arguments_ODY_RST_DELAY -1, -1, -1, -1
1096
1097 /**
1098 * Register (RSL) rst_dev_map#
1099 *
1100 * RST Device Map Register
1101 * This register configures the reset domain of devices. Index {a} is enumerated by RST_DEV_E.
1102 * Writes to these registers should only occur when all the bits of RST_BIST_ACTIVE are clear.
1103 * See RST_BIST_ACTIVE for details.
1104 * Only one RST_DEV_MAP() should be written at a time.
1105 *
1106 * This register is not accessible through ROM scripts; see SCR_WRITE32_S[ADDR].
1107 */
1108 union ody_rst_dev_mapx {
1109 uint64_t u;
1110 struct ody_rst_dev_mapx_s {
1111 uint64_t dmn : 3;
1112 uint64_t reserved_3_63 : 61;
1113 } s;
1114 /* struct ody_rst_dev_mapx_s cn; */
1115 };
1116 typedef union ody_rst_dev_mapx ody_rst_dev_mapx_t;
1117
1118 static inline uint64_t ODY_RST_DEV_MAPX(uint64_t a) __attribute__ ((pure, always_inline));
ODY_RST_DEV_MAPX(uint64_t a)1119 static inline uint64_t ODY_RST_DEV_MAPX(uint64_t a)
1120 {
1121 if (a <= 47)
1122 return 0x87e00a001a00ll + 8ll * ((a) & 0x3f);
1123 __ody_csr_fatal("RST_DEV_MAPX", 1, a, 0, 0, 0, 0, 0);
1124 }
1125
1126 #define typedef_ODY_RST_DEV_MAPX(a) ody_rst_dev_mapx_t
1127 #define bustype_ODY_RST_DEV_MAPX(a) CSR_TYPE_RSL
1128 #define basename_ODY_RST_DEV_MAPX(a) "RST_DEV_MAPX"
1129 #define device_bar_ODY_RST_DEV_MAPX(a) 0x2 /* PF_BAR2 */
1130 #define busnum_ODY_RST_DEV_MAPX(a) (a)
1131 #define arguments_ODY_RST_DEV_MAPX(a) (a), -1, -1, -1
1132
1133 /**
1134 * Register (RSL) rst_int
1135 *
1136 * RST Interrupt Register
1137 * This register is not accessible through ROM scripts; see SCR_WRITE32_S[ADDR].
1138 */
1139 union ody_rst_int {
1140 uint64_t u;
1141 struct ody_rst_int_s {
1142 uint64_t reserved_0_47 : 48;
1143 uint64_t core_reset : 1;
1144 uint64_t mcp_reset : 1;
1145 uint64_t scp_reset : 1;
1146 uint64_t bphy_reset : 1;
1147 uint64_t xcp2_reset : 1;
1148 uint64_t reserved_53_63 : 11;
1149 } s;
1150 /* struct ody_rst_int_s cn; */
1151 };
1152 typedef union ody_rst_int ody_rst_int_t;
1153
1154 #define ODY_RST_INT ODY_RST_INT_FUNC()
1155 static inline uint64_t ODY_RST_INT_FUNC(void) __attribute__ ((pure, always_inline));
ODY_RST_INT_FUNC(void)1156 static inline uint64_t ODY_RST_INT_FUNC(void)
1157 {
1158 return 0x87e006001628ll;
1159 }
1160
1161 #define typedef_ODY_RST_INT ody_rst_int_t
1162 #define bustype_ODY_RST_INT CSR_TYPE_RSL
1163 #define basename_ODY_RST_INT "RST_INT"
1164 #define device_bar_ODY_RST_INT 0x0 /* PF_BAR0 */
1165 #define busnum_ODY_RST_INT 0
1166 #define arguments_ODY_RST_INT -1, -1, -1, -1
1167
1168 /**
1169 * Register (RSL) rst_int_ena_w1c
1170 *
1171 * RST Interrupt Enable Clear Register
1172 * This register clears interrupt enable bits.
1173 */
1174 union ody_rst_int_ena_w1c {
1175 uint64_t u;
1176 struct ody_rst_int_ena_w1c_s {
1177 uint64_t reserved_0_47 : 48;
1178 uint64_t core_reset : 1;
1179 uint64_t mcp_reset : 1;
1180 uint64_t scp_reset : 1;
1181 uint64_t bphy_reset : 1;
1182 uint64_t xcp2_reset : 1;
1183 uint64_t reserved_53_63 : 11;
1184 } s;
1185 /* struct ody_rst_int_ena_w1c_s cn; */
1186 };
1187 typedef union ody_rst_int_ena_w1c ody_rst_int_ena_w1c_t;
1188
1189 #define ODY_RST_INT_ENA_W1C ODY_RST_INT_ENA_W1C_FUNC()
1190 static inline uint64_t ODY_RST_INT_ENA_W1C_FUNC(void) __attribute__ ((pure, always_inline));
ODY_RST_INT_ENA_W1C_FUNC(void)1191 static inline uint64_t ODY_RST_INT_ENA_W1C_FUNC(void)
1192 {
1193 return 0x87e0060016a8ll;
1194 }
1195
1196 #define typedef_ODY_RST_INT_ENA_W1C ody_rst_int_ena_w1c_t
1197 #define bustype_ODY_RST_INT_ENA_W1C CSR_TYPE_RSL
1198 #define basename_ODY_RST_INT_ENA_W1C "RST_INT_ENA_W1C"
1199 #define device_bar_ODY_RST_INT_ENA_W1C 0x0 /* PF_BAR0 */
1200 #define busnum_ODY_RST_INT_ENA_W1C 0
1201 #define arguments_ODY_RST_INT_ENA_W1C -1, -1, -1, -1
1202
1203 /**
1204 * Register (RSL) rst_int_ena_w1s
1205 *
1206 * RST Interrupt Enable Set Register
1207 * This register sets interrupt enable bits.
1208 */
1209 union ody_rst_int_ena_w1s {
1210 uint64_t u;
1211 struct ody_rst_int_ena_w1s_s {
1212 uint64_t reserved_0_47 : 48;
1213 uint64_t core_reset : 1;
1214 uint64_t mcp_reset : 1;
1215 uint64_t scp_reset : 1;
1216 uint64_t bphy_reset : 1;
1217 uint64_t xcp2_reset : 1;
1218 uint64_t reserved_53_63 : 11;
1219 } s;
1220 /* struct ody_rst_int_ena_w1s_s cn; */
1221 };
1222 typedef union ody_rst_int_ena_w1s ody_rst_int_ena_w1s_t;
1223
1224 #define ODY_RST_INT_ENA_W1S ODY_RST_INT_ENA_W1S_FUNC()
1225 static inline uint64_t ODY_RST_INT_ENA_W1S_FUNC(void) __attribute__ ((pure, always_inline));
ODY_RST_INT_ENA_W1S_FUNC(void)1226 static inline uint64_t ODY_RST_INT_ENA_W1S_FUNC(void)
1227 {
1228 return 0x87e0060016a0ll;
1229 }
1230
1231 #define typedef_ODY_RST_INT_ENA_W1S ody_rst_int_ena_w1s_t
1232 #define bustype_ODY_RST_INT_ENA_W1S CSR_TYPE_RSL
1233 #define basename_ODY_RST_INT_ENA_W1S "RST_INT_ENA_W1S"
1234 #define device_bar_ODY_RST_INT_ENA_W1S 0x0 /* PF_BAR0 */
1235 #define busnum_ODY_RST_INT_ENA_W1S 0
1236 #define arguments_ODY_RST_INT_ENA_W1S -1, -1, -1, -1
1237
1238 /**
1239 * Register (RSL) rst_int_w1s
1240 *
1241 * RST Interrupt Set Register
1242 * This register sets interrupt bits.
1243 */
1244 union ody_rst_int_w1s {
1245 uint64_t u;
1246 struct ody_rst_int_w1s_s {
1247 uint64_t reserved_0_47 : 48;
1248 uint64_t core_reset : 1;
1249 uint64_t mcp_reset : 1;
1250 uint64_t scp_reset : 1;
1251 uint64_t bphy_reset : 1;
1252 uint64_t xcp2_reset : 1;
1253 uint64_t reserved_53_63 : 11;
1254 } s;
1255 /* struct ody_rst_int_w1s_s cn; */
1256 };
1257 typedef union ody_rst_int_w1s ody_rst_int_w1s_t;
1258
1259 #define ODY_RST_INT_W1S ODY_RST_INT_W1S_FUNC()
1260 static inline uint64_t ODY_RST_INT_W1S_FUNC(void) __attribute__ ((pure, always_inline));
ODY_RST_INT_W1S_FUNC(void)1261 static inline uint64_t ODY_RST_INT_W1S_FUNC(void)
1262 {
1263 return 0x87e006001630ll;
1264 }
1265
1266 #define typedef_ODY_RST_INT_W1S ody_rst_int_w1s_t
1267 #define bustype_ODY_RST_INT_W1S CSR_TYPE_RSL
1268 #define basename_ODY_RST_INT_W1S "RST_INT_W1S"
1269 #define device_bar_ODY_RST_INT_W1S 0x0 /* PF_BAR0 */
1270 #define busnum_ODY_RST_INT_W1S 0
1271 #define arguments_ODY_RST_INT_W1S -1, -1, -1, -1
1272
1273 /**
1274 * Register (RSL) rst_lboot
1275 *
1276 * RST Last Boot Register
1277 * This register is not accessible through ROM scripts; see SCR_WRITE32_S[ADDR].
1278 */
1279 union ody_rst_lboot {
1280 uint64_t u;
1281 struct ody_rst_lboot_s {
1282 uint64_t lboot : 56;
1283 uint64_t reserved_56_63 : 8;
1284 } s;
1285 /* struct ody_rst_lboot_s cn; */
1286 };
1287 typedef union ody_rst_lboot ody_rst_lboot_t;
1288
1289 #define ODY_RST_LBOOT ODY_RST_LBOOT_FUNC()
1290 static inline uint64_t ODY_RST_LBOOT_FUNC(void) __attribute__ ((pure, always_inline));
ODY_RST_LBOOT_FUNC(void)1291 static inline uint64_t ODY_RST_LBOOT_FUNC(void)
1292 {
1293 return 0x87e006001620ll;
1294 }
1295
1296 #define typedef_ODY_RST_LBOOT ody_rst_lboot_t
1297 #define bustype_ODY_RST_LBOOT CSR_TYPE_RSL
1298 #define basename_ODY_RST_LBOOT "RST_LBOOT"
1299 #define device_bar_ODY_RST_LBOOT 0x0 /* PF_BAR0 */
1300 #define busnum_ODY_RST_LBOOT 0
1301 #define arguments_ODY_RST_LBOOT -1, -1, -1, -1
1302
1303 /**
1304 * Register (RSL) rst_man_pll#
1305 *
1306 * RST Manual PLL Control Register
1307 * These registers are used in conjunction with the RST_PLL() registers when
1308 * the RST_PLL()[NEXT_MAN] field is set. Indexed by RST_PLL_E.
1309 * These register is not accessible through ROM scripts; see SCR_WRITE32_S[ADDR].
1310 *
1311 * The logic associated with the PLL functions can only process one operation at a time.
1312 * Writes to this register should only occur when both the RST_PLL(x)[NEXT_PGM] and
1313 * RST_PLL(x)[NEXT_SWITCH] fields are zero.
1314 *
1315 * This register is always reset on a chip domain reset.
1316 */
1317 union ody_rst_man_pllx {
1318 uint64_t u;
1319 struct ody_rst_man_pllx_s {
1320 uint64_t update_rate : 10;
1321 uint64_t dlf_ki : 5;
1322 uint64_t dlf_kp : 5;
1323 uint64_t icp : 4;
1324 uint64_t vco_fract : 10;
1325 uint64_t vco_mul : 10;
1326 uint64_t bw : 2;
1327 uint64_t post_div : 9;
1328 uint64_t reserved_55 : 1;
1329 uint64_t ref_div : 4;
1330 uint64_t power_down : 3;
1331 uint64_t reserved_63 : 1;
1332 } s;
1333 /* struct ody_rst_man_pllx_s cn; */
1334 };
1335 typedef union ody_rst_man_pllx ody_rst_man_pllx_t;
1336
1337 static inline uint64_t ODY_RST_MAN_PLLX(uint64_t a) __attribute__ ((pure, always_inline));
ODY_RST_MAN_PLLX(uint64_t a)1338 static inline uint64_t ODY_RST_MAN_PLLX(uint64_t a)
1339 {
1340 if (a <= 15)
1341 return 0x87e00a001008ll + 0x10ll * ((a) & 0xf);
1342 __ody_csr_fatal("RST_MAN_PLLX", 1, a, 0, 0, 0, 0, 0);
1343 }
1344
1345 #define typedef_ODY_RST_MAN_PLLX(a) ody_rst_man_pllx_t
1346 #define bustype_ODY_RST_MAN_PLLX(a) CSR_TYPE_RSL
1347 #define basename_ODY_RST_MAN_PLLX(a) "RST_MAN_PLLX"
1348 #define device_bar_ODY_RST_MAN_PLLX(a) 0x2 /* PF_BAR2 */
1349 #define busnum_ODY_RST_MAN_PLLX(a) (a)
1350 #define arguments_ODY_RST_MAN_PLLX(a) (a), -1, -1, -1
1351
1352 /**
1353 * Register (RSL) rst_mcp_domain_w1c
1354 *
1355 * RST MCP Domain Soft Reset Clear Register
1356 * This register is not accessible through ROM scripts; see SCR_WRITE32_S[ADDR].
1357 */
1358 union ody_rst_mcp_domain_w1c {
1359 uint64_t u;
1360 struct ody_rst_mcp_domain_w1c_s {
1361 uint64_t soft_rst : 1;
1362 uint64_t reserved_1_63 : 63;
1363 } s;
1364 /* struct ody_rst_mcp_domain_w1c_s cn; */
1365 };
1366 typedef union ody_rst_mcp_domain_w1c ody_rst_mcp_domain_w1c_t;
1367
1368 #define ODY_RST_MCP_DOMAIN_W1C ODY_RST_MCP_DOMAIN_W1C_FUNC()
1369 static inline uint64_t ODY_RST_MCP_DOMAIN_W1C_FUNC(void) __attribute__ ((pure, always_inline));
ODY_RST_MCP_DOMAIN_W1C_FUNC(void)1370 static inline uint64_t ODY_RST_MCP_DOMAIN_W1C_FUNC(void)
1371 {
1372 return 0x87e006001838ll;
1373 }
1374
1375 #define typedef_ODY_RST_MCP_DOMAIN_W1C ody_rst_mcp_domain_w1c_t
1376 #define bustype_ODY_RST_MCP_DOMAIN_W1C CSR_TYPE_RSL
1377 #define basename_ODY_RST_MCP_DOMAIN_W1C "RST_MCP_DOMAIN_W1C"
1378 #define device_bar_ODY_RST_MCP_DOMAIN_W1C 0x0 /* PF_BAR0 */
1379 #define busnum_ODY_RST_MCP_DOMAIN_W1C 0
1380 #define arguments_ODY_RST_MCP_DOMAIN_W1C -1, -1, -1, -1
1381
1382 /**
1383 * Register (RSL) rst_mcp_domain_w1s
1384 *
1385 * RST MCP Domain Soft Reset Set Register
1386 * This register is not accessible through ROM scripts; see SCR_WRITE32_S[ADDR].
1387 */
1388 union ody_rst_mcp_domain_w1s {
1389 uint64_t u;
1390 struct ody_rst_mcp_domain_w1s_s {
1391 uint64_t soft_rst : 1;
1392 uint64_t force_rst : 1;
1393 uint64_t reserved_2_63 : 62;
1394 } s;
1395 /* struct ody_rst_mcp_domain_w1s_s cn; */
1396 };
1397 typedef union ody_rst_mcp_domain_w1s ody_rst_mcp_domain_w1s_t;
1398
1399 #define ODY_RST_MCP_DOMAIN_W1S ODY_RST_MCP_DOMAIN_W1S_FUNC()
1400 static inline uint64_t ODY_RST_MCP_DOMAIN_W1S_FUNC(void) __attribute__ ((pure, always_inline));
ODY_RST_MCP_DOMAIN_W1S_FUNC(void)1401 static inline uint64_t ODY_RST_MCP_DOMAIN_W1S_FUNC(void)
1402 {
1403 return 0x87e006001830ll;
1404 }
1405
1406 #define typedef_ODY_RST_MCP_DOMAIN_W1S ody_rst_mcp_domain_w1s_t
1407 #define bustype_ODY_RST_MCP_DOMAIN_W1S CSR_TYPE_RSL
1408 #define basename_ODY_RST_MCP_DOMAIN_W1S "RST_MCP_DOMAIN_W1S"
1409 #define device_bar_ODY_RST_MCP_DOMAIN_W1S 0x0 /* PF_BAR0 */
1410 #define busnum_ODY_RST_MCP_DOMAIN_W1S 0
1411 #define arguments_ODY_RST_MCP_DOMAIN_W1S -1, -1, -1, -1
1412
1413 /**
1414 * Register (RSL) rst_msix_pba#
1415 *
1416 * RST MSI-X Pending Bit Array Registers
1417 * This register is the MSI-X PBA table; the bit number is indexed by the RST_INT_VEC_E
1418 * enumeration.
1419 *
1420 * This register is not accessible through ROM scripts; see SCR_WRITE32_S[ADDR].
1421 */
1422 union ody_rst_msix_pbax {
1423 uint64_t u;
1424 struct ody_rst_msix_pbax_s {
1425 uint64_t pend : 64;
1426 } s;
1427 /* struct ody_rst_msix_pbax_s cn; */
1428 };
1429 typedef union ody_rst_msix_pbax ody_rst_msix_pbax_t;
1430
1431 static inline uint64_t ODY_RST_MSIX_PBAX(uint64_t a) __attribute__ ((pure, always_inline));
ODY_RST_MSIX_PBAX(uint64_t a)1432 static inline uint64_t ODY_RST_MSIX_PBAX(uint64_t a)
1433 {
1434 if (a == 0)
1435 return 0x87e006ff0000ll;
1436 __ody_csr_fatal("RST_MSIX_PBAX", 1, a, 0, 0, 0, 0, 0);
1437 }
1438
1439 #define typedef_ODY_RST_MSIX_PBAX(a) ody_rst_msix_pbax_t
1440 #define bustype_ODY_RST_MSIX_PBAX(a) CSR_TYPE_RSL
1441 #define basename_ODY_RST_MSIX_PBAX(a) "RST_MSIX_PBAX"
1442 #define device_bar_ODY_RST_MSIX_PBAX(a) 0x4 /* PF_BAR4 */
1443 #define busnum_ODY_RST_MSIX_PBAX(a) (a)
1444 #define arguments_ODY_RST_MSIX_PBAX(a) (a), -1, -1, -1
1445
1446 /**
1447 * Register (RSL) rst_msix_vec#_addr
1448 *
1449 * RST MSI-X Vector-Table Address Register
1450 * This register is the MSI-X vector table, indexed by the RST_INT_VEC_E enumeration.
1451 *
1452 * This register is not accessible through ROM scripts; see SCR_WRITE32_S[ADDR].
1453 */
1454 union ody_rst_msix_vecx_addr {
1455 uint64_t u;
1456 struct ody_rst_msix_vecx_addr_s {
1457 uint64_t secvec : 1;
1458 uint64_t reserved_1 : 1;
1459 uint64_t addr : 51;
1460 uint64_t reserved_53_63 : 11;
1461 } s;
1462 /* struct ody_rst_msix_vecx_addr_s cn; */
1463 };
1464 typedef union ody_rst_msix_vecx_addr ody_rst_msix_vecx_addr_t;
1465
1466 static inline uint64_t ODY_RST_MSIX_VECX_ADDR(uint64_t a) __attribute__ ((pure, always_inline));
ODY_RST_MSIX_VECX_ADDR(uint64_t a)1467 static inline uint64_t ODY_RST_MSIX_VECX_ADDR(uint64_t a)
1468 {
1469 if (a == 0)
1470 return 0x87e006f00000ll;
1471 __ody_csr_fatal("RST_MSIX_VECX_ADDR", 1, a, 0, 0, 0, 0, 0);
1472 }
1473
1474 #define typedef_ODY_RST_MSIX_VECX_ADDR(a) ody_rst_msix_vecx_addr_t
1475 #define bustype_ODY_RST_MSIX_VECX_ADDR(a) CSR_TYPE_RSL
1476 #define basename_ODY_RST_MSIX_VECX_ADDR(a) "RST_MSIX_VECX_ADDR"
1477 #define device_bar_ODY_RST_MSIX_VECX_ADDR(a) 0x4 /* PF_BAR4 */
1478 #define busnum_ODY_RST_MSIX_VECX_ADDR(a) (a)
1479 #define arguments_ODY_RST_MSIX_VECX_ADDR(a) (a), -1, -1, -1
1480
1481 /**
1482 * Register (RSL) rst_msix_vec#_ctl
1483 *
1484 * RST MSI-X Vector-Table Control and Data Register
1485 * This register is the MSI-X vector table, indexed by the RST_INT_VEC_E enumeration.
1486 *
1487 * This register is not accessible through ROM scripts; see SCR_WRITE32_S[ADDR].
1488 */
1489 union ody_rst_msix_vecx_ctl {
1490 uint64_t u;
1491 struct ody_rst_msix_vecx_ctl_s {
1492 uint64_t data : 32;
1493 uint64_t mask : 1;
1494 uint64_t reserved_33_63 : 31;
1495 } s;
1496 /* struct ody_rst_msix_vecx_ctl_s cn; */
1497 };
1498 typedef union ody_rst_msix_vecx_ctl ody_rst_msix_vecx_ctl_t;
1499
1500 static inline uint64_t ODY_RST_MSIX_VECX_CTL(uint64_t a) __attribute__ ((pure, always_inline));
ODY_RST_MSIX_VECX_CTL(uint64_t a)1501 static inline uint64_t ODY_RST_MSIX_VECX_CTL(uint64_t a)
1502 {
1503 if (a == 0)
1504 return 0x87e006f00008ll;
1505 __ody_csr_fatal("RST_MSIX_VECX_CTL", 1, a, 0, 0, 0, 0, 0);
1506 }
1507
1508 #define typedef_ODY_RST_MSIX_VECX_CTL(a) ody_rst_msix_vecx_ctl_t
1509 #define bustype_ODY_RST_MSIX_VECX_CTL(a) CSR_TYPE_RSL
1510 #define basename_ODY_RST_MSIX_VECX_CTL(a) "RST_MSIX_VECX_CTL"
1511 #define device_bar_ODY_RST_MSIX_VECX_CTL(a) 0x4 /* PF_BAR4 */
1512 #define busnum_ODY_RST_MSIX_VECX_CTL(a) (a)
1513 #define arguments_ODY_RST_MSIX_VECX_CTL(a) (a), -1, -1, -1
1514
1515 /**
1516 * Register (RSL) rst_pll#
1517 *
1518 * RST PLL Control Register
1519 * This register is not accessible through ROM scripts; see SCR_WRITE32_S[ADDR].
1520 * Each index of this register controls a PLL on the chip. The register is used for
1521 * typical programming operations and is supplemented with the RST_MAN_PLL()
1522 * register when selected. Indexed by RST_PLL_E.
1523 *
1524 * The logic associated with the PLL functions can only process one operation at a time.
1525 * Writes to this register and to both RST_MAN_PLL(x) and RST_TEST_PLL(x) of the same
1526 * index should only occur when both the NEXT_PGM and NEXT_SWITCH fields are zero.
1527 * It is typically necessary to poll this register to confirm this.
1528 *
1529 * The register fields are returned to reset values on a chip domain reset unless
1530 * specifically noted.
1531 */
1532 union ody_rst_pllx {
1533 uint64_t u;
1534 struct ody_rst_pllx_s {
1535 uint64_t next_switch : 16;
1536 uint64_t next_pgm : 1;
1537 uint64_t next_man : 1;
1538 uint64_t reserved_18_20 : 3;
1539 uint64_t next_pll_sel : 3;
1540 uint64_t next_mul : 7;
1541 uint64_t reserved_31 : 1;
1542 uint64_t init_mul : 7;
1543 uint64_t reserved_39 : 1;
1544 uint64_t max_mul : 7;
1545 uint64_t reserved_47 : 1;
1546 uint64_t cur_mul : 7;
1547 uint64_t no_rst_chip : 1;
1548 uint64_t no_auto_pgm : 1;
1549 uint64_t cur_pll_sel : 3;
1550 uint64_t reserved_60 : 1;
1551 uint64_t alt_ref : 1;
1552 uint64_t pll1_present : 1;
1553 uint64_t aro_present : 1;
1554 } s;
1555 /* struct ody_rst_pllx_s cn; */
1556 };
1557 typedef union ody_rst_pllx ody_rst_pllx_t;
1558
1559 static inline uint64_t ODY_RST_PLLX(uint64_t a) __attribute__ ((pure, always_inline));
ODY_RST_PLLX(uint64_t a)1560 static inline uint64_t ODY_RST_PLLX(uint64_t a)
1561 {
1562 if (a <= 15)
1563 return 0x87e00a001000ll + 0x10ll * ((a) & 0xf);
1564 __ody_csr_fatal("RST_PLLX", 1, a, 0, 0, 0, 0, 0);
1565 }
1566
1567 #define typedef_ODY_RST_PLLX(a) ody_rst_pllx_t
1568 #define bustype_ODY_RST_PLLX(a) CSR_TYPE_RSL
1569 #define basename_ODY_RST_PLLX(a) "RST_PLLX"
1570 #define device_bar_ODY_RST_PLLX(a) 0x2 /* PF_BAR2 */
1571 #define busnum_ODY_RST_PLLX(a) (a)
1572 #define arguments_ODY_RST_PLLX(a) (a), -1, -1, -1
1573
1574 /**
1575 * Register (RSL) rst_ref_cntr
1576 *
1577 * RST Reference-Counter Register
1578 * This register is not accessible through ROM scripts; see SCR_WRITE32_S[ADDR].
1579 */
1580 union ody_rst_ref_cntr {
1581 uint64_t u;
1582 struct ody_rst_ref_cntr_s {
1583 uint64_t cnt : 64;
1584 } s;
1585 /* struct ody_rst_ref_cntr_s cn; */
1586 };
1587 typedef union ody_rst_ref_cntr ody_rst_ref_cntr_t;
1588
1589 #define ODY_RST_REF_CNTR ODY_RST_REF_CNTR_FUNC()
1590 static inline uint64_t ODY_RST_REF_CNTR_FUNC(void) __attribute__ ((pure, always_inline));
ODY_RST_REF_CNTR_FUNC(void)1591 static inline uint64_t ODY_RST_REF_CNTR_FUNC(void)
1592 {
1593 return 0x87e006001758ll;
1594 }
1595
1596 #define typedef_ODY_RST_REF_CNTR ody_rst_ref_cntr_t
1597 #define bustype_ODY_RST_REF_CNTR CSR_TYPE_RSL
1598 #define basename_ODY_RST_REF_CNTR "RST_REF_CNTR"
1599 #define device_bar_ODY_RST_REF_CNTR 0x0 /* PF_BAR0 */
1600 #define busnum_ODY_RST_REF_CNTR 0
1601 #define arguments_ODY_RST_REF_CNTR -1, -1, -1, -1
1602
1603 /**
1604 * Register (RSL) rst_reset_active
1605 *
1606 * RST Domain Reset Active Status Register
1607 * This register is not accessible through ROM scripts; see SCR_WRITE32_S[ADDR].
1608 */
1609 union ody_rst_reset_active {
1610 uint64_t u;
1611 struct ody_rst_reset_active_s {
1612 uint64_t chip : 1;
1613 uint64_t core : 1;
1614 uint64_t mcp : 1;
1615 uint64_t scp : 1;
1616 uint64_t bphy : 1;
1617 uint64_t xcp2 : 1;
1618 uint64_t reserved_6_63 : 58;
1619 } s;
1620 /* struct ody_rst_reset_active_s cn; */
1621 };
1622 typedef union ody_rst_reset_active ody_rst_reset_active_t;
1623
1624 #define ODY_RST_RESET_ACTIVE ODY_RST_RESET_ACTIVE_FUNC()
1625 static inline uint64_t ODY_RST_RESET_ACTIVE_FUNC(void) __attribute__ ((pure, always_inline));
ODY_RST_RESET_ACTIVE_FUNC(void)1626 static inline uint64_t ODY_RST_RESET_ACTIVE_FUNC(void)
1627 {
1628 return 0x87e006001888ll;
1629 }
1630
1631 #define typedef_ODY_RST_RESET_ACTIVE ody_rst_reset_active_t
1632 #define bustype_ODY_RST_RESET_ACTIVE CSR_TYPE_RSL
1633 #define basename_ODY_RST_RESET_ACTIVE "RST_RESET_ACTIVE"
1634 #define device_bar_ODY_RST_RESET_ACTIVE 0x0 /* PF_BAR0 */
1635 #define busnum_ODY_RST_RESET_ACTIVE 0
1636 #define arguments_ODY_RST_RESET_ACTIVE -1, -1, -1, -1
1637
1638 /**
1639 * Register (RSL) rst_scp_domain_w1c
1640 *
1641 * RST SCP Domain Soft Reset Clear Register
1642 * This register is not accessible through ROM scripts; see SCR_WRITE32_S[ADDR].
1643 */
1644 union ody_rst_scp_domain_w1c {
1645 uint64_t u;
1646 struct ody_rst_scp_domain_w1c_s {
1647 uint64_t soft_rst : 1;
1648 uint64_t reserved_1_63 : 63;
1649 } s;
1650 /* struct ody_rst_scp_domain_w1c_s cn; */
1651 };
1652 typedef union ody_rst_scp_domain_w1c ody_rst_scp_domain_w1c_t;
1653
1654 #define ODY_RST_SCP_DOMAIN_W1C ODY_RST_SCP_DOMAIN_W1C_FUNC()
1655 static inline uint64_t ODY_RST_SCP_DOMAIN_W1C_FUNC(void) __attribute__ ((pure, always_inline));
ODY_RST_SCP_DOMAIN_W1C_FUNC(void)1656 static inline uint64_t ODY_RST_SCP_DOMAIN_W1C_FUNC(void)
1657 {
1658 return 0x87e006001848ll;
1659 }
1660
1661 #define typedef_ODY_RST_SCP_DOMAIN_W1C ody_rst_scp_domain_w1c_t
1662 #define bustype_ODY_RST_SCP_DOMAIN_W1C CSR_TYPE_RSL
1663 #define basename_ODY_RST_SCP_DOMAIN_W1C "RST_SCP_DOMAIN_W1C"
1664 #define device_bar_ODY_RST_SCP_DOMAIN_W1C 0x0 /* PF_BAR0 */
1665 #define busnum_ODY_RST_SCP_DOMAIN_W1C 0
1666 #define arguments_ODY_RST_SCP_DOMAIN_W1C -1, -1, -1, -1
1667
1668 /**
1669 * Register (RSL) rst_scp_domain_w1s
1670 *
1671 * RST SCP Domain Soft Reset Set Register
1672 * This register is not accessible through ROM scripts; see SCR_WRITE32_S[ADDR].
1673 */
1674 union ody_rst_scp_domain_w1s {
1675 uint64_t u;
1676 struct ody_rst_scp_domain_w1s_s {
1677 uint64_t soft_rst : 1;
1678 uint64_t force_rst : 1;
1679 uint64_t reserved_2_63 : 62;
1680 } s;
1681 /* struct ody_rst_scp_domain_w1s_s cn; */
1682 };
1683 typedef union ody_rst_scp_domain_w1s ody_rst_scp_domain_w1s_t;
1684
1685 #define ODY_RST_SCP_DOMAIN_W1S ODY_RST_SCP_DOMAIN_W1S_FUNC()
1686 static inline uint64_t ODY_RST_SCP_DOMAIN_W1S_FUNC(void) __attribute__ ((pure, always_inline));
ODY_RST_SCP_DOMAIN_W1S_FUNC(void)1687 static inline uint64_t ODY_RST_SCP_DOMAIN_W1S_FUNC(void)
1688 {
1689 return 0x87e006001840ll;
1690 }
1691
1692 #define typedef_ODY_RST_SCP_DOMAIN_W1S ody_rst_scp_domain_w1s_t
1693 #define bustype_ODY_RST_SCP_DOMAIN_W1S CSR_TYPE_RSL
1694 #define basename_ODY_RST_SCP_DOMAIN_W1S "RST_SCP_DOMAIN_W1S"
1695 #define device_bar_ODY_RST_SCP_DOMAIN_W1S 0x0 /* PF_BAR0 */
1696 #define busnum_ODY_RST_SCP_DOMAIN_W1S 0
1697 #define arguments_ODY_RST_SCP_DOMAIN_W1S -1, -1, -1, -1
1698
1699 /**
1700 * Register (RSL) rst_sw_w1s
1701 *
1702 * RST Software W1S Data Register
1703 * This register is not accessible through ROM scripts; see SCR_WRITE32_S[ADDR].
1704 */
1705 union ody_rst_sw_w1s {
1706 uint64_t u;
1707 struct ody_rst_sw_w1s_s {
1708 uint64_t data : 64;
1709 } s;
1710 /* struct ody_rst_sw_w1s_s cn; */
1711 };
1712 typedef union ody_rst_sw_w1s ody_rst_sw_w1s_t;
1713
1714 #define ODY_RST_SW_W1S ODY_RST_SW_W1S_FUNC()
1715 static inline uint64_t ODY_RST_SW_W1S_FUNC(void) __attribute__ ((pure, always_inline));
ODY_RST_SW_W1S_FUNC(void)1716 static inline uint64_t ODY_RST_SW_W1S_FUNC(void)
1717 {
1718 return 0x87e0060017f0ll;
1719 }
1720
1721 #define typedef_ODY_RST_SW_W1S ody_rst_sw_w1s_t
1722 #define bustype_ODY_RST_SW_W1S CSR_TYPE_RSL
1723 #define basename_ODY_RST_SW_W1S "RST_SW_W1S"
1724 #define device_bar_ODY_RST_SW_W1S 0x0 /* PF_BAR0 */
1725 #define busnum_ODY_RST_SW_W1S 0
1726 #define arguments_ODY_RST_SW_W1S -1, -1, -1, -1
1727
1728 /**
1729 * Register (RSL) rst_test_pll#
1730 *
1731 * RST Manual PLL Control Register
1732 * These registers control manual ARO programming and Test features.
1733 *
1734 * The logic associated with the PLL functions can only process one operation at a time.
1735 * Writes to this register should only occur when both the RST_PLL(x)[NEXT_PGM] and
1736 * RST_PLL(x)[NEXT_SWITCH] fields are zero. Additionally a read operation should occur
1737 * between writes to this register to allow time for the test setting to be transmitted
1738 * successfully before new setting are applied.
1739 */
1740 union ody_rst_test_pllx {
1741 uint64_t u;
1742 struct ody_rst_test_pllx_s {
1743 uint64_t stop_cnt : 32;
1744 uint64_t stop_clk : 1;
1745 uint64_t msc_enable : 1;
1746 uint64_t testclk_pll1 : 1;
1747 uint64_t reserved_35_39 : 5;
1748 uint64_t test_ana : 5;
1749 uint64_t test_rsvd : 3;
1750 uint64_t reserved_48_63 : 16;
1751 } s;
1752 /* struct ody_rst_test_pllx_s cn; */
1753 };
1754 typedef union ody_rst_test_pllx ody_rst_test_pllx_t;
1755
1756 static inline uint64_t ODY_RST_TEST_PLLX(uint64_t a) __attribute__ ((pure, always_inline));
ODY_RST_TEST_PLLX(uint64_t a)1757 static inline uint64_t ODY_RST_TEST_PLLX(uint64_t a)
1758 {
1759 if (a <= 15)
1760 return 0x87e00a001200ll + 8ll * ((a) & 0xf);
1761 __ody_csr_fatal("RST_TEST_PLLX", 1, a, 0, 0, 0, 0, 0);
1762 }
1763
1764 #define typedef_ODY_RST_TEST_PLLX(a) ody_rst_test_pllx_t
1765 #define bustype_ODY_RST_TEST_PLLX(a) CSR_TYPE_RSL
1766 #define basename_ODY_RST_TEST_PLLX(a) "RST_TEST_PLLX"
1767 #define device_bar_ODY_RST_TEST_PLLX(a) 0x2 /* PF_BAR2 */
1768 #define busnum_ODY_RST_TEST_PLLX(a) (a)
1769 #define arguments_ODY_RST_TEST_PLLX(a) (a), -1, -1, -1
1770
1771 /**
1772 * Register (RSL) rst_thermal_alert
1773 *
1774 * RST Thermal Alert Register
1775 * This register is not accessible through ROM scripts; see SCR_WRITE32_S[ADDR].
1776 */
1777 union ody_rst_thermal_alert {
1778 uint64_t u;
1779 struct ody_rst_thermal_alert_s {
1780 uint64_t alert : 1;
1781 uint64_t reserved_1_7 : 7;
1782 uint64_t trip : 1;
1783 uint64_t reserved_9_63 : 55;
1784 } s;
1785 /* struct ody_rst_thermal_alert_s cn; */
1786 };
1787 typedef union ody_rst_thermal_alert ody_rst_thermal_alert_t;
1788
1789 #define ODY_RST_THERMAL_ALERT ODY_RST_THERMAL_ALERT_FUNC()
1790 static inline uint64_t ODY_RST_THERMAL_ALERT_FUNC(void) __attribute__ ((pure, always_inline));
ODY_RST_THERMAL_ALERT_FUNC(void)1791 static inline uint64_t ODY_RST_THERMAL_ALERT_FUNC(void)
1792 {
1793 return 0x87e006001690ll;
1794 }
1795
1796 #define typedef_ODY_RST_THERMAL_ALERT ody_rst_thermal_alert_t
1797 #define bustype_ODY_RST_THERMAL_ALERT CSR_TYPE_RSL
1798 #define basename_ODY_RST_THERMAL_ALERT "RST_THERMAL_ALERT"
1799 #define device_bar_ODY_RST_THERMAL_ALERT 0x0 /* PF_BAR0 */
1800 #define busnum_ODY_RST_THERMAL_ALERT 0
1801 #define arguments_ODY_RST_THERMAL_ALERT -1, -1, -1, -1
1802
1803 /**
1804 * Register (RSL) rst_xcp2_domain_w1c
1805 *
1806 * RST CCP/XCP2 Domain Soft Reset Clear Register
1807 * This register is not accessible through ROM scripts; see SCR_WRITE32_S[ADDR].
1808 */
1809 union ody_rst_xcp2_domain_w1c {
1810 uint64_t u;
1811 struct ody_rst_xcp2_domain_w1c_s {
1812 uint64_t soft_rst : 1;
1813 uint64_t reserved_1_63 : 63;
1814 } s;
1815 /* struct ody_rst_xcp2_domain_w1c_s cn; */
1816 };
1817 typedef union ody_rst_xcp2_domain_w1c ody_rst_xcp2_domain_w1c_t;
1818
1819 #define ODY_RST_XCP2_DOMAIN_W1C ODY_RST_XCP2_DOMAIN_W1C_FUNC()
1820 static inline uint64_t ODY_RST_XCP2_DOMAIN_W1C_FUNC(void) __attribute__ ((pure, always_inline));
ODY_RST_XCP2_DOMAIN_W1C_FUNC(void)1821 static inline uint64_t ODY_RST_XCP2_DOMAIN_W1C_FUNC(void)
1822 {
1823 return 0x87e006001878ll;
1824 }
1825
1826 #define typedef_ODY_RST_XCP2_DOMAIN_W1C ody_rst_xcp2_domain_w1c_t
1827 #define bustype_ODY_RST_XCP2_DOMAIN_W1C CSR_TYPE_RSL
1828 #define basename_ODY_RST_XCP2_DOMAIN_W1C "RST_XCP2_DOMAIN_W1C"
1829 #define device_bar_ODY_RST_XCP2_DOMAIN_W1C 0x0 /* PF_BAR0 */
1830 #define busnum_ODY_RST_XCP2_DOMAIN_W1C 0
1831 #define arguments_ODY_RST_XCP2_DOMAIN_W1C -1, -1, -1, -1
1832
1833 /**
1834 * Register (RSL) rst_xcp2_domain_w1s
1835 *
1836 * RST CCP/XCP2 Domain Soft Reset Set Register
1837 * This register is not accessible through ROM scripts; see SCR_WRITE32_S[ADDR].
1838 */
1839 union ody_rst_xcp2_domain_w1s {
1840 uint64_t u;
1841 struct ody_rst_xcp2_domain_w1s_s {
1842 uint64_t soft_rst : 1;
1843 uint64_t force_rst : 1;
1844 uint64_t reserved_2_63 : 62;
1845 } s;
1846 /* struct ody_rst_xcp2_domain_w1s_s cn; */
1847 };
1848 typedef union ody_rst_xcp2_domain_w1s ody_rst_xcp2_domain_w1s_t;
1849
1850 #define ODY_RST_XCP2_DOMAIN_W1S ODY_RST_XCP2_DOMAIN_W1S_FUNC()
1851 static inline uint64_t ODY_RST_XCP2_DOMAIN_W1S_FUNC(void) __attribute__ ((pure, always_inline));
ODY_RST_XCP2_DOMAIN_W1S_FUNC(void)1852 static inline uint64_t ODY_RST_XCP2_DOMAIN_W1S_FUNC(void)
1853 {
1854 return 0x87e006001870ll;
1855 }
1856
1857 #define typedef_ODY_RST_XCP2_DOMAIN_W1S ody_rst_xcp2_domain_w1s_t
1858 #define bustype_ODY_RST_XCP2_DOMAIN_W1S CSR_TYPE_RSL
1859 #define basename_ODY_RST_XCP2_DOMAIN_W1S "RST_XCP2_DOMAIN_W1S"
1860 #define device_bar_ODY_RST_XCP2_DOMAIN_W1S 0x0 /* PF_BAR0 */
1861 #define busnum_ODY_RST_XCP2_DOMAIN_W1S 0
1862 #define arguments_ODY_RST_XCP2_DOMAIN_W1S -1, -1, -1, -1
1863
1864 #endif /* __ODY_CSRS_RST_H__ */
1865