1 #ifndef __ODY_CSRS_PCCPF_H__
2 #define __ODY_CSRS_PCCPF_H__
3 /* This file is auto-generated. Do not edit */
4
5 /***********************license start***********************************
6 * Copyright (C) 2021-2026 Marvell.
7 * SPDX-License-Identifier: BSD-3-Clause
8 * https://spdx.org/licenses
9 ***********************license end**************************************/
10
11
12 /**
13 * @file
14 *
15 * Configuration and status register (CSR) address and type definitions for
16 * PCCPF.
17 *
18 * This file is auto generated. Do not edit.
19 *
20 */
21
22 /**
23 * Enumeration pcc_dev_con_e
24 *
25 * PCC Device Connection Enumeration
26 * Enumerates where the device is connected in the topology. Software must rely on discovery and
27 * not use this enumeration as the values will vary by product, and the mnemonics are a super-set
28 * of the devices available. The value of the enumeration is formatted as defined by
29 * PCC_DEV_CON_S.
30 */
31 #define ODY_PCC_DEV_CON_E_APAX(a) (0x480 + (a))
32 #define ODY_PCC_DEV_CON_E_AVS (0xf8)
33 #define ODY_PCC_DEV_CON_E_BTS (0x168)
34 #define ODY_PCC_DEV_CON_E_CPC (0xd0)
35 #define ODY_PCC_DEV_CON_E_CST (0x90)
36 #define ODY_PCC_DEV_CON_E_DSSX(a) (0x2c0 + (a))
37 #define ODY_PCC_DEV_CON_E_EHSM (0xd8)
38 #define ODY_PCC_DEV_CON_E_FUS (0x103)
39 #define ODY_PCC_DEV_CON_E_GIC (0x30)
40 #define ODY_PCC_DEV_CON_E_GPIO (0x88)
41 #define ODY_PCC_DEV_CON_E_GSERP_32GX(a) (0x1e0 + (a))
42 #define ODY_PCC_DEV_CON_E_GTI (0x38)
43 #define ODY_PCC_DEV_CON_E_I3CMOX(a) (0x4f0 + (a))
44 #define ODY_PCC_DEV_CON_E_I3CSMX(a) (0x4f4 + (a))
45 #define ODY_PCC_DEV_CON_E_IOBNX(a) (0x150 + (a))
46 #define ODY_PCC_DEV_CON_E_IOBPCX(a) (0x158 + (a))
47 #define ODY_PCC_DEV_CON_E_MDC (0x160)
48 #define ODY_PCC_DEV_CON_E_MIO_PTP (0x50)
49 #define ODY_PCC_DEV_CON_E_MIO_TWSX(a) (0x1c0 + (a))
50 #define ODY_PCC_DEV_CON_E_MRML (0x100)
51 #define ODY_PCC_DEV_CON_E_MRMLB1 (0x200)
52 #define ODY_PCC_DEV_CON_E_MRMLB2 (0x300)
53 #define ODY_PCC_DEV_CON_E_MRMLB3 (0x400)
54 #define ODY_PCC_DEV_CON_E_NCBX(a) (0x1a0 + (a))
55 #define ODY_PCC_DEV_CON_E_NCBPCX(a) (0x1b0 + (a))
56 #define ODY_PCC_DEV_CON_E_OCLAX(a) (0x301 + (a))
57 #define ODY_PCC_DEV_CON_E_ODM0 (0x800)
58 #define ODY_PCC_DEV_CON_E_PCCBR_MRML (8)
59 #define ODY_PCC_DEV_CON_E_PCCBR_MRMLB1 (0x60)
60 #define ODY_PCC_DEV_CON_E_PCCBR_MRMLB2 (0x68)
61 #define ODY_PCC_DEV_CON_E_PCCBR_MRMLB3 (0x70)
62 #define ODY_PCC_DEV_CON_E_PCCBR_ODM0 (0xc0)
63 #define ODY_PCC_DEV_CON_E_PCCBR_RNM (0x78)
64 #define ODY_PCC_DEV_CON_E_PCIERCX(a) (0x30000 + 0x10000 * (a))
65 #define ODY_PCC_DEV_CON_E_PEMX(a) (0x10080 + 8 * (a))
66 #define ODY_PCC_DEV_CON_E_PEMSECX(a) (0x10000 + 8 * (a))
67 #define ODY_PCC_DEV_CON_E_RNM (0x500)
68 #define ODY_PCC_DEV_CON_E_RST (0x101)
69 #define ODY_PCC_DEV_CON_E_SMMU0 (0x10)
70 #define ODY_PCC_DEV_CON_E_SMMU1 (0x18)
71 #define ODY_PCC_DEV_CON_E_SMMU2 (0x20)
72 #define ODY_PCC_DEV_CON_E_SMMU3 (0x28)
73 #define ODY_PCC_DEV_CON_E_SPIX(a) (0x40 + 8 * (a))
74 #define ODY_PCC_DEV_CON_E_TADX(a) (0x380 + (a))
75 #define ODY_PCC_DEV_CON_E_TSNX(a) (0x401 + (a))
76 #define ODY_PCC_DEV_CON_E_UAAX(a) (0x1d8 + (a))
77 #define ODY_PCC_DEV_CON_E_XCPX(a) (0xe0 + 8 * (a))
78
79 /**
80 * Enumeration pcc_dev_idl_e
81 *
82 * PCC Device ID Low Enumeration
83 * Enumerates the values of the PCI configuration header Device ID bits
84 * \<7:0\>.
85 */
86 #define ODY_PCC_DEV_IDL_E_AP5 (0x76)
87 #define ODY_PCC_DEV_IDL_E_AP6 (0x86)
88 #define ODY_PCC_DEV_IDL_E_APA (0x93)
89 #define ODY_PCC_DEV_IDL_E_AVS (0x6a)
90 #define ODY_PCC_DEV_IDL_E_BCH (0x43)
91 #define ODY_PCC_DEV_IDL_E_BCH_VF (0x44)
92 #define ODY_PCC_DEV_IDL_E_BGX (0x26)
93 #define ODY_PCC_DEV_IDL_E_BPHY (0x89)
94 #define ODY_PCC_DEV_IDL_E_BTS (0x88)
95 #define ODY_PCC_DEV_IDL_E_CCS (0x6e)
96 #define ODY_PCC_DEV_IDL_E_CCU (0x6f)
97 #define ODY_PCC_DEV_IDL_E_CGX (0x59)
98 #define ODY_PCC_DEV_IDL_E_CHIP (0)
99 #define ODY_PCC_DEV_IDL_E_CHIP_VF (3)
100 #define ODY_PCC_DEV_IDL_E_CPC (0x68)
101 #define ODY_PCC_DEV_IDL_E_CPT (0x40)
102 #define ODY_PCC_DEV_IDL_E_CPT_VF (0x41)
103 #define ODY_PCC_DEV_IDL_E_CST (0x9d)
104 #define ODY_PCC_DEV_IDL_E_DAP (0x2c)
105 #define ODY_PCC_DEV_IDL_E_DDF (0x45)
106 #define ODY_PCC_DEV_IDL_E_DDF_VF (0x46)
107 #define ODY_PCC_DEV_IDL_E_DFA (0x19)
108 #define ODY_PCC_DEV_IDL_E_DPI (0x57)
109 #define ODY_PCC_DEV_IDL_E_DPI5 (0x80)
110 #define ODY_PCC_DEV_IDL_E_DPI5_VF (0x81)
111 #define ODY_PCC_DEV_IDL_E_DPI_VF (0x58)
112 #define ODY_PCC_DEV_IDL_E_DSS (0x90)
113 #define ODY_PCC_DEV_IDL_E_EHSM (0x72)
114 #define ODY_PCC_DEV_IDL_E_EMMC2 (0x95)
115 #define ODY_PCC_DEV_IDL_E_FPA (0x52)
116 #define ODY_PCC_DEV_IDL_E_FPA_VF (0x53)
117 #define ODY_PCC_DEV_IDL_E_FUS5 (0x74)
118 #define ODY_PCC_DEV_IDL_E_FUSF (0x32)
119 #define ODY_PCC_DEV_IDL_E_GIC (9)
120 #define ODY_PCC_DEV_IDL_E_GIC5 (0x71)
121 #define ODY_PCC_DEV_IDL_E_GPIO (0xa)
122 #define ODY_PCC_DEV_IDL_E_GSER (0x25)
123 #define ODY_PCC_DEV_IDL_E_GSERC (0x3b)
124 #define ODY_PCC_DEV_IDL_E_GSERJ (0x3c)
125 #define ODY_PCC_DEV_IDL_E_GSERM (0x9a)
126 #define ODY_PCC_DEV_IDL_E_GSERP (0x3a)
127 #define ODY_PCC_DEV_IDL_E_GSERP_32G (0x3e)
128 #define ODY_PCC_DEV_IDL_E_GSERP_64G (0x3f)
129 #define ODY_PCC_DEV_IDL_E_GSERR (0x39)
130 #define ODY_PCC_DEV_IDL_E_GTI (0x17)
131 #define ODY_PCC_DEV_IDL_E_I3C (0x9c)
132 #define ODY_PCC_DEV_IDL_E_I3CMO (0xa0)
133 #define ODY_PCC_DEV_IDL_E_I3CSM (0xa1)
134 #define ODY_PCC_DEV_IDL_E_IOBN (0x27)
135 #define ODY_PCC_DEV_IDL_E_IOBN5 (0x6b)
136 #define ODY_PCC_DEV_IDL_E_IOBN6 (0x94)
137 #define ODY_PCC_DEV_IDL_E_IOBPC (0xa3)
138 #define ODY_PCC_DEV_IDL_E_KEY (0x16)
139 #define ODY_PCC_DEV_IDL_E_L2C (0x21)
140 #define ODY_PCC_DEV_IDL_E_L2C_CBC (0x2f)
141 #define ODY_PCC_DEV_IDL_E_L2C_MCI (0x30)
142 #define ODY_PCC_DEV_IDL_E_L2C_TAD (0x2e)
143 #define ODY_PCC_DEV_IDL_E_LBK (0x42)
144 #define ODY_PCC_DEV_IDL_E_LBK5 (0x61)
145 #define ODY_PCC_DEV_IDL_E_LMC (0x22)
146 #define ODY_PCC_DEV_IDL_E_MCC (0x70)
147 #define ODY_PCC_DEV_IDL_E_MCS (0x96)
148 #define ODY_PCC_DEV_IDL_E_MDC (0x73)
149 #define ODY_PCC_DEV_IDL_E_MIO_BOOT (0x11)
150 #define ODY_PCC_DEV_IDL_E_MIO_EMM (0x10)
151 #define ODY_PCC_DEV_IDL_E_MIO_FUS (0x31)
152 #define ODY_PCC_DEV_IDL_E_MIO_PTP (0xc)
153 #define ODY_PCC_DEV_IDL_E_MIO_PTP5 (0x9e)
154 #define ODY_PCC_DEV_IDL_E_MIO_TWS (0x12)
155 #define ODY_PCC_DEV_IDL_E_MIX (0xd)
156 #define ODY_PCC_DEV_IDL_E_ML (0x92)
157 #define ODY_PCC_DEV_IDL_E_MPI (0xb)
158 #define ODY_PCC_DEV_IDL_E_MRML (1)
159 #define ODY_PCC_DEV_IDL_E_MRML5 (0x75)
160 #define ODY_PCC_DEV_IDL_E_NCB (0x97)
161 #define ODY_PCC_DEV_IDL_E_NCBPC (0xa2)
162 #define ODY_PCC_DEV_IDL_E_NCSI (0x29)
163 #define ODY_PCC_DEV_IDL_E_NDF (0x4f)
164 #define ODY_PCC_DEV_IDL_E_NIC (0x1e)
165 #define ODY_PCC_DEV_IDL_E_NIC_VF (0x34)
166 #define ODY_PCC_DEV_IDL_E_OCLA (0x23)
167 #define ODY_PCC_DEV_IDL_E_OCX (0x13)
168 #define ODY_PCC_DEV_IDL_E_OCX5 (0x79)
169 #define ODY_PCC_DEV_IDL_E_ODM (0x8b)
170 #define ODY_PCC_DEV_IDL_E_ODM_VF (0x8c)
171 #define ODY_PCC_DEV_IDL_E_OSM (0x24)
172 #define ODY_PCC_DEV_IDL_E_PBUS (0x35)
173 #define ODY_PCC_DEV_IDL_E_PCCBR (2)
174 #define ODY_PCC_DEV_IDL_E_PCIERC (0x2d)
175 #define ODY_PCC_DEV_IDL_E_PCM (0x4e)
176 #define ODY_PCC_DEV_IDL_E_PEM (0x20)
177 #define ODY_PCC_DEV_IDL_E_PEM5 (0x6c)
178 #define ODY_PCC_DEV_IDL_E_PEMSEC (0x28)
179 #define ODY_PCC_DEV_IDL_E_PKI (0x47)
180 #define ODY_PCC_DEV_IDL_E_PKO (0x48)
181 #define ODY_PCC_DEV_IDL_E_PKO_VF (0x49)
182 #define ODY_PCC_DEV_IDL_E_PSBM (0x69)
183 #define ODY_PCC_DEV_IDL_E_RAD (0x1d)
184 #define ODY_PCC_DEV_IDL_E_RAD_VF (0x36)
185 #define ODY_PCC_DEV_IDL_E_RGX (0x54)
186 #define ODY_PCC_DEV_IDL_E_RNM (0x18)
187 #define ODY_PCC_DEV_IDL_E_RNM2 (0x98)
188 #define ODY_PCC_DEV_IDL_E_RNM2_VF (0x99)
189 #define ODY_PCC_DEV_IDL_E_RNM_VF (0x33)
190 #define ODY_PCC_DEV_IDL_E_RPM (0x60)
191 #define ODY_PCC_DEV_IDL_E_RPM2 (0x9f)
192 #define ODY_PCC_DEV_IDL_E_RST (0xe)
193 #define ODY_PCC_DEV_IDL_E_RST5 (0x85)
194 #define ODY_PCC_DEV_IDL_E_RSVD_NONE (0xff)
195 #define ODY_PCC_DEV_IDL_E_RTT (0x8a)
196 #define ODY_PCC_DEV_IDL_E_RVU (0x63)
197 #define ODY_PCC_DEV_IDL_E_RVU_AF (0x65)
198 #define ODY_PCC_DEV_IDL_E_RVU_VF (0x64)
199 #define ODY_PCC_DEV_IDL_E_SATA (0x1c)
200 #define ODY_PCC_DEV_IDL_E_SATA5 (0x84)
201 #define ODY_PCC_DEV_IDL_E_SGP (0x2a)
202 #define ODY_PCC_DEV_IDL_E_SLI (0x15)
203 #define ODY_PCC_DEV_IDL_E_SLIRE (0x38)
204 #define ODY_PCC_DEV_IDL_E_SMI (0x2b)
205 #define ODY_PCC_DEV_IDL_E_SMMU (8)
206 #define ODY_PCC_DEV_IDL_E_SMMU3 (0x62)
207 #define ODY_PCC_DEV_IDL_E_SPI (0x9b)
208 #define ODY_PCC_DEV_IDL_E_SSO (0x4a)
209 #define ODY_PCC_DEV_IDL_E_SSOW (0x4c)
210 #define ODY_PCC_DEV_IDL_E_SSOW_VF (0x4d)
211 #define ODY_PCC_DEV_IDL_E_SSO_VF (0x4b)
212 #define ODY_PCC_DEV_IDL_E_SW_RSVDX(a) (0xe0 + (a))
213 #define ODY_PCC_DEV_IDL_E_SW_RVU_AF_VF (0xf8)
214 #define ODY_PCC_DEV_IDL_E_SW_RVU_CPT10_PF (0xf2)
215 #define ODY_PCC_DEV_IDL_E_SW_RVU_CPT10_VF (0xf3)
216 #define ODY_PCC_DEV_IDL_E_SW_RVU_CPT_PF (0xfd)
217 #define ODY_PCC_DEV_IDL_E_SW_RVU_CPT_VF (0xfe)
218 #define ODY_PCC_DEV_IDL_E_SW_RVU_IPSEC_INLINE_PF (0xf0)
219 #define ODY_PCC_DEV_IDL_E_SW_RVU_IPSEC_INLINE_VF (0xf1)
220 #define ODY_PCC_DEV_IDL_E_SW_RVU_NPA_PF (0xfb)
221 #define ODY_PCC_DEV_IDL_E_SW_RVU_NPA_VF (0xfc)
222 #define ODY_PCC_DEV_IDL_E_SW_RVU_REE_PF (0xf4)
223 #define ODY_PCC_DEV_IDL_E_SW_RVU_REE_VF (0xf5)
224 #define ODY_PCC_DEV_IDL_E_SW_RVU_SDP_PF (0xf6)
225 #define ODY_PCC_DEV_IDL_E_SW_RVU_SDP_VF (0xf7)
226 #define ODY_PCC_DEV_IDL_E_SW_RVU_SSO_TIM_PF (0xf9)
227 #define ODY_PCC_DEV_IDL_E_SW_RVU_SSO_TIM_VF (0xfa)
228 #define ODY_PCC_DEV_IDL_E_TAD (0x91)
229 #define ODY_PCC_DEV_IDL_E_TIM (0x50)
230 #define ODY_PCC_DEV_IDL_E_TIM_VF (0x51)
231 #define ODY_PCC_DEV_IDL_E_TNS (0x1f)
232 #define ODY_PCC_DEV_IDL_E_TSN (0x6d)
233 #define ODY_PCC_DEV_IDL_E_UAA (0xf)
234 #define ODY_PCC_DEV_IDL_E_USBDRD (0x55)
235 #define ODY_PCC_DEV_IDL_E_USBH (0x1b)
236 #define ODY_PCC_DEV_IDL_E_VRM (0x14)
237 #define ODY_PCC_DEV_IDL_E_XCP (0x67)
238 #define ODY_PCC_DEV_IDL_E_XCV (0x56)
239 #define ODY_PCC_DEV_IDL_E_ZIP (0x1a)
240 #define ODY_PCC_DEV_IDL_E_ZIP5 (0x82)
241 #define ODY_PCC_DEV_IDL_E_ZIP5_VF (0x83)
242 #define ODY_PCC_DEV_IDL_E_ZIP_VF (0x37)
243
244 /**
245 * Enumeration pcc_jtag_dev_e
246 *
247 * PCC JTAG Device Enumeration
248 * Enumerates the device number sub-field of Marvell-assigned JTAG ID_Codes. Device number is
249 * mapped to Part_Number[7:4]. Where Part_Number [15:0] is mapped to ID_Code[27:12].
250 */
251 #define ODY_PCC_JTAG_DEV_E_DAP (1)
252 #define ODY_PCC_JTAG_DEV_E_ECP (4)
253 #define ODY_PCC_JTAG_DEV_E_EHSM (5)
254 #define ODY_PCC_JTAG_DEV_E_MAIN (0)
255 #define ODY_PCC_JTAG_DEV_E_MCP (3)
256 #define ODY_PCC_JTAG_DEV_E_SCP (2)
257
258 /**
259 * Enumeration pcc_pidr_partnum0_e
260 *
261 * PCC PIDR Part Number 0 Enumeration
262 * When *_PIDR1[PARTNUM1] = PCC_PIDR_PARTNUM1_E::COMP, enumerates the values of Marvell-
263 * assigned CoreSight PIDR part number 0 fields.
264 * For example SMMU()_PIDR0[PARTNUM0].
265 */
266 #define ODY_PCC_PIDR_PARTNUM0_E_CTI (0xd)
267 #define ODY_PCC_PIDR_PARTNUM0_E_DBG (0xe)
268 #define ODY_PCC_PIDR_PARTNUM0_E_ETR (0x13)
269 #define ODY_PCC_PIDR_PARTNUM0_E_GTI_BZ (4)
270 #define ODY_PCC_PIDR_PARTNUM0_E_GTI_CC (5)
271 #define ODY_PCC_PIDR_PARTNUM0_E_GTI_CTL (6)
272 #define ODY_PCC_PIDR_PARTNUM0_E_GTI_RD (7)
273 #define ODY_PCC_PIDR_PARTNUM0_E_GTI_WC (8)
274 #define ODY_PCC_PIDR_PARTNUM0_E_GTI_WR (9)
275 #define ODY_PCC_PIDR_PARTNUM0_E_NONE (0)
276 #define ODY_PCC_PIDR_PARTNUM0_E_PMU (0xa)
277 #define ODY_PCC_PIDR_PARTNUM0_E_RAS (0x12)
278 #define ODY_PCC_PIDR_PARTNUM0_E_RAS_MCC (0x14)
279 #define ODY_PCC_PIDR_PARTNUM0_E_SMMU (0xb)
280 #define ODY_PCC_PIDR_PARTNUM0_E_SMMU3 (0x11)
281 #define ODY_PCC_PIDR_PARTNUM0_E_SYSCTI (0xf)
282 #define ODY_PCC_PIDR_PARTNUM0_E_TRC (0x10)
283 #define ODY_PCC_PIDR_PARTNUM0_E_UAA (0xc)
284
285 /**
286 * Enumeration pcc_pidr_partnum1_e
287 *
288 * PCC PIDR Part Number 1 Enumeration
289 * Enumerates the values of Marvell-assigned CoreSight PIDR PARTNUM1 fields, for example
290 * SMMU()_PIDR1[PARTNUM1].
291 */
292 #define ODY_PCC_PIDR_PARTNUM1_E_COMP (2)
293 #define ODY_PCC_PIDR_PARTNUM1_E_PROD (1)
294
295 /**
296 * Enumeration pcc_prod_e
297 *
298 * PCC Device ID Product Enumeration
299 * Enumerates the die's chip identifier, used in PCCPF_XXX_ID[DEVID]\<15:8\> and other
300 * chip identification registers.
301 *
302 * See also GPIO_PKG_VER to differentiate between package variants.
303 */
304 #define ODY_PCC_PROD_E_CN103XX (0xbd)
305 #define ODY_PCC_PROD_E_CN106XX (0xb9)
306 #define ODY_PCC_PROD_E_CN109XX (0xb8)
307 #define ODY_PCC_PROD_E_CN81XX (0xa2)
308 #define ODY_PCC_PROD_E_CN83XX (0xa3)
309 #define ODY_PCC_PROD_E_CN88XX (0xa1)
310 #define ODY_PCC_PROD_E_CN93XX (0xb2)
311 #define ODY_PCC_PROD_E_CN98XX (0xb1)
312 #define ODY_PCC_PROD_E_CN99XX (0xaf)
313 #define ODY_PCC_PROD_E_CNF105XX (0xba)
314 #define ODY_PCC_PROD_E_CNF95XX (0xb3)
315 #define ODY_PCC_PROD_E_CNF95XXMM (0xb5)
316 #define ODY_PCC_PROD_E_GEN (0xa0)
317 #define ODY_PCC_PROD_E_LOKI (0xb4)
318 #define ODY_PCC_PROD_E_ODYSSEY (0xbf)
319 #define ODY_PCC_PROD_E_THOR (0xbc)
320
321 /**
322 * Enumeration pcc_vendor_e
323 *
324 * PCC Vendor ID Enumeration
325 * Enumerates the values of the PCI configuration header vendor ID.
326 */
327 #define ODY_PCC_VENDOR_E_CAVIUM (0x177d)
328
329 /**
330 * Enumeration pcc_vsecid_e
331 *
332 * PCC Vendor-Specific Capability ID Enumeration
333 * Enumerates the values of Marvell's vendor-specific PCI capability IDs.
334 */
335 #define ODY_PCC_VSECID_E_NONE (0)
336 #define ODY_PCC_VSECID_E_SY_RAS_DES (2)
337 #define ODY_PCC_VSECID_E_SY_RAS_DP (1)
338 #define ODY_PCC_VSECID_E_SY_RSVDX(a) (0 + (a))
339 #define ODY_PCC_VSECID_E_TX_BR (0xa1)
340 #define ODY_PCC_VSECID_E_TX_PF (0xa0)
341 #define ODY_PCC_VSECID_E_TX_VF (0xa2)
342
343 /**
344 * Structure pcc_class_code_s
345 *
346 * PCC Class Code Structure
347 * Defines the components of the PCC class code.
348 */
349 union ody_pcc_class_code_s {
350 uint32_t u;
351 struct ody_pcc_class_code_s_s {
352 uint32_t pi : 8;
353 uint32_t sc : 8;
354 uint32_t bcc : 8;
355 uint32_t reserved_24_31 : 8;
356 } s;
357 /* struct ody_pcc_class_code_s_s cn; */
358 };
359
360 /**
361 * Structure pcc_dev_con_s
362 *
363 * PCC Device Connection Structure
364 * Defines the components of the PCC device connection values enumerated by PCC_DEV_CON_E,
365 * using ARI format.
366 */
367 union ody_pcc_dev_con_s {
368 uint32_t u;
369 struct ody_pcc_dev_con_s_s {
370 uint32_t func : 8;
371 uint32_t bus : 8;
372 uint32_t dmn : 6;
373 uint32_t reserved_22_31 : 10;
374 } s;
375 /* struct ody_pcc_dev_con_s_s cn; */
376 };
377
378 /**
379 * Structure pcc_ea_entry_s
380 *
381 * PCC PCI Enhanced Allocation Entry Structure
382 * This structure describes the format of an enhanced allocation entry stored in
383 * PCCPF_XXX_EA_ENTRY(). This describes what PCC hardware generates only; software must
384 * implement a full EA parser including testing the [ENTRY_SIZE], [BASE64] and
385 * [OFFSET64] fields.
386 *
387 * PCI configuration registers are 32-bits, however due to tool limitations this
388 * structure is described as a little-endian 64-bit wide structure.
389 */
390 union ody_pcc_ea_entry_s {
391 uint64_t u[3];
392 struct ody_pcc_ea_entry_s_s {
393 uint64_t entry_size : 3;
394 uint64_t reserved_3 : 1;
395 uint64_t bei : 4;
396 uint64_t pri_prop : 8;
397 uint64_t sec_prop : 8;
398 uint64_t reserved_24_29 : 6;
399 uint64_t w : 1;
400 uint64_t enable : 1;
401 uint64_t reserved_32 : 1;
402 uint64_t base64 : 1;
403 uint64_t basel : 30;
404 uint64_t reserved_64 : 1;
405 uint64_t offset64 : 1;
406 uint64_t offsetl : 30;
407 uint64_t baseh : 32;
408 uint64_t offseth : 32;
409 uint64_t reserved_160_191 : 32;
410 } s;
411 /* struct ody_pcc_ea_entry_s_s cn; */
412 };
413
414 /**
415 * Register (PCCPF) pccpf_xxx_aer_cap_hdr
416 *
417 * PCC PF AER Capability Header Register
418 * This register is the header of the 44-byte PCI advanced error reporting (AER) capability
419 * structure.
420 */
421 union ody_pccpf_xxx_aer_cap_hdr {
422 uint32_t u;
423 struct ody_pccpf_xxx_aer_cap_hdr_s {
424 uint32_t aerid : 16;
425 uint32_t cv : 4;
426 uint32_t nco : 12;
427 } s;
428 /* struct ody_pccpf_xxx_aer_cap_hdr_s cn; */
429 };
430 typedef union ody_pccpf_xxx_aer_cap_hdr ody_pccpf_xxx_aer_cap_hdr_t;
431
432 #define ODY_PCCPF_XXX_AER_CAP_HDR ODY_PCCPF_XXX_AER_CAP_HDR_FUNC()
433 static inline uint64_t ODY_PCCPF_XXX_AER_CAP_HDR_FUNC(void) __attribute__ ((pure, always_inline));
ODY_PCCPF_XXX_AER_CAP_HDR_FUNC(void)434 static inline uint64_t ODY_PCCPF_XXX_AER_CAP_HDR_FUNC(void)
435 {
436 return 0x140;
437 }
438
439 #define typedef_ODY_PCCPF_XXX_AER_CAP_HDR ody_pccpf_xxx_aer_cap_hdr_t
440 #define bustype_ODY_PCCPF_XXX_AER_CAP_HDR CSR_TYPE_PCCPF
441 #define basename_ODY_PCCPF_XXX_AER_CAP_HDR "PCCPF_XXX_AER_CAP_HDR"
442 #define busnum_ODY_PCCPF_XXX_AER_CAP_HDR 0
443 #define arguments_ODY_PCCPF_XXX_AER_CAP_HDR -1, -1, -1, -1
444
445 /**
446 * Register (PCCPF) pccpf_xxx_aer_cor_mask
447 *
448 * PCC PF AER Correctable Error Mask Register
449 * This register contains a mask bit for each nonreserved bit in PCCPF_XXX_AER_COR_STATUS.
450 * The mask bits are R/W for PCIe and software compatibility but are not used by hardware.
451 *
452 * This register is reset on a chip domain reset.
453 */
454 union ody_pccpf_xxx_aer_cor_mask {
455 uint32_t u;
456 struct ody_pccpf_xxx_aer_cor_mask_s {
457 uint32_t rcvr : 1;
458 uint32_t reserved_1_5 : 5;
459 uint32_t bad_tlp : 1;
460 uint32_t bad_dllp : 1;
461 uint32_t rep_roll : 1;
462 uint32_t reserved_9_11 : 3;
463 uint32_t rep_timer : 1;
464 uint32_t adv_nfat : 1;
465 uint32_t cor_intn : 1;
466 uint32_t reserved_15_31 : 17;
467 } s;
468 /* struct ody_pccpf_xxx_aer_cor_mask_s cn; */
469 };
470 typedef union ody_pccpf_xxx_aer_cor_mask ody_pccpf_xxx_aer_cor_mask_t;
471
472 #define ODY_PCCPF_XXX_AER_COR_MASK ODY_PCCPF_XXX_AER_COR_MASK_FUNC()
473 static inline uint64_t ODY_PCCPF_XXX_AER_COR_MASK_FUNC(void) __attribute__ ((pure, always_inline));
ODY_PCCPF_XXX_AER_COR_MASK_FUNC(void)474 static inline uint64_t ODY_PCCPF_XXX_AER_COR_MASK_FUNC(void)
475 {
476 return 0x154;
477 }
478
479 #define typedef_ODY_PCCPF_XXX_AER_COR_MASK ody_pccpf_xxx_aer_cor_mask_t
480 #define bustype_ODY_PCCPF_XXX_AER_COR_MASK CSR_TYPE_PCCPF
481 #define basename_ODY_PCCPF_XXX_AER_COR_MASK "PCCPF_XXX_AER_COR_MASK"
482 #define busnum_ODY_PCCPF_XXX_AER_COR_MASK 0
483 #define arguments_ODY_PCCPF_XXX_AER_COR_MASK -1, -1, -1, -1
484
485 /**
486 * Register (PCCPF) pccpf_xxx_aer_cor_status
487 *
488 * PCC PF AER Correctable Error Status Register
489 * This register is reset on a chip domain reset.
490 */
491 union ody_pccpf_xxx_aer_cor_status {
492 uint32_t u;
493 struct ody_pccpf_xxx_aer_cor_status_s {
494 uint32_t rcvr : 1;
495 uint32_t reserved_1_5 : 5;
496 uint32_t bad_tlp : 1;
497 uint32_t bad_dllp : 1;
498 uint32_t rep_roll : 1;
499 uint32_t reserved_9_11 : 3;
500 uint32_t rep_timer : 1;
501 uint32_t adv_nfat : 1;
502 uint32_t cor_intn : 1;
503 uint32_t reserved_15_31 : 17;
504 } s;
505 /* struct ody_pccpf_xxx_aer_cor_status_s cn; */
506 };
507 typedef union ody_pccpf_xxx_aer_cor_status ody_pccpf_xxx_aer_cor_status_t;
508
509 #define ODY_PCCPF_XXX_AER_COR_STATUS ODY_PCCPF_XXX_AER_COR_STATUS_FUNC()
510 static inline uint64_t ODY_PCCPF_XXX_AER_COR_STATUS_FUNC(void) __attribute__ ((pure, always_inline));
ODY_PCCPF_XXX_AER_COR_STATUS_FUNC(void)511 static inline uint64_t ODY_PCCPF_XXX_AER_COR_STATUS_FUNC(void)
512 {
513 return 0x150;
514 }
515
516 #define typedef_ODY_PCCPF_XXX_AER_COR_STATUS ody_pccpf_xxx_aer_cor_status_t
517 #define bustype_ODY_PCCPF_XXX_AER_COR_STATUS CSR_TYPE_PCCPF
518 #define basename_ODY_PCCPF_XXX_AER_COR_STATUS "PCCPF_XXX_AER_COR_STATUS"
519 #define busnum_ODY_PCCPF_XXX_AER_COR_STATUS 0
520 #define arguments_ODY_PCCPF_XXX_AER_COR_STATUS -1, -1, -1, -1
521
522 /**
523 * Register (PCCPF) pccpf_xxx_aer_uncor_mask
524 *
525 * PCC PF AER Uncorrectable Error Mask Register
526 * This register contains a mask bit for each nonreserved bit in PCCPF_XXX_AER_UNCOR_STATUS.
527 * The mask bits are R/W for PCIe and software compatibility but are not used by hardware.
528 *
529 * This register is reset on a chip domain reset.
530 */
531 union ody_pccpf_xxx_aer_uncor_mask {
532 uint32_t u;
533 struct ody_pccpf_xxx_aer_uncor_mask_s {
534 uint32_t reserved_0_3 : 4;
535 uint32_t dlp : 1;
536 uint32_t reserved_5_11 : 7;
537 uint32_t poison_tlp : 1;
538 uint32_t reserved_13 : 1;
539 uint32_t comp_time : 1;
540 uint32_t reserved_15 : 1;
541 uint32_t unx_comp : 1;
542 uint32_t reserved_17 : 1;
543 uint32_t malf_tlp : 1;
544 uint32_t reserved_19 : 1;
545 uint32_t unsup : 1;
546 uint32_t reserved_21 : 1;
547 uint32_t uncor_intn : 1;
548 uint32_t reserved_23_31 : 9;
549 } s;
550 /* struct ody_pccpf_xxx_aer_uncor_mask_s cn; */
551 };
552 typedef union ody_pccpf_xxx_aer_uncor_mask ody_pccpf_xxx_aer_uncor_mask_t;
553
554 #define ODY_PCCPF_XXX_AER_UNCOR_MASK ODY_PCCPF_XXX_AER_UNCOR_MASK_FUNC()
555 static inline uint64_t ODY_PCCPF_XXX_AER_UNCOR_MASK_FUNC(void) __attribute__ ((pure, always_inline));
ODY_PCCPF_XXX_AER_UNCOR_MASK_FUNC(void)556 static inline uint64_t ODY_PCCPF_XXX_AER_UNCOR_MASK_FUNC(void)
557 {
558 return 0x148;
559 }
560
561 #define typedef_ODY_PCCPF_XXX_AER_UNCOR_MASK ody_pccpf_xxx_aer_uncor_mask_t
562 #define bustype_ODY_PCCPF_XXX_AER_UNCOR_MASK CSR_TYPE_PCCPF
563 #define basename_ODY_PCCPF_XXX_AER_UNCOR_MASK "PCCPF_XXX_AER_UNCOR_MASK"
564 #define busnum_ODY_PCCPF_XXX_AER_UNCOR_MASK 0
565 #define arguments_ODY_PCCPF_XXX_AER_UNCOR_MASK -1, -1, -1, -1
566
567 /**
568 * Register (PCCPF) pccpf_xxx_aer_uncor_sever
569 *
570 * PCC PF AER Uncorrectable Error Severity Register
571 * This register controls whether an individual error is reported as a nonfatal or
572 * fatal error. An error is reported as fatal when the corresponding severity bit is set, and
573 * nonfatal otherwise.
574 *
575 * This register is reset on a chip domain reset.
576 */
577 union ody_pccpf_xxx_aer_uncor_sever {
578 uint32_t u;
579 struct ody_pccpf_xxx_aer_uncor_sever_s {
580 uint32_t reserved_0_3 : 4;
581 uint32_t dlp : 1;
582 uint32_t reserved_5_11 : 7;
583 uint32_t poison_tlp : 1;
584 uint32_t reserved_13 : 1;
585 uint32_t comp_time : 1;
586 uint32_t reserved_15 : 1;
587 uint32_t unx_comp : 1;
588 uint32_t reserved_17 : 1;
589 uint32_t malf_tlp : 1;
590 uint32_t reserved_19 : 1;
591 uint32_t unsup : 1;
592 uint32_t reserved_21 : 1;
593 uint32_t uncor_intn : 1;
594 uint32_t reserved_23_31 : 9;
595 } s;
596 /* struct ody_pccpf_xxx_aer_uncor_sever_s cn; */
597 };
598 typedef union ody_pccpf_xxx_aer_uncor_sever ody_pccpf_xxx_aer_uncor_sever_t;
599
600 #define ODY_PCCPF_XXX_AER_UNCOR_SEVER ODY_PCCPF_XXX_AER_UNCOR_SEVER_FUNC()
601 static inline uint64_t ODY_PCCPF_XXX_AER_UNCOR_SEVER_FUNC(void) __attribute__ ((pure, always_inline));
ODY_PCCPF_XXX_AER_UNCOR_SEVER_FUNC(void)602 static inline uint64_t ODY_PCCPF_XXX_AER_UNCOR_SEVER_FUNC(void)
603 {
604 return 0x14c;
605 }
606
607 #define typedef_ODY_PCCPF_XXX_AER_UNCOR_SEVER ody_pccpf_xxx_aer_uncor_sever_t
608 #define bustype_ODY_PCCPF_XXX_AER_UNCOR_SEVER CSR_TYPE_PCCPF
609 #define basename_ODY_PCCPF_XXX_AER_UNCOR_SEVER "PCCPF_XXX_AER_UNCOR_SEVER"
610 #define busnum_ODY_PCCPF_XXX_AER_UNCOR_SEVER 0
611 #define arguments_ODY_PCCPF_XXX_AER_UNCOR_SEVER -1, -1, -1, -1
612
613 /**
614 * Register (PCCPF) pccpf_xxx_aer_uncor_status
615 *
616 * PCC PF AER Uncorrectable Error Status Register
617 * This register is reset on a chip domain reset.
618 */
619 union ody_pccpf_xxx_aer_uncor_status {
620 uint32_t u;
621 struct ody_pccpf_xxx_aer_uncor_status_s {
622 uint32_t reserved_0_3 : 4;
623 uint32_t dlp : 1;
624 uint32_t reserved_5_11 : 7;
625 uint32_t poison_tlp : 1;
626 uint32_t reserved_13 : 1;
627 uint32_t comp_time : 1;
628 uint32_t reserved_15 : 1;
629 uint32_t unx_comp : 1;
630 uint32_t reserved_17 : 1;
631 uint32_t malf_tlp : 1;
632 uint32_t reserved_19 : 1;
633 uint32_t unsup : 1;
634 uint32_t reserved_21 : 1;
635 uint32_t uncor_intn : 1;
636 uint32_t reserved_23_31 : 9;
637 } s;
638 /* struct ody_pccpf_xxx_aer_uncor_status_s cn; */
639 };
640 typedef union ody_pccpf_xxx_aer_uncor_status ody_pccpf_xxx_aer_uncor_status_t;
641
642 #define ODY_PCCPF_XXX_AER_UNCOR_STATUS ODY_PCCPF_XXX_AER_UNCOR_STATUS_FUNC()
643 static inline uint64_t ODY_PCCPF_XXX_AER_UNCOR_STATUS_FUNC(void) __attribute__ ((pure, always_inline));
ODY_PCCPF_XXX_AER_UNCOR_STATUS_FUNC(void)644 static inline uint64_t ODY_PCCPF_XXX_AER_UNCOR_STATUS_FUNC(void)
645 {
646 return 0x144;
647 }
648
649 #define typedef_ODY_PCCPF_XXX_AER_UNCOR_STATUS ody_pccpf_xxx_aer_uncor_status_t
650 #define bustype_ODY_PCCPF_XXX_AER_UNCOR_STATUS CSR_TYPE_PCCPF
651 #define basename_ODY_PCCPF_XXX_AER_UNCOR_STATUS "PCCPF_XXX_AER_UNCOR_STATUS"
652 #define busnum_ODY_PCCPF_XXX_AER_UNCOR_STATUS 0
653 #define arguments_ODY_PCCPF_XXX_AER_UNCOR_STATUS -1, -1, -1, -1
654
655 /**
656 * Register (PCCPF) pccpf_xxx_ari_cap_hdr
657 *
658 * PCC PF ARI Capability Header Register
659 * This register is the header of the eight-byte PCI ARI capability structure.
660 * If this device is on bus 0x0, this ARI header is not present and reads as 0x0.
661 */
662 union ody_pccpf_xxx_ari_cap_hdr {
663 uint32_t u;
664 struct ody_pccpf_xxx_ari_cap_hdr_s {
665 uint32_t ariid : 16;
666 uint32_t cv : 4;
667 uint32_t nco : 12;
668 } s;
669 /* struct ody_pccpf_xxx_ari_cap_hdr_s cn; */
670 };
671 typedef union ody_pccpf_xxx_ari_cap_hdr ody_pccpf_xxx_ari_cap_hdr_t;
672
673 #define ODY_PCCPF_XXX_ARI_CAP_HDR ODY_PCCPF_XXX_ARI_CAP_HDR_FUNC()
674 static inline uint64_t ODY_PCCPF_XXX_ARI_CAP_HDR_FUNC(void) __attribute__ ((pure, always_inline));
ODY_PCCPF_XXX_ARI_CAP_HDR_FUNC(void)675 static inline uint64_t ODY_PCCPF_XXX_ARI_CAP_HDR_FUNC(void)
676 {
677 return 0x170;
678 }
679
680 #define typedef_ODY_PCCPF_XXX_ARI_CAP_HDR ody_pccpf_xxx_ari_cap_hdr_t
681 #define bustype_ODY_PCCPF_XXX_ARI_CAP_HDR CSR_TYPE_PCCPF
682 #define basename_ODY_PCCPF_XXX_ARI_CAP_HDR "PCCPF_XXX_ARI_CAP_HDR"
683 #define busnum_ODY_PCCPF_XXX_ARI_CAP_HDR 0
684 #define arguments_ODY_PCCPF_XXX_ARI_CAP_HDR -1, -1, -1, -1
685
686 /**
687 * Register (PCCPF) pccpf_xxx_bar0l
688 *
689 * PCC PF Base Address 0 Lower Register
690 */
691 union ody_pccpf_xxx_bar0l {
692 uint32_t u;
693 struct ody_pccpf_xxx_bar0l_s {
694 uint32_t bar : 32;
695 } s;
696 /* struct ody_pccpf_xxx_bar0l_s cn; */
697 };
698 typedef union ody_pccpf_xxx_bar0l ody_pccpf_xxx_bar0l_t;
699
700 #define ODY_PCCPF_XXX_BAR0L ODY_PCCPF_XXX_BAR0L_FUNC()
701 static inline uint64_t ODY_PCCPF_XXX_BAR0L_FUNC(void) __attribute__ ((pure, always_inline));
ODY_PCCPF_XXX_BAR0L_FUNC(void)702 static inline uint64_t ODY_PCCPF_XXX_BAR0L_FUNC(void)
703 {
704 return 0x10;
705 }
706
707 #define typedef_ODY_PCCPF_XXX_BAR0L ody_pccpf_xxx_bar0l_t
708 #define bustype_ODY_PCCPF_XXX_BAR0L CSR_TYPE_PCCPF
709 #define basename_ODY_PCCPF_XXX_BAR0L "PCCPF_XXX_BAR0L"
710 #define busnum_ODY_PCCPF_XXX_BAR0L 0
711 #define arguments_ODY_PCCPF_XXX_BAR0L -1, -1, -1, -1
712
713 /**
714 * Register (PCCPF) pccpf_xxx_bar0u
715 *
716 * PCC PF Base Address 0 Upper Register
717 */
718 union ody_pccpf_xxx_bar0u {
719 uint32_t u;
720 struct ody_pccpf_xxx_bar0u_s {
721 uint32_t bar : 32;
722 } s;
723 /* struct ody_pccpf_xxx_bar0u_s cn; */
724 };
725 typedef union ody_pccpf_xxx_bar0u ody_pccpf_xxx_bar0u_t;
726
727 #define ODY_PCCPF_XXX_BAR0U ODY_PCCPF_XXX_BAR0U_FUNC()
728 static inline uint64_t ODY_PCCPF_XXX_BAR0U_FUNC(void) __attribute__ ((pure, always_inline));
ODY_PCCPF_XXX_BAR0U_FUNC(void)729 static inline uint64_t ODY_PCCPF_XXX_BAR0U_FUNC(void)
730 {
731 return 0x14;
732 }
733
734 #define typedef_ODY_PCCPF_XXX_BAR0U ody_pccpf_xxx_bar0u_t
735 #define bustype_ODY_PCCPF_XXX_BAR0U CSR_TYPE_PCCPF
736 #define basename_ODY_PCCPF_XXX_BAR0U "PCCPF_XXX_BAR0U"
737 #define busnum_ODY_PCCPF_XXX_BAR0U 0
738 #define arguments_ODY_PCCPF_XXX_BAR0U -1, -1, -1, -1
739
740 /**
741 * Register (PCCPF) pccpf_xxx_bar2l
742 *
743 * PCC PF Base Address 2 Lower Register
744 */
745 union ody_pccpf_xxx_bar2l {
746 uint32_t u;
747 struct ody_pccpf_xxx_bar2l_s {
748 uint32_t bar : 32;
749 } s;
750 /* struct ody_pccpf_xxx_bar2l_s cn; */
751 };
752 typedef union ody_pccpf_xxx_bar2l ody_pccpf_xxx_bar2l_t;
753
754 #define ODY_PCCPF_XXX_BAR2L ODY_PCCPF_XXX_BAR2L_FUNC()
755 static inline uint64_t ODY_PCCPF_XXX_BAR2L_FUNC(void) __attribute__ ((pure, always_inline));
ODY_PCCPF_XXX_BAR2L_FUNC(void)756 static inline uint64_t ODY_PCCPF_XXX_BAR2L_FUNC(void)
757 {
758 return 0x18;
759 }
760
761 #define typedef_ODY_PCCPF_XXX_BAR2L ody_pccpf_xxx_bar2l_t
762 #define bustype_ODY_PCCPF_XXX_BAR2L CSR_TYPE_PCCPF
763 #define basename_ODY_PCCPF_XXX_BAR2L "PCCPF_XXX_BAR2L"
764 #define busnum_ODY_PCCPF_XXX_BAR2L 0
765 #define arguments_ODY_PCCPF_XXX_BAR2L -1, -1, -1, -1
766
767 /**
768 * Register (PCCPF) pccpf_xxx_bar2u
769 *
770 * PCC PF Base Address 2 Upper Register
771 */
772 union ody_pccpf_xxx_bar2u {
773 uint32_t u;
774 struct ody_pccpf_xxx_bar2u_s {
775 uint32_t bar : 32;
776 } s;
777 /* struct ody_pccpf_xxx_bar2u_s cn; */
778 };
779 typedef union ody_pccpf_xxx_bar2u ody_pccpf_xxx_bar2u_t;
780
781 #define ODY_PCCPF_XXX_BAR2U ODY_PCCPF_XXX_BAR2U_FUNC()
782 static inline uint64_t ODY_PCCPF_XXX_BAR2U_FUNC(void) __attribute__ ((pure, always_inline));
ODY_PCCPF_XXX_BAR2U_FUNC(void)783 static inline uint64_t ODY_PCCPF_XXX_BAR2U_FUNC(void)
784 {
785 return 0x1c;
786 }
787
788 #define typedef_ODY_PCCPF_XXX_BAR2U ody_pccpf_xxx_bar2u_t
789 #define bustype_ODY_PCCPF_XXX_BAR2U CSR_TYPE_PCCPF
790 #define basename_ODY_PCCPF_XXX_BAR2U "PCCPF_XXX_BAR2U"
791 #define busnum_ODY_PCCPF_XXX_BAR2U 0
792 #define arguments_ODY_PCCPF_XXX_BAR2U -1, -1, -1, -1
793
794 /**
795 * Register (PCCPF) pccpf_xxx_bar4l
796 *
797 * PCC PF Base Address 4 Lower Register
798 */
799 union ody_pccpf_xxx_bar4l {
800 uint32_t u;
801 struct ody_pccpf_xxx_bar4l_s {
802 uint32_t bar : 32;
803 } s;
804 /* struct ody_pccpf_xxx_bar4l_s cn; */
805 };
806 typedef union ody_pccpf_xxx_bar4l ody_pccpf_xxx_bar4l_t;
807
808 #define ODY_PCCPF_XXX_BAR4L ODY_PCCPF_XXX_BAR4L_FUNC()
809 static inline uint64_t ODY_PCCPF_XXX_BAR4L_FUNC(void) __attribute__ ((pure, always_inline));
ODY_PCCPF_XXX_BAR4L_FUNC(void)810 static inline uint64_t ODY_PCCPF_XXX_BAR4L_FUNC(void)
811 {
812 return 0x20;
813 }
814
815 #define typedef_ODY_PCCPF_XXX_BAR4L ody_pccpf_xxx_bar4l_t
816 #define bustype_ODY_PCCPF_XXX_BAR4L CSR_TYPE_PCCPF
817 #define basename_ODY_PCCPF_XXX_BAR4L "PCCPF_XXX_BAR4L"
818 #define busnum_ODY_PCCPF_XXX_BAR4L 0
819 #define arguments_ODY_PCCPF_XXX_BAR4L -1, -1, -1, -1
820
821 /**
822 * Register (PCCPF) pccpf_xxx_bar4u
823 *
824 * PCC PF Base Address 4 Upper Register
825 */
826 union ody_pccpf_xxx_bar4u {
827 uint32_t u;
828 struct ody_pccpf_xxx_bar4u_s {
829 uint32_t bar : 32;
830 } s;
831 /* struct ody_pccpf_xxx_bar4u_s cn; */
832 };
833 typedef union ody_pccpf_xxx_bar4u ody_pccpf_xxx_bar4u_t;
834
835 #define ODY_PCCPF_XXX_BAR4U ODY_PCCPF_XXX_BAR4U_FUNC()
836 static inline uint64_t ODY_PCCPF_XXX_BAR4U_FUNC(void) __attribute__ ((pure, always_inline));
ODY_PCCPF_XXX_BAR4U_FUNC(void)837 static inline uint64_t ODY_PCCPF_XXX_BAR4U_FUNC(void)
838 {
839 return 0x24;
840 }
841
842 #define typedef_ODY_PCCPF_XXX_BAR4U ody_pccpf_xxx_bar4u_t
843 #define bustype_ODY_PCCPF_XXX_BAR4U CSR_TYPE_PCCPF
844 #define basename_ODY_PCCPF_XXX_BAR4U "PCCPF_XXX_BAR4U"
845 #define busnum_ODY_PCCPF_XXX_BAR4U 0
846 #define arguments_ODY_PCCPF_XXX_BAR4U -1, -1, -1, -1
847
848 /**
849 * Register (PCCPF) pccpf_xxx_cap_ptr
850 *
851 * PCC PF Capability Pointer Register
852 */
853 union ody_pccpf_xxx_cap_ptr {
854 uint32_t u;
855 struct ody_pccpf_xxx_cap_ptr_s {
856 uint32_t cp : 8;
857 uint32_t reserved_8_31 : 24;
858 } s;
859 /* struct ody_pccpf_xxx_cap_ptr_s cn; */
860 };
861 typedef union ody_pccpf_xxx_cap_ptr ody_pccpf_xxx_cap_ptr_t;
862
863 #define ODY_PCCPF_XXX_CAP_PTR ODY_PCCPF_XXX_CAP_PTR_FUNC()
864 static inline uint64_t ODY_PCCPF_XXX_CAP_PTR_FUNC(void) __attribute__ ((pure, always_inline));
ODY_PCCPF_XXX_CAP_PTR_FUNC(void)865 static inline uint64_t ODY_PCCPF_XXX_CAP_PTR_FUNC(void)
866 {
867 return 0x34;
868 }
869
870 #define typedef_ODY_PCCPF_XXX_CAP_PTR ody_pccpf_xxx_cap_ptr_t
871 #define bustype_ODY_PCCPF_XXX_CAP_PTR CSR_TYPE_PCCPF
872 #define basename_ODY_PCCPF_XXX_CAP_PTR "PCCPF_XXX_CAP_PTR"
873 #define busnum_ODY_PCCPF_XXX_CAP_PTR 0
874 #define arguments_ODY_PCCPF_XXX_CAP_PTR -1, -1, -1, -1
875
876 /**
877 * Register (PCCPF) pccpf_xxx_clsize
878 *
879 * PCC PF Cache Line Size Register
880 */
881 union ody_pccpf_xxx_clsize {
882 uint32_t u;
883 struct ody_pccpf_xxx_clsize_s {
884 uint32_t clsize : 8;
885 uint32_t lattim : 8;
886 uint32_t hdrtype : 8;
887 uint32_t bist : 8;
888 } s;
889 /* struct ody_pccpf_xxx_clsize_s cn; */
890 };
891 typedef union ody_pccpf_xxx_clsize ody_pccpf_xxx_clsize_t;
892
893 #define ODY_PCCPF_XXX_CLSIZE ODY_PCCPF_XXX_CLSIZE_FUNC()
894 static inline uint64_t ODY_PCCPF_XXX_CLSIZE_FUNC(void) __attribute__ ((pure, always_inline));
ODY_PCCPF_XXX_CLSIZE_FUNC(void)895 static inline uint64_t ODY_PCCPF_XXX_CLSIZE_FUNC(void)
896 {
897 return 0xc;
898 }
899
900 #define typedef_ODY_PCCPF_XXX_CLSIZE ody_pccpf_xxx_clsize_t
901 #define bustype_ODY_PCCPF_XXX_CLSIZE CSR_TYPE_PCCPF
902 #define basename_ODY_PCCPF_XXX_CLSIZE "PCCPF_XXX_CLSIZE"
903 #define busnum_ODY_PCCPF_XXX_CLSIZE 0
904 #define arguments_ODY_PCCPF_XXX_CLSIZE -1, -1, -1, -1
905
906 /**
907 * Register (PCCPF) pccpf_xxx_cmd
908 *
909 * PCC PF Command/Status Register
910 * This register is reset on a block domain reset or PF function level reset.
911 */
912 union ody_pccpf_xxx_cmd {
913 uint32_t u;
914 struct ody_pccpf_xxx_cmd_s {
915 uint32_t reserved_0 : 1;
916 uint32_t msae : 1;
917 uint32_t me : 1;
918 uint32_t reserved_3_19 : 17;
919 uint32_t cl : 1;
920 uint32_t reserved_21_31 : 11;
921 } s;
922 /* struct ody_pccpf_xxx_cmd_s cn; */
923 };
924 typedef union ody_pccpf_xxx_cmd ody_pccpf_xxx_cmd_t;
925
926 #define ODY_PCCPF_XXX_CMD ODY_PCCPF_XXX_CMD_FUNC()
927 static inline uint64_t ODY_PCCPF_XXX_CMD_FUNC(void) __attribute__ ((pure, always_inline));
ODY_PCCPF_XXX_CMD_FUNC(void)928 static inline uint64_t ODY_PCCPF_XXX_CMD_FUNC(void)
929 {
930 return 4;
931 }
932
933 #define typedef_ODY_PCCPF_XXX_CMD ody_pccpf_xxx_cmd_t
934 #define bustype_ODY_PCCPF_XXX_CMD CSR_TYPE_PCCPF
935 #define basename_ODY_PCCPF_XXX_CMD "PCCPF_XXX_CMD"
936 #define busnum_ODY_PCCPF_XXX_CMD 0
937 #define arguments_ODY_PCCPF_XXX_CMD -1, -1, -1, -1
938
939 /**
940 * Register (PCCPF) pccpf_xxx_e_cap_hdr
941 *
942 * PCC PF PCI Express Capabilities Register
943 * This register is the header of the 64-byte PCIe capability header.
944 */
945 union ody_pccpf_xxx_e_cap_hdr {
946 uint32_t u;
947 struct ody_pccpf_xxx_e_cap_hdr_s {
948 uint32_t pcieid : 8;
949 uint32_t ncp : 8;
950 uint32_t pciecv : 4;
951 uint32_t dpt : 4;
952 uint32_t reserved_24_31 : 8;
953 } s;
954 /* struct ody_pccpf_xxx_e_cap_hdr_s cn; */
955 };
956 typedef union ody_pccpf_xxx_e_cap_hdr ody_pccpf_xxx_e_cap_hdr_t;
957
958 #define ODY_PCCPF_XXX_E_CAP_HDR ODY_PCCPF_XXX_E_CAP_HDR_FUNC()
959 static inline uint64_t ODY_PCCPF_XXX_E_CAP_HDR_FUNC(void) __attribute__ ((pure, always_inline));
ODY_PCCPF_XXX_E_CAP_HDR_FUNC(void)960 static inline uint64_t ODY_PCCPF_XXX_E_CAP_HDR_FUNC(void)
961 {
962 return 0x40;
963 }
964
965 #define typedef_ODY_PCCPF_XXX_E_CAP_HDR ody_pccpf_xxx_e_cap_hdr_t
966 #define bustype_ODY_PCCPF_XXX_E_CAP_HDR CSR_TYPE_PCCPF
967 #define basename_ODY_PCCPF_XXX_E_CAP_HDR "PCCPF_XXX_E_CAP_HDR"
968 #define busnum_ODY_PCCPF_XXX_E_CAP_HDR 0
969 #define arguments_ODY_PCCPF_XXX_E_CAP_HDR -1, -1, -1, -1
970
971 /**
972 * Register (PCCPF) pccpf_xxx_e_dev_cap
973 *
974 * PCC PF PCI Express Device Capabilities Register
975 */
976 union ody_pccpf_xxx_e_dev_cap {
977 uint32_t u;
978 struct ody_pccpf_xxx_e_dev_cap_s {
979 uint32_t reserved_0_14 : 15;
980 uint32_t rber : 1;
981 uint32_t reserved_16_27 : 12;
982 uint32_t flr : 1;
983 uint32_t reserved_29_31 : 3;
984 } s;
985 /* struct ody_pccpf_xxx_e_dev_cap_s cn; */
986 };
987 typedef union ody_pccpf_xxx_e_dev_cap ody_pccpf_xxx_e_dev_cap_t;
988
989 #define ODY_PCCPF_XXX_E_DEV_CAP ODY_PCCPF_XXX_E_DEV_CAP_FUNC()
990 static inline uint64_t ODY_PCCPF_XXX_E_DEV_CAP_FUNC(void) __attribute__ ((pure, always_inline));
ODY_PCCPF_XXX_E_DEV_CAP_FUNC(void)991 static inline uint64_t ODY_PCCPF_XXX_E_DEV_CAP_FUNC(void)
992 {
993 return 0x44;
994 }
995
996 #define typedef_ODY_PCCPF_XXX_E_DEV_CAP ody_pccpf_xxx_e_dev_cap_t
997 #define bustype_ODY_PCCPF_XXX_E_DEV_CAP CSR_TYPE_PCCPF
998 #define basename_ODY_PCCPF_XXX_E_DEV_CAP "PCCPF_XXX_E_DEV_CAP"
999 #define busnum_ODY_PCCPF_XXX_E_DEV_CAP 0
1000 #define arguments_ODY_PCCPF_XXX_E_DEV_CAP -1, -1, -1, -1
1001
1002 /**
1003 * Register (PCCPF) pccpf_xxx_e_dev_ctl
1004 *
1005 * PCC PF PCI Express Device Control and Status Register
1006 * This register is reset on a block domain reset or PF function level reset.
1007 */
1008 union ody_pccpf_xxx_e_dev_ctl {
1009 uint32_t u;
1010 struct ody_pccpf_xxx_e_dev_ctl_s {
1011 uint32_t cere : 1;
1012 uint32_t nfere : 1;
1013 uint32_t fere : 1;
1014 uint32_t urre : 1;
1015 uint32_t reserved_4_14 : 11;
1016 uint32_t bcr_flr : 1;
1017 uint32_t ced : 1;
1018 uint32_t nfed : 1;
1019 uint32_t fed : 1;
1020 uint32_t urd : 1;
1021 uint32_t reserved_20 : 1;
1022 uint32_t trpend : 1;
1023 uint32_t reserved_22_31 : 10;
1024 } s;
1025 /* struct ody_pccpf_xxx_e_dev_ctl_s cn; */
1026 };
1027 typedef union ody_pccpf_xxx_e_dev_ctl ody_pccpf_xxx_e_dev_ctl_t;
1028
1029 #define ODY_PCCPF_XXX_E_DEV_CTL ODY_PCCPF_XXX_E_DEV_CTL_FUNC()
1030 static inline uint64_t ODY_PCCPF_XXX_E_DEV_CTL_FUNC(void) __attribute__ ((pure, always_inline));
ODY_PCCPF_XXX_E_DEV_CTL_FUNC(void)1031 static inline uint64_t ODY_PCCPF_XXX_E_DEV_CTL_FUNC(void)
1032 {
1033 return 0x48;
1034 }
1035
1036 #define typedef_ODY_PCCPF_XXX_E_DEV_CTL ody_pccpf_xxx_e_dev_ctl_t
1037 #define bustype_ODY_PCCPF_XXX_E_DEV_CTL CSR_TYPE_PCCPF
1038 #define basename_ODY_PCCPF_XXX_E_DEV_CTL "PCCPF_XXX_E_DEV_CTL"
1039 #define busnum_ODY_PCCPF_XXX_E_DEV_CTL 0
1040 #define arguments_ODY_PCCPF_XXX_E_DEV_CTL -1, -1, -1, -1
1041
1042 /**
1043 * Register (PCCPF) pccpf_xxx_ea_cap_hdr
1044 *
1045 * PCC PF PCI Enhanced Allocation Capabilities Register
1046 * This register is the header of the variable-sized PCI enhanced allocation capability
1047 * structure for type 0 devices.
1048 */
1049 union ody_pccpf_xxx_ea_cap_hdr {
1050 uint32_t u;
1051 struct ody_pccpf_xxx_ea_cap_hdr_s {
1052 uint32_t pcieid : 8;
1053 uint32_t ncp : 8;
1054 uint32_t num_entries : 6;
1055 uint32_t reserved_22_31 : 10;
1056 } s;
1057 /* struct ody_pccpf_xxx_ea_cap_hdr_s cn; */
1058 };
1059 typedef union ody_pccpf_xxx_ea_cap_hdr ody_pccpf_xxx_ea_cap_hdr_t;
1060
1061 #define ODY_PCCPF_XXX_EA_CAP_HDR ODY_PCCPF_XXX_EA_CAP_HDR_FUNC()
1062 static inline uint64_t ODY_PCCPF_XXX_EA_CAP_HDR_FUNC(void) __attribute__ ((pure, always_inline));
ODY_PCCPF_XXX_EA_CAP_HDR_FUNC(void)1063 static inline uint64_t ODY_PCCPF_XXX_EA_CAP_HDR_FUNC(void)
1064 {
1065 return 0x98;
1066 }
1067
1068 #define typedef_ODY_PCCPF_XXX_EA_CAP_HDR ody_pccpf_xxx_ea_cap_hdr_t
1069 #define bustype_ODY_PCCPF_XXX_EA_CAP_HDR CSR_TYPE_PCCPF
1070 #define basename_ODY_PCCPF_XXX_EA_CAP_HDR "PCCPF_XXX_EA_CAP_HDR"
1071 #define busnum_ODY_PCCPF_XXX_EA_CAP_HDR 0
1072 #define arguments_ODY_PCCPF_XXX_EA_CAP_HDR -1, -1, -1, -1
1073
1074 /**
1075 * Register (PCCPF) pccpf_xxx_ea_entry#
1076 *
1077 * PCC PF PCI Enhanced Allocation Entry Registers
1078 * These registers contain up to four sequential enhanced allocation entries. Each
1079 * entry consists of five sequential 32-bit words described by PCC_EA_ENTRY_S.
1080 */
1081 union ody_pccpf_xxx_ea_entryx {
1082 uint32_t u;
1083 struct ody_pccpf_xxx_ea_entryx_s {
1084 uint32_t data : 32;
1085 } s;
1086 /* struct ody_pccpf_xxx_ea_entryx_s cn; */
1087 };
1088 typedef union ody_pccpf_xxx_ea_entryx ody_pccpf_xxx_ea_entryx_t;
1089
1090 static inline uint64_t ODY_PCCPF_XXX_EA_ENTRYX(uint64_t a) __attribute__ ((pure, always_inline));
ODY_PCCPF_XXX_EA_ENTRYX(uint64_t a)1091 static inline uint64_t ODY_PCCPF_XXX_EA_ENTRYX(uint64_t a)
1092 {
1093 if (a <= 24)
1094 return 0x9c + 4 * ((a) & 0x1f);
1095 __ody_csr_fatal("PCCPF_XXX_EA_ENTRYX", 1, a, 0, 0, 0, 0, 0);
1096 }
1097
1098 #define typedef_ODY_PCCPF_XXX_EA_ENTRYX(a) ody_pccpf_xxx_ea_entryx_t
1099 #define bustype_ODY_PCCPF_XXX_EA_ENTRYX(a) CSR_TYPE_PCCPF
1100 #define basename_ODY_PCCPF_XXX_EA_ENTRYX(a) "PCCPF_XXX_EA_ENTRYX"
1101 #define busnum_ODY_PCCPF_XXX_EA_ENTRYX(a) (a)
1102 #define arguments_ODY_PCCPF_XXX_EA_ENTRYX(a) (a), -1, -1, -1
1103
1104 /**
1105 * Register (PCCPF) pccpf_xxx_id
1106 *
1107 * PCC PF Vendor and Device ID Register
1108 * This register is the header of the 64-byte PCI type 0 configuration structure.
1109 */
1110 union ody_pccpf_xxx_id {
1111 uint32_t u;
1112 struct ody_pccpf_xxx_id_s {
1113 uint32_t vendid : 16;
1114 uint32_t devid : 16;
1115 } s;
1116 /* struct ody_pccpf_xxx_id_s cn; */
1117 };
1118 typedef union ody_pccpf_xxx_id ody_pccpf_xxx_id_t;
1119
1120 #define ODY_PCCPF_XXX_ID ODY_PCCPF_XXX_ID_FUNC()
1121 static inline uint64_t ODY_PCCPF_XXX_ID_FUNC(void) __attribute__ ((pure, always_inline));
ODY_PCCPF_XXX_ID_FUNC(void)1122 static inline uint64_t ODY_PCCPF_XXX_ID_FUNC(void)
1123 {
1124 return 0;
1125 }
1126
1127 #define typedef_ODY_PCCPF_XXX_ID ody_pccpf_xxx_id_t
1128 #define bustype_ODY_PCCPF_XXX_ID CSR_TYPE_PCCPF
1129 #define basename_ODY_PCCPF_XXX_ID "PCCPF_XXX_ID"
1130 #define busnum_ODY_PCCPF_XXX_ID 0
1131 #define arguments_ODY_PCCPF_XXX_ID -1, -1, -1, -1
1132
1133 /**
1134 * Register (PCCPF) pccpf_xxx_msix_cap_hdr
1135 *
1136 * PCC PF MSI-X Capability Header Register
1137 * This register is the header of the 36-byte PCI MSI-X capability structure.
1138 *
1139 * This register is reset on a block domain reset or PF function level reset.
1140 */
1141 union ody_pccpf_xxx_msix_cap_hdr {
1142 uint32_t u;
1143 struct ody_pccpf_xxx_msix_cap_hdr_s {
1144 uint32_t msixcid : 8;
1145 uint32_t ncp : 8;
1146 uint32_t msixts : 11;
1147 uint32_t reserved_27_29 : 3;
1148 uint32_t funm : 1;
1149 uint32_t msixen : 1;
1150 } s;
1151 /* struct ody_pccpf_xxx_msix_cap_hdr_s cn; */
1152 };
1153 typedef union ody_pccpf_xxx_msix_cap_hdr ody_pccpf_xxx_msix_cap_hdr_t;
1154
1155 #define ODY_PCCPF_XXX_MSIX_CAP_HDR ODY_PCCPF_XXX_MSIX_CAP_HDR_FUNC()
1156 static inline uint64_t ODY_PCCPF_XXX_MSIX_CAP_HDR_FUNC(void) __attribute__ ((pure, always_inline));
ODY_PCCPF_XXX_MSIX_CAP_HDR_FUNC(void)1157 static inline uint64_t ODY_PCCPF_XXX_MSIX_CAP_HDR_FUNC(void)
1158 {
1159 return 0x80;
1160 }
1161
1162 #define typedef_ODY_PCCPF_XXX_MSIX_CAP_HDR ody_pccpf_xxx_msix_cap_hdr_t
1163 #define bustype_ODY_PCCPF_XXX_MSIX_CAP_HDR CSR_TYPE_PCCPF
1164 #define basename_ODY_PCCPF_XXX_MSIX_CAP_HDR "PCCPF_XXX_MSIX_CAP_HDR"
1165 #define busnum_ODY_PCCPF_XXX_MSIX_CAP_HDR 0
1166 #define arguments_ODY_PCCPF_XXX_MSIX_CAP_HDR -1, -1, -1, -1
1167
1168 /**
1169 * Register (PCCPF) pccpf_xxx_msix_pba
1170 *
1171 * PCC PF MSI-X PBA Offset and BIR Register
1172 */
1173 union ody_pccpf_xxx_msix_pba {
1174 uint32_t u;
1175 struct ody_pccpf_xxx_msix_pba_s {
1176 uint32_t msixpbir : 3;
1177 uint32_t msixpoffs : 29;
1178 } s;
1179 /* struct ody_pccpf_xxx_msix_pba_s cn; */
1180 };
1181 typedef union ody_pccpf_xxx_msix_pba ody_pccpf_xxx_msix_pba_t;
1182
1183 #define ODY_PCCPF_XXX_MSIX_PBA ODY_PCCPF_XXX_MSIX_PBA_FUNC()
1184 static inline uint64_t ODY_PCCPF_XXX_MSIX_PBA_FUNC(void) __attribute__ ((pure, always_inline));
ODY_PCCPF_XXX_MSIX_PBA_FUNC(void)1185 static inline uint64_t ODY_PCCPF_XXX_MSIX_PBA_FUNC(void)
1186 {
1187 return 0x88;
1188 }
1189
1190 #define typedef_ODY_PCCPF_XXX_MSIX_PBA ody_pccpf_xxx_msix_pba_t
1191 #define bustype_ODY_PCCPF_XXX_MSIX_PBA CSR_TYPE_PCCPF
1192 #define basename_ODY_PCCPF_XXX_MSIX_PBA "PCCPF_XXX_MSIX_PBA"
1193 #define busnum_ODY_PCCPF_XXX_MSIX_PBA 0
1194 #define arguments_ODY_PCCPF_XXX_MSIX_PBA -1, -1, -1, -1
1195
1196 /**
1197 * Register (PCCPF) pccpf_xxx_msix_table
1198 *
1199 * PCC PF MSI-X Table Offset and BIR Register
1200 */
1201 union ody_pccpf_xxx_msix_table {
1202 uint32_t u;
1203 struct ody_pccpf_xxx_msix_table_s {
1204 uint32_t msixtbir : 3;
1205 uint32_t msixtoffs : 29;
1206 } s;
1207 /* struct ody_pccpf_xxx_msix_table_s cn; */
1208 };
1209 typedef union ody_pccpf_xxx_msix_table ody_pccpf_xxx_msix_table_t;
1210
1211 #define ODY_PCCPF_XXX_MSIX_TABLE ODY_PCCPF_XXX_MSIX_TABLE_FUNC()
1212 static inline uint64_t ODY_PCCPF_XXX_MSIX_TABLE_FUNC(void) __attribute__ ((pure, always_inline));
ODY_PCCPF_XXX_MSIX_TABLE_FUNC(void)1213 static inline uint64_t ODY_PCCPF_XXX_MSIX_TABLE_FUNC(void)
1214 {
1215 return 0x84;
1216 }
1217
1218 #define typedef_ODY_PCCPF_XXX_MSIX_TABLE ody_pccpf_xxx_msix_table_t
1219 #define bustype_ODY_PCCPF_XXX_MSIX_TABLE CSR_TYPE_PCCPF
1220 #define basename_ODY_PCCPF_XXX_MSIX_TABLE "PCCPF_XXX_MSIX_TABLE"
1221 #define busnum_ODY_PCCPF_XXX_MSIX_TABLE 0
1222 #define arguments_ODY_PCCPF_XXX_MSIX_TABLE -1, -1, -1, -1
1223
1224 /**
1225 * Register (PCCPF) pccpf_xxx_rev
1226 *
1227 * PCC PF Class Code/Revision ID Register
1228 */
1229 union ody_pccpf_xxx_rev {
1230 uint32_t u;
1231 struct ody_pccpf_xxx_rev_s {
1232 uint32_t rid : 8;
1233 uint32_t pi : 8;
1234 uint32_t sc : 8;
1235 uint32_t bcc : 8;
1236 } s;
1237 /* struct ody_pccpf_xxx_rev_s cn; */
1238 };
1239 typedef union ody_pccpf_xxx_rev ody_pccpf_xxx_rev_t;
1240
1241 #define ODY_PCCPF_XXX_REV ODY_PCCPF_XXX_REV_FUNC()
1242 static inline uint64_t ODY_PCCPF_XXX_REV_FUNC(void) __attribute__ ((pure, always_inline));
ODY_PCCPF_XXX_REV_FUNC(void)1243 static inline uint64_t ODY_PCCPF_XXX_REV_FUNC(void)
1244 {
1245 return 8;
1246 }
1247
1248 #define typedef_ODY_PCCPF_XXX_REV ody_pccpf_xxx_rev_t
1249 #define bustype_ODY_PCCPF_XXX_REV CSR_TYPE_PCCPF
1250 #define basename_ODY_PCCPF_XXX_REV "PCCPF_XXX_REV"
1251 #define busnum_ODY_PCCPF_XXX_REV 0
1252 #define arguments_ODY_PCCPF_XXX_REV -1, -1, -1, -1
1253
1254 /**
1255 * Register (PCCPF) pccpf_xxx_sari_nxt
1256 *
1257 * PCC PF ARI Capability Register
1258 * If this device is on bus 0x0, this ARI header is not present and reads as 0x0.
1259 */
1260 union ody_pccpf_xxx_sari_nxt {
1261 uint32_t u;
1262 struct ody_pccpf_xxx_sari_nxt_s {
1263 uint32_t reserved_0_7 : 8;
1264 uint32_t nxtfn : 8;
1265 uint32_t reserved_16_31 : 16;
1266 } s;
1267 /* struct ody_pccpf_xxx_sari_nxt_s cn; */
1268 };
1269 typedef union ody_pccpf_xxx_sari_nxt ody_pccpf_xxx_sari_nxt_t;
1270
1271 #define ODY_PCCPF_XXX_SARI_NXT ODY_PCCPF_XXX_SARI_NXT_FUNC()
1272 static inline uint64_t ODY_PCCPF_XXX_SARI_NXT_FUNC(void) __attribute__ ((pure, always_inline));
ODY_PCCPF_XXX_SARI_NXT_FUNC(void)1273 static inline uint64_t ODY_PCCPF_XXX_SARI_NXT_FUNC(void)
1274 {
1275 return 0x174;
1276 }
1277
1278 #define typedef_ODY_PCCPF_XXX_SARI_NXT ody_pccpf_xxx_sari_nxt_t
1279 #define bustype_ODY_PCCPF_XXX_SARI_NXT CSR_TYPE_PCCPF
1280 #define basename_ODY_PCCPF_XXX_SARI_NXT "PCCPF_XXX_SARI_NXT"
1281 #define busnum_ODY_PCCPF_XXX_SARI_NXT 0
1282 #define arguments_ODY_PCCPF_XXX_SARI_NXT -1, -1, -1, -1
1283
1284 /**
1285 * Register (PCCPF) pccpf_xxx_sriov_bar0l
1286 *
1287 * PCC PF SR-IOV BAR 0 Lower Register
1288 */
1289 union ody_pccpf_xxx_sriov_bar0l {
1290 uint32_t u;
1291 struct ody_pccpf_xxx_sriov_bar0l_s {
1292 uint32_t bar : 32;
1293 } s;
1294 /* struct ody_pccpf_xxx_sriov_bar0l_s cn; */
1295 };
1296 typedef union ody_pccpf_xxx_sriov_bar0l ody_pccpf_xxx_sriov_bar0l_t;
1297
1298 #define ODY_PCCPF_XXX_SRIOV_BAR0L ODY_PCCPF_XXX_SRIOV_BAR0L_FUNC()
1299 static inline uint64_t ODY_PCCPF_XXX_SRIOV_BAR0L_FUNC(void) __attribute__ ((pure, always_inline));
ODY_PCCPF_XXX_SRIOV_BAR0L_FUNC(void)1300 static inline uint64_t ODY_PCCPF_XXX_SRIOV_BAR0L_FUNC(void)
1301 {
1302 return 0x1a4;
1303 }
1304
1305 #define typedef_ODY_PCCPF_XXX_SRIOV_BAR0L ody_pccpf_xxx_sriov_bar0l_t
1306 #define bustype_ODY_PCCPF_XXX_SRIOV_BAR0L CSR_TYPE_PCCPF
1307 #define basename_ODY_PCCPF_XXX_SRIOV_BAR0L "PCCPF_XXX_SRIOV_BAR0L"
1308 #define busnum_ODY_PCCPF_XXX_SRIOV_BAR0L 0
1309 #define arguments_ODY_PCCPF_XXX_SRIOV_BAR0L -1, -1, -1, -1
1310
1311 /**
1312 * Register (PCCPF) pccpf_xxx_sriov_bar0u
1313 *
1314 * PCC PF SR-IOV BAR 0 Upper Register
1315 */
1316 union ody_pccpf_xxx_sriov_bar0u {
1317 uint32_t u;
1318 struct ody_pccpf_xxx_sriov_bar0u_s {
1319 uint32_t bar : 32;
1320 } s;
1321 /* struct ody_pccpf_xxx_sriov_bar0u_s cn; */
1322 };
1323 typedef union ody_pccpf_xxx_sriov_bar0u ody_pccpf_xxx_sriov_bar0u_t;
1324
1325 #define ODY_PCCPF_XXX_SRIOV_BAR0U ODY_PCCPF_XXX_SRIOV_BAR0U_FUNC()
1326 static inline uint64_t ODY_PCCPF_XXX_SRIOV_BAR0U_FUNC(void) __attribute__ ((pure, always_inline));
ODY_PCCPF_XXX_SRIOV_BAR0U_FUNC(void)1327 static inline uint64_t ODY_PCCPF_XXX_SRIOV_BAR0U_FUNC(void)
1328 {
1329 return 0x1a8;
1330 }
1331
1332 #define typedef_ODY_PCCPF_XXX_SRIOV_BAR0U ody_pccpf_xxx_sriov_bar0u_t
1333 #define bustype_ODY_PCCPF_XXX_SRIOV_BAR0U CSR_TYPE_PCCPF
1334 #define basename_ODY_PCCPF_XXX_SRIOV_BAR0U "PCCPF_XXX_SRIOV_BAR0U"
1335 #define busnum_ODY_PCCPF_XXX_SRIOV_BAR0U 0
1336 #define arguments_ODY_PCCPF_XXX_SRIOV_BAR0U -1, -1, -1, -1
1337
1338 /**
1339 * Register (PCCPF) pccpf_xxx_sriov_bar2l
1340 *
1341 * PCC PF SR-IOV BAR 2 Lower Register
1342 */
1343 union ody_pccpf_xxx_sriov_bar2l {
1344 uint32_t u;
1345 struct ody_pccpf_xxx_sriov_bar2l_s {
1346 uint32_t bar : 32;
1347 } s;
1348 /* struct ody_pccpf_xxx_sriov_bar2l_s cn; */
1349 };
1350 typedef union ody_pccpf_xxx_sriov_bar2l ody_pccpf_xxx_sriov_bar2l_t;
1351
1352 #define ODY_PCCPF_XXX_SRIOV_BAR2L ODY_PCCPF_XXX_SRIOV_BAR2L_FUNC()
1353 static inline uint64_t ODY_PCCPF_XXX_SRIOV_BAR2L_FUNC(void) __attribute__ ((pure, always_inline));
ODY_PCCPF_XXX_SRIOV_BAR2L_FUNC(void)1354 static inline uint64_t ODY_PCCPF_XXX_SRIOV_BAR2L_FUNC(void)
1355 {
1356 return 0x1ac;
1357 }
1358
1359 #define typedef_ODY_PCCPF_XXX_SRIOV_BAR2L ody_pccpf_xxx_sriov_bar2l_t
1360 #define bustype_ODY_PCCPF_XXX_SRIOV_BAR2L CSR_TYPE_PCCPF
1361 #define basename_ODY_PCCPF_XXX_SRIOV_BAR2L "PCCPF_XXX_SRIOV_BAR2L"
1362 #define busnum_ODY_PCCPF_XXX_SRIOV_BAR2L 0
1363 #define arguments_ODY_PCCPF_XXX_SRIOV_BAR2L -1, -1, -1, -1
1364
1365 /**
1366 * Register (PCCPF) pccpf_xxx_sriov_bar2u
1367 *
1368 * PCC PF SR-IOV BAR 2 Upper Register
1369 */
1370 union ody_pccpf_xxx_sriov_bar2u {
1371 uint32_t u;
1372 struct ody_pccpf_xxx_sriov_bar2u_s {
1373 uint32_t bar : 32;
1374 } s;
1375 /* struct ody_pccpf_xxx_sriov_bar2u_s cn; */
1376 };
1377 typedef union ody_pccpf_xxx_sriov_bar2u ody_pccpf_xxx_sriov_bar2u_t;
1378
1379 #define ODY_PCCPF_XXX_SRIOV_BAR2U ODY_PCCPF_XXX_SRIOV_BAR2U_FUNC()
1380 static inline uint64_t ODY_PCCPF_XXX_SRIOV_BAR2U_FUNC(void) __attribute__ ((pure, always_inline));
ODY_PCCPF_XXX_SRIOV_BAR2U_FUNC(void)1381 static inline uint64_t ODY_PCCPF_XXX_SRIOV_BAR2U_FUNC(void)
1382 {
1383 return 0x1b0;
1384 }
1385
1386 #define typedef_ODY_PCCPF_XXX_SRIOV_BAR2U ody_pccpf_xxx_sriov_bar2u_t
1387 #define bustype_ODY_PCCPF_XXX_SRIOV_BAR2U CSR_TYPE_PCCPF
1388 #define basename_ODY_PCCPF_XXX_SRIOV_BAR2U "PCCPF_XXX_SRIOV_BAR2U"
1389 #define busnum_ODY_PCCPF_XXX_SRIOV_BAR2U 0
1390 #define arguments_ODY_PCCPF_XXX_SRIOV_BAR2U -1, -1, -1, -1
1391
1392 /**
1393 * Register (PCCPF) pccpf_xxx_sriov_bar4l
1394 *
1395 * PCC PF SR-IOV BAR 4 Lower Register
1396 */
1397 union ody_pccpf_xxx_sriov_bar4l {
1398 uint32_t u;
1399 struct ody_pccpf_xxx_sriov_bar4l_s {
1400 uint32_t bar : 32;
1401 } s;
1402 /* struct ody_pccpf_xxx_sriov_bar4l_s cn; */
1403 };
1404 typedef union ody_pccpf_xxx_sriov_bar4l ody_pccpf_xxx_sriov_bar4l_t;
1405
1406 #define ODY_PCCPF_XXX_SRIOV_BAR4L ODY_PCCPF_XXX_SRIOV_BAR4L_FUNC()
1407 static inline uint64_t ODY_PCCPF_XXX_SRIOV_BAR4L_FUNC(void) __attribute__ ((pure, always_inline));
ODY_PCCPF_XXX_SRIOV_BAR4L_FUNC(void)1408 static inline uint64_t ODY_PCCPF_XXX_SRIOV_BAR4L_FUNC(void)
1409 {
1410 return 0x1b4;
1411 }
1412
1413 #define typedef_ODY_PCCPF_XXX_SRIOV_BAR4L ody_pccpf_xxx_sriov_bar4l_t
1414 #define bustype_ODY_PCCPF_XXX_SRIOV_BAR4L CSR_TYPE_PCCPF
1415 #define basename_ODY_PCCPF_XXX_SRIOV_BAR4L "PCCPF_XXX_SRIOV_BAR4L"
1416 #define busnum_ODY_PCCPF_XXX_SRIOV_BAR4L 0
1417 #define arguments_ODY_PCCPF_XXX_SRIOV_BAR4L -1, -1, -1, -1
1418
1419 /**
1420 * Register (PCCPF) pccpf_xxx_sriov_bar4u
1421 *
1422 * PCC PF SR-IOV BAR 4 Upper Register
1423 */
1424 union ody_pccpf_xxx_sriov_bar4u {
1425 uint32_t u;
1426 struct ody_pccpf_xxx_sriov_bar4u_s {
1427 uint32_t bar : 32;
1428 } s;
1429 /* struct ody_pccpf_xxx_sriov_bar4u_s cn; */
1430 };
1431 typedef union ody_pccpf_xxx_sriov_bar4u ody_pccpf_xxx_sriov_bar4u_t;
1432
1433 #define ODY_PCCPF_XXX_SRIOV_BAR4U ODY_PCCPF_XXX_SRIOV_BAR4U_FUNC()
1434 static inline uint64_t ODY_PCCPF_XXX_SRIOV_BAR4U_FUNC(void) __attribute__ ((pure, always_inline));
ODY_PCCPF_XXX_SRIOV_BAR4U_FUNC(void)1435 static inline uint64_t ODY_PCCPF_XXX_SRIOV_BAR4U_FUNC(void)
1436 {
1437 return 0x1b8;
1438 }
1439
1440 #define typedef_ODY_PCCPF_XXX_SRIOV_BAR4U ody_pccpf_xxx_sriov_bar4u_t
1441 #define bustype_ODY_PCCPF_XXX_SRIOV_BAR4U CSR_TYPE_PCCPF
1442 #define basename_ODY_PCCPF_XXX_SRIOV_BAR4U "PCCPF_XXX_SRIOV_BAR4U"
1443 #define busnum_ODY_PCCPF_XXX_SRIOV_BAR4U 0
1444 #define arguments_ODY_PCCPF_XXX_SRIOV_BAR4U -1, -1, -1, -1
1445
1446 /**
1447 * Register (PCCPF) pccpf_xxx_sriov_cap
1448 *
1449 * PCC PF SR-IOV Capability Register
1450 */
1451 union ody_pccpf_xxx_sriov_cap {
1452 uint32_t u;
1453 struct ody_pccpf_xxx_sriov_cap_s {
1454 uint32_t vfmc : 1;
1455 uint32_t arichp : 1;
1456 uint32_t reserved_2_20 : 19;
1457 uint32_t vfmimn : 11;
1458 } s;
1459 /* struct ody_pccpf_xxx_sriov_cap_s cn; */
1460 };
1461 typedef union ody_pccpf_xxx_sriov_cap ody_pccpf_xxx_sriov_cap_t;
1462
1463 #define ODY_PCCPF_XXX_SRIOV_CAP ODY_PCCPF_XXX_SRIOV_CAP_FUNC()
1464 static inline uint64_t ODY_PCCPF_XXX_SRIOV_CAP_FUNC(void) __attribute__ ((pure, always_inline));
ODY_PCCPF_XXX_SRIOV_CAP_FUNC(void)1465 static inline uint64_t ODY_PCCPF_XXX_SRIOV_CAP_FUNC(void)
1466 {
1467 return 0x184;
1468 }
1469
1470 #define typedef_ODY_PCCPF_XXX_SRIOV_CAP ody_pccpf_xxx_sriov_cap_t
1471 #define bustype_ODY_PCCPF_XXX_SRIOV_CAP CSR_TYPE_PCCPF
1472 #define basename_ODY_PCCPF_XXX_SRIOV_CAP "PCCPF_XXX_SRIOV_CAP"
1473 #define busnum_ODY_PCCPF_XXX_SRIOV_CAP 0
1474 #define arguments_ODY_PCCPF_XXX_SRIOV_CAP -1, -1, -1, -1
1475
1476 /**
1477 * Register (PCCPF) pccpf_xxx_sriov_cap_hdr
1478 *
1479 * PCC PF SR-IOV Capability Header Register
1480 * This register is the header of the 64-byte PCI SR-IOV capability structure.
1481 */
1482 union ody_pccpf_xxx_sriov_cap_hdr {
1483 uint32_t u;
1484 struct ody_pccpf_xxx_sriov_cap_hdr_s {
1485 uint32_t pcieec : 16;
1486 uint32_t cv : 4;
1487 uint32_t nco : 12;
1488 } s;
1489 /* struct ody_pccpf_xxx_sriov_cap_hdr_s cn; */
1490 };
1491 typedef union ody_pccpf_xxx_sriov_cap_hdr ody_pccpf_xxx_sriov_cap_hdr_t;
1492
1493 #define ODY_PCCPF_XXX_SRIOV_CAP_HDR ODY_PCCPF_XXX_SRIOV_CAP_HDR_FUNC()
1494 static inline uint64_t ODY_PCCPF_XXX_SRIOV_CAP_HDR_FUNC(void) __attribute__ ((pure, always_inline));
ODY_PCCPF_XXX_SRIOV_CAP_HDR_FUNC(void)1495 static inline uint64_t ODY_PCCPF_XXX_SRIOV_CAP_HDR_FUNC(void)
1496 {
1497 return 0x180;
1498 }
1499
1500 #define typedef_ODY_PCCPF_XXX_SRIOV_CAP_HDR ody_pccpf_xxx_sriov_cap_hdr_t
1501 #define bustype_ODY_PCCPF_XXX_SRIOV_CAP_HDR CSR_TYPE_PCCPF
1502 #define basename_ODY_PCCPF_XXX_SRIOV_CAP_HDR "PCCPF_XXX_SRIOV_CAP_HDR"
1503 #define busnum_ODY_PCCPF_XXX_SRIOV_CAP_HDR 0
1504 #define arguments_ODY_PCCPF_XXX_SRIOV_CAP_HDR -1, -1, -1, -1
1505
1506 /**
1507 * Register (PCCPF) pccpf_xxx_sriov_ctl
1508 *
1509 * PCC PF SR-IOV Control/Status Register
1510 * This register is reset on a chip domain reset.
1511 */
1512 union ody_pccpf_xxx_sriov_ctl {
1513 uint32_t u;
1514 struct ody_pccpf_xxx_sriov_ctl_s {
1515 uint32_t vfe : 1;
1516 uint32_t me : 1;
1517 uint32_t mie : 1;
1518 uint32_t mse : 1;
1519 uint32_t ach : 1;
1520 uint32_t reserved_5_15 : 11;
1521 uint32_t ms : 1;
1522 uint32_t reserved_17_31 : 15;
1523 } s;
1524 /* struct ody_pccpf_xxx_sriov_ctl_s cn; */
1525 };
1526 typedef union ody_pccpf_xxx_sriov_ctl ody_pccpf_xxx_sriov_ctl_t;
1527
1528 #define ODY_PCCPF_XXX_SRIOV_CTL ODY_PCCPF_XXX_SRIOV_CTL_FUNC()
1529 static inline uint64_t ODY_PCCPF_XXX_SRIOV_CTL_FUNC(void) __attribute__ ((pure, always_inline));
ODY_PCCPF_XXX_SRIOV_CTL_FUNC(void)1530 static inline uint64_t ODY_PCCPF_XXX_SRIOV_CTL_FUNC(void)
1531 {
1532 return 0x188;
1533 }
1534
1535 #define typedef_ODY_PCCPF_XXX_SRIOV_CTL ody_pccpf_xxx_sriov_ctl_t
1536 #define bustype_ODY_PCCPF_XXX_SRIOV_CTL CSR_TYPE_PCCPF
1537 #define basename_ODY_PCCPF_XXX_SRIOV_CTL "PCCPF_XXX_SRIOV_CTL"
1538 #define busnum_ODY_PCCPF_XXX_SRIOV_CTL 0
1539 #define arguments_ODY_PCCPF_XXX_SRIOV_CTL -1, -1, -1, -1
1540
1541 /**
1542 * Register (PCCPF) pccpf_xxx_sriov_dev
1543 *
1544 * PCC PF SR-IOV VF Device ID Register
1545 */
1546 union ody_pccpf_xxx_sriov_dev {
1547 uint32_t u;
1548 struct ody_pccpf_xxx_sriov_dev_s {
1549 uint32_t reserved_0_15 : 16;
1550 uint32_t vfdev : 16;
1551 } s;
1552 /* struct ody_pccpf_xxx_sriov_dev_s cn; */
1553 };
1554 typedef union ody_pccpf_xxx_sriov_dev ody_pccpf_xxx_sriov_dev_t;
1555
1556 #define ODY_PCCPF_XXX_SRIOV_DEV ODY_PCCPF_XXX_SRIOV_DEV_FUNC()
1557 static inline uint64_t ODY_PCCPF_XXX_SRIOV_DEV_FUNC(void) __attribute__ ((pure, always_inline));
ODY_PCCPF_XXX_SRIOV_DEV_FUNC(void)1558 static inline uint64_t ODY_PCCPF_XXX_SRIOV_DEV_FUNC(void)
1559 {
1560 return 0x198;
1561 }
1562
1563 #define typedef_ODY_PCCPF_XXX_SRIOV_DEV ody_pccpf_xxx_sriov_dev_t
1564 #define bustype_ODY_PCCPF_XXX_SRIOV_DEV CSR_TYPE_PCCPF
1565 #define basename_ODY_PCCPF_XXX_SRIOV_DEV "PCCPF_XXX_SRIOV_DEV"
1566 #define busnum_ODY_PCCPF_XXX_SRIOV_DEV 0
1567 #define arguments_ODY_PCCPF_XXX_SRIOV_DEV -1, -1, -1, -1
1568
1569 /**
1570 * Register (PCCPF) pccpf_xxx_sriov_fo
1571 *
1572 * PCC PF SR-IOV First VF Offset/VF Stride Register
1573 */
1574 union ody_pccpf_xxx_sriov_fo {
1575 uint32_t u;
1576 struct ody_pccpf_xxx_sriov_fo_s {
1577 uint32_t fo : 16;
1578 uint32_t vfs : 16;
1579 } s;
1580 /* struct ody_pccpf_xxx_sriov_fo_s cn; */
1581 };
1582 typedef union ody_pccpf_xxx_sriov_fo ody_pccpf_xxx_sriov_fo_t;
1583
1584 #define ODY_PCCPF_XXX_SRIOV_FO ODY_PCCPF_XXX_SRIOV_FO_FUNC()
1585 static inline uint64_t ODY_PCCPF_XXX_SRIOV_FO_FUNC(void) __attribute__ ((pure, always_inline));
ODY_PCCPF_XXX_SRIOV_FO_FUNC(void)1586 static inline uint64_t ODY_PCCPF_XXX_SRIOV_FO_FUNC(void)
1587 {
1588 return 0x194;
1589 }
1590
1591 #define typedef_ODY_PCCPF_XXX_SRIOV_FO ody_pccpf_xxx_sriov_fo_t
1592 #define bustype_ODY_PCCPF_XXX_SRIOV_FO CSR_TYPE_PCCPF
1593 #define basename_ODY_PCCPF_XXX_SRIOV_FO "PCCPF_XXX_SRIOV_FO"
1594 #define busnum_ODY_PCCPF_XXX_SRIOV_FO 0
1595 #define arguments_ODY_PCCPF_XXX_SRIOV_FO -1, -1, -1, -1
1596
1597 /**
1598 * Register (PCCPF) pccpf_xxx_sriov_nvf
1599 *
1600 * PCC PF SR-IOV Number of VFs/Function Dependency Link Register
1601 */
1602 union ody_pccpf_xxx_sriov_nvf {
1603 uint32_t u;
1604 struct ody_pccpf_xxx_sriov_nvf_s {
1605 uint32_t nvf : 16;
1606 uint32_t fdl : 8;
1607 uint32_t reserved_24_31 : 8;
1608 } s;
1609 /* struct ody_pccpf_xxx_sriov_nvf_s cn; */
1610 };
1611 typedef union ody_pccpf_xxx_sriov_nvf ody_pccpf_xxx_sriov_nvf_t;
1612
1613 #define ODY_PCCPF_XXX_SRIOV_NVF ODY_PCCPF_XXX_SRIOV_NVF_FUNC()
1614 static inline uint64_t ODY_PCCPF_XXX_SRIOV_NVF_FUNC(void) __attribute__ ((pure, always_inline));
ODY_PCCPF_XXX_SRIOV_NVF_FUNC(void)1615 static inline uint64_t ODY_PCCPF_XXX_SRIOV_NVF_FUNC(void)
1616 {
1617 return 0x190;
1618 }
1619
1620 #define typedef_ODY_PCCPF_XXX_SRIOV_NVF ody_pccpf_xxx_sriov_nvf_t
1621 #define bustype_ODY_PCCPF_XXX_SRIOV_NVF CSR_TYPE_PCCPF
1622 #define basename_ODY_PCCPF_XXX_SRIOV_NVF "PCCPF_XXX_SRIOV_NVF"
1623 #define busnum_ODY_PCCPF_XXX_SRIOV_NVF 0
1624 #define arguments_ODY_PCCPF_XXX_SRIOV_NVF -1, -1, -1, -1
1625
1626 /**
1627 * Register (PCCPF) pccpf_xxx_sriov_ps
1628 *
1629 * PCC PF SR-IOV System Page Sizes Register
1630 */
1631 union ody_pccpf_xxx_sriov_ps {
1632 uint32_t u;
1633 struct ody_pccpf_xxx_sriov_ps_s {
1634 uint32_t ps : 32;
1635 } s;
1636 /* struct ody_pccpf_xxx_sriov_ps_s cn; */
1637 };
1638 typedef union ody_pccpf_xxx_sriov_ps ody_pccpf_xxx_sriov_ps_t;
1639
1640 #define ODY_PCCPF_XXX_SRIOV_PS ODY_PCCPF_XXX_SRIOV_PS_FUNC()
1641 static inline uint64_t ODY_PCCPF_XXX_SRIOV_PS_FUNC(void) __attribute__ ((pure, always_inline));
ODY_PCCPF_XXX_SRIOV_PS_FUNC(void)1642 static inline uint64_t ODY_PCCPF_XXX_SRIOV_PS_FUNC(void)
1643 {
1644 return 0x1a0;
1645 }
1646
1647 #define typedef_ODY_PCCPF_XXX_SRIOV_PS ody_pccpf_xxx_sriov_ps_t
1648 #define bustype_ODY_PCCPF_XXX_SRIOV_PS CSR_TYPE_PCCPF
1649 #define basename_ODY_PCCPF_XXX_SRIOV_PS "PCCPF_XXX_SRIOV_PS"
1650 #define busnum_ODY_PCCPF_XXX_SRIOV_PS 0
1651 #define arguments_ODY_PCCPF_XXX_SRIOV_PS -1, -1, -1, -1
1652
1653 /**
1654 * Register (PCCPF) pccpf_xxx_sriov_supps
1655 *
1656 * PCC PF SR-IOV Supported Page Sizes Register
1657 */
1658 union ody_pccpf_xxx_sriov_supps {
1659 uint32_t u;
1660 struct ody_pccpf_xxx_sriov_supps_s {
1661 uint32_t supps : 32;
1662 } s;
1663 /* struct ody_pccpf_xxx_sriov_supps_s cn; */
1664 };
1665 typedef union ody_pccpf_xxx_sriov_supps ody_pccpf_xxx_sriov_supps_t;
1666
1667 #define ODY_PCCPF_XXX_SRIOV_SUPPS ODY_PCCPF_XXX_SRIOV_SUPPS_FUNC()
1668 static inline uint64_t ODY_PCCPF_XXX_SRIOV_SUPPS_FUNC(void) __attribute__ ((pure, always_inline));
ODY_PCCPF_XXX_SRIOV_SUPPS_FUNC(void)1669 static inline uint64_t ODY_PCCPF_XXX_SRIOV_SUPPS_FUNC(void)
1670 {
1671 return 0x19c;
1672 }
1673
1674 #define typedef_ODY_PCCPF_XXX_SRIOV_SUPPS ody_pccpf_xxx_sriov_supps_t
1675 #define bustype_ODY_PCCPF_XXX_SRIOV_SUPPS CSR_TYPE_PCCPF
1676 #define basename_ODY_PCCPF_XXX_SRIOV_SUPPS "PCCPF_XXX_SRIOV_SUPPS"
1677 #define busnum_ODY_PCCPF_XXX_SRIOV_SUPPS 0
1678 #define arguments_ODY_PCCPF_XXX_SRIOV_SUPPS -1, -1, -1, -1
1679
1680 /**
1681 * Register (PCCPF) pccpf_xxx_sriov_vfs
1682 *
1683 * PCC PF SR-IOV Initial VFs/Total VFs Register
1684 */
1685 union ody_pccpf_xxx_sriov_vfs {
1686 uint32_t u;
1687 struct ody_pccpf_xxx_sriov_vfs_s {
1688 uint32_t ivf : 16;
1689 uint32_t tvf : 16;
1690 } s;
1691 /* struct ody_pccpf_xxx_sriov_vfs_s cn; */
1692 };
1693 typedef union ody_pccpf_xxx_sriov_vfs ody_pccpf_xxx_sriov_vfs_t;
1694
1695 #define ODY_PCCPF_XXX_SRIOV_VFS ODY_PCCPF_XXX_SRIOV_VFS_FUNC()
1696 static inline uint64_t ODY_PCCPF_XXX_SRIOV_VFS_FUNC(void) __attribute__ ((pure, always_inline));
ODY_PCCPF_XXX_SRIOV_VFS_FUNC(void)1697 static inline uint64_t ODY_PCCPF_XXX_SRIOV_VFS_FUNC(void)
1698 {
1699 return 0x18c;
1700 }
1701
1702 #define typedef_ODY_PCCPF_XXX_SRIOV_VFS ody_pccpf_xxx_sriov_vfs_t
1703 #define bustype_ODY_PCCPF_XXX_SRIOV_VFS CSR_TYPE_PCCPF
1704 #define basename_ODY_PCCPF_XXX_SRIOV_VFS "PCCPF_XXX_SRIOV_VFS"
1705 #define busnum_ODY_PCCPF_XXX_SRIOV_VFS 0
1706 #define arguments_ODY_PCCPF_XXX_SRIOV_VFS -1, -1, -1, -1
1707
1708 /**
1709 * Register (PCCPF) pccpf_xxx_subid
1710 *
1711 * PCC PF Subsystem ID/Subsystem Vendor ID Register
1712 */
1713 union ody_pccpf_xxx_subid {
1714 uint32_t u;
1715 struct ody_pccpf_xxx_subid_s {
1716 uint32_t ssvid : 16;
1717 uint32_t ssid : 16;
1718 } s;
1719 /* struct ody_pccpf_xxx_subid_s cn; */
1720 };
1721 typedef union ody_pccpf_xxx_subid ody_pccpf_xxx_subid_t;
1722
1723 #define ODY_PCCPF_XXX_SUBID ODY_PCCPF_XXX_SUBID_FUNC()
1724 static inline uint64_t ODY_PCCPF_XXX_SUBID_FUNC(void) __attribute__ ((pure, always_inline));
ODY_PCCPF_XXX_SUBID_FUNC(void)1725 static inline uint64_t ODY_PCCPF_XXX_SUBID_FUNC(void)
1726 {
1727 return 0x2c;
1728 }
1729
1730 #define typedef_ODY_PCCPF_XXX_SUBID ody_pccpf_xxx_subid_t
1731 #define bustype_ODY_PCCPF_XXX_SUBID CSR_TYPE_PCCPF
1732 #define basename_ODY_PCCPF_XXX_SUBID "PCCPF_XXX_SUBID"
1733 #define busnum_ODY_PCCPF_XXX_SUBID 0
1734 #define arguments_ODY_PCCPF_XXX_SUBID -1, -1, -1, -1
1735
1736 /**
1737 * Register (PCCPF) pccpf_xxx_vsec_cap_hdr
1738 *
1739 * PCC PF Vendor-Specific Capability Header Register
1740 * This register is the header of the 64-byte {ProductLine} family PF capability
1741 * structure.
1742 */
1743 union ody_pccpf_xxx_vsec_cap_hdr {
1744 uint32_t u;
1745 struct ody_pccpf_xxx_vsec_cap_hdr_s {
1746 uint32_t vsecid : 16;
1747 uint32_t cv : 4;
1748 uint32_t nco : 12;
1749 } s;
1750 /* struct ody_pccpf_xxx_vsec_cap_hdr_s cn; */
1751 };
1752 typedef union ody_pccpf_xxx_vsec_cap_hdr ody_pccpf_xxx_vsec_cap_hdr_t;
1753
1754 #define ODY_PCCPF_XXX_VSEC_CAP_HDR ODY_PCCPF_XXX_VSEC_CAP_HDR_FUNC()
1755 static inline uint64_t ODY_PCCPF_XXX_VSEC_CAP_HDR_FUNC(void) __attribute__ ((pure, always_inline));
ODY_PCCPF_XXX_VSEC_CAP_HDR_FUNC(void)1756 static inline uint64_t ODY_PCCPF_XXX_VSEC_CAP_HDR_FUNC(void)
1757 {
1758 return 0x100;
1759 }
1760
1761 #define typedef_ODY_PCCPF_XXX_VSEC_CAP_HDR ody_pccpf_xxx_vsec_cap_hdr_t
1762 #define bustype_ODY_PCCPF_XXX_VSEC_CAP_HDR CSR_TYPE_PCCPF
1763 #define basename_ODY_PCCPF_XXX_VSEC_CAP_HDR "PCCPF_XXX_VSEC_CAP_HDR"
1764 #define busnum_ODY_PCCPF_XXX_VSEC_CAP_HDR 0
1765 #define arguments_ODY_PCCPF_XXX_VSEC_CAP_HDR -1, -1, -1, -1
1766
1767 /**
1768 * Register (PCCPF) pccpf_xxx_vsec_ctl
1769 *
1770 * PCC PF Vendor-Specific Control Register
1771 * This register is reset on a chip domain reset.
1772 */
1773 union ody_pccpf_xxx_vsec_ctl {
1774 uint32_t u;
1775 struct ody_pccpf_xxx_vsec_ctl_s {
1776 uint32_t inst_num : 8;
1777 uint32_t poison_tlp : 1;
1778 uint32_t uncor_intn : 1;
1779 uint32_t adv_nfat : 1;
1780 uint32_t cor_intn : 1;
1781 uint32_t reserved_12_23 : 12;
1782 uint32_t nxtfn_ns : 8;
1783 } s;
1784 /* struct ody_pccpf_xxx_vsec_ctl_s cn; */
1785 };
1786 typedef union ody_pccpf_xxx_vsec_ctl ody_pccpf_xxx_vsec_ctl_t;
1787
1788 #define ODY_PCCPF_XXX_VSEC_CTL ODY_PCCPF_XXX_VSEC_CTL_FUNC()
1789 static inline uint64_t ODY_PCCPF_XXX_VSEC_CTL_FUNC(void) __attribute__ ((pure, always_inline));
ODY_PCCPF_XXX_VSEC_CTL_FUNC(void)1790 static inline uint64_t ODY_PCCPF_XXX_VSEC_CTL_FUNC(void)
1791 {
1792 return 0x108;
1793 }
1794
1795 #define typedef_ODY_PCCPF_XXX_VSEC_CTL ody_pccpf_xxx_vsec_ctl_t
1796 #define bustype_ODY_PCCPF_XXX_VSEC_CTL CSR_TYPE_PCCPF
1797 #define basename_ODY_PCCPF_XXX_VSEC_CTL "PCCPF_XXX_VSEC_CTL"
1798 #define busnum_ODY_PCCPF_XXX_VSEC_CTL 0
1799 #define arguments_ODY_PCCPF_XXX_VSEC_CTL -1, -1, -1, -1
1800
1801 /**
1802 * Register (PCCPF) pccpf_xxx_vsec_id
1803 *
1804 * PCC PF Vendor-Specific Identification Register
1805 */
1806 union ody_pccpf_xxx_vsec_id {
1807 uint32_t u;
1808 struct ody_pccpf_xxx_vsec_id_s {
1809 uint32_t id : 16;
1810 uint32_t rev : 4;
1811 uint32_t len : 12;
1812 } s;
1813 /* struct ody_pccpf_xxx_vsec_id_s cn; */
1814 };
1815 typedef union ody_pccpf_xxx_vsec_id ody_pccpf_xxx_vsec_id_t;
1816
1817 #define ODY_PCCPF_XXX_VSEC_ID ODY_PCCPF_XXX_VSEC_ID_FUNC()
1818 static inline uint64_t ODY_PCCPF_XXX_VSEC_ID_FUNC(void) __attribute__ ((pure, always_inline));
ODY_PCCPF_XXX_VSEC_ID_FUNC(void)1819 static inline uint64_t ODY_PCCPF_XXX_VSEC_ID_FUNC(void)
1820 {
1821 return 0x104;
1822 }
1823
1824 #define typedef_ODY_PCCPF_XXX_VSEC_ID ody_pccpf_xxx_vsec_id_t
1825 #define bustype_ODY_PCCPF_XXX_VSEC_ID CSR_TYPE_PCCPF
1826 #define basename_ODY_PCCPF_XXX_VSEC_ID "PCCPF_XXX_VSEC_ID"
1827 #define busnum_ODY_PCCPF_XXX_VSEC_ID 0
1828 #define arguments_ODY_PCCPF_XXX_VSEC_ID -1, -1, -1, -1
1829
1830 /**
1831 * Register (PCCPF) pccpf_xxx_vsec_sctl
1832 *
1833 * PCC PF Vendor-Specific Secure Control Register
1834 * This register is reset on a chip domain reset.
1835 */
1836 union ody_pccpf_xxx_vsec_sctl {
1837 uint32_t u;
1838 struct ody_pccpf_xxx_vsec_sctl_s {
1839 uint32_t msix_phys : 1;
1840 uint32_t msix_sec : 1;
1841 uint32_t msix_sec_en : 1;
1842 uint32_t ea : 1;
1843 uint32_t node : 2;
1844 uint32_t gia_timeout : 6;
1845 uint32_t reserved_12_14 : 3;
1846 uint32_t msix_sec_phys : 1;
1847 uint32_t rid : 8;
1848 uint32_t nxtfn_s : 8;
1849 } s;
1850 /* struct ody_pccpf_xxx_vsec_sctl_s cn; */
1851 };
1852 typedef union ody_pccpf_xxx_vsec_sctl ody_pccpf_xxx_vsec_sctl_t;
1853
1854 #define ODY_PCCPF_XXX_VSEC_SCTL ODY_PCCPF_XXX_VSEC_SCTL_FUNC()
1855 static inline uint64_t ODY_PCCPF_XXX_VSEC_SCTL_FUNC(void) __attribute__ ((pure, always_inline));
ODY_PCCPF_XXX_VSEC_SCTL_FUNC(void)1856 static inline uint64_t ODY_PCCPF_XXX_VSEC_SCTL_FUNC(void)
1857 {
1858 return 0x10c;
1859 }
1860
1861 #define typedef_ODY_PCCPF_XXX_VSEC_SCTL ody_pccpf_xxx_vsec_sctl_t
1862 #define bustype_ODY_PCCPF_XXX_VSEC_SCTL CSR_TYPE_PCCPF
1863 #define basename_ODY_PCCPF_XXX_VSEC_SCTL "PCCPF_XXX_VSEC_SCTL"
1864 #define busnum_ODY_PCCPF_XXX_VSEC_SCTL 0
1865 #define arguments_ODY_PCCPF_XXX_VSEC_SCTL -1, -1, -1, -1
1866
1867 /**
1868 * Register (PCCPF) pccpf_xxx_vsec_sctl2
1869 *
1870 * PCC PF Vendor-Specific Secure Control 2 Register
1871 * This register is reset on a chip domain reset.
1872 */
1873 union ody_pccpf_xxx_vsec_sctl2 {
1874 uint32_t u;
1875 struct ody_pccpf_xxx_vsec_sctl2_s {
1876 uint32_t ssid : 16;
1877 uint32_t reserved_16_31 : 16;
1878 } s;
1879 /* struct ody_pccpf_xxx_vsec_sctl2_s cn; */
1880 };
1881 typedef union ody_pccpf_xxx_vsec_sctl2 ody_pccpf_xxx_vsec_sctl2_t;
1882
1883 #define ODY_PCCPF_XXX_VSEC_SCTL2 ODY_PCCPF_XXX_VSEC_SCTL2_FUNC()
1884 static inline uint64_t ODY_PCCPF_XXX_VSEC_SCTL2_FUNC(void) __attribute__ ((pure, always_inline));
ODY_PCCPF_XXX_VSEC_SCTL2_FUNC(void)1885 static inline uint64_t ODY_PCCPF_XXX_VSEC_SCTL2_FUNC(void)
1886 {
1887 return 0x110;
1888 }
1889
1890 #define typedef_ODY_PCCPF_XXX_VSEC_SCTL2 ody_pccpf_xxx_vsec_sctl2_t
1891 #define bustype_ODY_PCCPF_XXX_VSEC_SCTL2 CSR_TYPE_PCCPF
1892 #define basename_ODY_PCCPF_XXX_VSEC_SCTL2 "PCCPF_XXX_VSEC_SCTL2"
1893 #define busnum_ODY_PCCPF_XXX_VSEC_SCTL2 0
1894 #define arguments_ODY_PCCPF_XXX_VSEC_SCTL2 -1, -1, -1, -1
1895
1896 #endif /* __ODY_CSRS_PCCPF_H__ */
1897