1Build Options 2============= 3 4The TF-A build system supports the following build options. Unless mentioned 5otherwise, these options are expected to be specified at the build command 6line and are not to be modified in any component makefiles. Note that the 7build system doesn't track dependency for build options. Therefore, if any of 8the build options are changed from a previous build, a clean build must be 9performed. 10 11.. _build_options_common: 12 13Common build options 14-------------------- 15 16- ``AARCH32_INSTRUCTION_SET``: Choose the AArch32 instruction set that the 17 compiler should use. Valid values are T32 and A32. It defaults to T32 due to 18 code having a smaller resulting size. 19 20- ``AARCH32_SP`` : Choose the AArch32 Secure Payload component to be built as 21 as the BL32 image when ``ARCH=aarch32``. The value should be the path to the 22 directory containing the SP source, relative to the ``bl32/``; the directory 23 is expected to contain a makefile called ``<aarch32_sp-value>.mk``. 24 25- ``AMU_RESTRICT_COUNTERS``: Register reads to the group 1 counters will return 26 zero at all but the highest implemented exception level. External 27 memory-mapped debug accesses are unaffected by this control. 28 The default value is 1 for all platforms. 29 30- ``ARCH`` : Choose the target build architecture for TF-A. It can take either 31 ``aarch64`` or ``aarch32`` as values. By default, it is defined to 32 ``aarch64``. 33 34- ``ARM_ARCH_FEATURE``: Optional Arm Architecture build option which specifies 35 one or more feature modifiers. This option has the form ``[no]feature+...`` 36 and defaults to ``none``. It translates into compiler option 37 ``-march=armvX[.Y]-a+[no]feature+...``. See compiler's documentation for the 38 list of supported feature modifiers. 39 40- ``ARM_ARCH_MAJOR``: The major version of Arm Architecture to target when 41 compiling TF-A. Its value must be numeric, and defaults to 8 . See also, 42 *Armv8 Architecture Extensions* and *Armv7 Architecture Extensions* in 43 :ref:`Firmware Design`. 44 45- ``ARM_ARCH_MINOR``: The minor version of Arm Architecture to target when 46 compiling TF-A. Its value must be a numeric, and defaults to 0. See also, 47 *Armv8 Architecture Extensions* in :ref:`Firmware Design`. 48 49- ``ARM_BL2_SP_LIST_DTS``: Path to DTS file snippet to override the hardcoded 50 SP nodes in tb_fw_config. 51 52- ``ARM_SPMC_MANIFEST_DTS`` : path to an alternate manifest file used as the 53 SPMC Core manifest. Valid when ``SPD=spmd`` is selected. 54 55- ``BL2``: This is an optional build option which specifies the path to BL2 56 image for the ``fip`` target. In this case, the BL2 in the TF-A will not be 57 built. 58 59- ``BL2U``: This is an optional build option which specifies the path to 60 BL2U image. In this case, the BL2U in TF-A will not be built. 61 62- ``RESET_TO_BL2``: Boolean option to enable BL2 entrypoint as the CPU reset 63 vector instead of the BL1 entrypoint. It can take the value 0 (CPU reset to BL1 64 entrypoint) or 1 (CPU reset to BL2 entrypoint). 65 The default value is 0. 66 67- ``BL2_RUNS_AT_EL3``: This is an implicit flag to denote that BL2 runs at EL3. 68 While it is explicitly set to 1 when RESET_TO_BL2 is set to 1 it can also be 69 true in a 4-world system where RESET_TO_BL2 is 0. 70 71- ``BL2_ENABLE_SP_LOAD``: Boolean option to enable loading SP packages from the 72 FIP. Automatically enabled if ``SP_LAYOUT_FILE`` is provided. 73 74- ``BL2_IN_XIP_MEM``: In some use-cases BL2 will be stored in eXecute In Place 75 (XIP) memory, like BL1. In these use-cases, it is necessary to initialize 76 the RW sections in RAM, while leaving the RO sections in place. This option 77 enable this use-case. For now, this option is only supported 78 when RESET_TO_BL2 is set to '1'. 79 80- ``BL31``: This is an optional build option which specifies the path to 81 BL31 image for the ``fip`` target. In this case, the BL31 in TF-A will not 82 be built. 83 84- ``BL31_KEY``: This option is used when ``GENERATE_COT=1``. It specifies a 85 file that contains the BL31 private key in PEM format or a PKCS11 URI. If 86 ``SAVE_KEYS=1``, only a file is accepted and it will be used to save the key. 87 88- ``BL32``: This is an optional build option which specifies the path to 89 BL32 image for the ``fip`` target. In this case, the BL32 in TF-A will not 90 be built. 91 92- ``BL32_EXTRA1``: This is an optional build option which specifies the path to 93 Trusted OS Extra1 image for the ``fip`` target. 94 95- ``BL32_EXTRA2``: This is an optional build option which specifies the path to 96 Trusted OS Extra2 image for the ``fip`` target. 97 98- ``BL32_KEY``: This option is used when ``GENERATE_COT=1``. It specifies a 99 file that contains the BL32 private key in PEM format or a PKCS11 URI. If 100 ``SAVE_KEYS=1``, only a file is accepted and it will be used to save the key. 101 102- ``RMM``: This is an optional build option used when ``ENABLE_RME`` is set. 103 It specifies the path to RMM binary for the ``fip`` target. If the RMM option 104 is not specified, TF-A builds the TRP to load and run at R-EL2. 105 106- ``BL33``: Path to BL33 image in the host file system. This is mandatory for 107 ``fip`` target in case TF-A BL2 is used. 108 109- ``BL33_KEY``: This option is used when ``GENERATE_COT=1``. It specifies a 110 file that contains the BL33 private key in PEM format or a PKCS11 URI. If 111 ``SAVE_KEYS=1``, only a file is accepted and it will be used to save the key. 112 113- ``BRANCH_PROTECTION``: Numeric value to enable ARMv8.3 Pointer Authentication 114 and ARMv8.5 Branch Target Identification support for TF-A BL images themselves. 115 If enabled, it is needed to use a compiler that supports the option 116 ``-mbranch-protection``. The value of the ``-march`` (via ``ARM_ARCH_MINOR`` 117 and ``ARM_ARCH_MAJOR``) option will control which instructions will be 118 emitted (HINT space or not). Selects the branch protection features to use: 119- 0: Default value turns off all types of branch protection (FEAT_STATE_DISABLED) 120- 1: Enables all types of branch protection features 121- 2: Return address signing to its standard level 122- 3: Extend the signing to include leaf functions 123- 4: Turn on branch target identification mechanism 124- 5: Enables all types of branch protection features, only if present in 125 hardware (FEAT_STATE_CHECK). 126 127 The table below summarizes ``BRANCH_PROTECTION`` values, GCC compilation options 128 and resulting PAuth/BTI features. 129 130 +-------+--------------+-------+-----+ 131 | Value | GCC option | PAuth | BTI | 132 +=======+==============+=======+=====+ 133 | 0 | none | N | N | 134 +-------+--------------+-------+-----+ 135 | 1 | standard | Y | Y | 136 +-------+--------------+-------+-----+ 137 | 2 | pac-ret | Y | N | 138 +-------+--------------+-------+-----+ 139 | 3 | pac-ret+leaf | Y | N | 140 +-------+--------------+-------+-----+ 141 | 4 | bti | N | Y | 142 +-------+--------------+-------+-----+ 143 | 5 | dynamic | Y | Y | 144 +-------+--------------+-------+-----+ 145 146 This option defaults to 0. 147 Note that Pointer Authentication is enabled for Non-secure world 148 irrespective of the value of this option if the CPU supports it. 149 150- ``BUILD_MESSAGE_TIMESTAMP``: String used to identify the time and date of the 151 compilation of each build. It must be set to a C string (including quotes 152 where applicable). Defaults to a string that contains the time and date of 153 the compilation. 154 155- ``BUILD_STRING``: Input string for VERSION_STRING, which allows the TF-A 156 build to be uniquely identified. Defaults to the current git commit id. 157 158- ``BUILD_BASE``: Output directory for the build. Defaults to ``./build`` 159 160- ``CFLAGS``: Extra user options appended on the compiler's command line in 161 addition to the options set by the build system. 162 163- ``COLD_BOOT_SINGLE_CPU``: This option indicates whether the platform may 164 release several CPUs out of reset. It can take either 0 (several CPUs may be 165 brought up) or 1 (only one CPU will ever be brought up during cold reset). 166 Default is 0. If the platform always brings up a single CPU, there is no 167 need to distinguish between primary and secondary CPUs and the boot path can 168 be optimised. The ``plat_is_my_cpu_primary()`` and 169 ``plat_secondary_cold_boot_setup()`` platform porting interfaces do not need 170 to be implemented in this case. 171 172- ``COT``: When Trusted Boot is enabled, selects the desired chain of trust. 173 Defaults to ``tbbr``. 174 175- ``CRASH_REPORTING``: A non-zero value enables a console dump of processor 176 register state when an unexpected exception occurs during execution of 177 BL31. This option defaults to the value of ``DEBUG`` - i.e. by default 178 this is only enabled for a debug build of the firmware. 179 180- ``CREATE_KEYS``: This option is used when ``GENERATE_COT=1``. It tells the 181 certificate generation tool to create new keys in case no valid keys are 182 present or specified. Allowed options are '0' or '1'. Default is '1'. 183 184- ``CTX_INCLUDE_AARCH32_REGS`` : Boolean option that, when set to 1, will cause 185 the AArch32 system registers to be included when saving and restoring the 186 CPU context. The option must be set to 0 for AArch64-only platforms (that 187 is on hardware that does not implement AArch32, or at least not at EL1 and 188 higher ELs). Default value is 1. 189 190- ``CTX_INCLUDE_FPREGS``: Boolean option that, when set to 1, will cause the FP 191 registers to be included when saving and restoring the CPU context. Default 192 is 0. 193 194- ``CTX_INCLUDE_MPAM_REGS``: Boolean option that, when set to 1, will cause the 195 Memory System Resource Partitioning and Monitoring (MPAM) 196 registers to be included when saving and restoring the CPU context. 197 Default is '0'. 198 199- ``CTX_INCLUDE_NEVE_REGS``: Numeric value, when set will cause the Armv8.4-NV 200 registers to be saved/restored when entering/exiting an EL2 execution 201 context. This flag can take values 0 to 2, to align with the 202 ``ENABLE_FEAT`` mechanism. Default value is 0. 203 204- ``CTX_INCLUDE_PAUTH_REGS``: Numeric value to enable the Pointer 205 Authentication for Secure world. This will cause the ARMv8.3-PAuth registers 206 to be included when saving and restoring the CPU context as part of world 207 switch. Automatically enabled when ``BRANCH_PROTECTION`` is enabled. This flag 208 can take values 0 to 2, to align with ``ENABLE_FEAT`` mechanism. Default value 209 is 0. 210 211 Note that Pointer Authentication is enabled for Non-secure world irrespective 212 of the value of this flag if the CPU supports it. Alternatively, when 213 ``BRANCH_PROTECTION`` is enabled, this flag is superseded. 214 215- ``CTX_INCLUDE_SVE_REGS``: Boolean option that, when set to 1, will cause the 216 SVE registers to be included when saving and restoring the CPU context. Note 217 that this build option requires ``ENABLE_SVE_FOR_SWD`` to be enabled. In 218 general, it is recommended to perform SVE context management in lower ELs 219 and skip in EL3 due to the additional cost of maintaining large data 220 structures to track the SVE state. Hence, the default value is 0. 221 222- ``DEBUG``: Chooses between a debug and release build. It can take either 0 223 (release) or 1 (debug) as values. 0 is the default. 224 225- ``DECRYPTION_SUPPORT``: This build flag enables the user to select the 226 authenticated decryption algorithm to be used to decrypt firmware/s during 227 boot. It accepts 2 values: ``aes_gcm`` and ``none``. The default value of 228 this flag is ``none`` to disable firmware decryption which is an optional 229 feature as per TBBR. 230 231- ``DISABLE_BIN_GENERATION``: Boolean option to disable the generation 232 of the binary image. If set to 1, then only the ELF image is built. 233 0 is the default. 234 235- ``DISABLE_MTPMU``: Numeric option to disable ``FEAT_MTPMU`` (Multi Threaded 236 PMU). ``FEAT_MTPMU`` is an optional feature available on Armv8.6 onwards. 237 This flag can take values 0 to 2, to align with the ``ENABLE_FEAT`` 238 mechanism. Default is ``0``. 239 240- ``DYN_DISABLE_AUTH``: Provides the capability to dynamically disable Trusted 241 Board Boot authentication at runtime. This option is meant to be enabled only 242 for development platforms. ``TRUSTED_BOARD_BOOT`` flag must be set if this 243 flag has to be enabled. 0 is the default. 244 245- ``E``: Boolean option to make warnings into errors. Default is 1. 246 247 When specifying higher warnings levels (``W=1`` and higher), this option 248 defaults to 0. This is done to encourage contributors to use them, as they 249 are expected to produce warnings that would otherwise fail the build. New 250 contributions are still expected to build with ``W=0`` and ``E=1`` (the 251 default). 252 253- ``EARLY_CONSOLE``: This option is used to enable early traces before default 254 console is properly setup. It introduces EARLY_* traces macros, that will 255 use the non-EARLY traces macros if the flag is enabled, or do nothing 256 otherwise. To use this feature, platforms will have to create the function 257 plat_setup_early_console(). 258 Default is 0 (disabled) 259 260- ``EL3_PAYLOAD_BASE``: This option enables booting an EL3 payload instead of 261 the normal boot flow. It must specify the entry point address of the EL3 262 payload. Please refer to the "Booting an EL3 payload" section for more 263 details. 264 265- ``ENABLE_AMU_AUXILIARY_COUNTERS``: Enables support for AMU auxiliary counters 266 (also known as group 1 counters). These are implementation-defined counters, 267 and as such require additional platform configuration. Default is 0. 268 269- ``ENABLE_ASSERTIONS``: This option controls whether or not calls to ``assert()`` 270 are compiled out. For debug builds, this option defaults to 1, and calls to 271 ``assert()`` are left in place. For release builds, this option defaults to 0 272 and calls to ``assert()`` function are compiled out. This option can be set 273 independently of ``DEBUG``. It can also be used to hide any auxiliary code 274 that is only required for the assertion and does not fit in the assertion 275 itself. 276 277- ``ENABLE_BACKTRACE``: This option controls whether to enable backtrace 278 dumps or not. It is supported in both AArch64 and AArch32. However, in 279 AArch32 the format of the frame records are not defined in the AAPCS and they 280 are defined by the implementation. This implementation of backtrace only 281 supports the format used by GCC when T32 interworking is disabled. For this 282 reason enabling this option in AArch32 will force the compiler to only 283 generate A32 code. This option is enabled by default only in AArch64 debug 284 builds, but this behaviour can be overridden in each platform's Makefile or 285 in the build command line. 286 287- ``ENABLE_FEAT_AMU``: Numeric value to enable Activity Monitor Unit 288 extensions. This flag can take the values 0 to 2, to align with the 289 ``ENABLE_FEAT`` mechanism. This is an optional architectural feature 290 available on v8.4 onwards. Some v8.2 implementations also implement an AMU 291 and this option can be used to enable this feature on those systems as well. 292 This flag can take the values 0 to 2, the default is 0. 293 294- ``ENABLE_FEAT_AMUv1p1``: Numeric value to enable the ``FEAT_AMUv1p1`` 295 extension. ``FEAT_AMUv1p1`` is an optional feature available on Arm v8.6 296 onwards. This flag can take the values 0 to 2, to align with the 297 ``ENABLE_FEAT`` mechanism. Default value is ``0``. 298 299- ``ENABLE_FEAT_CLRBHB``: Numeric value to enable the CLRBHB instruction. 300 Clear Branch History clears the branch history for the current context to 301 the extent that branch history information created before the CLRBHB instruction 302 cannot be used by code. This is an optional architectural feature available on v8.0 303 onwards and is a mandatory feature from v8.9 onwards. 304 This flag can take the values of 0 to 2, to align with the ``ENABLE_FEAT`` mechanism. 305 Default value is ``0``. 306 307- ``ENABLE_FEAT_CPA2``: Numeric value to enable the ``FEAT_CPA2`` extension. 308 It enables checked pointer arithmetic in EL3, which will result in address 309 faults in the event that a pointer arithmetic overflow error occurs. This is 310 an optional feature starting from Arm v9.4 and This flag can take values 0 to 311 2, to align with the ``ENABLE_FEAT`` mechanism. Default value is ``0``. 312 313- ``ENABLE_FEAT_CSV2_2``: Numeric value to enable the ``FEAT_CSV2_2`` 314 extension. It allows access to the SCXTNUM_EL2 (Software Context Number) 315 register during EL2 context save/restore operations. ``FEAT_CSV2_2`` is an 316 optional feature available on Arm v8.0 onwards. This flag can take values 317 0 to 2, to align with the ``ENABLE_FEAT`` mechanism. 318 Default value is ``0``. 319 320- ``ENABLE_FEAT_CSV2_3``: Numeric value to enable support for ``FEAT_CSV2_3`` 321 extension. This feature is supported in AArch64 state only and is an optional 322 feature available in Arm v8.0 implementations. 323 ``FEAT_CSV2_3`` implies the implementation of ``FEAT_CSV2_2``. 324 The flag can take values 0 to 2, to align with the ``ENABLE_FEAT`` 325 mechanism. Default value is ``0``. 326 327- ``ENABLE_FEAT_CRYPTO``: Numeric value to enable the ``FEAT_CRYPTO`` 328 extension. It allows using the SIMD crypto extension AES, SHA1 and SHA2 329 instructions for mbedtls HASH256, which speeds up the authentication process 330 of the subsequent images in BL1 and BL2. ``FEAT_CRYPTO`` is an optional 331 feature available on Arm v8 onwards. This flag can take values 332 0 to 2, to align with the ``ENABLE_FEAT`` mechanism, however, value ``2`` 333 is treated as ``0`` since there is no way to perform runtime check. 334 Default value is ``0``. 335 336- ``ENABLE_FEAT_CRYPTO_SHA3``: Numeric value to enable the ``FEAT_CRYPTO`` 337 extension. It allows using the SIMD crypto extension SHA3 instructions for 338 mbedtls HASH384 and HASH512, which speeds up the authentication process of 339 the subsequent images in BL1 and BL2. ``FEAT_CRYPTO_SHA3`` is an optional 340 feature available on Arm v8.2 onwards. This flag can take values 341 0 to 1, to align with the ``ENABLE_FEAT`` mechanism, however, value ``2`` 342 is treated as ``0`` since there is no way to perform runtime check. 343 Default value is ``0``. 344 345- ``ENABLE_FEAT_DEBUGV8P9``: Numeric value to enable ``FEAT_DEBUGV8P9`` 346 extension which allows the ability to implement more than 16 breakpoints 347 and/or watchpoints. This feature is mandatory from v8.9 and is optional 348 from v8.8. This flag can take the values of 0 to 2, to align with the 349 ``ENABLE_FEAT`` mechanism. Default value is ``0``. 350 351- ``ENABLE_FEAT_DIT``: Numeric value to enable ``FEAT_DIT`` (Data Independent 352 Timing) extension. It allows setting the ``DIT`` bit of PSTATE in EL3. 353 ``FEAT_DIT`` is a mandatory architectural feature and is enabled from v8.4 354 and upwards. This flag can take the values 0 to 2, to align with the 355 ``ENABLE_FEAT`` mechanism. Default value is ``0``. 356 357- ``ENABLE_FEAT_ECV``: Numeric value to enable support for the Enhanced Counter 358 Virtualization feature, allowing for access to the CNTPOFF_EL2 (Counter-timer 359 Physical Offset register) during EL2 to EL3 context save/restore operations. 360 Its a mandatory architectural feature and is enabled from v8.6 and upwards. 361 This flag can take the values 0 to 2, to align with the ``ENABLE_FEAT`` 362 mechanism. Default value is ``0``. 363 364- ``ENABLE_FEAT_FPMR``: Numerical value to enable support for Floating Point 365 Mode Register feature, allowing access to the FPMR register. FPMR register 366 controls the behaviors of FP8 instructions. It is an optional architectural 367 feature from v9.2 and upwards. This flag can take value of 0 to 2, to align 368 with the ``FEATURE_DETECTION`` mechanism. Default value is ``0``. 369 370- ``ENABLE_FEAT_FGT``: Numeric value to enable support for FGT (Fine Grain Traps) 371 feature allowing for access to the HDFGRTR_EL2 (Hypervisor Debug Fine-Grained 372 Read Trap Register) during EL2 to EL3 context save/restore operations. 373 Its a mandatory architectural feature and is enabled from v8.6 and upwards. 374 This flag can take the values 0 to 2, to align with the ``ENABLE_FEAT`` 375 mechanism. Default value is ``0``. 376 377- ``ENABLE_FEAT_FGT2``: Numeric value to enable support for FGT2 378 (Fine Grain Traps 2) feature allowing for access to Fine-grained trap 2 registers 379 during EL2 to EL3 context save/restore operations. 380 Its an optional architectural feature and is available from v8.8 and upwards. 381 This flag can take the values 0 to 2, to align with the ``ENABLE_FEAT`` 382 mechanism. Default value is ``0``. 383 384- ``ENABLE_FEAT_FGWTE3``: Numeric value to enable support for 385 Fine Grained Write Trap EL3 (FEAT_FGWTE3), a feature that allows EL3 to 386 restrict overwriting certain EL3 registers after boot. 387 This lockdown is established by setting individual trap bits for 388 system registers that are not expected to be overwritten after boot. 389 This feature is an optional architectural feature and is available from 390 Armv9.4 onwards. This flag can take values from 0 to 2, aligning with 391 the ``ENABLE_FEAT`` mechanism. The default value is 0. 392 393 .. note:: 394 This feature currently traps access to all EL3 registers in 395 ``FGWTE3_EL3``, except for ``MDCR_EL3``, ``MPAM3_EL3``, 396 ``TPIDR_EL3``(when ``CRASH_REPORTING=1``), and 397 ``SCTLR_EL3``(when ``HW_ASSISTED_COHERENCY=0``). 398 If additional traps need to be disabled for specific platforms, 399 please contact the Arm team on `TF-A public mailing list`_. 400 401- ``ENABLE_FEAT_HCX``: Numeric value to set the bit SCR_EL3.HXEn in EL3 to 402 allow access to HCRX_EL2 (extended hypervisor control register) from EL2 as 403 well as adding HCRX_EL2 to the EL2 context save/restore operations. Its a 404 mandatory architectural feature and is enabled from v8.7 and upwards. This 405 flag can take the values 0 to 2, to align with the ``ENABLE_FEAT`` 406 mechanism. Default value is ``0``. 407 408- ``ENABLE_FEAT_IDTE3``: Numeric value to set SCR_EL3.TID3/TID5 bits which 409 enables trapping of ID register reads by lower ELs to EL3. This allows EL3 410 to control the feature visibility to lower ELs by returning a sanitized value 411 based on current feature enablement status. Hypervisors are expected to 412 cache ID register during their boot stage. This flag can take the 413 values 0 to 2, to align with the ``ENABLE_FEAT`` mechanism. 414 Default value is ``0``. This feature is EXPERIMENTAL. 415 416 .. note:: 417 This feature traps all lower EL accesses to Group 3 and Group 5 418 ID registers to EL3. This can incur a performance impact and platforms 419 should enable them only if they have a specific need. 420 421- ``ENABLE_FEAT_MOPS``: Numeric value to enable FEAT_MOPS (Standardization 422 of memory operations) when INIT_UNUSED_NS_EL2=1. 423 This feature is mandatory from v8.8 and enabling of FEAT_MOPS does not 424 require any settings from EL3 as the controls are present in EL2 registers 425 (HCRX_EL2.{MSCEn,MCE2} and SCTLR_EL2.MSCEn) and in most configurations 426 we expect EL2 to be present. But in case of INIT_UNUSED_NS_EL2=1 , 427 EL3 should configure the EL2 registers. This flag 428 can take values 0 to 2, to align with the ``ENABLE_FEAT`` mechanism. 429 Default value is ``0``. 430 431- ``ENABLE_FEAT_MTE2``: Numeric value to enable Memory Tagging Extension2 432 if the platform wants to use this feature and MTE2 is enabled at ELX. 433 This flag can take values 0 to 2, to align with the ``ENABLE_FEAT`` 434 mechanism. Default value is ``0``. 435 436- ``ENABLE_FEAT_PAN``: Numeric value to enable the ``FEAT_PAN`` (Privileged 437 Access Never) extension. ``FEAT_PAN`` adds a bit to PSTATE, generating a 438 permission fault for any privileged data access from EL1/EL2 to virtual 439 memory address, accessible at EL0, provided (HCR_EL2.E2H=1). It is a 440 mandatory architectural feature and is enabled from v8.1 and upwards. This 441 flag can take values 0 to 2, to align with the ``ENABLE_FEAT`` 442 mechanism. Default value is ``0``. 443 444- ``ENABLE_FEAT_PAUTH_LR``: Numeric value to enable the ``FEAT_PAUTH_LR`` 445 extension. ``FEAT_PAUTH_LR`` is an optional feature available from Arm v9.4 446 onwards. This feature requires PAUTH to be enabled via the 447 ``BRANCH_PROTECTION`` flag. This flag can take the values 0 to 2, to align 448 with the ``ENABLE_FEAT`` mechanism. Default value is ``0``. 449 450- ``ENABLE_FEAT_RNG``: Numeric value to enable the ``FEAT_RNG`` extension. 451 ``FEAT_RNG`` is an optional feature available on Arm v8.5 onwards. This 452 flag can take the values 0 to 2, to align with the ``ENABLE_FEAT`` 453 mechanism. Default value is ``0``. 454 455- ``ENABLE_FEAT_RNG_TRAP``: Numeric value to enable the ``FEAT_RNG_TRAP`` 456 extension. This feature is only supported in AArch64 state. This flag can 457 take values 0 to 2, to align with the ``ENABLE_FEAT`` mechanism. 458 Default value is ``0``. ``FEAT_RNG_TRAP`` is an optional feature from 459 Armv8.5 onwards. 460 461- ``ENABLE_FEAT_SB``: Numeric option to let the TF-A code use the ``FEAT_SB`` 462 (Speculation Barrier) instruction ``FEAT_SB`` is an optional feature and 463 defaults to ``0`` for pre-Armv8.5 CPUs, but is mandatory for Armv8.5 or 464 later CPUs. It is enabled from v8.5 and upwards and if needed can be 465 overidden from platforms explicitly. This flag can take values 0 to 2, to 466 align with the ``ENABLE_FEAT`` mechanism. Default value is ``0``. 467 468- ``ENABLE_FEAT_SEL2``: Numeric value to enable the ``FEAT_SEL2`` (Secure EL2) 469 extension. ``FEAT_SEL2`` is a mandatory feature available on Arm v8.4. 470 This flag can take values 0 to 2, to align with the ``ENABLE_FEAT`` 471 mechanism. Default is ``0``. 472 473- ``ENABLE_FEAT_TWED``: Numeric value to enable the ``FEAT_TWED`` (Delayed 474 trapping of WFE Instruction) extension. ``FEAT_TWED`` is a optional feature 475 available on Arm v8.6. This flag can take values 0 to 2, to align with the 476 ``ENABLE_FEAT`` mechanism. Default is ``0``. 477 478 When ``ENABLE_FEAT_TWED`` is set to ``1``, WFE instruction trapping gets 479 delayed by the amount of value in ``TWED_DELAY``. 480 481- ``ENABLE_FEAT_VHE``: Numeric value to enable the ``FEAT_VHE`` (Virtualization 482 Host Extensions) extension. It allows access to CONTEXTIDR_EL2 register 483 during EL2 context save/restore operations.``FEAT_VHE`` is a mandatory 484 architectural feature and is enabled from v8.1 and upwards. It can take 485 values 0 to 2, to align with the ``ENABLE_FEAT`` mechanism. 486 Default value is ``0``. 487 488- ``ENABLE_FEAT_TCR2``: Numeric value to set the bit SCR_EL3.ENTCR2 in EL3 to 489 allow access to TCR2_EL2 (extended translation control) from EL2 as 490 well as adding TCR2_EL2 to the EL2 context save/restore operations. Its a 491 mandatory architectural feature and is enabled from v8.9 and upwards. This 492 flag can take the values 0 to 2, to align with the ``ENABLE_FEAT`` 493 mechanism. Default value is ``0``. 494 495- ``ENABLE_FEAT_S2PIE``: Numeric value to enable support for FEAT_S2PIE 496 at EL2 and below, and context switch relevant registers. This flag 497 can take the values 0 to 2, to align with the ``ENABLE_FEAT`` 498 mechanism. Default value is ``0``. 499 500- ``ENABLE_FEAT_S1PIE``: Numeric value to enable support for FEAT_S1PIE 501 at EL2 and below, and context switch relevant registers. This flag 502 can take the values 0 to 2, to align with the ``ENABLE_FEAT`` 503 mechanism. Default value is ``0``. 504 505- ``ENABLE_FEAT_S2POE``: Numeric value to enable support for FEAT_S2POE 506 at EL2 and below, and context switch relevant registers. This flag 507 can take the values 0 to 2, to align with the ``ENABLE_FEAT`` 508 mechanism. Default value is ``0``. 509 510- ``ENABLE_FEAT_S1POE``: Numeric value to enable support for FEAT_S1POE 511 at EL2 and below, and context switch relevant registers. This flag 512 can take the values 0 to 2, to align with the ``ENABLE_FEAT`` 513 mechanism. Default value is ``0``. 514 515- ``ENABLE_FEAT_GCS``: Numeric value to set the bit SCR_EL3.GCSEn in EL3 to 516 allow use of Guarded Control Stack from EL2 as well as adding the GCS 517 registers to the EL2 context save/restore operations. This flag can take 518 the values 0 to 2, to align with the ``ENABLE_FEAT`` mechanism. 519 Default value is ``0``. 520 521 - ``ENABLE_FEAT_GCIE``: Boolean value to enable support for the GICv5 CPU 522 interface (see ``USE_GIC_DRIVER`` for the IRI). GICv5 and GICv3 are mutually 523 exclusive, so the ``ENABLE_FEAT`` mechanism is currently not supported. 524 Default value is ``0``. 525 526- ``ENABLE_FEAT_THE``: Numeric value to enable support for FEAT_THE 527 (Translation Hardening Extension) at EL2 and below, setting the bit 528 SCR_EL3.RCWMASKEn in EL3 to allow access to RCWMASK_EL1 and RCWSMASK_EL1 529 registers and context switch them. 530 Its an optional architectural feature and is available from v8.8 and upwards. 531 This flag can take the values 0 to 2, to align with the ``ENABLE_FEAT`` 532 mechanism. Default value is ``0``. 533 534- ``ENABLE_FEAT_SCTLR2``: Numeric value to enable support for FEAT_SCTLR2 535 (Extension to SCTLR_ELx) at EL2 and below, setting the bit 536 SCR_EL3.SCTLR2En in EL3 to allow access to SCTLR2_ELx registers and 537 context switch them. This feature is OPTIONAL from Armv8.0 implementations 538 and mandatory in Armv8.9 implementations. 539 This flag can take the values 0 to 2, to align with the ``ENABLE_FEAT`` 540 mechanism. Default value is ``0``. 541 542- ``ENABLE_FEAT_D128``: Numeric value to enable support for FEAT_D128 543 at EL2 and below, setting the bit SCT_EL3.D128En in EL3 to allow access to 544 128 bit version of system registers like PAR_EL1, TTBR0_EL1, TTBR1_EL1, 545 TTBR0_EL2, TTBR1_EL2, TTBR0_EL12, TTBR1_EL12 , VTTBR_EL2, RCWMASK_EL1, and 546 RCWSMASK_EL1. Its an optional architectural feature and is available from 547 9.3 and upwards. 548 This flag can take the values 0 to 2, to align with the ``ENABLE_FEAT`` 549 mechanism. Default value is ``0``. 550 551- ``ENABLE_FEAT_UINJ``: Numerical value to enable FEAT_UINJ support which 552 is hardware based injection of undefined instruction exceptions. 553 The objective of this feature is to provide higher privilege software with a 554 future proofed mechanism to inject an Undefined Instruction exception into 555 lower privilege software. It is an optional architectural feature from v9.0 556 and mandatory from v9.6. This flag can take value of 0 to 2, 557 to align with the ``FEATURE_DETECTION`` mechanism. Default value is ``0``. 558 559- ``ENABLE_LTO``: Boolean option to enable Link Time Optimization (LTO) 560 support. This option is currently only supported for AArch64. On GCC it only 561 applies to TF-A proper, and not its libraries. If LTO on libraries (except 562 the libc) is desired a platform can pass `-flto -ffat-lto-objects` as long as 563 GCC >= 14 is in use. ``ENABLE_LTO`` is enabled by default on release builds. 564 Default is 0. 565 566- ``ENABLE_FEAT_MPAM``: Numeric value to enable lower ELs to use MPAM 567 feature. MPAM is an optional Armv8.4 extension that enables various memory 568 system components and resources to define partitions; software running at 569 various ELs can assign themselves to desired partition to control their 570 performance aspects. 571 572 This flag can take values 0 to 2, to align with the ``ENABLE_FEAT`` 573 mechanism. When this option is set to ``1`` or ``2``, EL3 allows lower ELs to 574 access their own MPAM registers without trapping into EL3. This option 575 doesn't make use of partitioning in EL3, however. Platform initialisation 576 code should configure and use partitions in EL3 as required. This option 577 defaults to ``2`` since MPAM is enabled by default for NS world only. 578 The flag is automatically disabled when the target 579 architecture is AArch32. 580 581- ``ENABLE_FEAT_MPAM_PE_BW_CTRL``: This option enables Armv9.3 MPAM 582 PE-side bandwidth controls and disables traps to EL3/EL2 (when 583 ``INIT_UNUSED_NS_EL2`` = 1). The flag accepts values from 0 to 2, in 584 line with the ``ENABLE_FEAT`` mechanism, and defaults to ``0``. 585 586- ``ENABLE_FEAT_LS64_ACCDATA``: Numeric value to enable access and save and 587 restore the ACCDATA_EL1 system register, at EL2 and below. This flag can 588 take the values 0 to 2, to align with the ``ENABLE_FEAT`` mechanism. 589 Default value is ``0``. 590 591- ``ENABLE_FEAT_AIE``: Numeric value to enable access to the (A)MAIR2 system 592 registers from non-secure world. This flag can take the values 0 to 2, to 593 align with the ``ENABLE_FEAT`` mechanism. 594 Default value is ``0``. 595 596- ``ENABLE_FEAT_PFAR``: Numeric value to enable access to the PFAR system 597 registers from non-secure world. This flag can take the values 0 to 2, to 598 align with the ``ENABLE_FEAT`` mechanism. 599 Default value is ``0``. 600 601- ``ENABLE_MPMM``: Boolean option to enable support for the Maximum Power 602 Mitigation Mechanism supported by certain Arm cores, which allows the SoC 603 firmware to detect and limit high activity events to assist in SoC processor 604 power domain dynamic power budgeting and limit the triggering of whole-rail 605 (i.e. clock chopping) responses to overcurrent conditions. Defaults to ``0``. 606 607- ``ENABLE_PIE``: Boolean option to enable Position Independent Executable(PIE) 608 support within generic code in TF-A. This option is currently only supported 609 in BL2, BL31, and BL32 (TSP) for AARCH64 binaries, and 610 in BL32 (SP_min) for AARCH32. Default is 0. 611 612- ``ENABLE_PMF``: Boolean option to enable support for optional Performance 613 Measurement Framework(PMF). Default is 0. 614 615- ``ENABLE_PSCI_STAT``: Boolean option to enable support for optional PSCI 616 functions ``PSCI_STAT_RESIDENCY`` and ``PSCI_STAT_COUNT``. Default is 0. 617 In the absence of an alternate stat collection backend, ``ENABLE_PMF`` must 618 be enabled. If ``ENABLE_PMF`` is set, the residency statistics are tracked in 619 software. 620 621- ``ENABLE_RUNTIME_INSTRUMENTATION``: Boolean option to enable runtime 622 instrumentation which injects timestamp collection points into TF-A to 623 allow runtime performance to be measured. Currently, only PSCI is 624 instrumented. Enabling this option enables the ``ENABLE_PMF`` build option 625 as well. Default is 0. 626 627- ``ENABLE_SPE_FOR_NS`` : Numeric value to enable Statistical Profiling 628 extensions. This is an optional architectural feature for AArch64. 629 This flag can take the values 0 to 2, to align with the ``ENABLE_FEAT`` 630 mechanism. The default is 2 but is automatically disabled when the target 631 architecture is AArch32. 632 633- ``ENABLE_SVE_FOR_NS``: Numeric value to enable Scalable Vector Extension 634 (SVE) for the Non-secure world only. SVE is an optional architectural feature 635 for AArch64. This flag can take the values 0 to 2, to align with the 636 ``ENABLE_FEAT`` mechanism. At this time, this build option cannot be used on 637 systems that have SPM_MM enabled. The default value is 2. 638 639 Note that when SVE is enabled for the Non-secure world, access 640 to SVE, SIMD and floating-point functionality from the Secure world is 641 independently controlled by build option ``ENABLE_SVE_FOR_SWD``. When enabling 642 ``CTX_INCLUDE_FPREGS`` and ``ENABLE_SVE_FOR_NS`` together, it is mandatory to 643 enable ``CTX_INCLUDE_SVE_REGS``. This is to avoid corruption of the Non-secure 644 world data in the Z-registers which are aliased by the SIMD and FP registers. 645 646- ``ENABLE_SVE_FOR_SWD``: Boolean option to enable SVE and FPU/SIMD functionality 647 for the Secure world. SVE is an optional architectural feature for AArch64. 648 The default is 0 and it is automatically disabled when the target architecture 649 is AArch32. 650 651 .. note:: 652 This build flag requires ``ENABLE_SVE_FOR_NS`` to be enabled. When enabling 653 ``ENABLE_SVE_FOR_SWD``, a developer must carefully consider whether 654 ``CTX_INCLUDE_SVE_REGS`` is also needed. 655 656- ``ENABLE_STACK_PROTECTOR``: String option to enable the stack protection 657 checks in GCC. Allowed values are "all", "strong", "default" and "none". The 658 default value is set to "none". "strong" is the recommended stack protection 659 level if this feature is desired. "none" disables the stack protection. For 660 all values other than "none", the ``plat_get_stack_protector_canary()`` 661 platform hook needs to be implemented. The value is passed as the last 662 component of the option ``-fstack-protector-$ENABLE_STACK_PROTECTOR``. 663 664- ``ENABLE_ERRATA_ALL``: This option is used only for testing purposes, Boolean 665 option to enable the workarounds for all errata that TF-A implements. Normally 666 they should be explicitly enabled depending on each platform's needs. Not 667 recommended for release builds. This option is default set to 0. 668 669- ``ENABLE_FEAT_MORELLO`` : Numeric option to enable the Morello capability aware 670 firmware. This flag can take the values 0 to 2, to align with the 671 ``ENABLE_FEAT`` mechanism. This option is experimental and supported only with 672 LLVM CLANG toolchain and not with GCC toolchain. Capability awareness is 673 currently enabled only in BL31 firmware and not in other firmware types of 674 trusted firmware. Enabling this on regular AARCH64 system might not work. 675 676- ``ENCRYPT_BL31``: Binary flag to enable encryption of BL31 firmware. This 677 flag depends on ``DECRYPTION_SUPPORT`` build flag. 678 679- ``ENCRYPT_BL32``: Binary flag to enable encryption of Secure BL32 payload. 680 This flag depends on ``DECRYPTION_SUPPORT`` build flag. 681 682- ``ENC_KEY``: A 32-byte (256-bit) symmetric key in hex string format. It could 683 either be SSK or BSSK depending on ``FW_ENC_STATUS`` flag. This value depends 684 on ``DECRYPTION_SUPPORT`` build flag. 685 686- ``ENC_NONCE``: A 12-byte (96-bit) encryption nonce or Initialization Vector 687 (IV) in hex string format. This value depends on ``DECRYPTION_SUPPORT`` 688 build flag. 689 690- ``ERROR_DEPRECATED``: This option decides whether to treat the usage of 691 deprecated platform APIs, helper functions or drivers within Trusted 692 Firmware as error. It can take the value 1 (flag the use of deprecated 693 APIs as error) or 0. The default is 0. 694 695- ``ETHOSN_NPU_DRIVER``: boolean option to enable a SiP service that can 696 configure an Arm® Ethos™-N NPU. To use this service the target platform's 697 ``HW_CONFIG`` must include the device tree nodes for the NPU. Currently, only 698 the Arm Juno platform has this included in its ``HW_CONFIG`` and the platform 699 only loads the ``HW_CONFIG`` in AArch64 builds. Default is 0. 700 701- ``ETHOSN_NPU_TZMP1``: boolean option to enable TZMP1 support for the 702 Arm® Ethos™-N NPU. Requires ``ETHOSN_NPU_DRIVER`` and 703 ``TRUSTED_BOARD_BOOT`` to be enabled. 704 705- ``ETHOSN_NPU_FW``: location of the NPU firmware binary 706 (```ethosn.bin```). This firmware image will be included in the FIP and 707 loaded at runtime. 708 709- ``EL3_EXCEPTION_HANDLING``: When set to ``1``, enable handling of exceptions 710 targeted at EL3. When set ``0`` (default), no exceptions are expected or 711 handled at EL3, and a panic will result. The exception to this rule is when 712 ``SPMD_SPM_AT_SEL2`` is set to ``1``, in which case, only exceptions 713 occuring during normal world execution, are trapped to EL3. Any exception 714 trapped during secure world execution are trapped to the SPMC. This is 715 supported only for AArch64 builds. 716 717- ``FAULT_INJECTION_SUPPORT``: ARMv8.4 extensions introduced support for fault 718 injection from lower ELs, and this build option enables lower ELs to use 719 Error Records accessed via System Registers to inject faults. This is 720 applicable only to AArch64 builds. 721 722 This feature is intended for testing purposes only, and is advisable to keep 723 disabled for production images. 724 725- ``FIP_NAME``: This is an optional build option which specifies the FIP 726 filename for the ``fip`` target. Default is ``fip.bin``. 727 728- ``FWU_FIP_NAME``: This is an optional build option which specifies the FWU 729 FIP filename for the ``fwu_fip`` target. Default is ``fwu_fip.bin``. 730 731- ``FW_ENC_STATUS``: Top level firmware's encryption numeric flag, values: 732 733 :: 734 735 0: Encryption is done with Secret Symmetric Key (SSK) which is common 736 for a class of devices. 737 1: Encryption is done with Binding Secret Symmetric Key (BSSK) which is 738 unique per device. 739 740 This flag depends on ``DECRYPTION_SUPPORT`` build flag. 741 742- ``GENERATE_COT``: Boolean flag used to build and execute the ``cert_create`` 743 tool to create certificates as per the Chain of Trust described in 744 :ref:`Trusted Board Boot`. The build system then calls ``fiptool`` to 745 include the certificates in the FIP and FWU_FIP. Default value is '0'. 746 747 Specify both ``TRUSTED_BOARD_BOOT=1`` and ``GENERATE_COT=1`` to include support 748 for the Trusted Board Boot feature in the BL1 and BL2 images, to generate 749 the corresponding certificates, and to include those certificates in the 750 FIP and FWU_FIP. 751 752 Note that if ``TRUSTED_BOARD_BOOT=0`` and ``GENERATE_COT=1``, the BL1 and BL2 753 images will not include support for Trusted Board Boot. The FIP will still 754 include the corresponding certificates. This FIP can be used to verify the 755 Chain of Trust on the host machine through other mechanisms. 756 757 Note that if ``TRUSTED_BOARD_BOOT=1`` and ``GENERATE_COT=0``, the BL1 and BL2 758 images will include support for Trusted Board Boot, but the FIP and FWU_FIP 759 will not include the corresponding certificates, causing a boot failure. 760 761- ``GICV2_G0_FOR_EL3``: Unlike GICv3, the GICv2 architecture doesn't have 762 inherent support for specific EL3 type interrupts. Setting this build option 763 to ``1`` assumes GICv2 *Group 0* interrupts are expected to target EL3, both 764 by :ref:`platform abstraction layer<platform Interrupt Controller API>` and 765 :ref:`Interrupt Management Framework<Interrupt Management Framework>`. 766 This allows GICv2 platforms to enable features requiring EL3 interrupt type. 767 This also means that all GICv2 Group 0 interrupts are delivered to EL3, and 768 the Secure Payload interrupts needs to be synchronously handed over to Secure 769 EL1 for handling. The default value of this option is ``0``, which means the 770 Group 0 interrupts are assumed to be handled by Secure EL1. 771 772- ``HANDLE_EA_EL3_FIRST_NS``: When set to ``1``, External Aborts and SError 773 Interrupts, resulting from errors in NS world, will be always trapped in 774 EL3 i.e. in BL31 at runtime. When set to ``0`` (default), these exceptions 775 will be trapped in the current exception level (or in EL1 if the current 776 exception level is EL0). 777 778- ``HW_ASSISTED_COHERENCY``: On most Arm systems to-date, platform-specific 779 software operations are required for CPUs to enter and exit coherency. 780 However, newer systems exist where CPUs' entry to and exit from coherency 781 is managed in hardware. Such systems require software to only initiate these 782 operations, and the rest is managed in hardware, minimizing active software 783 management. In such systems, this boolean option enables TF-A to carry out 784 build and run-time optimizations during boot and power management operations. 785 This option defaults to 0 and if it is enabled, then it implies 786 ``WARMBOOT_ENABLE_DCACHE_EARLY`` is also enabled. 787 788 If this flag is disabled while the platform which TF-A is compiled for 789 includes cores that manage coherency in hardware, then a compilation error is 790 generated. This is based on the fact that a system cannot have, at the same 791 time, cores that manage coherency in hardware and cores that don't. In other 792 words, a platform cannot have, at the same time, cores that require 793 ``HW_ASSISTED_COHERENCY=1`` and cores that require 794 ``HW_ASSISTED_COHERENCY=0``. 795 796 Note that, when ``HW_ASSISTED_COHERENCY`` is enabled, version 2 of 797 translation library (xlat tables v2) must be used; version 1 of translation 798 library is not supported. 799 800- ``IMPDEF_SYSREG_TRAP``: Numeric value to enable the handling traps for 801 implementation defined system register accesses from lower ELs. Default 802 value is ``0``. 803 804- ``INVERTED_MEMMAP``: memmap tool print by default lower addresses at the 805 bottom, higher addresses at the top. This build flag can be set to '1' to 806 invert this behavior. Lower addresses will be printed at the top and higher 807 addresses at the bottom. 808 809- ``INIT_UNUSED_NS_EL2``: This build flag guards code that disables EL2 810 safely in scenario where NS-EL2 is present but unused. This flag is set to 0 811 by default. Platforms without NS-EL2 in use must enable this flag. 812 813- ``KEY_ALG``: This build flag enables the user to select the algorithm to be 814 used for generating the PKCS keys and subsequent signing of the certificate. 815 It accepts 5 values: ``rsa``, ``rsa_1_5``, ``ecdsa``, ``ecdsa-brainpool-regular`` 816 and ``ecdsa-brainpool-twisted``. The option ``rsa_1_5`` is the legacy PKCS#1 817 RSA 1.5 algorithm which is not TBBR compliant and is retained only for 818 compatibility. The default value of this flag is ``rsa`` which is the TBBR 819 compliant PKCS#1 RSA 2.1 scheme. 820 821- ``KEY_SIZE``: This build flag enables the user to select the key size for 822 the algorithm specified by ``KEY_ALG``. The valid values for ``KEY_SIZE`` 823 depend on the chosen algorithm and the cryptographic module. 824 825 +---------------------------+------------------------------------+ 826 | KEY_ALG | Possible key sizes | 827 +===========================+====================================+ 828 | rsa | 1024 , 2048 (default), 3072, 4096 | 829 +---------------------------+------------------------------------+ 830 | ecdsa | 256 (default), 384 | 831 +---------------------------+------------------------------------+ 832 | ecdsa-brainpool-regular | 256 (default) | 833 +---------------------------+------------------------------------+ 834 | ecdsa-brainpool-twisted | 256 (default) | 835 +---------------------------+------------------------------------+ 836 837- ``HASH_ALG``: This build flag enables the user to select the secure hash 838 algorithm. It accepts 3 values: ``sha256``, ``sha384`` and ``sha512``. 839 The default value of this flag is ``sha256``. 840 841- ``HW_CONFIG_BASE``: This option specifies the location in memory where the DTB 842 should either be loaded by BL2 or can be found by later stages. 843 844- ``LDFLAGS``: Extra user options appended to the linkers' command line in 845 addition to the one set by the build system. 846 847- ``LOG_LEVEL``: Chooses the log level, which controls the amount of console log 848 output compiled into the build. This should be one of the following: 849 850 :: 851 852 0 (LOG_LEVEL_NONE) 853 10 (LOG_LEVEL_ERROR) 854 20 (LOG_LEVEL_NOTICE) 855 30 (LOG_LEVEL_WARNING) 856 40 (LOG_LEVEL_INFO) 857 50 (LOG_LEVEL_VERBOSE) 858 859 All log output up to and including the selected log level is compiled into 860 the build. The default value is 40 in debug builds and 20 in release builds. 861 862 ``LOG_DEBUG``: Boolean option to enable support for module level internal 863 logs. There can be situation where a module has detail internal debugging 864 logs, these debugging logs may not be required to print even when log level 865 is VERBOSE. Such logs can be put under this flag. This is a file 866 level build flag. By default this should be disabled (``0``) in each file. 867 868- ``MEASURED_BOOT``: Boolean flag to include support for the Measured Boot 869 feature. This flag can be enabled with ``TRUSTED_BOARD_BOOT`` in order to 870 provide trust that the code taking the measurements and recording them has 871 not been tampered with. 872 873 This option defaults to 0. 874 875- ``DISCRETE_TPM``: Boolean flag to include support for a Discrete TPM. 876 877 This option defaults to 0. 878 879- ``TPM_INTERFACE``: When ``DISCRETE_TPM=1``, this is a required flag to 880 select the TPM interface. Currently only one interface is supported: 881 882 :: 883 884 FIFO_SPI 885 886- ``MBOOT_TPM_HASH_ALG``: Build flag to select the TPM hash algorithm used during 887 Measured Boot. Currently only accepts ``sha256`` as a valid algorithm. 888 889- ``MARCH_DIRECTIVE``: used to pass a -march option from the platform build 890 options to the compiler. An example usage: 891 892 .. code:: make 893 894 MARCH_DIRECTIVE := -march=armv8.5-a 895 896- ``HARDEN_SLS``: used to pass -mharden-sls=all from the TF-A build 897 options to the compiler currently supporting only of the options. 898 GCC documentation: 899 https://gcc.gnu.org/onlinedocs/gcc/AArch64-Options.html#index-mharden-sls 900 901 An example usage: 902 903 .. code:: make 904 905 HARDEN_SLS := 1 906 907 This option defaults to 0. 908 909- ``NON_TRUSTED_WORLD_KEY``: This option is used when ``GENERATE_COT=1``. It 910 specifies a file that contains the Non-Trusted World private key in PEM 911 format or a PKCS11 URI. If ``SAVE_KEYS=1``, only a file is accepted and it 912 will be used to save the key. 913 914- ``NS_BL2U``: Path to NS_BL2U image in the host file system. This image is 915 optional. It is only needed if the platform makefile specifies that it 916 is required in order to build the ``fwu_fip`` target. 917 918- ``NS_TIMER_SWITCH``: (deprecated) Enable save and restore for non-secure 919 timer register contents upon world switch. It can take either 0 (don't save 920 and restore) or 1 (do save and restore). 0 is the default. An SPD may set 921 this to 1 if it wants the timer registers to be saved and restored. This 922 option has been deprecated since it breaks Linux preemption model. 923 924- ``OVERRIDE_LIBC``: This option allows platforms to override the default libc 925 for the BL image. It can be either 0 (include) or 1 (remove). The default 926 value is 0. 927 928- ``PL011_GENERIC_UART``: Boolean option to indicate the PL011 driver that 929 the underlying hardware is not a full PL011 UART but a minimally compliant 930 generic UART, which is a subset of the PL011. The driver will not access 931 any register that is not part of the SBSA generic UART specification. 932 Default value is 0 (a full PL011 compliant UART is present). 933 934- ``PLAT``: Choose a platform to build TF-A for. The chosen platform name 935 must be subdirectory of any depth under ``plat/``, and must contain a 936 platform makefile named ``platform.mk``. For example, to build TF-A for the 937 Arm Juno board, select PLAT=juno. 938 939- ``PLATFORM_REPORT_CTX_MEM_USE``: Reports the context memory allocated for 940 each core as well as the global context. The data includes the memory used 941 by each world and each privileged exception level. This build option is 942 applicable only for ``ARCH=aarch64`` builds. The default value is 0. 943 944- ``PLAT_EXTRA_LD_SCRIPT``: Allows the platform to include a custom LD script 945 snippet for any custom sections that cannot be expressed otherwise. Defaults 946 to 0. 947 948- ``PRELOADED_BL33_BASE``: This option enables booting a preloaded BL33 image 949 instead of the normal boot flow. When defined, it must specify the entry 950 point address for the preloaded BL33 image. This option is incompatible with 951 ``EL3_PAYLOAD_BASE``. If both are defined, ``EL3_PAYLOAD_BASE`` has priority 952 over ``PRELOADED_BL33_BASE``. 953 954- ``PRESERVE_DSU_PMU_REGS``: This options when enabled allows the platform to 955 save/restore the DynamIQ Shared Unit's(DSU) Performance Monitoring Unit(PMU) 956 registers when the cluster goes through a power cycle. This is disabled by 957 default and platforms that require this feature have to enable them. 958 959- ``PROGRAMMABLE_RESET_ADDRESS``: This option indicates whether the reset 960 vector address can be programmed or is fixed on the platform. It can take 961 either 0 (fixed) or 1 (programmable). Default is 0. If the platform has a 962 programmable reset address, it is expected that a CPU will start executing 963 code directly at the right address, both on a cold and warm reset. In this 964 case, there is no need to identify the entrypoint on boot and the boot path 965 can be optimised. The ``plat_get_my_entrypoint()`` platform porting interface 966 does not need to be implemented in this case. 967 968- ``PSCI_EXTENDED_STATE_ID``: As per PSCI1.0 Specification, there are 2 formats 969 possible for the PSCI power-state parameter: original and extended State-ID 970 formats. This flag if set to 1, configures the generic PSCI layer to use the 971 extended format. The default value of this flag is 0, which means by default 972 the original power-state format is used by the PSCI implementation. This flag 973 should be specified by the platform makefile and it governs the return value 974 of PSCI_FEATURES API for CPU_SUSPEND smc function id. When this option is 975 enabled on Arm platforms, the option ``ARM_RECOM_STATE_ID_ENC`` needs to be 976 set to 1 as well. 977 978- ``PSCI_OS_INIT_MODE``: Boolean flag to enable support for optional PSCI 979 OS-initiated mode. This option defaults to 0. 980 981- ``ARCH_FEATURE_AVAILABILITY``: Boolean flag to enable support for the 982 optional SMCCC_ARCH_FEATURE_AVAILABILITY call. This option implicitly 983 interacts with IMPDEF_SYSREG_TRAP and software emulation. This option 984 defaults to 0. 985 986- ``ENABLE_FEAT_RAS``: Numeric flag to enable Armv8.2 RAS features. RAS 987 features are an optional extension for pre-Armv8.2 CPUs, but are mandatory 988 for Armv8.2 or later CPUs. NOTE: This flag enables use of IESB capability to 989 reduce entry latency into EL3 even when RAS error handling is not performed 990 on the platform. Hence this flag is recommended to be turned on Armv8.2 and 991 later CPUs. This flag can take the values 0 to 2, to align with the 992 ``ENABLE_FEAT`` mechanism. The default is 0. 993 994- ``RESET_TO_BL31``: Enable BL31 entrypoint as the CPU reset vector instead 995 of the BL1 entrypoint. It can take the value 0 (CPU reset to BL1 996 entrypoint) or 1 (CPU reset to BL31 entrypoint). 997 The default value is 0. 998 999- ``RESET_TO_SP_MIN``: SP_MIN is the minimal AArch32 Secure Payload provided 1000 in TF-A. This flag configures SP_MIN entrypoint as the CPU reset vector 1001 instead of the BL1 entrypoint. It can take the value 0 (CPU reset to BL1 1002 entrypoint) or 1 (CPU reset to SP_MIN entrypoint). The default value is 0. 1003 1004- ``RME_GPT_BITLOCK_BLOCK``: This defines the block size (in number of 512MB 1005- blocks) covered by a single bit of the bitlock structure during RME GPT 1006- operations. The lower the block size, the better opportunity for 1007- parallelising GPT operations but at the cost of more bits being needed 1008- for the bitlock structure. This numeric parameter can take the values 1009- from 0 to 512 and must be a power of 2. The value of 0 is special and 1010- and it chooses a single spinlock for all GPT L1 table entries. Default 1011- value is 1 which corresponds to block size of 512MB per bit of bitlock 1012- structure. 1013 1014- ``RME_GPT_MAX_BLOCK``: Numeric value in MB to define the maximum size of 1015 supported contiguous blocks in GPT Library. This parameter can take the 1016 values 0, 2, 32 and 512. Setting this value to 0 disables use of Contigious 1017 descriptors. Default value is 512. 1018 1019- ``ROT_KEY``: This option is used when ``GENERATE_COT=1``. It specifies a 1020 file that contains the ROT private key in PEM format or a PKCS11 URI and 1021 enforces public key hash generation. If ``SAVE_KEYS=1``, only a file is 1022 accepted and it will be used to save the key. 1023 1024- ``SAVE_KEYS``: This option is used when ``GENERATE_COT=1``. It tells the 1025 certificate generation tool to save the keys used to establish the Chain of 1026 Trust. Allowed options are '0' or '1'. Default is '0' (do not save). 1027 1028- ``SCP_BL2``: Path to SCP_BL2 image in the host file system. This image is optional. 1029 If a SCP_BL2 image is present then this option must be passed for the ``fip`` 1030 target. 1031 1032- ``SCP_BL2_KEY``: This option is used when ``GENERATE_COT=1``. It specifies a 1033 file that contains the SCP_BL2 private key in PEM format or a PKCS11 URI. 1034 If ``SAVE_KEYS=1``, only a file is accepted and it will be used to save the key. 1035 1036- ``SCP_BL2U``: Path to SCP_BL2U image in the host file system. This image is 1037 optional. It is only needed if the platform makefile specifies that it 1038 is required in order to build the ``fwu_fip`` target. 1039 1040- ``SDEI_SUPPORT``: Setting this to ``1`` enables support for Software 1041 Delegated Exception Interface to BL31 image. This defaults to ``0``. 1042 1043 When set to ``1``, the build option ``EL3_EXCEPTION_HANDLING`` must also be 1044 set to ``1``. 1045 1046- ``SEPARATE_CODE_AND_RODATA``: Whether code and read-only data should be 1047 isolated on separate memory pages. This is a trade-off between security and 1048 memory usage. See "Isolating code and read-only data on separate memory 1049 pages" section in :ref:`Firmware Design`. This flag is disabled by default 1050 and affects all BL images. 1051 1052- ``SEPARATE_NOBITS_REGION``: Setting this option to ``1`` allows the NOBITS 1053 sections of BL31 (.bss, stacks, page tables, and coherent memory) to be 1054 allocated in RAM discontiguous from the loaded firmware image. When set, the 1055 platform is expected to provide definitions for ``BL31_NOBITS_BASE`` and 1056 ``BL31_NOBITS_LIMIT``. When the option is ``0`` (the default), NOBITS 1057 sections are placed in RAM immediately following the loaded firmware image. 1058 1059- ``SEPARATE_BL2_NOLOAD_REGION``: Setting this option to ``1`` allows the 1060 NOLOAD sections of BL2 (.bss, stacks, page tables) to be allocated in RAM 1061 discontiguous from loaded firmware images. When set, the platform need to 1062 provide definitions of ``BL2_NOLOAD_START`` and ``BL2_NOLOAD_LIMIT``. This 1063 flag is disabled by default and NOLOAD sections are placed in RAM immediately 1064 following the loaded firmware image. 1065 1066- ``SEPARATE_BL2_FIP``: This option enables the separation of the BL2 FIP image 1067 from the main FIP image. When this option is enabled, the BL2 FIP image is built 1068 as a separate FIP image. The default value is 0. 1069 1070- ``SEPARATE_SIMD_SECTION``: Setting this option to ``1`` allows the SIMD context 1071 data structures to be put in a dedicated memory region as decided by platform 1072 integrator. Default value is ``0`` which means the SIMD context is put in BSS 1073 section of EL3 firmware. 1074 1075- ``SMC_PCI_SUPPORT``: This option allows platforms to handle PCI configuration 1076 access requests via a standard SMCCC defined in `DEN0115`_. When combined with 1077 UEFI+ACPI this can provide a certain amount of OS forward compatibility 1078 with newer platforms that aren't ECAM compliant. 1079 1080- ``SPD``: Choose a Secure Payload Dispatcher component to be built into TF-A. 1081 This build option is only valid if ``ARCH=aarch64``. The value should be 1082 the path to the directory containing the SPD source, relative to 1083 ``services/spd/``; the directory is expected to contain a makefile called 1084 ``<spd-value>.mk``. The SPM Dispatcher standard service is located in 1085 services/std_svc/spmd and enabled by ``SPD=spmd``. The SPM Dispatcher 1086 cannot be enabled when the ``SPM_MM`` option is enabled. 1087 1088- ``SPIN_ON_BL1_EXIT``: This option introduces an infinite loop in BL1. It can 1089 take either 0 (no loop) or 1 (add a loop). 0 is the default. This loop stops 1090 execution in BL1 just before handing over to BL31. At this point, all 1091 firmware images have been loaded in memory, and the MMU and caches are 1092 turned off. Refer to the "Debugging options" section for more details. 1093 1094- ``SPMC_AT_EL3`` : This boolean option is used jointly with the SPM 1095 Dispatcher option (``SPD=spmd``). When enabled (1) it indicates the SPMC 1096 component runs at the EL3 exception level. The default value is ``0`` ( 1097 disabled). This configuration supports pre-Armv8.4 platforms (aka not 1098 implementing the ``FEAT_SEL2`` extension). 1099 1100- ``SPMC_AT_EL3_SEL0_SP`` : Boolean option to enable SEL0 SP load support when 1101 ``SPMC_AT_EL3`` is enabled. The default value if ``0`` (disabled). This 1102 option cannot be enabled (``1``) when (``SPMC_AT_EL3``) is disabled. 1103 1104- ``SPMC_OPTEE`` : This boolean option is used jointly with the SPM 1105 Dispatcher option (``SPD=spmd``) and with ``SPMD_SPM_AT_SEL2=0`` to 1106 indicate that the SPMC at S-EL1 is OP-TEE and an OP-TEE specific loading 1107 mechanism should be used. 1108 1109- ``SPMD_SPM_AT_SEL2`` : This boolean option is used jointly with the SPM 1110 Dispatcher option (``SPD=spmd``). When enabled (1) it indicates the SPMC 1111 component runs at the S-EL2 exception level provided by the ``FEAT_SEL2`` 1112 extension. This is the default when enabling the SPM Dispatcher. When 1113 disabled (0) it indicates the SPMC component runs at the S-EL1 execution 1114 state or at EL3 if ``SPMC_AT_EL3`` is enabled. The latter configurations 1115 support pre-Armv8.4 platforms (aka not implementing the ``FEAT_SEL2`` 1116 extension). 1117 1118- ``SPM_MM`` : Boolean option to enable the Management Mode (MM)-based Secure 1119 Partition Manager (SPM) implementation. The default value is ``0`` 1120 (disabled). This option cannot be enabled (``1``) when SPM Dispatcher is 1121 enabled (``SPD=spmd``). 1122 1123- ``SP_LAYOUT_FILE``: Platform provided path to JSON file containing the 1124 description of secure partitions. The build system will parse this file and 1125 package all secure partition blobs into the FIP. This file is not 1126 necessarily part of TF-A tree. Only available when ``SPD=spmd``. 1127 1128- ``SP_MIN_WITH_SECURE_FIQ``: Boolean flag to indicate the SP_MIN handles 1129 secure interrupts (caught through the FIQ line). Platforms can enable 1130 this directive if they need to handle such interruption. When enabled, 1131 the FIQ are handled in monitor mode and non secure world is not allowed 1132 to mask these events. Platforms that enable FIQ handling in SP_MIN shall 1133 implement the api ``sp_min_plat_fiq_handler()``. The default value is 0. 1134 1135- ``SVE_VECTOR_LEN``: SVE vector length to configure in ZCR_EL3. 1136 Platforms can configure this if they need to lower the hardware 1137 limit, for example due to asymmetric configuration or limitations of 1138 software run at lower ELs. The default is the architectural maximum 1139 of 2048 which should be suitable for most configurations, the 1140 hardware will limit the effective VL to the maximum physically supported 1141 VL. 1142 1143- ``TRNG_SUPPORT``: Setting this to ``1`` enables support for True 1144 Random Number Generator Interface to BL31 image. This defaults to ``0``. 1145 1146- ``TRUSTED_BOARD_BOOT``: Boolean flag to include support for the Trusted Board 1147 Boot feature. When set to '1', BL1 and BL2 images include support to load 1148 and verify the certificates and images in a FIP, and BL1 includes support 1149 for the Firmware Update. The default value is '0'. Generation and inclusion 1150 of certificates in the FIP and FWU_FIP depends upon the value of the 1151 ``GENERATE_COT`` option. 1152 1153 .. warning:: 1154 This option depends on ``CREATE_KEYS`` to be enabled. If the keys 1155 already exist in disk, they will be overwritten without further notice. 1156 1157- ``TRUSTED_WORLD_KEY``: This option is used when ``GENERATE_COT=1``. It 1158 specifies a file that contains the Trusted World private key in PEM 1159 format or a PKCS11 URI. If ``SAVE_KEYS=1``, only a file is accepted and 1160 it will be used to save the key. 1161 1162- ``TSP_INIT_ASYNC``: Choose BL32 initialization method as asynchronous or 1163 synchronous, (see "Initializing a BL32 Image" section in 1164 :ref:`Firmware Design`). It can take the value 0 (BL32 is initialized using 1165 synchronous method) or 1 (BL32 is initialized using asynchronous method). 1166 Default is 0. 1167 1168- ``TSP_NS_INTR_ASYNC_PREEMPT``: A non zero value enables the interrupt 1169 routing model which routes non-secure interrupts asynchronously from TSP 1170 to EL3 causing immediate preemption of TSP. The EL3 is responsible 1171 for saving and restoring the TSP context in this routing model. The 1172 default routing model (when the value is 0) is to route non-secure 1173 interrupts to TSP allowing it to save its context and hand over 1174 synchronously to EL3 via an SMC. 1175 1176 .. note:: 1177 When ``EL3_EXCEPTION_HANDLING`` is ``1``, ``TSP_NS_INTR_ASYNC_PREEMPT`` 1178 must also be set to ``1``. 1179 1180- ``TS_SP_FW_CONFIG``: DTC build flag to include Trusted Services (Crypto and 1181 internal-trusted-storage) as SP in tb_fw_config device tree. 1182 1183- ``TWED_DELAY``: Numeric value to be set in order to delay the trapping of 1184 WFE instruction. ``ENABLE_FEAT_TWED`` build option must be enabled to set 1185 this delay. It can take values in the range (0-15). Default value is ``0`` 1186 and based on this value, 2^(TWED_DELAY + 8) cycles will be delayed. 1187 Platforms need to explicitly update this value based on their requirements. 1188 1189- ``USE_ARM_LINK``: This flag determines whether to enable support for ARM 1190 linker. When the ``LINKER`` build variable points to the armlink linker, 1191 this flag is enabled automatically. To enable support for armlink, platforms 1192 will have to provide a scatter file for the BL image. Currently, Tegra 1193 platforms use the armlink support to compile BL3-1 images. 1194 1195- ``USE_COHERENT_MEM``: This flag determines whether to include the coherent 1196 memory region in the BL memory map or not (see "Use of Coherent memory in 1197 TF-A" section in :ref:`Firmware Design`). It can take the value 1 1198 (Coherent memory region is included) or 0 (Coherent memory region is 1199 excluded). Default is 1. 1200 1201- ``USE_KERNEL_DT_CONVENTION``: When this option is enabled, the hardware 1202 device tree is passed to BL33 using register x0, aligning with the expectations 1203 of the Linux kernel on Arm platforms. If this option is disabled, a different 1204 register, typically x1, may be used instead. This build option is 1205 not necessary when firmware handoff is active (that is, when TRANSFER_LIST=1 1206 is set), and it will be removed once all platforms have transitioned to that 1207 convention. 1208 1209- ``USE_DSU_DRIVER``: This flag enables DSU (DynamIQ Shared Unit) driver. 1210 The DSU driver allows save/restore of DSU PMU registers through 1211 ``PRESERVE_DSU_PMU_REGS`` build option, provides access to PMU registers at 1212 EL1 and allows platforms to configure powerdown and power settings of DSU. 1213 1214- ``ARM_IO_IN_DTB``: This flag determines whether to use IO based on the 1215 firmware configuration framework. This will move the io_policies into a 1216 configuration device tree, instead of static structure in the code base. 1217 1218- ``COT_DESC_IN_DTB``: This flag determines whether to create COT descriptors 1219 at runtime using fconf. If this flag is enabled, COT descriptors are 1220 statically captured in tb_fw_config file in the form of device tree nodes 1221 and properties. Currently, COT descriptors used by BL2 are moved to the 1222 device tree and COT descriptors used by BL1 are retained in the code 1223 base statically. 1224 1225- ``SDEI_IN_FCONF``: This flag determines whether to configure SDEI setup in 1226 runtime using firmware configuration framework. The platform specific SDEI 1227 shared and private events configuration is retrieved from device tree rather 1228 than static C structures at compile time. This is only supported if 1229 SDEI_SUPPORT build flag is enabled. 1230 1231- ``SEC_INT_DESC_IN_FCONF``: This flag determines whether to configure Group 0 1232 and Group1 secure interrupts using the firmware configuration framework. The 1233 platform specific secure interrupt property descriptor is retrieved from 1234 device tree in runtime rather than depending on static C structure at compile 1235 time. 1236 1237- ``USE_ROMLIB``: This flag determines whether library at ROM will be used. 1238 This feature creates a library of functions to be placed in ROM and thus 1239 reduces SRAM usage. Refer to :ref:`Library at ROM` for further details. Default 1240 is 0. 1241 1242- ``V``: Verbose build. If assigned anything other than 0, the build commands 1243 are printed. Default is 0. 1244 1245- ``VERSION_STRING``: String used in the log output for each TF-A image. 1246 Defaults to a string formed by concatenating the version number, build type 1247 and build string. 1248 1249- ``W``: Warning level. Some compiler warning options of interest have been 1250 regrouped and put in the root Makefile. This flag can take the values 0 to 3, 1251 each level enabling more warning options. Default is 0. 1252 1253 This option is closely related to the ``E`` option, which enables 1254 ``-Werror``. 1255 1256 - ``W=0`` (default) 1257 1258 Enables a wide assortment of warnings, most notably ``-Wall`` and 1259 ``-Wextra``, as well as various bad practices and things that are likely to 1260 result in errors. Includes some compiler specific flags. No warnings are 1261 expected at this level for any build. 1262 1263 - ``W=1`` 1264 1265 Enables warnings we want the generic build to include but are too time 1266 consuming to fix at the moment. It re-enables warnings taken out for 1267 ``W=0`` builds (a few of the ``-Wextra`` additions). This level is expected 1268 to eventually be merged into ``W=0``. Some warnings are expected on some 1269 builds, but new contributions should not introduce new ones. 1270 1271 - ``W=2`` (recommended) 1272 1273 Enables warnings we want the generic build to include but cannot be enabled 1274 due to external libraries. This level is expected to eventually be merged 1275 into ``W=0``. Lots of warnings are expected, primarily from external 1276 libraries like zlib and compiler-rt, but new controbutions should not 1277 introduce new ones. 1278 1279 - ``W=3`` 1280 1281 Enables warnings that are informative but not necessary and generally too 1282 verbose and frequently ignored. A very large number of warnings are 1283 expected. 1284 1285 The exact set of warning flags depends on the compiler and TF-A warning 1286 level, however they are all succinctly set in the top-level Makefile. Please 1287 refer to the `GCC`_ or `Clang`_ documentation for more information on the 1288 individual flags. 1289 1290- ``WARMBOOT_ENABLE_DCACHE_EARLY`` : Boolean option to enable D-cache early on 1291 the CPU after warm boot. This is applicable for platforms which do not 1292 require interconnect programming to enable cache coherency (eg: single 1293 cluster platforms). If this option is enabled, then warm boot path 1294 enables D-caches immediately after enabling MMU. This option defaults to 0. 1295 1296- ``ERRATA_SPECULATIVE_AT``: This flag determines whether to enable ``AT`` 1297 speculative errata workaround or not. It accepts 2 values: ``1`` and ``0``. 1298 The default value of this flag is ``0``. 1299 1300 ``AT`` speculative errata workaround disables stage1 page table walk for 1301 lower ELs (EL1 and EL0) in EL3 so that ``AT`` speculative fetch at any point 1302 produces either the correct result or failure without TLB allocation. 1303 1304 This boolean option enables errata for all below CPUs. 1305 1306 +---------+--------------+-------------------------+ 1307 | Errata | CPU | Workaround Define | 1308 +=========+==============+=========================+ 1309 | 1165522 | Cortex-A76 | ``ERRATA_A76_1165522`` | 1310 +---------+--------------+-------------------------+ 1311 | 1319367 | Cortex-A72 | ``ERRATA_A72_1319367`` | 1312 +---------+--------------+-------------------------+ 1313 | 1541130 | Cortex-A65 | ``ERRATA_A65_1541130`` | 1314 +---------+--------------+-------------------------+ 1315 | 1319537 | Cortex-A57 | ``ERRATA_A57_1319537`` | 1316 +---------+--------------+-------------------------+ 1317 | 1530923 | Cortex-A55 | ``ERRATA_A55_1530923`` | 1318 +---------+--------------+-------------------------+ 1319 | 1530924 | Cortex-A53 | ``ERRATA_A53_1530924`` | 1320 +---------+--------------+-------------------------+ 1321 1322 .. note:: 1323 This option is enabled by build only if platform sets any of above defines 1324 mentioned in ’Workaround Define' column in the table. 1325 If this option is enabled for the EL3 software then EL2 software also must 1326 implement this workaround due to the behaviour of the errata mentioned 1327 in new SDEN document which will get published soon. 1328 1329- ``ERRATA_SME_POWER_DOWN``: Boolean option to disconnect the SME unit (PSTATE.{ZA,SM}=0) 1330 before power down and downgrade a suspend to power down request to a normal 1331 suspend request. This is necessary when software running at lower ELs requests 1332 power down without first clearing these bits. On affected cores, the CME 1333 connected to it will reject its power down request. The default value is 0. 1334 1335- ``RAS_TRAP_NS_ERR_REC_ACCESS``: This flag enables/disables the SCR_EL3.TERR 1336 bit, to trap access to the RAS ERR and RAS ERX registers from lower ELs. 1337 This flag is disabled by default. 1338 1339- ``OPENSSL_DIR``: This option is used to provide the path to a directory on the 1340 host machine where a custom installation of OpenSSL is located, which is used 1341 to build the certificate generation, firmware encryption and FIP tools. If 1342 this option is not set, the default OS installation will be used. 1343 1344- ``USE_SP804_TIMER``: Use the SP804 timer instead of the Generic Timer for 1345 functions that wait for an arbitrary time length (udelay and mdelay). The 1346 default value is 0. 1347 1348- ``ENABLE_BRBE_FOR_NS``: Numeric value to enable access to the branch record 1349 buffer registers from NS ELs when FEAT_BRBE is implemented. BRBE is an 1350 optional architectural feature for AArch64. This flag can take the values 1351 0 to 2, to align with the ``ENABLE_FEAT`` mechanism. The default is 0 1352 and it is automatically disabled when the target architecture is AArch32. 1353 1354- ``ENABLE_TRBE_FOR_NS``: Numeric value to enable access of trace buffer 1355 control registers from NS ELs, NS-EL2 or NS-EL1(when NS-EL2 is implemented 1356 but unused) when FEAT_TRBE is implemented. TRBE is an optional architectural 1357 feature for AArch64. This flag can take the values 0 to 2, to align with the 1358 ``ENABLE_FEAT`` mechanism. The default is 0 and it is automatically 1359 disabled when the target architecture is AArch32. 1360 1361- ``USE_SPINLOCK_CAS``: Numeric value to use FEAT_LSE atomics instead of 1362 load/store exclusive instructions with spinlocks. FEAT_LSE is a mandatory 1363 feature from v8.1, however it is only architecturally guaranteed to work on 1364 "conventional memory" which may not apply to tightly coupled memory (eg. SRAM, 1365 TF-A's usual place). Platforms must check if TF-A's memory can be targetted 1366 by atomics before enabling this feature. Expected to increase performance on 1367 systems with many cores. This flag can take the values 0 to 2, to align with 1368 the ``ENABLE_FEAT`` mechanism. The default is 0. 1369 1370- ``ENABLE_SYS_REG_TRACE_FOR_NS``: Numeric value to enable trace system 1371 registers access from NS ELs, NS-EL2 or NS-EL1 (when NS-EL2 is implemented 1372 but unused). This feature is available if trace unit such as ETMv4.x, and 1373 ETE(extending ETM feature) is implemented. This flag can take the values 1374 0 to 2, to align with the ``ENABLE_FEAT`` mechanism. The default is 0. 1375 1376- ``ENABLE_TRF_FOR_NS``: Numeric value to enable trace filter control registers 1377 access from NS ELs, NS-EL2 or NS-EL1 (when NS-EL2 is implemented but unused), 1378 if FEAT_TRF is implemented. This flag can take the values 0 to 2, to align 1379 with the ``ENABLE_FEAT`` mechanism. This flag is disabled by default. 1380 1381- ``CONDITIONAL_CMO``: Boolean option to enable call to platform-defined routine 1382 ``plat_can_cmo`` which will return zero if cache management operations should 1383 be skipped and non-zero otherwise. By default, this option is disabled which 1384 means platform hook won't be checked and CMOs will always be performed when 1385 related functions are called. 1386 1387- ``ERRATA_ABI_SUPPORT``: Boolean option to enable support for Errata management 1388 firmware interface for the BL31 image. By default its disabled (``0``). 1389 1390- ``ERRATA_NON_ARM_INTERCONNECT``: Boolean option to enable support for the 1391 errata mitigation for platforms with a non-arm interconnect using the errata 1392 ABI. By default its disabled (``0``). 1393 1394- ``ENABLE_CONSOLE_GETC``: Boolean option to enable `getc()` feature in console 1395 driver(s). By default it is disabled (``0``) because it constitutes an attack 1396 vector into TF-A by potentially allowing an attacker to inject arbitrary data. 1397 This option should only be enabled on a need basis if there is a use case for 1398 reading characters from the console. 1399 1400GIC driver options 1401-------------------- 1402 1403The generic GIC driver can be included with the ``USE_GIC_DRIVER`` option. It is 1404a numeric option that can take the following values: 1405 1406 - ``0``: generic GIC driver not enabled. Any support is entirely in platform 1407 code. Strongly discouraged for GIC based interrupt controllers. 1408 1409 - ``1``: enable the use of the generic GIC driver but do not include any files 1410 or function definitions. It is then the platform's responsibility to provide 1411 these. This is useful if the platform either has a custom GIC implementation 1412 or an alternative interrupt controller design. Use of this option is strongly 1413 discouraged for standard GIC implementations. 1414 1415 - ``2``: use the GICv2 driver 1416 1417 - ``3``: use the GICv3 driver. See the next section on how to further configure 1418 it. Use this option for GICv4 implementations. Requires calling 1419 ``gic_set_gicr_frames()``. 1420 1421 - ``5``: use the EXPERIMENTAL GICv5 driver. Requires ``ENABLE_FEAT_GCIE=1``. 1422 1423 For GIC driver versions other than ``1``, deciding when to save and restore GIC 1424 context on a power domain state transition, as well as any GIC actions outside 1425 of the PSCI library's visibility are the platform's responsibility. The driver 1426 provides implementations of all necessary subroutines, they only need to be 1427 called as appropriate. 1428 1429GICv3 driver options 1430~~~~~~~~~~~~~~~~~~~~ 1431 1432``USE_GIC_DRIVER=3`` is the preferred way of including GICv3 driver files. The 1433old (deprecated) way of included them is using the directive: 1434``include drivers/arm/gic/v3/gicv3.mk`` 1435 1436The driver can be configured with the following options set in the platform 1437makefile: 1438 1439- ``GICV3_SUPPORT_GIC600``: Add support for the GIC-600 variants of GICv3. 1440 Enabling this option will add runtime detection support for the 1441 GIC-600, so is safe to select even for a GIC500 implementation. 1442 This option defaults to 0. 1443 1444- ``GICV3_SUPPORT_GIC600AE_FMU``: Add support for the Fault Management Unit 1445 for GIC-600 AE. Enabling this option will introduce support to initialize 1446 the FMU. Platforms should call the init function during boot to enable the 1447 FMU and its safety mechanisms. This option defaults to 0. 1448 1449- ``GICV3_IMPL_GIC600_MULTICHIP``: Selects GIC-600 variant with multichip 1450 functionality. This option defaults to 0 1451 1452- ``GICV3_OVERRIDE_DISTIF_PWR_OPS``: Allows override of default implementation 1453 of ``arm_gicv3_distif_pre_save`` and ``arm_gicv3_distif_post_restore`` 1454 functions. This is required for FVP platform which need to simulate GIC save 1455 and restore during SYSTEM_SUSPEND without powering down GIC. Default is 0. 1456 1457- ``GIC_ENABLE_V4_EXTN`` : Enables GICv4 related changes in GICv3 driver. 1458 This option defaults to 0. 1459 1460- ``GIC_EXT_INTID``: When set to ``1``, GICv3 driver will support extended 1461 PPI (1056-1119) and SPI (4096-5119) range. This option defaults to 0. 1462 1463Debugging options 1464----------------- 1465 1466To compile a debug version and make the build more verbose use 1467 1468.. code:: shell 1469 1470 make PLAT=<platform> DEBUG=1 V=1 all 1471 1472AArch64 GCC 11 uses DWARF version 5 debugging symbols by default. Some tools 1473(for example Arm-DS) might not support this and may need an older version of 1474DWARF symbols to be emitted by GCC. This can be achieved by using the 1475``-gdwarf-<version>`` flag, with the version being set to 2, 3, 4 or 5. Setting 1476the version to 4 is recommended for Arm-DS. 1477 1478When debugging logic problems it might also be useful to disable all compiler 1479optimizations by using ``-O0``. 1480 1481.. warning:: 1482 Using ``-O0`` could cause output images to be larger and base addresses 1483 might need to be recalculated (see the **Memory layout on Arm development 1484 platforms** section in the :ref:`Firmware Design`). 1485 1486Extra debug options can be passed to the build system by setting ``CFLAGS`` or 1487``LDFLAGS``: 1488 1489.. code:: shell 1490 1491 CFLAGS='-O0 -gdwarf-2' \ 1492 make PLAT=<platform> DEBUG=1 V=1 all 1493 1494Note that using ``-Wl,`` style compilation driver options in ``CFLAGS`` will be 1495ignored as the linker is called directly. 1496 1497It is also possible to introduce an infinite loop to help in debugging the 1498post-BL2 phase of TF-A. This can be done by rebuilding BL1 with the 1499``SPIN_ON_BL1_EXIT=1`` build flag. Refer to the :ref:`build_options_common` 1500section. In this case, the developer may take control of the target using a 1501debugger when indicated by the console output. When using Arm-DS, the following 1502commands can be used: 1503 1504:: 1505 1506 # Stop target execution 1507 interrupt 1508 1509 # 1510 # Prepare your debugging environment, e.g. set breakpoints 1511 # 1512 1513 # Jump over the debug loop 1514 set var $AARCH64::$Core::$PC = $AARCH64::$Core::$PC + 4 1515 1516 # Resume execution 1517 continue 1518 1519.. _build_options_experimental: 1520 1521Experimental build options 1522--------------------------- 1523 1524Common build options 1525~~~~~~~~~~~~~~~~~~~~ 1526 1527- ``DICE_PROTECTION_ENVIRONMENT``: Boolean flag to specify the measured boot 1528 backend when ``MEASURED_BOOT`` is enabled. The default value is ``0``. When 1529 set to ``1`` then measurements and additional metadata collected during the 1530 measured boot process are sent to the DICE Protection Environment for storage 1531 and processing. A certificate chain, which represents the boot state of the 1532 device, can be queried from the DPE. 1533 1534- ``DRTM_SUPPORT``: Boolean flag to enable support for Dynamic Root of Trust 1535 for Measurement (DRTM). This feature has trust dependency on BL31 for taking 1536 the measurements and recording them as per `PSA DRTM specification`_. For 1537 platforms which use BL2 to load/authenticate BL31 ``TRUSTED_BOARD_BOOT`` can 1538 be used and for the platforms which use ``RESET_TO_BL31`` platform owners 1539 should have mechanism to authenticate BL31. This option defaults to 0. 1540 1541- ``ENABLE_RME``: Numeric value to enable support for the ARMv9 Realm 1542 Management Extension. This flag can take the values 0 to 2, to align with 1543 the ``ENABLE_FEAT`` mechanism. Default value is 0. 1544 1545- ``ENABLE_FEAT_MEC``: Numeric value to enable support for the ARMv9.2 Memory 1546 Encryption Contexts (MEC). This flag can take the values 0 to 2, to align 1547 with the ``ENABLE_FEAT`` mechanism. MEC supports multiple encryption 1548 contexts for Realm security state and only one encryption context for the 1549 rest of the security states. Default value is 0. 1550 1551- ``RMMD_ENABLE_EL3_TOKEN_SIGN``: Numeric value to enable support for singing 1552 realm attestation token signing requests in EL3. This flag can take the 1553 values 0 and 1. The default value is ``0``. When set to ``1``, this option 1554 enables additional RMMD SMCs to push and pop requests for signing to 1555 EL3 along with platform hooks that must be implemented to service those 1556 requests and responses. 1557 1558- ``ENABLE_SME_FOR_NS``: Numeric value to enable Scalable Matrix Extension 1559 (SME), SVE, and FPU/SIMD for the non-secure world only. These features share 1560 registers so are enabled together. Using this option without 1561 ENABLE_SME_FOR_SWD=1 will cause SME, SVE, and FPU/SIMD instructions in secure 1562 world to trap to EL3. Requires ``ENABLE_SVE_FOR_NS`` to be set as SME is a 1563 superset of SVE. SME is an optional architectural feature for AArch64. 1564 At this time, this build option cannot be used on systems that have 1565 SPD=spmd/SPM_MM and atempting to build with this option will fail. 1566 This flag can take the values 0 to 2, to align with the ``ENABLE_FEAT`` 1567 mechanism. Default is 0. 1568 1569- ``ENABLE_SME2_FOR_NS``: Numeric value to enable Scalable Matrix Extension 1570 version 2 (SME2) for the non-secure world only. SME2 is an optional 1571 architectural feature for AArch64. 1572 This should be set along with ENABLE_SME_FOR_NS=1, if not, the default SME 1573 accesses will still be trapped. This flag can take the values 0 to 2, to 1574 align with the ``ENABLE_FEAT`` mechanism. Default is 0. 1575 1576- ``ENABLE_SME_FOR_SWD``: Boolean option to enable the Scalable Matrix 1577 Extension for secure world. Used along with SVE and FPU/SIMD. 1578 ENABLE_SME_FOR_NS and ENABLE_SVE_FOR_SWD must also be set to use this. 1579 Default is 0. 1580 1581- ``ENABLE_SPMD_LP`` : This boolean option is used jointly with the SPM 1582 Dispatcher option (``SPD=spmd``). When enabled (1) it indicates support 1583 for logical partitions in EL3, managed by the SPMD as defined in the 1584 FF-A v1.2 specification. This flag is disabled by default. This flag 1585 must not be used if ``SPMC_AT_EL3`` is enabled. 1586 1587- ``FEATURE_DETECTION``: Boolean option to enable the architectural features 1588 verification mechanism. This is a debug feature that compares the 1589 architectural features enabled through the feature specific build flags 1590 (ENABLE_FEAT_xxx) with the features actually available on the CPU running, 1591 and reports any discrepancies. 1592 This flag will also enable errata ordering checking for ``DEBUG`` builds. 1593 1594 It is expected that this feature is only used for flexible platforms like 1595 software emulators, or for hardware platforms at bringup time, to verify 1596 that the configured feature set matches the CPU. 1597 The ``FEATURE_DETECTION`` macro is disabled by default. 1598 1599- ``PSA_CRYPTO``: Boolean option for enabling MbedTLS PSA crypto APIs support. 1600 The platform will use PSA compliant Crypto APIs during authentication and 1601 image measurement process by enabling this option. It uses APIs defined as 1602 per the `PSA Crypto API specification`_. This feature is only supported if 1603 using MbedTLS 3.x version. It is disabled (``0``) by default. 1604 1605- ``LFA_SUPPORT``: Boolean flag to enable support for Live Firmware 1606 activation as per the specification. This option defaults to 0. 1607 1608- ``TRANSFER_LIST``: Setting this to ``1`` enables support for Firmware 1609 Handoff using Transfer List defined in `Firmware Handoff specification`_. 1610 This defaults to ``0``. Current implementation follows the Firmware Handoff 1611 specification v0.9. 1612 1613- ``USE_DEBUGFS``: When set to 1 this option exposes a virtual filesystem 1614 interface through BL31 as a SiP SMC function. 1615 Default is disabled (0). 1616 1617- ``HOB_LIST``: Setting this to ``1`` enables support for passing boot 1618 information using HOB defined in `Platform Initialization specification`_. 1619 This defaults to ``0``. 1620 1621- ``ENABLE_ACS_SMC``: When set to ``1``, this enables support for ACS SMC 1622 handler code to handle SMC calls from the Architecture Compliance Suite. The 1623 handler is intentionally empty to reserve the SMC section and allow 1624 project-specific implementations in future ACS use cases. 1625 1626Firmware update options 1627~~~~~~~~~~~~~~~~~~~~~~~ 1628 1629- ``PSA_FWU_SUPPORT``: Enable the firmware update mechanism as per the 1630 `PSA FW update specification`_. The default value is 0. 1631 PSA firmware update implementation has few limitations, such as: 1632 1633 - BL2 is not part of the protocol-updatable images. If BL2 needs to 1634 be updated, then it should be done through another platform-defined 1635 mechanism. 1636 1637 - It assumes the platform's hardware supports CRC32 instructions. 1638 1639- ``NR_OF_FW_BANKS``: Define the number of firmware banks. This flag is used 1640 in defining the firmware update metadata structure. This flag is by default 1641 set to '2'. 1642 1643- ``NR_OF_IMAGES_IN_FW_BANK``: Define the number of firmware images in each 1644 firmware bank. Each firmware bank must have the same number of images as per 1645 the `PSA FW update specification`_. 1646 This flag is used in defining the firmware update metadata structure. This 1647 flag is by default set to '1'. 1648 1649- ``PSA_FWU_METADATA_FW_STORE_DESC``: To be enabled when the FWU 1650 metadata contains image description. The default value is 1. 1651 1652 The version 2 of the FWU metadata allows for an opaque metadata 1653 structure where a platform can choose to not include the firmware 1654 store description in the metadata structure. This option indicates 1655 if the firmware store description, which provides information on 1656 the updatable images is part of the structure. 1657 1658-------------- 1659 1660*Copyright (c) 2019-2026, Arm Limited. All rights reserved.* 1661 1662.. _DEN0115: https://developer.arm.com/docs/den0115/latest 1663.. _PSA FW update specification: https://developer.arm.com/documentation/den0118/latest/ 1664.. _PSA DRTM specification: https://developer.arm.com/documentation/den0113/a 1665.. _GCC: https://gcc.gnu.org/onlinedocs/gcc/Warning-Options.html 1666.. _Clang: https://clang.llvm.org/docs/DiagnosticsReference.html 1667.. _Firmware Handoff specification: https://github.com/FirmwareHandoff/firmware_handoff/releases/tag/v0.9 1668.. _PSA Crypto API specification: https://armmbed.github.io/mbed-crypto/html/ 1669.. _Platform Initialization specification: https://uefi.org/specs/PI/1.8/index.html 1670.. _TF-A public mailing list: https://lists.trustedfirmware.org/mailman3/lists/tf-a.lists.trustedfirmware.org/ 1671