1 #ifndef __ODY_CSRS_UAA_H__
2 #define __ODY_CSRS_UAA_H__
3 /* This file is auto-generated. Do not edit */
4
5 /***********************license start***********************************
6 * Copyright (C) 2021-2026 Marvell.
7 * SPDX-License-Identifier: BSD-3-Clause
8 * https://spdx.org/licenses
9 ***********************license end**************************************/
10
11
12 /**
13 * @file
14 *
15 * Configuration and status register (CSR) address and type definitions for
16 * UAA.
17 *
18 * This file is auto generated. Do not edit.
19 *
20 */
21
22 /**
23 * Enumeration uaa_bar_e
24 *
25 * UART Base Address Register Enumeration
26 * Enumerates the base address registers.
27 */
28 #define ODY_UAA_BAR_E_UAAX_PF_BAR0(a) (0x87e028000000ll + 0x1000000ll * (a))
29 #define ODY_UAA_BAR_E_UAAX_PF_BAR0_SIZE 0x10000ull
30 #define ODY_UAA_BAR_E_UAAX_PF_BAR4(a) (0x87e028f00000ll + 0x1000000ll * (a))
31 #define ODY_UAA_BAR_E_UAAX_PF_BAR4_SIZE 0x100000ull
32
33 /**
34 * Enumeration uaa_int_vec_e
35 *
36 * UART MSI-X Vector Enumeration
37 * Enumerates the MSI-X interrupt vectors.
38 */
39 #define ODY_UAA_INT_VEC_E_INTS (0)
40 #define ODY_UAA_INT_VEC_E_INTS_CLEAR (1)
41
42 /**
43 * Register (RSL32b) uaa#_cidr0
44 *
45 * UART Component Identification Register 0
46 */
47 union ody_uaax_cidr0 {
48 uint32_t u;
49 struct ody_uaax_cidr0_s {
50 uint32_t preamble : 8;
51 uint32_t reserved_8_31 : 24;
52 } s;
53 /* struct ody_uaax_cidr0_s cn; */
54 };
55 typedef union ody_uaax_cidr0 ody_uaax_cidr0_t;
56
57 static inline uint64_t ODY_UAAX_CIDR0(uint64_t a) __attribute__ ((pure, always_inline));
ODY_UAAX_CIDR0(uint64_t a)58 static inline uint64_t ODY_UAAX_CIDR0(uint64_t a)
59 {
60 if (a <= 7)
61 return 0x87e028000ff0ll + 0x1000000ll * ((a) & 0x7);
62 __ody_csr_fatal("UAAX_CIDR0", 1, a, 0, 0, 0, 0, 0);
63 }
64
65 #define typedef_ODY_UAAX_CIDR0(a) ody_uaax_cidr0_t
66 #define bustype_ODY_UAAX_CIDR0(a) CSR_TYPE_RSL32b
67 #define basename_ODY_UAAX_CIDR0(a) "UAAX_CIDR0"
68 #define device_bar_ODY_UAAX_CIDR0(a) 0x0 /* PF_BAR0 */
69 #define busnum_ODY_UAAX_CIDR0(a) (a)
70 #define arguments_ODY_UAAX_CIDR0(a) (a), -1, -1, -1
71
72 /**
73 * Register (RSL32b) uaa#_cidr1
74 *
75 * UART Component Identification Register 1
76 */
77 union ody_uaax_cidr1 {
78 uint32_t u;
79 struct ody_uaax_cidr1_s {
80 uint32_t preamble : 8;
81 uint32_t reserved_8_31 : 24;
82 } s;
83 /* struct ody_uaax_cidr1_s cn; */
84 };
85 typedef union ody_uaax_cidr1 ody_uaax_cidr1_t;
86
87 static inline uint64_t ODY_UAAX_CIDR1(uint64_t a) __attribute__ ((pure, always_inline));
ODY_UAAX_CIDR1(uint64_t a)88 static inline uint64_t ODY_UAAX_CIDR1(uint64_t a)
89 {
90 if (a <= 7)
91 return 0x87e028000ff4ll + 0x1000000ll * ((a) & 0x7);
92 __ody_csr_fatal("UAAX_CIDR1", 1, a, 0, 0, 0, 0, 0);
93 }
94
95 #define typedef_ODY_UAAX_CIDR1(a) ody_uaax_cidr1_t
96 #define bustype_ODY_UAAX_CIDR1(a) CSR_TYPE_RSL32b
97 #define basename_ODY_UAAX_CIDR1(a) "UAAX_CIDR1"
98 #define device_bar_ODY_UAAX_CIDR1(a) 0x0 /* PF_BAR0 */
99 #define busnum_ODY_UAAX_CIDR1(a) (a)
100 #define arguments_ODY_UAAX_CIDR1(a) (a), -1, -1, -1
101
102 /**
103 * Register (RSL32b) uaa#_cidr2
104 *
105 * UART Component Identification Register 2
106 */
107 union ody_uaax_cidr2 {
108 uint32_t u;
109 struct ody_uaax_cidr2_s {
110 uint32_t preamble : 8;
111 uint32_t reserved_8_31 : 24;
112 } s;
113 /* struct ody_uaax_cidr2_s cn; */
114 };
115 typedef union ody_uaax_cidr2 ody_uaax_cidr2_t;
116
117 static inline uint64_t ODY_UAAX_CIDR2(uint64_t a) __attribute__ ((pure, always_inline));
ODY_UAAX_CIDR2(uint64_t a)118 static inline uint64_t ODY_UAAX_CIDR2(uint64_t a)
119 {
120 if (a <= 7)
121 return 0x87e028000ff8ll + 0x1000000ll * ((a) & 0x7);
122 __ody_csr_fatal("UAAX_CIDR2", 1, a, 0, 0, 0, 0, 0);
123 }
124
125 #define typedef_ODY_UAAX_CIDR2(a) ody_uaax_cidr2_t
126 #define bustype_ODY_UAAX_CIDR2(a) CSR_TYPE_RSL32b
127 #define basename_ODY_UAAX_CIDR2(a) "UAAX_CIDR2"
128 #define device_bar_ODY_UAAX_CIDR2(a) 0x0 /* PF_BAR0 */
129 #define busnum_ODY_UAAX_CIDR2(a) (a)
130 #define arguments_ODY_UAAX_CIDR2(a) (a), -1, -1, -1
131
132 /**
133 * Register (RSL32b) uaa#_cidr3
134 *
135 * UART Component Identification Register 3
136 */
137 union ody_uaax_cidr3 {
138 uint32_t u;
139 struct ody_uaax_cidr3_s {
140 uint32_t preamble : 8;
141 uint32_t reserved_8_31 : 24;
142 } s;
143 /* struct ody_uaax_cidr3_s cn; */
144 };
145 typedef union ody_uaax_cidr3 ody_uaax_cidr3_t;
146
147 static inline uint64_t ODY_UAAX_CIDR3(uint64_t a) __attribute__ ((pure, always_inline));
ODY_UAAX_CIDR3(uint64_t a)148 static inline uint64_t ODY_UAAX_CIDR3(uint64_t a)
149 {
150 if (a <= 7)
151 return 0x87e028000ffcll + 0x1000000ll * ((a) & 0x7);
152 __ody_csr_fatal("UAAX_CIDR3", 1, a, 0, 0, 0, 0, 0);
153 }
154
155 #define typedef_ODY_UAAX_CIDR3(a) ody_uaax_cidr3_t
156 #define bustype_ODY_UAAX_CIDR3(a) CSR_TYPE_RSL32b
157 #define basename_ODY_UAAX_CIDR3(a) "UAAX_CIDR3"
158 #define device_bar_ODY_UAAX_CIDR3(a) 0x0 /* PF_BAR0 */
159 #define busnum_ODY_UAAX_CIDR3(a) (a)
160 #define arguments_ODY_UAAX_CIDR3(a) (a), -1, -1, -1
161
162 /**
163 * Register (RSL32b) uaa#_cr
164 *
165 * UART Control Register
166 */
167 union ody_uaax_cr {
168 uint32_t u;
169 struct ody_uaax_cr_s {
170 uint32_t uarten : 1;
171 uint32_t reserved_1_6 : 6;
172 uint32_t lbe : 1;
173 uint32_t txe : 1;
174 uint32_t rxe : 1;
175 uint32_t dtr : 1;
176 uint32_t rts : 1;
177 uint32_t out1 : 1;
178 uint32_t out2 : 1;
179 uint32_t rtsen : 1;
180 uint32_t ctsen : 1;
181 uint32_t reserved_16_31 : 16;
182 } s;
183 struct ody_uaax_cr_cn {
184 uint32_t uarten : 1;
185 uint32_t reserved_1 : 1;
186 uint32_t reserved_2 : 1;
187 uint32_t reserved_3_6 : 4;
188 uint32_t lbe : 1;
189 uint32_t txe : 1;
190 uint32_t rxe : 1;
191 uint32_t dtr : 1;
192 uint32_t rts : 1;
193 uint32_t out1 : 1;
194 uint32_t out2 : 1;
195 uint32_t rtsen : 1;
196 uint32_t ctsen : 1;
197 uint32_t reserved_16_31 : 16;
198 } cn;
199 };
200 typedef union ody_uaax_cr ody_uaax_cr_t;
201
202 static inline uint64_t ODY_UAAX_CR(uint64_t a) __attribute__ ((pure, always_inline));
ODY_UAAX_CR(uint64_t a)203 static inline uint64_t ODY_UAAX_CR(uint64_t a)
204 {
205 if (a <= 7)
206 return 0x87e028000030ll + 0x1000000ll * ((a) & 0x7);
207 __ody_csr_fatal("UAAX_CR", 1, a, 0, 0, 0, 0, 0);
208 }
209
210 #define typedef_ODY_UAAX_CR(a) ody_uaax_cr_t
211 #define bustype_ODY_UAAX_CR(a) CSR_TYPE_RSL32b
212 #define basename_ODY_UAAX_CR(a) "UAAX_CR"
213 #define device_bar_ODY_UAAX_CR(a) 0x0 /* PF_BAR0 */
214 #define busnum_ODY_UAAX_CR(a) (a)
215 #define arguments_ODY_UAAX_CR(a) (a), -1, -1, -1
216
217 /**
218 * Register (RSL32b) uaa#_dr
219 *
220 * UART Data Register
221 * Writing to this register pushes data to the FIFO for transmission. Reading it retrieves
222 * received data from the receive FIFO.
223 */
224 union ody_uaax_dr {
225 uint32_t u;
226 struct ody_uaax_dr_s {
227 uint32_t data : 8;
228 uint32_t fe : 1;
229 uint32_t pe : 1;
230 uint32_t be : 1;
231 uint32_t oe : 1;
232 uint32_t reserved_12_31 : 20;
233 } s;
234 /* struct ody_uaax_dr_s cn; */
235 };
236 typedef union ody_uaax_dr ody_uaax_dr_t;
237
238 static inline uint64_t ODY_UAAX_DR(uint64_t a) __attribute__ ((pure, always_inline));
ODY_UAAX_DR(uint64_t a)239 static inline uint64_t ODY_UAAX_DR(uint64_t a)
240 {
241 if (a <= 7)
242 return 0x87e028000000ll + 0x1000000ll * ((a) & 0x7);
243 __ody_csr_fatal("UAAX_DR", 1, a, 0, 0, 0, 0, 0);
244 }
245
246 #define typedef_ODY_UAAX_DR(a) ody_uaax_dr_t
247 #define bustype_ODY_UAAX_DR(a) CSR_TYPE_RSL32b
248 #define basename_ODY_UAAX_DR(a) "UAAX_DR"
249 #define device_bar_ODY_UAAX_DR(a) 0x0 /* PF_BAR0 */
250 #define busnum_ODY_UAAX_DR(a) (a)
251 #define arguments_ODY_UAAX_DR(a) (a), -1, -1, -1
252
253 /**
254 * Register (RSL32b) uaa#_fbrd
255 *
256 * UART Fractional Baud Rate Register
257 */
258 union ody_uaax_fbrd {
259 uint32_t u;
260 struct ody_uaax_fbrd_s {
261 uint32_t baud_divfrac : 6;
262 uint32_t reserved_6_31 : 26;
263 } s;
264 /* struct ody_uaax_fbrd_s cn; */
265 };
266 typedef union ody_uaax_fbrd ody_uaax_fbrd_t;
267
268 static inline uint64_t ODY_UAAX_FBRD(uint64_t a) __attribute__ ((pure, always_inline));
ODY_UAAX_FBRD(uint64_t a)269 static inline uint64_t ODY_UAAX_FBRD(uint64_t a)
270 {
271 if (a <= 7)
272 return 0x87e028000028ll + 0x1000000ll * ((a) & 0x7);
273 __ody_csr_fatal("UAAX_FBRD", 1, a, 0, 0, 0, 0, 0);
274 }
275
276 #define typedef_ODY_UAAX_FBRD(a) ody_uaax_fbrd_t
277 #define bustype_ODY_UAAX_FBRD(a) CSR_TYPE_RSL32b
278 #define basename_ODY_UAAX_FBRD(a) "UAAX_FBRD"
279 #define device_bar_ODY_UAAX_FBRD(a) 0x0 /* PF_BAR0 */
280 #define busnum_ODY_UAAX_FBRD(a) (a)
281 #define arguments_ODY_UAAX_FBRD(a) (a), -1, -1, -1
282
283 /**
284 * Register (RSL32b) uaa#_fr
285 *
286 * UART Flag Register
287 */
288 union ody_uaax_fr {
289 uint32_t u;
290 struct ody_uaax_fr_s {
291 uint32_t cts : 1;
292 uint32_t dsr : 1;
293 uint32_t dcd : 1;
294 uint32_t busy : 1;
295 uint32_t rxfe : 1;
296 uint32_t txff : 1;
297 uint32_t rxff : 1;
298 uint32_t txfe : 1;
299 uint32_t ri : 1;
300 uint32_t reserved_9_31 : 23;
301 } s;
302 /* struct ody_uaax_fr_s cn; */
303 };
304 typedef union ody_uaax_fr ody_uaax_fr_t;
305
306 static inline uint64_t ODY_UAAX_FR(uint64_t a) __attribute__ ((pure, always_inline));
ODY_UAAX_FR(uint64_t a)307 static inline uint64_t ODY_UAAX_FR(uint64_t a)
308 {
309 if (a <= 7)
310 return 0x87e028000018ll + 0x1000000ll * ((a) & 0x7);
311 __ody_csr_fatal("UAAX_FR", 1, a, 0, 0, 0, 0, 0);
312 }
313
314 #define typedef_ODY_UAAX_FR(a) ody_uaax_fr_t
315 #define bustype_ODY_UAAX_FR(a) CSR_TYPE_RSL32b
316 #define basename_ODY_UAAX_FR(a) "UAAX_FR"
317 #define device_bar_ODY_UAAX_FR(a) 0x0 /* PF_BAR0 */
318 #define busnum_ODY_UAAX_FR(a) (a)
319 #define arguments_ODY_UAAX_FR(a) (a), -1, -1, -1
320
321 /**
322 * Register (RSL32b) uaa#_ibrd
323 *
324 * UART Integer Baud Rate Register
325 */
326 union ody_uaax_ibrd {
327 uint32_t u;
328 struct ody_uaax_ibrd_s {
329 uint32_t baud_divint : 16;
330 uint32_t reserved_16_31 : 16;
331 } s;
332 /* struct ody_uaax_ibrd_s cn; */
333 };
334 typedef union ody_uaax_ibrd ody_uaax_ibrd_t;
335
336 static inline uint64_t ODY_UAAX_IBRD(uint64_t a) __attribute__ ((pure, always_inline));
ODY_UAAX_IBRD(uint64_t a)337 static inline uint64_t ODY_UAAX_IBRD(uint64_t a)
338 {
339 if (a <= 7)
340 return 0x87e028000024ll + 0x1000000ll * ((a) & 0x7);
341 __ody_csr_fatal("UAAX_IBRD", 1, a, 0, 0, 0, 0, 0);
342 }
343
344 #define typedef_ODY_UAAX_IBRD(a) ody_uaax_ibrd_t
345 #define bustype_ODY_UAAX_IBRD(a) CSR_TYPE_RSL32b
346 #define basename_ODY_UAAX_IBRD(a) "UAAX_IBRD"
347 #define device_bar_ODY_UAAX_IBRD(a) 0x0 /* PF_BAR0 */
348 #define busnum_ODY_UAAX_IBRD(a) (a)
349 #define arguments_ODY_UAAX_IBRD(a) (a), -1, -1, -1
350
351 /**
352 * Register (RSL32b) uaa#_icr
353 *
354 * UART Interrupt Clear Register
355 * Read value is zero for this register, not the interrupt state.
356 */
357 union ody_uaax_icr {
358 uint32_t u;
359 struct ody_uaax_icr_s {
360 uint32_t rimic : 1;
361 uint32_t ctsmic : 1;
362 uint32_t dcdmic : 1;
363 uint32_t dsrmic : 1;
364 uint32_t rxic : 1;
365 uint32_t txic : 1;
366 uint32_t rtic : 1;
367 uint32_t feic : 1;
368 uint32_t peic : 1;
369 uint32_t beic : 1;
370 uint32_t oeic : 1;
371 uint32_t reserved_11_31 : 21;
372 } s;
373 /* struct ody_uaax_icr_s cn; */
374 };
375 typedef union ody_uaax_icr ody_uaax_icr_t;
376
377 static inline uint64_t ODY_UAAX_ICR(uint64_t a) __attribute__ ((pure, always_inline));
ODY_UAAX_ICR(uint64_t a)378 static inline uint64_t ODY_UAAX_ICR(uint64_t a)
379 {
380 if (a <= 7)
381 return 0x87e028000044ll + 0x1000000ll * ((a) & 0x7);
382 __ody_csr_fatal("UAAX_ICR", 1, a, 0, 0, 0, 0, 0);
383 }
384
385 #define typedef_ODY_UAAX_ICR(a) ody_uaax_icr_t
386 #define bustype_ODY_UAAX_ICR(a) CSR_TYPE_RSL32b
387 #define basename_ODY_UAAX_ICR(a) "UAAX_ICR"
388 #define device_bar_ODY_UAAX_ICR(a) 0x0 /* PF_BAR0 */
389 #define busnum_ODY_UAAX_ICR(a) (a)
390 #define arguments_ODY_UAAX_ICR(a) (a), -1, -1, -1
391
392 /**
393 * Register (RSL32b) uaa#_ifls
394 *
395 * UART Interrupt FIFO Level Select Register
396 */
397 union ody_uaax_ifls {
398 uint32_t u;
399 struct ody_uaax_ifls_s {
400 uint32_t txiflsel : 3;
401 uint32_t rxiflsel : 3;
402 uint32_t reserved_6_31 : 26;
403 } s;
404 /* struct ody_uaax_ifls_s cn; */
405 };
406 typedef union ody_uaax_ifls ody_uaax_ifls_t;
407
408 static inline uint64_t ODY_UAAX_IFLS(uint64_t a) __attribute__ ((pure, always_inline));
ODY_UAAX_IFLS(uint64_t a)409 static inline uint64_t ODY_UAAX_IFLS(uint64_t a)
410 {
411 if (a <= 7)
412 return 0x87e028000034ll + 0x1000000ll * ((a) & 0x7);
413 __ody_csr_fatal("UAAX_IFLS", 1, a, 0, 0, 0, 0, 0);
414 }
415
416 #define typedef_ODY_UAAX_IFLS(a) ody_uaax_ifls_t
417 #define bustype_ODY_UAAX_IFLS(a) CSR_TYPE_RSL32b
418 #define basename_ODY_UAAX_IFLS(a) "UAAX_IFLS"
419 #define device_bar_ODY_UAAX_IFLS(a) 0x0 /* PF_BAR0 */
420 #define busnum_ODY_UAAX_IFLS(a) (a)
421 #define arguments_ODY_UAAX_IFLS(a) (a), -1, -1, -1
422
423 /**
424 * Register (RSL32b) uaa#_imsc
425 *
426 * UART Interrupt Mask Set/Clear Register
427 */
428 union ody_uaax_imsc {
429 uint32_t u;
430 struct ody_uaax_imsc_s {
431 uint32_t rimim : 1;
432 uint32_t ctsmim : 1;
433 uint32_t dcdmim : 1;
434 uint32_t dsrmim : 1;
435 uint32_t rxim : 1;
436 uint32_t txim : 1;
437 uint32_t rtim : 1;
438 uint32_t feim : 1;
439 uint32_t peim : 1;
440 uint32_t beim : 1;
441 uint32_t oeim : 1;
442 uint32_t reserved_11_31 : 21;
443 } s;
444 /* struct ody_uaax_imsc_s cn; */
445 };
446 typedef union ody_uaax_imsc ody_uaax_imsc_t;
447
448 static inline uint64_t ODY_UAAX_IMSC(uint64_t a) __attribute__ ((pure, always_inline));
ODY_UAAX_IMSC(uint64_t a)449 static inline uint64_t ODY_UAAX_IMSC(uint64_t a)
450 {
451 if (a <= 7)
452 return 0x87e028000038ll + 0x1000000ll * ((a) & 0x7);
453 __ody_csr_fatal("UAAX_IMSC", 1, a, 0, 0, 0, 0, 0);
454 }
455
456 #define typedef_ODY_UAAX_IMSC(a) ody_uaax_imsc_t
457 #define bustype_ODY_UAAX_IMSC(a) CSR_TYPE_RSL32b
458 #define basename_ODY_UAAX_IMSC(a) "UAAX_IMSC"
459 #define device_bar_ODY_UAAX_IMSC(a) 0x0 /* PF_BAR0 */
460 #define busnum_ODY_UAAX_IMSC(a) (a)
461 #define arguments_ODY_UAAX_IMSC(a) (a), -1, -1, -1
462
463 /**
464 * Register (RSL) uaa#_io_ctl
465 *
466 * UART IO Control Register
467 * This register controls the UAA[0..1] IO drive strength and slew rates. The additional
468 * UAA interfaces are controlled by GPIO_IO_CTL[DRIVEx] and GPIO_IO_CTL[SLEWx] based
469 * on the selected pins.
470 */
471 union ody_uaax_io_ctl {
472 uint64_t u;
473 struct ody_uaax_io_ctl_s {
474 uint64_t slew : 2;
475 uint64_t drive : 2;
476 uint64_t reserved_4_63 : 60;
477 } s;
478 /* struct ody_uaax_io_ctl_s cn; */
479 };
480 typedef union ody_uaax_io_ctl ody_uaax_io_ctl_t;
481
482 static inline uint64_t ODY_UAAX_IO_CTL(uint64_t a) __attribute__ ((pure, always_inline));
ODY_UAAX_IO_CTL(uint64_t a)483 static inline uint64_t ODY_UAAX_IO_CTL(uint64_t a)
484 {
485 if (a <= 7)
486 return 0x87e028001028ll + 0x1000000ll * ((a) & 0x7);
487 __ody_csr_fatal("UAAX_IO_CTL", 1, a, 0, 0, 0, 0, 0);
488 }
489
490 #define typedef_ODY_UAAX_IO_CTL(a) ody_uaax_io_ctl_t
491 #define bustype_ODY_UAAX_IO_CTL(a) CSR_TYPE_RSL
492 #define basename_ODY_UAAX_IO_CTL(a) "UAAX_IO_CTL"
493 #define device_bar_ODY_UAAX_IO_CTL(a) 0x0 /* PF_BAR0 */
494 #define busnum_ODY_UAAX_IO_CTL(a) (a)
495 #define arguments_ODY_UAAX_IO_CTL(a) (a), -1, -1, -1
496
497 /**
498 * Register (RSL32b) uaa#_lcr_h
499 *
500 * UART Line Control Register
501 */
502 union ody_uaax_lcr_h {
503 uint32_t u;
504 struct ody_uaax_lcr_h_s {
505 uint32_t brk : 1;
506 uint32_t pen : 1;
507 uint32_t eps : 1;
508 uint32_t stp2 : 1;
509 uint32_t fen : 1;
510 uint32_t wlen : 2;
511 uint32_t sps : 1;
512 uint32_t reserved_8_31 : 24;
513 } s;
514 /* struct ody_uaax_lcr_h_s cn; */
515 };
516 typedef union ody_uaax_lcr_h ody_uaax_lcr_h_t;
517
518 static inline uint64_t ODY_UAAX_LCR_H(uint64_t a) __attribute__ ((pure, always_inline));
ODY_UAAX_LCR_H(uint64_t a)519 static inline uint64_t ODY_UAAX_LCR_H(uint64_t a)
520 {
521 if (a <= 7)
522 return 0x87e02800002cll + 0x1000000ll * ((a) & 0x7);
523 __ody_csr_fatal("UAAX_LCR_H", 1, a, 0, 0, 0, 0, 0);
524 }
525
526 #define typedef_ODY_UAAX_LCR_H(a) ody_uaax_lcr_h_t
527 #define bustype_ODY_UAAX_LCR_H(a) CSR_TYPE_RSL32b
528 #define basename_ODY_UAAX_LCR_H(a) "UAAX_LCR_H"
529 #define device_bar_ODY_UAAX_LCR_H(a) 0x0 /* PF_BAR0 */
530 #define busnum_ODY_UAAX_LCR_H(a) (a)
531 #define arguments_ODY_UAAX_LCR_H(a) (a), -1, -1, -1
532
533 /**
534 * Register (RSL32b) uaa#_mis
535 *
536 * UART Masked Interrupt Status Register
537 * Indicates state of interrupts after masking.
538 */
539 union ody_uaax_mis {
540 uint32_t u;
541 struct ody_uaax_mis_s {
542 uint32_t rimmis : 1;
543 uint32_t ctsmmis : 1;
544 uint32_t dcdmmis : 1;
545 uint32_t dsrmmis : 1;
546 uint32_t rxmis : 1;
547 uint32_t txmis : 1;
548 uint32_t rtmis : 1;
549 uint32_t femis : 1;
550 uint32_t pemis : 1;
551 uint32_t bemis : 1;
552 uint32_t oemis : 1;
553 uint32_t reserved_11_31 : 21;
554 } s;
555 /* struct ody_uaax_mis_s cn; */
556 };
557 typedef union ody_uaax_mis ody_uaax_mis_t;
558
559 static inline uint64_t ODY_UAAX_MIS(uint64_t a) __attribute__ ((pure, always_inline));
ODY_UAAX_MIS(uint64_t a)560 static inline uint64_t ODY_UAAX_MIS(uint64_t a)
561 {
562 if (a <= 7)
563 return 0x87e028000040ll + 0x1000000ll * ((a) & 0x7);
564 __ody_csr_fatal("UAAX_MIS", 1, a, 0, 0, 0, 0, 0);
565 }
566
567 #define typedef_ODY_UAAX_MIS(a) ody_uaax_mis_t
568 #define bustype_ODY_UAAX_MIS(a) CSR_TYPE_RSL32b
569 #define basename_ODY_UAAX_MIS(a) "UAAX_MIS"
570 #define device_bar_ODY_UAAX_MIS(a) 0x0 /* PF_BAR0 */
571 #define busnum_ODY_UAAX_MIS(a) (a)
572 #define arguments_ODY_UAAX_MIS(a) (a), -1, -1, -1
573
574 /**
575 * Register (RSL) uaa#_msix_pba#
576 *
577 * UART MSI-X Pending Bit Array Registers
578 * This register is the MSI-X PBA table, the bit number is indexed by the UAA_INT_VEC_E enumeration.
579 */
580 union ody_uaax_msix_pbax {
581 uint64_t u;
582 struct ody_uaax_msix_pbax_s {
583 uint64_t pend : 64;
584 } s;
585 /* struct ody_uaax_msix_pbax_s cn; */
586 };
587 typedef union ody_uaax_msix_pbax ody_uaax_msix_pbax_t;
588
589 static inline uint64_t ODY_UAAX_MSIX_PBAX(uint64_t a, uint64_t b) __attribute__ ((pure, always_inline));
ODY_UAAX_MSIX_PBAX(uint64_t a,uint64_t b)590 static inline uint64_t ODY_UAAX_MSIX_PBAX(uint64_t a, uint64_t b)
591 {
592 if ((a <= 7) && (b == 0))
593 return 0x87e028ff0000ll + 0x1000000ll * ((a) & 0x7);
594 __ody_csr_fatal("UAAX_MSIX_PBAX", 2, a, b, 0, 0, 0, 0);
595 }
596
597 #define typedef_ODY_UAAX_MSIX_PBAX(a, b) ody_uaax_msix_pbax_t
598 #define bustype_ODY_UAAX_MSIX_PBAX(a, b) CSR_TYPE_RSL
599 #define basename_ODY_UAAX_MSIX_PBAX(a, b) "UAAX_MSIX_PBAX"
600 #define device_bar_ODY_UAAX_MSIX_PBAX(a, b) 0x4 /* PF_BAR4 */
601 #define busnum_ODY_UAAX_MSIX_PBAX(a, b) (a)
602 #define arguments_ODY_UAAX_MSIX_PBAX(a, b) (a), (b), -1, -1
603
604 /**
605 * Register (RSL) uaa#_msix_vec#_addr
606 *
607 * UART MSI-X Vector Table Address Registers
608 * This register is the MSI-X vector table, indexed by the UAA_INT_VEC_E enumeration.
609 */
610 union ody_uaax_msix_vecx_addr {
611 uint64_t u;
612 struct ody_uaax_msix_vecx_addr_s {
613 uint64_t secvec : 1;
614 uint64_t reserved_1 : 1;
615 uint64_t addr : 51;
616 uint64_t reserved_53_63 : 11;
617 } s;
618 /* struct ody_uaax_msix_vecx_addr_s cn; */
619 };
620 typedef union ody_uaax_msix_vecx_addr ody_uaax_msix_vecx_addr_t;
621
622 static inline uint64_t ODY_UAAX_MSIX_VECX_ADDR(uint64_t a, uint64_t b) __attribute__ ((pure, always_inline));
ODY_UAAX_MSIX_VECX_ADDR(uint64_t a,uint64_t b)623 static inline uint64_t ODY_UAAX_MSIX_VECX_ADDR(uint64_t a, uint64_t b)
624 {
625 if ((a <= 7) && (b <= 1))
626 return 0x87e028f00000ll + 0x1000000ll * ((a) & 0x7) + 0x10ll * ((b) & 0x1);
627 __ody_csr_fatal("UAAX_MSIX_VECX_ADDR", 2, a, b, 0, 0, 0, 0);
628 }
629
630 #define typedef_ODY_UAAX_MSIX_VECX_ADDR(a, b) ody_uaax_msix_vecx_addr_t
631 #define bustype_ODY_UAAX_MSIX_VECX_ADDR(a, b) CSR_TYPE_RSL
632 #define basename_ODY_UAAX_MSIX_VECX_ADDR(a, b) "UAAX_MSIX_VECX_ADDR"
633 #define device_bar_ODY_UAAX_MSIX_VECX_ADDR(a, b) 0x4 /* PF_BAR4 */
634 #define busnum_ODY_UAAX_MSIX_VECX_ADDR(a, b) (a)
635 #define arguments_ODY_UAAX_MSIX_VECX_ADDR(a, b) (a), (b), -1, -1
636
637 /**
638 * Register (RSL) uaa#_msix_vec#_ctl
639 *
640 * UART MSI-X Vector Table Control and Data Registers
641 * This register is the MSI-X vector table, indexed by the UAA_INT_VEC_E enumeration.
642 */
643 union ody_uaax_msix_vecx_ctl {
644 uint64_t u;
645 struct ody_uaax_msix_vecx_ctl_s {
646 uint64_t data : 32;
647 uint64_t mask : 1;
648 uint64_t reserved_33_63 : 31;
649 } s;
650 /* struct ody_uaax_msix_vecx_ctl_s cn; */
651 };
652 typedef union ody_uaax_msix_vecx_ctl ody_uaax_msix_vecx_ctl_t;
653
654 static inline uint64_t ODY_UAAX_MSIX_VECX_CTL(uint64_t a, uint64_t b) __attribute__ ((pure, always_inline));
ODY_UAAX_MSIX_VECX_CTL(uint64_t a,uint64_t b)655 static inline uint64_t ODY_UAAX_MSIX_VECX_CTL(uint64_t a, uint64_t b)
656 {
657 if ((a <= 7) && (b <= 1))
658 return 0x87e028f00008ll + 0x1000000ll * ((a) & 0x7) + 0x10ll * ((b) & 0x1);
659 __ody_csr_fatal("UAAX_MSIX_VECX_CTL", 2, a, b, 0, 0, 0, 0);
660 }
661
662 #define typedef_ODY_UAAX_MSIX_VECX_CTL(a, b) ody_uaax_msix_vecx_ctl_t
663 #define bustype_ODY_UAAX_MSIX_VECX_CTL(a, b) CSR_TYPE_RSL
664 #define basename_ODY_UAAX_MSIX_VECX_CTL(a, b) "UAAX_MSIX_VECX_CTL"
665 #define device_bar_ODY_UAAX_MSIX_VECX_CTL(a, b) 0x4 /* PF_BAR4 */
666 #define busnum_ODY_UAAX_MSIX_VECX_CTL(a, b) (a)
667 #define arguments_ODY_UAAX_MSIX_VECX_CTL(a, b) (a), (b), -1, -1
668
669 /**
670 * Register (RSL32b) uaa#_pidr0
671 *
672 * UART Component Identification Register 0
673 */
674 union ody_uaax_pidr0 {
675 uint32_t u;
676 struct ody_uaax_pidr0_s {
677 uint32_t partnum0 : 8;
678 uint32_t reserved_8_31 : 24;
679 } s;
680 /* struct ody_uaax_pidr0_s cn; */
681 };
682 typedef union ody_uaax_pidr0 ody_uaax_pidr0_t;
683
684 static inline uint64_t ODY_UAAX_PIDR0(uint64_t a) __attribute__ ((pure, always_inline));
ODY_UAAX_PIDR0(uint64_t a)685 static inline uint64_t ODY_UAAX_PIDR0(uint64_t a)
686 {
687 if (a <= 7)
688 return 0x87e028000fe0ll + 0x1000000ll * ((a) & 0x7);
689 __ody_csr_fatal("UAAX_PIDR0", 1, a, 0, 0, 0, 0, 0);
690 }
691
692 #define typedef_ODY_UAAX_PIDR0(a) ody_uaax_pidr0_t
693 #define bustype_ODY_UAAX_PIDR0(a) CSR_TYPE_RSL32b
694 #define basename_ODY_UAAX_PIDR0(a) "UAAX_PIDR0"
695 #define device_bar_ODY_UAAX_PIDR0(a) 0x0 /* PF_BAR0 */
696 #define busnum_ODY_UAAX_PIDR0(a) (a)
697 #define arguments_ODY_UAAX_PIDR0(a) (a), -1, -1, -1
698
699 /**
700 * Register (RSL32b) uaa#_pidr1
701 *
702 * UART Peripheral Identification Register 1
703 */
704 union ody_uaax_pidr1 {
705 uint32_t u;
706 struct ody_uaax_pidr1_s {
707 uint32_t partnum1 : 4;
708 uint32_t idcode : 4;
709 uint32_t reserved_8_31 : 24;
710 } s;
711 /* struct ody_uaax_pidr1_s cn; */
712 };
713 typedef union ody_uaax_pidr1 ody_uaax_pidr1_t;
714
715 static inline uint64_t ODY_UAAX_PIDR1(uint64_t a) __attribute__ ((pure, always_inline));
ODY_UAAX_PIDR1(uint64_t a)716 static inline uint64_t ODY_UAAX_PIDR1(uint64_t a)
717 {
718 if (a <= 7)
719 return 0x87e028000fe4ll + 0x1000000ll * ((a) & 0x7);
720 __ody_csr_fatal("UAAX_PIDR1", 1, a, 0, 0, 0, 0, 0);
721 }
722
723 #define typedef_ODY_UAAX_PIDR1(a) ody_uaax_pidr1_t
724 #define bustype_ODY_UAAX_PIDR1(a) CSR_TYPE_RSL32b
725 #define basename_ODY_UAAX_PIDR1(a) "UAAX_PIDR1"
726 #define device_bar_ODY_UAAX_PIDR1(a) 0x0 /* PF_BAR0 */
727 #define busnum_ODY_UAAX_PIDR1(a) (a)
728 #define arguments_ODY_UAAX_PIDR1(a) (a), -1, -1, -1
729
730 /**
731 * Register (RSL32b) uaa#_pidr2
732 *
733 * UART Peripheral Identification Register 2
734 */
735 union ody_uaax_pidr2 {
736 uint32_t u;
737 struct ody_uaax_pidr2_s {
738 uint32_t idcode : 3;
739 uint32_t jedec : 1;
740 uint32_t revision : 4;
741 uint32_t reserved_8_31 : 24;
742 } s;
743 /* struct ody_uaax_pidr2_s cn; */
744 };
745 typedef union ody_uaax_pidr2 ody_uaax_pidr2_t;
746
747 static inline uint64_t ODY_UAAX_PIDR2(uint64_t a) __attribute__ ((pure, always_inline));
ODY_UAAX_PIDR2(uint64_t a)748 static inline uint64_t ODY_UAAX_PIDR2(uint64_t a)
749 {
750 if (a <= 7)
751 return 0x87e028000fe8ll + 0x1000000ll * ((a) & 0x7);
752 __ody_csr_fatal("UAAX_PIDR2", 1, a, 0, 0, 0, 0, 0);
753 }
754
755 #define typedef_ODY_UAAX_PIDR2(a) ody_uaax_pidr2_t
756 #define bustype_ODY_UAAX_PIDR2(a) CSR_TYPE_RSL32b
757 #define basename_ODY_UAAX_PIDR2(a) "UAAX_PIDR2"
758 #define device_bar_ODY_UAAX_PIDR2(a) 0x0 /* PF_BAR0 */
759 #define busnum_ODY_UAAX_PIDR2(a) (a)
760 #define arguments_ODY_UAAX_PIDR2(a) (a), -1, -1, -1
761
762 /**
763 * Register (RSL32b) uaa#_pidr3
764 *
765 * UART Peripheral Identification Register 3
766 */
767 union ody_uaax_pidr3 {
768 uint32_t u;
769 struct ody_uaax_pidr3_s {
770 uint32_t cust : 4;
771 uint32_t revand : 4;
772 uint32_t reserved_8_31 : 24;
773 } s;
774 /* struct ody_uaax_pidr3_s cn; */
775 };
776 typedef union ody_uaax_pidr3 ody_uaax_pidr3_t;
777
778 static inline uint64_t ODY_UAAX_PIDR3(uint64_t a) __attribute__ ((pure, always_inline));
ODY_UAAX_PIDR3(uint64_t a)779 static inline uint64_t ODY_UAAX_PIDR3(uint64_t a)
780 {
781 if (a <= 7)
782 return 0x87e028000fecll + 0x1000000ll * ((a) & 0x7);
783 __ody_csr_fatal("UAAX_PIDR3", 1, a, 0, 0, 0, 0, 0);
784 }
785
786 #define typedef_ODY_UAAX_PIDR3(a) ody_uaax_pidr3_t
787 #define bustype_ODY_UAAX_PIDR3(a) CSR_TYPE_RSL32b
788 #define basename_ODY_UAAX_PIDR3(a) "UAAX_PIDR3"
789 #define device_bar_ODY_UAAX_PIDR3(a) 0x0 /* PF_BAR0 */
790 #define busnum_ODY_UAAX_PIDR3(a) (a)
791 #define arguments_ODY_UAAX_PIDR3(a) (a), -1, -1, -1
792
793 /**
794 * Register (RSL32b) uaa#_pidr4
795 *
796 * UART Peripheral Identification Register 4
797 */
798 union ody_uaax_pidr4 {
799 uint32_t u;
800 struct ody_uaax_pidr4_s {
801 uint32_t reserved_0_31 : 32;
802 } s;
803 /* struct ody_uaax_pidr4_s cn; */
804 };
805 typedef union ody_uaax_pidr4 ody_uaax_pidr4_t;
806
807 static inline uint64_t ODY_UAAX_PIDR4(uint64_t a) __attribute__ ((pure, always_inline));
ODY_UAAX_PIDR4(uint64_t a)808 static inline uint64_t ODY_UAAX_PIDR4(uint64_t a)
809 {
810 if (a <= 7)
811 return 0x87e028000fd0ll + 0x1000000ll * ((a) & 0x7);
812 __ody_csr_fatal("UAAX_PIDR4", 1, a, 0, 0, 0, 0, 0);
813 }
814
815 #define typedef_ODY_UAAX_PIDR4(a) ody_uaax_pidr4_t
816 #define bustype_ODY_UAAX_PIDR4(a) CSR_TYPE_RSL32b
817 #define basename_ODY_UAAX_PIDR4(a) "UAAX_PIDR4"
818 #define device_bar_ODY_UAAX_PIDR4(a) 0x0 /* PF_BAR0 */
819 #define busnum_ODY_UAAX_PIDR4(a) (a)
820 #define arguments_ODY_UAAX_PIDR4(a) (a), -1, -1, -1
821
822 /**
823 * Register (RSL32b) uaa#_pidr5
824 *
825 * UART Peripheral Identification Register 5
826 */
827 union ody_uaax_pidr5 {
828 uint32_t u;
829 struct ody_uaax_pidr5_s {
830 uint32_t reserved_0_31 : 32;
831 } s;
832 /* struct ody_uaax_pidr5_s cn; */
833 };
834 typedef union ody_uaax_pidr5 ody_uaax_pidr5_t;
835
836 static inline uint64_t ODY_UAAX_PIDR5(uint64_t a) __attribute__ ((pure, always_inline));
ODY_UAAX_PIDR5(uint64_t a)837 static inline uint64_t ODY_UAAX_PIDR5(uint64_t a)
838 {
839 if (a <= 7)
840 return 0x87e028000fd4ll + 0x1000000ll * ((a) & 0x7);
841 __ody_csr_fatal("UAAX_PIDR5", 1, a, 0, 0, 0, 0, 0);
842 }
843
844 #define typedef_ODY_UAAX_PIDR5(a) ody_uaax_pidr5_t
845 #define bustype_ODY_UAAX_PIDR5(a) CSR_TYPE_RSL32b
846 #define basename_ODY_UAAX_PIDR5(a) "UAAX_PIDR5"
847 #define device_bar_ODY_UAAX_PIDR5(a) 0x0 /* PF_BAR0 */
848 #define busnum_ODY_UAAX_PIDR5(a) (a)
849 #define arguments_ODY_UAAX_PIDR5(a) (a), -1, -1, -1
850
851 /**
852 * Register (RSL32b) uaa#_pidr6
853 *
854 * UART Peripheral Identification Register 6
855 */
856 union ody_uaax_pidr6 {
857 uint32_t u;
858 struct ody_uaax_pidr6_s {
859 uint32_t reserved_0_31 : 32;
860 } s;
861 /* struct ody_uaax_pidr6_s cn; */
862 };
863 typedef union ody_uaax_pidr6 ody_uaax_pidr6_t;
864
865 static inline uint64_t ODY_UAAX_PIDR6(uint64_t a) __attribute__ ((pure, always_inline));
ODY_UAAX_PIDR6(uint64_t a)866 static inline uint64_t ODY_UAAX_PIDR6(uint64_t a)
867 {
868 if (a <= 7)
869 return 0x87e028000fd8ll + 0x1000000ll * ((a) & 0x7);
870 __ody_csr_fatal("UAAX_PIDR6", 1, a, 0, 0, 0, 0, 0);
871 }
872
873 #define typedef_ODY_UAAX_PIDR6(a) ody_uaax_pidr6_t
874 #define bustype_ODY_UAAX_PIDR6(a) CSR_TYPE_RSL32b
875 #define basename_ODY_UAAX_PIDR6(a) "UAAX_PIDR6"
876 #define device_bar_ODY_UAAX_PIDR6(a) 0x0 /* PF_BAR0 */
877 #define busnum_ODY_UAAX_PIDR6(a) (a)
878 #define arguments_ODY_UAAX_PIDR6(a) (a), -1, -1, -1
879
880 /**
881 * Register (RSL32b) uaa#_pidr7
882 *
883 * UART Peripheral Identification Register 7
884 */
885 union ody_uaax_pidr7 {
886 uint32_t u;
887 struct ody_uaax_pidr7_s {
888 uint32_t reserved_0_31 : 32;
889 } s;
890 /* struct ody_uaax_pidr7_s cn; */
891 };
892 typedef union ody_uaax_pidr7 ody_uaax_pidr7_t;
893
894 static inline uint64_t ODY_UAAX_PIDR7(uint64_t a) __attribute__ ((pure, always_inline));
ODY_UAAX_PIDR7(uint64_t a)895 static inline uint64_t ODY_UAAX_PIDR7(uint64_t a)
896 {
897 if (a <= 7)
898 return 0x87e028000fdcll + 0x1000000ll * ((a) & 0x7);
899 __ody_csr_fatal("UAAX_PIDR7", 1, a, 0, 0, 0, 0, 0);
900 }
901
902 #define typedef_ODY_UAAX_PIDR7(a) ody_uaax_pidr7_t
903 #define bustype_ODY_UAAX_PIDR7(a) CSR_TYPE_RSL32b
904 #define basename_ODY_UAAX_PIDR7(a) "UAAX_PIDR7"
905 #define device_bar_ODY_UAAX_PIDR7(a) 0x0 /* PF_BAR0 */
906 #define busnum_ODY_UAAX_PIDR7(a) (a)
907 #define arguments_ODY_UAAX_PIDR7(a) (a), -1, -1, -1
908
909 /**
910 * Register (RSL) uaa#_redirect
911 *
912 * UART REDIRECT Control Register
913 */
914 union ody_uaax_redirect {
915 uint64_t u;
916 struct ody_uaax_redirect_s {
917 uint64_t in_sel : 3;
918 uint64_t in_ena : 1;
919 uint64_t out_dis : 1;
920 uint64_t reserved_5_63 : 59;
921 } s;
922 /* struct ody_uaax_redirect_s cn; */
923 };
924 typedef union ody_uaax_redirect ody_uaax_redirect_t;
925
926 static inline uint64_t ODY_UAAX_REDIRECT(uint64_t a) __attribute__ ((pure, always_inline));
ODY_UAAX_REDIRECT(uint64_t a)927 static inline uint64_t ODY_UAAX_REDIRECT(uint64_t a)
928 {
929 if (a <= 7)
930 return 0x87e028001020ll + 0x1000000ll * ((a) & 0x7);
931 __ody_csr_fatal("UAAX_REDIRECT", 1, a, 0, 0, 0, 0, 0);
932 }
933
934 #define typedef_ODY_UAAX_REDIRECT(a) ody_uaax_redirect_t
935 #define bustype_ODY_UAAX_REDIRECT(a) CSR_TYPE_RSL
936 #define basename_ODY_UAAX_REDIRECT(a) "UAAX_REDIRECT"
937 #define device_bar_ODY_UAAX_REDIRECT(a) 0x0 /* PF_BAR0 */
938 #define busnum_ODY_UAAX_REDIRECT(a) (a)
939 #define arguments_ODY_UAAX_REDIRECT(a) (a), -1, -1, -1
940
941 /**
942 * Register (RSL32b) uaa#_ris
943 *
944 * UART Raw Interrupt Status Register
945 * Indicates state of interrupts before masking.
946 */
947 union ody_uaax_ris {
948 uint32_t u;
949 struct ody_uaax_ris_s {
950 uint32_t rirmis : 1;
951 uint32_t ctsrmis : 1;
952 uint32_t dcdrmis : 1;
953 uint32_t dsrrmis : 1;
954 uint32_t rxris : 1;
955 uint32_t txris : 1;
956 uint32_t rtris : 1;
957 uint32_t feris : 1;
958 uint32_t peris : 1;
959 uint32_t beris : 1;
960 uint32_t oeris : 1;
961 uint32_t reserved_11_31 : 21;
962 } s;
963 /* struct ody_uaax_ris_s cn; */
964 };
965 typedef union ody_uaax_ris ody_uaax_ris_t;
966
967 static inline uint64_t ODY_UAAX_RIS(uint64_t a) __attribute__ ((pure, always_inline));
ODY_UAAX_RIS(uint64_t a)968 static inline uint64_t ODY_UAAX_RIS(uint64_t a)
969 {
970 if (a <= 7)
971 return 0x87e02800003cll + 0x1000000ll * ((a) & 0x7);
972 __ody_csr_fatal("UAAX_RIS", 1, a, 0, 0, 0, 0, 0);
973 }
974
975 #define typedef_ODY_UAAX_RIS(a) ody_uaax_ris_t
976 #define bustype_ODY_UAAX_RIS(a) CSR_TYPE_RSL32b
977 #define basename_ODY_UAAX_RIS(a) "UAAX_RIS"
978 #define device_bar_ODY_UAAX_RIS(a) 0x0 /* PF_BAR0 */
979 #define busnum_ODY_UAAX_RIS(a) (a)
980 #define arguments_ODY_UAAX_RIS(a) (a), -1, -1, -1
981
982 /**
983 * Register (RSL32b) uaa#_rsr_ecr
984 *
985 * UART Receive Status Register/Error Clear Register
986 */
987 union ody_uaax_rsr_ecr {
988 uint32_t u;
989 struct ody_uaax_rsr_ecr_s {
990 uint32_t fe : 1;
991 uint32_t pe : 1;
992 uint32_t be : 1;
993 uint32_t oe : 1;
994 uint32_t reserved_4_31 : 28;
995 } s;
996 /* struct ody_uaax_rsr_ecr_s cn; */
997 };
998 typedef union ody_uaax_rsr_ecr ody_uaax_rsr_ecr_t;
999
1000 static inline uint64_t ODY_UAAX_RSR_ECR(uint64_t a) __attribute__ ((pure, always_inline));
ODY_UAAX_RSR_ECR(uint64_t a)1001 static inline uint64_t ODY_UAAX_RSR_ECR(uint64_t a)
1002 {
1003 if (a <= 7)
1004 return 0x87e028000004ll + 0x1000000ll * ((a) & 0x7);
1005 __ody_csr_fatal("UAAX_RSR_ECR", 1, a, 0, 0, 0, 0, 0);
1006 }
1007
1008 #define typedef_ODY_UAAX_RSR_ECR(a) ody_uaax_rsr_ecr_t
1009 #define bustype_ODY_UAAX_RSR_ECR(a) CSR_TYPE_RSL32b
1010 #define basename_ODY_UAAX_RSR_ECR(a) "UAAX_RSR_ECR"
1011 #define device_bar_ODY_UAAX_RSR_ECR(a) 0x0 /* PF_BAR0 */
1012 #define busnum_ODY_UAAX_RSR_ECR(a) (a)
1013 #define arguments_ODY_UAAX_RSR_ECR(a) (a), -1, -1, -1
1014
1015 /**
1016 * Register (RSL) uaa#_uctl_csclk_active_pc
1017 *
1018 * UAA UCTL Conditional Clock Counter Register
1019 * This register counts conditional clocks, for power analysis.
1020 * Reset by RSL reset.
1021 */
1022 union ody_uaax_uctl_csclk_active_pc {
1023 uint64_t u;
1024 struct ody_uaax_uctl_csclk_active_pc_s {
1025 uint64_t count : 64;
1026 } s;
1027 /* struct ody_uaax_uctl_csclk_active_pc_s cn; */
1028 };
1029 typedef union ody_uaax_uctl_csclk_active_pc ody_uaax_uctl_csclk_active_pc_t;
1030
1031 static inline uint64_t ODY_UAAX_UCTL_CSCLK_ACTIVE_PC(uint64_t a) __attribute__ ((pure, always_inline));
ODY_UAAX_UCTL_CSCLK_ACTIVE_PC(uint64_t a)1032 static inline uint64_t ODY_UAAX_UCTL_CSCLK_ACTIVE_PC(uint64_t a)
1033 {
1034 if (a <= 7)
1035 return 0x87e028001018ll + 0x1000000ll * ((a) & 0x7);
1036 __ody_csr_fatal("UAAX_UCTL_CSCLK_ACTIVE_PC", 1, a, 0, 0, 0, 0, 0);
1037 }
1038
1039 #define typedef_ODY_UAAX_UCTL_CSCLK_ACTIVE_PC(a) ody_uaax_uctl_csclk_active_pc_t
1040 #define bustype_ODY_UAAX_UCTL_CSCLK_ACTIVE_PC(a) CSR_TYPE_RSL
1041 #define basename_ODY_UAAX_UCTL_CSCLK_ACTIVE_PC(a) "UAAX_UCTL_CSCLK_ACTIVE_PC"
1042 #define device_bar_ODY_UAAX_UCTL_CSCLK_ACTIVE_PC(a) 0x0 /* PF_BAR0 */
1043 #define busnum_ODY_UAAX_UCTL_CSCLK_ACTIVE_PC(a) (a)
1044 #define arguments_ODY_UAAX_UCTL_CSCLK_ACTIVE_PC(a) (a), -1, -1, -1
1045
1046 /**
1047 * Register (RSL) uaa#_uctl_ctl
1048 *
1049 * UART UCTL Control Register
1050 */
1051 union ody_uaax_uctl_ctl {
1052 uint64_t u;
1053 struct ody_uaax_uctl_ctl_s {
1054 uint64_t uctl_rst : 1;
1055 uint64_t uaa_rst : 1;
1056 uint64_t reserved_2_3 : 2;
1057 uint64_t csclk_en : 1;
1058 uint64_t reserved_5_23 : 19;
1059 uint64_t h_clkdiv_sel : 3;
1060 uint64_t reserved_27 : 1;
1061 uint64_t h_clkdiv_rst : 1;
1062 uint64_t h_clk_byp_sel : 1;
1063 uint64_t h_clk_en : 1;
1064 uint64_t reserved_31_63 : 33;
1065 } s;
1066 /* struct ody_uaax_uctl_ctl_s cn; */
1067 };
1068 typedef union ody_uaax_uctl_ctl ody_uaax_uctl_ctl_t;
1069
1070 static inline uint64_t ODY_UAAX_UCTL_CTL(uint64_t a) __attribute__ ((pure, always_inline));
ODY_UAAX_UCTL_CTL(uint64_t a)1071 static inline uint64_t ODY_UAAX_UCTL_CTL(uint64_t a)
1072 {
1073 if (a <= 7)
1074 return 0x87e028001000ll + 0x1000000ll * ((a) & 0x7);
1075 __ody_csr_fatal("UAAX_UCTL_CTL", 1, a, 0, 0, 0, 0, 0);
1076 }
1077
1078 #define typedef_ODY_UAAX_UCTL_CTL(a) ody_uaax_uctl_ctl_t
1079 #define bustype_ODY_UAAX_UCTL_CTL(a) CSR_TYPE_RSL
1080 #define basename_ODY_UAAX_UCTL_CTL(a) "UAAX_UCTL_CTL"
1081 #define device_bar_ODY_UAAX_UCTL_CTL(a) 0x0 /* PF_BAR0 */
1082 #define busnum_ODY_UAAX_UCTL_CTL(a) (a)
1083 #define arguments_ODY_UAAX_UCTL_CTL(a) (a), -1, -1, -1
1084
1085 /**
1086 * Register (RSL) uaa#_uctl_spare0
1087 *
1088 * UART UCTL Spare Register 0
1089 * This register is a spare register. This register can be reset by NCB reset.
1090 */
1091 union ody_uaax_uctl_spare0 {
1092 uint64_t u;
1093 struct ody_uaax_uctl_spare0_s {
1094 uint64_t spare : 64;
1095 } s;
1096 /* struct ody_uaax_uctl_spare0_s cn; */
1097 };
1098 typedef union ody_uaax_uctl_spare0 ody_uaax_uctl_spare0_t;
1099
1100 static inline uint64_t ODY_UAAX_UCTL_SPARE0(uint64_t a) __attribute__ ((pure, always_inline));
ODY_UAAX_UCTL_SPARE0(uint64_t a)1101 static inline uint64_t ODY_UAAX_UCTL_SPARE0(uint64_t a)
1102 {
1103 if (a <= 7)
1104 return 0x87e028001010ll + 0x1000000ll * ((a) & 0x7);
1105 __ody_csr_fatal("UAAX_UCTL_SPARE0", 1, a, 0, 0, 0, 0, 0);
1106 }
1107
1108 #define typedef_ODY_UAAX_UCTL_SPARE0(a) ody_uaax_uctl_spare0_t
1109 #define bustype_ODY_UAAX_UCTL_SPARE0(a) CSR_TYPE_RSL
1110 #define basename_ODY_UAAX_UCTL_SPARE0(a) "UAAX_UCTL_SPARE0"
1111 #define device_bar_ODY_UAAX_UCTL_SPARE0(a) 0x0 /* PF_BAR0 */
1112 #define busnum_ODY_UAAX_UCTL_SPARE0(a) (a)
1113 #define arguments_ODY_UAAX_UCTL_SPARE0(a) (a), -1, -1, -1
1114
1115 /**
1116 * Register (RSL) uaa#_uctl_spare1
1117 *
1118 * UART UCTL Spare Register 1
1119 * This register is a spare register. This register can be reset by NCB reset.
1120 */
1121 union ody_uaax_uctl_spare1 {
1122 uint64_t u;
1123 struct ody_uaax_uctl_spare1_s {
1124 uint64_t spare : 64;
1125 } s;
1126 /* struct ody_uaax_uctl_spare1_s cn; */
1127 };
1128 typedef union ody_uaax_uctl_spare1 ody_uaax_uctl_spare1_t;
1129
1130 static inline uint64_t ODY_UAAX_UCTL_SPARE1(uint64_t a) __attribute__ ((pure, always_inline));
ODY_UAAX_UCTL_SPARE1(uint64_t a)1131 static inline uint64_t ODY_UAAX_UCTL_SPARE1(uint64_t a)
1132 {
1133 if (a <= 7)
1134 return 0x87e0280010f8ll + 0x1000000ll * ((a) & 0x7);
1135 __ody_csr_fatal("UAAX_UCTL_SPARE1", 1, a, 0, 0, 0, 0, 0);
1136 }
1137
1138 #define typedef_ODY_UAAX_UCTL_SPARE1(a) ody_uaax_uctl_spare1_t
1139 #define bustype_ODY_UAAX_UCTL_SPARE1(a) CSR_TYPE_RSL
1140 #define basename_ODY_UAAX_UCTL_SPARE1(a) "UAAX_UCTL_SPARE1"
1141 #define device_bar_ODY_UAAX_UCTL_SPARE1(a) 0x0 /* PF_BAR0 */
1142 #define busnum_ODY_UAAX_UCTL_SPARE1(a) (a)
1143 #define arguments_ODY_UAAX_UCTL_SPARE1(a) (a), -1, -1, -1
1144
1145 #endif /* __ODY_CSRS_UAA_H__ */
1146