1 #ifndef __ODY_CSRS_GPIO_H__
2 #define __ODY_CSRS_GPIO_H__
3 /* This file is auto-generated. Do not edit */
4
5 /***********************license start***********************************
6 * Copyright (C) 2021-2026 Marvell.
7 * SPDX-License-Identifier: BSD-3-Clause
8 * https://spdx.org/licenses
9 ***********************license end**************************************/
10
11
12 /**
13 * @file
14 *
15 * Configuration and status register (CSR) address and type definitions for
16 * GPIO.
17 *
18 * This file is auto generated. Do not edit.
19 *
20 */
21
22 /**
23 * Enumeration gpio_assigned_pin_e
24 *
25 * GPIO Assigned Pin Number Enumeration
26 * Enumerates GPIO pin numbers which have certain dedicated hardware and boot usage. In
27 * general a given GPIO may be used for the purpose listed here, or for any other
28 * purpose that is not listed here. For example SPI0_IO0 must use GPIO16 (0x10) if the
29 * SPI IO0 function is needed, but if SPI IO0 is not needed GPIO16 is free for use, but
30 * GPIO16 could not be used for BOOT_WAIT as BOOT_WAIT is listed here as requiring
31 * GPIO10 (0xA).
32 */
33 #define ODY_GPIO_ASSIGNED_PIN_E_BOOT_COMPLETE (0xa)
34 #define ODY_GPIO_ASSIGNED_PIN_E_BOOT_REQ (9)
35 #define ODY_GPIO_ASSIGNED_PIN_E_BOOT_WAIT (0xe)
36 #define ODY_GPIO_ASSIGNED_PIN_E_FAIL_CODE (0xb)
37 #define ODY_GPIO_ASSIGNED_PIN_E_GSERP_PHY_SIF_JTG_CLK (0x35)
38 #define ODY_GPIO_ASSIGNED_PIN_E_GSERP_PHY_SIF_JTG_DEN (0x37)
39 #define ODY_GPIO_ASSIGNED_PIN_E_GSERP_PHY_SIF_JTG_DIN (0x34)
40 #define ODY_GPIO_ASSIGNED_PIN_E_GSERP_PHY_SIF_JTG_DOUT (0x36)
41 #define ODY_GPIO_ASSIGNED_PIN_E_I3C3_SCL (0x31)
42 #define ODY_GPIO_ASSIGNED_PIN_E_I3C3_SDA (0x30)
43 #define ODY_GPIO_ASSIGNED_PIN_E_I3C4_SCL (0x33)
44 #define ODY_GPIO_ASSIGNED_PIN_E_I3C4_SDA (0x32)
45 #define ODY_GPIO_ASSIGNED_PIN_E_MCAST_IRQ_0 (4)
46 #define ODY_GPIO_ASSIGNED_PIN_E_MCAST_IRQ_1 (5)
47 #define ODY_GPIO_ASSIGNED_PIN_E_MCAST_IRQ_2 (6)
48 #define ODY_GPIO_ASSIGNED_PIN_E_MCAST_IRQ_3 (7)
49 #define ODY_GPIO_ASSIGNED_PIN_E_PLL_LOCK (0x2d)
50 #define ODY_GPIO_ASSIGNED_PIN_E_SPI0_CLK (0x18)
51 #define ODY_GPIO_ASSIGNED_PIN_E_SPI0_CS0 (0x1a)
52 #define ODY_GPIO_ASSIGNED_PIN_E_SPI0_CS1 (0x1b)
53 #define ODY_GPIO_ASSIGNED_PIN_E_SPI0_CS2 (0x1c)
54 #define ODY_GPIO_ASSIGNED_PIN_E_SPI0_CS3 (0x1d)
55 #define ODY_GPIO_ASSIGNED_PIN_E_SPI0_DQS (0x19)
56 #define ODY_GPIO_ASSIGNED_PIN_E_SPI0_IO0 (0x10)
57 #define ODY_GPIO_ASSIGNED_PIN_E_SPI0_IO1 (0x11)
58 #define ODY_GPIO_ASSIGNED_PIN_E_SPI0_IO2 (0x12)
59 #define ODY_GPIO_ASSIGNED_PIN_E_SPI0_IO3 (0x13)
60 #define ODY_GPIO_ASSIGNED_PIN_E_SPI0_IO4 (0x14)
61 #define ODY_GPIO_ASSIGNED_PIN_E_SPI0_IO5 (0x15)
62 #define ODY_GPIO_ASSIGNED_PIN_E_SPI0_IO6 (0x16)
63 #define ODY_GPIO_ASSIGNED_PIN_E_SPI0_IO7 (0x17)
64 #define ODY_GPIO_ASSIGNED_PIN_E_SPI0_RESET (0x2f)
65 #define ODY_GPIO_ASSIGNED_PIN_E_SPI1_CLK (0x26)
66 #define ODY_GPIO_ASSIGNED_PIN_E_SPI1_CS0 (0x28)
67 #define ODY_GPIO_ASSIGNED_PIN_E_SPI1_CS1 (0x29)
68 #define ODY_GPIO_ASSIGNED_PIN_E_SPI1_CS2 (0x2a)
69 #define ODY_GPIO_ASSIGNED_PIN_E_SPI1_CS3 (0x2b)
70 #define ODY_GPIO_ASSIGNED_PIN_E_SPI1_DQS (0x27)
71 #define ODY_GPIO_ASSIGNED_PIN_E_SPI1_IO0 (0x1e)
72 #define ODY_GPIO_ASSIGNED_PIN_E_SPI1_IO1 (0x1f)
73 #define ODY_GPIO_ASSIGNED_PIN_E_SPI1_IO2 (0x20)
74 #define ODY_GPIO_ASSIGNED_PIN_E_SPI1_IO3 (0x21)
75 #define ODY_GPIO_ASSIGNED_PIN_E_SPI1_IO4 (0x22)
76 #define ODY_GPIO_ASSIGNED_PIN_E_SPI1_IO5 (0x23)
77 #define ODY_GPIO_ASSIGNED_PIN_E_SPI1_IO6 (0x24)
78 #define ODY_GPIO_ASSIGNED_PIN_E_SPI1_IO7 (0x25)
79 #define ODY_GPIO_ASSIGNED_PIN_E_SPI1_RESET (0x2c)
80
81 /**
82 * Enumeration gpio_bar_e
83 *
84 * GPIO Base Address Register Enumeration
85 * Enumerates the base address registers.
86 */
87 #define ODY_GPIO_BAR_E_GPIO_PF_BAR0 (0x803000000000ll)
88 #define ODY_GPIO_BAR_E_GPIO_PF_BAR0_SIZE 0x10000ull
89 #define ODY_GPIO_BAR_E_GPIO_PF_BAR4 (0x803000f00000ll)
90 #define ODY_GPIO_BAR_E_GPIO_PF_BAR4_SIZE 0x100000ull
91
92 /**
93 * Enumeration gpio_int_vec_e
94 *
95 * GPIO MSI-X Vector Enumeration
96 * Enumerates the MSI-X interrupt vectors.
97 */
98 #define ODY_GPIO_INT_VEC_E_INTR_PINX(a) (0x52 + 2 * (a))
99 #define ODY_GPIO_INT_VEC_E_INTR_PINX_CLEAR(a) (0x53 + 2 * (a))
100 #define ODY_GPIO_INT_VEC_E_MC_INTR1_PPX(a) (0x40 + (a))
101 #define ODY_GPIO_INT_VEC_E_MC_INTR_PPX(a) (0 + (a))
102
103 /**
104 * Enumeration gpio_pin_sel_e
105 *
106 * GPIO Pin Select Enumeration
107 * Enumerates the GPIO pin function selections for GPIO_BIT_CFG()[PIN_SEL].
108 *
109 * The GPIO pins can be configured as either input, output or input/output/bidirectional
110 * depending on the GPIO_PIN_SEL_E used as described in the value's description. When
111 * a GPIO pin is used as input, the value is provided to the described function, and is
112 * also readable via GPIO_RX_DAT.
113 *
114 * Multiple GPIO pins may not be configured to point to the same input encoding, or
115 * the input result is unpredictable (e.g. GPIO_BIT_CFG(1)[PIN_SEL] and
116 * GPIO_BIT_CFG(2)[PIN_SEL] cannot both be 0x80).
117 *
118 * If a given select is not assigned to any pin, then that virtual input receives a
119 * logical zero. E.g. if no GPIO_BIT_CFG()[PIN_SEL] has the value ::TIM_GPIO_CLK,
120 * then the GPIO will provide the TIM block's external clock input with the value of
121 * zero.
122 */
123 #define ODY_GPIO_PIN_SEL_E_BOOT_REQ (0x3e0)
124 #define ODY_GPIO_PIN_SEL_E_BOOT_WAIT (0x3e1)
125 #define ODY_GPIO_PIN_SEL_E_BTS_BFN_CLK (0x506)
126 #define ODY_GPIO_PIN_SEL_E_BTS_BFN_IN (0x505)
127 #define ODY_GPIO_PIN_SEL_E_BTS_BFN_OUT (0x510)
128 #define ODY_GPIO_PIN_SEL_E_BTS_CGBFN_OUT (0x50d)
129 #define ODY_GPIO_PIN_SEL_E_BTS_CGCLK_OUT (0x50e)
130 #define ODY_GPIO_PIN_SEL_E_BTS_CGTENMS_OUT (0x50c)
131 #define ODY_GPIO_PIN_SEL_E_BTS_DAC_CLK (0x511)
132 #define ODY_GPIO_PIN_SEL_E_BTS_EXTREFX_CLK(a) (0x500 + (a))
133 #define ODY_GPIO_PIN_SEL_E_BTS_PWM_DOUT (0x513)
134 #define ODY_GPIO_PIN_SEL_E_BTS_PWM_SCLK (0x512)
135 #define ODY_GPIO_PIN_SEL_E_BTS_RFP_IN (0x504)
136 #define ODY_GPIO_PIN_SEL_E_BTS_RFP_OUT (0x50f)
137 #define ODY_GPIO_PIN_SEL_E_BTS_TPX(a) (0x507 + (a))
138 #define ODY_GPIO_PIN_SEL_E_CORE_RESET_IN (0x480)
139 #define ODY_GPIO_PIN_SEL_E_CORE_RESET_OUT (0x481)
140 #define ODY_GPIO_PIN_SEL_E_GPIO_CLKX(a) (0x260 + (a))
141 #define ODY_GPIO_PIN_SEL_E_GPIO_CLK_SYNCEX(a) (3 + (a))
142 #define ODY_GPIO_PIN_SEL_E_GPIO_PTP_CKOUT (1)
143 #define ODY_GPIO_PIN_SEL_E_GPIO_PTP_PPS (2)
144 #define ODY_GPIO_PIN_SEL_E_GPIO_PTP_SYSCK (8)
145 #define ODY_GPIO_PIN_SEL_E_GPIO_SW (0)
146 #define ODY_GPIO_PIN_SEL_E_GSERPX_DTESTX(a, b) (0x5a0 + 0x10 * (a) + (b))
147 #define ODY_GPIO_PIN_SEL_E_GSERPX_GPIX(a, b) (0x670 + 8 * (a) + (b))
148 #define ODY_GPIO_PIN_SEL_E_GSERPX_GPOX(a, b) (0x6e0 + 8 * (a) + (b))
149 #define ODY_GPIO_PIN_SEL_E_GSERPX_PHY_SIF_INX(a, b) (0x520 + 3 * (a) + (b))
150 #define ODY_GPIO_PIN_SEL_E_GSERPX_PHY_SIF_OUT(a) (0x580 + (a))
151 #define ODY_GPIO_PIN_SEL_E_GSERPX_PRAM_SIF_INX(a, b) (0x550 + 3 * (a) + (b))
152 #define ODY_GPIO_PIN_SEL_E_GSERPX_PRAM_SIF_OUT(a) (0x590 + (a))
153 #define ODY_GPIO_PIN_SEL_E_GSERPX_UART_RXX(a, b) (0x7a0 + 5 * (a) + (b))
154 #define ODY_GPIO_PIN_SEL_E_GSERPX_UART_TXX(a, b) (0x750 + 5 * (a) + (b))
155 #define ODY_GPIO_PIN_SEL_E_I3CX_SCL(a) (0x28d + (a))
156 #define ODY_GPIO_PIN_SEL_E_I3CX_SDA(a) (0x291 + (a))
157 #define ODY_GPIO_PIN_SEL_E_MCDX_IN(a) (0x23f + (a))
158 #define ODY_GPIO_PIN_SEL_E_MCDX_OUT(a) (0x242 + (a))
159 #define ODY_GPIO_PIN_SEL_E_MCP_RESET_IN (0x482)
160 #define ODY_GPIO_PIN_SEL_E_MCP_RESET_OUT (0x483)
161 #define ODY_GPIO_PIN_SEL_E_OCLA_EXT_TRIGGER (0x231)
162 #define ODY_GPIO_PIN_SEL_E_PBUS_ADX(a) (0xfa + (a))
163 #define ODY_GPIO_PIN_SEL_E_PBUS_ALEX(a) (0xe8 + (a))
164 #define ODY_GPIO_PIN_SEL_E_PBUS_CEX(a) (0xec + (a))
165 #define ODY_GPIO_PIN_SEL_E_PBUS_CLE (0xe0)
166 #define ODY_GPIO_PIN_SEL_E_PBUS_DIR (0xe4)
167 #define ODY_GPIO_PIN_SEL_E_PBUS_DMACKX(a) (0xe6 + (a))
168 #define ODY_GPIO_PIN_SEL_E_PBUS_DMARQX(a) (0x11a + (a))
169 #define ODY_GPIO_PIN_SEL_E_PBUS_OE (0xe3)
170 #define ODY_GPIO_PIN_SEL_E_PBUS_WAIT (0xe1)
171 #define ODY_GPIO_PIN_SEL_E_PBUS_WE (0xe2)
172 #define ODY_GPIO_PIN_SEL_E_PLL_LOCK (0x131)
173 #define ODY_GPIO_PIN_SEL_E_PTP_EVTCNT (0x252)
174 #define ODY_GPIO_PIN_SEL_E_PTP_EXT_CLK (0x250)
175 #define ODY_GPIO_PIN_SEL_E_PTP_TSTMP (0x251)
176 #define ODY_GPIO_PIN_SEL_E_SCP_RESET_IN (0x484)
177 #define ODY_GPIO_PIN_SEL_E_SCP_RESET_OUT (0x485)
178 #define ODY_GPIO_PIN_SEL_E_SMIX_MDC(a) (0x253 + (a))
179 #define ODY_GPIO_PIN_SEL_E_SMIX_MDIO(a) (0x255 + (a))
180 #define ODY_GPIO_PIN_SEL_E_SPI0_CLK (0x274)
181 #define ODY_GPIO_PIN_SEL_E_SPI0_CSX(a) (0x270 + (a))
182 #define ODY_GPIO_PIN_SEL_E_SPI0_DQS (0x275)
183 #define ODY_GPIO_PIN_SEL_E_SPI0_IOX(a) (0x278 + (a))
184 #define ODY_GPIO_PIN_SEL_E_SPI0_RESET (0x276)
185 #define ODY_GPIO_PIN_SEL_E_SPI1_CLK (0x280)
186 #define ODY_GPIO_PIN_SEL_E_SPI1_CSX(a) (0x284 + (a))
187 #define ODY_GPIO_PIN_SEL_E_SPI1_DQS (0x281)
188 #define ODY_GPIO_PIN_SEL_E_SPI1_IOX(a) (0x288 + (a))
189 #define ODY_GPIO_PIN_SEL_E_SPI1_RESET (0x282)
190 #define ODY_GPIO_PIN_SEL_E_TIMER (0x11c)
191 #define ODY_GPIO_PIN_SEL_E_TIM_GPIO_CLK (0x230)
192 #define ODY_GPIO_PIN_SEL_E_TWS_SCLX(a) (0x298 + (a))
193 #define ODY_GPIO_PIN_SEL_E_TWS_SDAX(a) (0x2a4 + (a))
194 #define ODY_GPIO_PIN_SEL_E_UARTX_CTS(a) (0x3c0 + (a))
195 #define ODY_GPIO_PIN_SEL_E_UARTX_DCD(a) (0x3b0 + (a))
196 #define ODY_GPIO_PIN_SEL_E_UARTX_DSR(a) (0x3b8 + (a))
197 #define ODY_GPIO_PIN_SEL_E_UARTX_DTR(a) (0x390 + (a))
198 #define ODY_GPIO_PIN_SEL_E_UARTX_RI(a) (0x3a8 + (a))
199 #define ODY_GPIO_PIN_SEL_E_UARTX_RTS(a) (0x398 + (a))
200 #define ODY_GPIO_PIN_SEL_E_UARTX_SIN(a) (0x3c8 + (a))
201 #define ODY_GPIO_PIN_SEL_E_UARTX_SOUT(a) (0x3a0 + (a))
202
203 /**
204 * Enumeration gpio_strap_pin_e
205 *
206 * GPIO Strap Pin Number Enumeration
207 * Enumerates GPIO pin numbers with their associated strap functions. The names of
208 * these values are used as the documented name of each
209 * strap. e.g. GPIO_STRAP_PIN_E::BOOT_METHOD0 describes the GPIO0/BOOT_METHOD0 strap.
210 * For strap state, see GPIO_STRAP and GPIO_STRAP1.
211 */
212 #define ODY_GPIO_STRAP_PIN_E_AVS_DISABLE (9)
213 #define ODY_GPIO_STRAP_PIN_E_BOOT_METHOD0 (0)
214 #define ODY_GPIO_STRAP_PIN_E_BOOT_METHOD1 (1)
215 #define ODY_GPIO_STRAP_PIN_E_BOOT_METHOD2 (2)
216 #define ODY_GPIO_STRAP_PIN_E_BOOT_METHOD3 (3)
217 #define ODY_GPIO_STRAP_PIN_E_BOOT_METHOD4 (0xc)
218 #define ODY_GPIO_STRAP_PIN_E_BOOT_METHOD5 (0xd)
219 #define ODY_GPIO_STRAP_PIN_E_PCIE0_EP_MODE (0xf)
220 #define ODY_GPIO_STRAP_PIN_E_REF_CLK_TERMINATION (0xb)
221
222 /**
223 * Register (NCB) gpio_bit_cfg#
224 *
225 * GPIO Bit Configuration Registers
226 * Each register provides configuration information for the corresponding GPIO
227 * pin. There may be more indicies in this register than GPIO pins, any such
228 * unimplemented indexes should not be reprogrammed.
229 *
230 * Each index is only accessible to the requestor(s) permitted with GPIO_BIT_PERMIT().
231 *
232 * When permitted, this register is accessible through ROM scripts; see SCR_WRITE32_S[ADDR].
233 */
234 union ody_gpio_bit_cfgx {
235 uint64_t u;
236 struct ody_gpio_bit_cfgx_s {
237 uint64_t tx_oe : 1;
238 uint64_t pin_xor : 1;
239 uint64_t int_en : 1;
240 uint64_t int_type : 1;
241 uint64_t fil_cnt : 4;
242 uint64_t fil_sel : 4;
243 uint64_t tx_od : 1;
244 uint64_t blink_en : 2;
245 uint64_t reserved_15 : 1;
246 uint64_t pin_sel : 11;
247 uint64_t reserved_27_63 : 37;
248 } s;
249 /* struct ody_gpio_bit_cfgx_s cn; */
250 };
251 typedef union ody_gpio_bit_cfgx ody_gpio_bit_cfgx_t;
252
253 static inline uint64_t ODY_GPIO_BIT_CFGX(uint64_t a) __attribute__ ((pure, always_inline));
ODY_GPIO_BIT_CFGX(uint64_t a)254 static inline uint64_t ODY_GPIO_BIT_CFGX(uint64_t a)
255 {
256 if (a <= 63)
257 return 0x803000000400ll + 8ll * ((a) & 0x3f);
258 __ody_csr_fatal("GPIO_BIT_CFGX", 1, a, 0, 0, 0, 0, 0);
259 }
260
261 #define typedef_ODY_GPIO_BIT_CFGX(a) ody_gpio_bit_cfgx_t
262 #define bustype_ODY_GPIO_BIT_CFGX(a) CSR_TYPE_NCB
263 #define basename_ODY_GPIO_BIT_CFGX(a) "GPIO_BIT_CFGX"
264 #define device_bar_ODY_GPIO_BIT_CFGX(a) 0x0 /* PF_BAR0 */
265 #define busnum_ODY_GPIO_BIT_CFGX(a) (a)
266 #define arguments_ODY_GPIO_BIT_CFGX(a) (a), -1, -1, -1
267
268 /**
269 * Register (NCB) gpio_bit_permit#
270 *
271 * GPIO Bit Permit Register
272 * This register determines which requestor(s) are permitted to access which GPIO pins.
273 *
274 * This register is only accessible to the requestor(s) permitted with GPIO_PERMIT.
275 * (That is, only the GPIO_PERMIT permitted agent can change the permission settings of
276 * all requestors.)
277 *
278 * This register is not accessible through ROM scripts; see SCR_WRITE32_S[ADDR].
279 */
280 union ody_gpio_bit_permitx {
281 uint64_t u;
282 struct ody_gpio_bit_permitx_s {
283 uint64_t permitdis : 5;
284 uint64_t reserved_5_63 : 59;
285 } s;
286 /* struct ody_gpio_bit_permitx_s cn; */
287 };
288 typedef union ody_gpio_bit_permitx ody_gpio_bit_permitx_t;
289
290 static inline uint64_t ODY_GPIO_BIT_PERMITX(uint64_t a) __attribute__ ((pure, always_inline));
ODY_GPIO_BIT_PERMITX(uint64_t a)291 static inline uint64_t ODY_GPIO_BIT_PERMITX(uint64_t a)
292 {
293 if (a <= 63)
294 return 0x803000002000ll + 8ll * ((a) & 0x3f);
295 __ody_csr_fatal("GPIO_BIT_PERMITX", 1, a, 0, 0, 0, 0, 0);
296 }
297
298 #define typedef_ODY_GPIO_BIT_PERMITX(a) ody_gpio_bit_permitx_t
299 #define bustype_ODY_GPIO_BIT_PERMITX(a) CSR_TYPE_NCB
300 #define basename_ODY_GPIO_BIT_PERMITX(a) "GPIO_BIT_PERMITX"
301 #define device_bar_ODY_GPIO_BIT_PERMITX(a) 0x0 /* PF_BAR0 */
302 #define busnum_ODY_GPIO_BIT_PERMITX(a) (a)
303 #define arguments_ODY_GPIO_BIT_PERMITX(a) (a), -1, -1, -1
304
305 /**
306 * Register (NCB) gpio_blink_cfg
307 *
308 * GPIO Output Blinker Configuration Register
309 * This register configures the blink generator.
310 *
311 * This register is only accessible to the requestor(s) permitted with GPIO_PERMIT.
312 *
313 * When permitted, this register is accessible through ROM scripts; see SCR_WRITE32_S[ADDR].
314 */
315 union ody_gpio_blink_cfg {
316 uint64_t u;
317 struct ody_gpio_blink_cfg_s {
318 uint64_t stretch_on : 4;
319 uint64_t stretch_off : 4;
320 uint64_t max_on : 4;
321 uint64_t force_off : 4;
322 uint64_t reserved_16_63 : 48;
323 } s;
324 /* struct ody_gpio_blink_cfg_s cn; */
325 };
326 typedef union ody_gpio_blink_cfg ody_gpio_blink_cfg_t;
327
328 #define ODY_GPIO_BLINK_CFG ODY_GPIO_BLINK_CFG_FUNC()
329 static inline uint64_t ODY_GPIO_BLINK_CFG_FUNC(void) __attribute__ ((pure, always_inline));
ODY_GPIO_BLINK_CFG_FUNC(void)330 static inline uint64_t ODY_GPIO_BLINK_CFG_FUNC(void)
331 {
332 return 0x803000001440ll;
333 }
334
335 #define typedef_ODY_GPIO_BLINK_CFG ody_gpio_blink_cfg_t
336 #define bustype_ODY_GPIO_BLINK_CFG CSR_TYPE_NCB
337 #define basename_ODY_GPIO_BLINK_CFG "GPIO_BLINK_CFG"
338 #define device_bar_ODY_GPIO_BLINK_CFG 0x0 /* PF_BAR0 */
339 #define busnum_ODY_GPIO_BLINK_CFG 0
340 #define arguments_ODY_GPIO_BLINK_CFG -1, -1, -1, -1
341
342 /**
343 * Register (NCB) gpio_blink_freq
344 *
345 * GPIO Blink Clock Register
346 * This register configures the blink generator.
347 *
348 * This register is only accessible to the requestor(s) permitted with GPIO_PERMIT.
349 *
350 * When permitted, this register is accessible through ROM scripts; see SCR_WRITE32_S[ADDR].
351 */
352 union ody_gpio_blink_freq {
353 uint64_t u;
354 struct ody_gpio_blink_freq_s {
355 uint64_t div : 27;
356 uint64_t reserved_27_63 : 37;
357 } s;
358 /* struct ody_gpio_blink_freq_s cn; */
359 };
360 typedef union ody_gpio_blink_freq ody_gpio_blink_freq_t;
361
362 #define ODY_GPIO_BLINK_FREQ ODY_GPIO_BLINK_FREQ_FUNC()
363 static inline uint64_t ODY_GPIO_BLINK_FREQ_FUNC(void) __attribute__ ((pure, always_inline));
ODY_GPIO_BLINK_FREQ_FUNC(void)364 static inline uint64_t ODY_GPIO_BLINK_FREQ_FUNC(void)
365 {
366 return 0x803000001448ll;
367 }
368
369 #define typedef_ODY_GPIO_BLINK_FREQ ody_gpio_blink_freq_t
370 #define bustype_ODY_GPIO_BLINK_FREQ CSR_TYPE_NCB
371 #define basename_ODY_GPIO_BLINK_FREQ "GPIO_BLINK_FREQ"
372 #define device_bar_ODY_GPIO_BLINK_FREQ 0x0 /* PF_BAR0 */
373 #define busnum_ODY_GPIO_BLINK_FREQ 0
374 #define arguments_ODY_GPIO_BLINK_FREQ -1, -1, -1, -1
375
376 /**
377 * Register (NCB) gpio_clk_gen#
378 *
379 * GPIO Clock Generator Registers
380 * This register configures the clock generators. The number of generators is
381 * discoverable in GPIO_CONST[CLKGEN].
382 *
383 * This register is only accessible to the requestor(s) permitted with GPIO_PERMIT.
384 *
385 * When permitted, this register is accessible through ROM scripts; see SCR_WRITE32_S[ADDR].
386 */
387 union ody_gpio_clk_genx {
388 uint64_t u;
389 struct ody_gpio_clk_genx_s {
390 uint64_t n : 32;
391 uint64_t high : 32;
392 } s;
393 /* struct ody_gpio_clk_genx_s cn; */
394 };
395 typedef union ody_gpio_clk_genx ody_gpio_clk_genx_t;
396
397 static inline uint64_t ODY_GPIO_CLK_GENX(uint64_t a) __attribute__ ((pure, always_inline));
ODY_GPIO_CLK_GENX(uint64_t a)398 static inline uint64_t ODY_GPIO_CLK_GENX(uint64_t a)
399 {
400 if (a <= 7)
401 return 0x803000001800ll + 8ll * ((a) & 0x7);
402 __ody_csr_fatal("GPIO_CLK_GENX", 1, a, 0, 0, 0, 0, 0);
403 }
404
405 #define typedef_ODY_GPIO_CLK_GENX(a) ody_gpio_clk_genx_t
406 #define bustype_ODY_GPIO_CLK_GENX(a) CSR_TYPE_NCB
407 #define basename_ODY_GPIO_CLK_GENX(a) "GPIO_CLK_GENX"
408 #define device_bar_ODY_GPIO_CLK_GENX(a) 0x0 /* PF_BAR0 */
409 #define busnum_ODY_GPIO_CLK_GENX(a) (a)
410 #define arguments_ODY_GPIO_CLK_GENX(a) (a), -1, -1, -1
411
412 /**
413 * Register (NCB) gpio_clk_synce#
414 *
415 * GPIO Clock SyncE Registers
416 * Certain SerDes may be configured as a clock source. The GPIO block can support up to two
417 * unique clocks to send out any GPIO pin as configured when GPIO_BIT_CFG()[PIN_SEL] =
418 * GPIO_PIN_SEL_E::GPIO_CLK_SYNCE(0..1). The clock can be divided by 20, 40, 80 or 160
419 * of the selected SerDes clock. Legal values are based on the number of SerDes.
420 *
421 * This register is only accessible to the requestor(s) permitted with GPIO_PERMIT.
422 *
423 * This register is not accessible through ROM scripts; see SCR_WRITE32_S[ADDR].
424 */
425 union ody_gpio_clk_syncex {
426 uint64_t u;
427 struct ody_gpio_clk_syncex_s {
428 uint64_t lane_sel : 2;
429 uint64_t div : 2;
430 uint64_t reserved_4_7 : 4;
431 uint64_t qlm_sel : 4;
432 uint64_t reserved_12_63 : 52;
433 } s;
434 /* struct ody_gpio_clk_syncex_s cn; */
435 };
436 typedef union ody_gpio_clk_syncex ody_gpio_clk_syncex_t;
437
438 static inline uint64_t ODY_GPIO_CLK_SYNCEX(uint64_t a) __attribute__ ((pure, always_inline));
ODY_GPIO_CLK_SYNCEX(uint64_t a)439 static inline uint64_t ODY_GPIO_CLK_SYNCEX(uint64_t a)
440 {
441 if (a <= 1)
442 return 0x803000000060ll + 8ll * ((a) & 0x1);
443 __ody_csr_fatal("GPIO_CLK_SYNCEX", 1, a, 0, 0, 0, 0, 0);
444 }
445
446 #define typedef_ODY_GPIO_CLK_SYNCEX(a) ody_gpio_clk_syncex_t
447 #define bustype_ODY_GPIO_CLK_SYNCEX(a) CSR_TYPE_NCB
448 #define basename_ODY_GPIO_CLK_SYNCEX(a) "GPIO_CLK_SYNCEX"
449 #define device_bar_ODY_GPIO_CLK_SYNCEX(a) 0x0 /* PF_BAR0 */
450 #define busnum_ODY_GPIO_CLK_SYNCEX(a) (a)
451 #define arguments_ODY_GPIO_CLK_SYNCEX(a) (a), -1, -1, -1
452
453 /**
454 * Register (NCB) gpio_const
455 *
456 * GPIO Constants Register
457 * This register contains constants for software discovery.
458 *
459 * This register is accessible to all requestors (regardless of GPIO_PERMIT).
460 *
461 * When permitted, this register is accessible through ROM scripts; see SCR_WRITE32_S[ADDR].
462 */
463 union ody_gpio_const {
464 uint64_t u;
465 struct ody_gpio_const_s {
466 uint64_t gpios : 8;
467 uint64_t pp : 8;
468 uint64_t clkgen : 4;
469 uint64_t reserved_20_63 : 44;
470 } s;
471 /* struct ody_gpio_const_s cn; */
472 };
473 typedef union ody_gpio_const ody_gpio_const_t;
474
475 #define ODY_GPIO_CONST ODY_GPIO_CONST_FUNC()
476 static inline uint64_t ODY_GPIO_CONST_FUNC(void) __attribute__ ((pure, always_inline));
ODY_GPIO_CONST_FUNC(void)477 static inline uint64_t ODY_GPIO_CONST_FUNC(void)
478 {
479 return 0x803000000090ll;
480 }
481
482 #define typedef_ODY_GPIO_CONST ody_gpio_const_t
483 #define bustype_ODY_GPIO_CONST CSR_TYPE_NCB
484 #define basename_ODY_GPIO_CONST "GPIO_CONST"
485 #define device_bar_ODY_GPIO_CONST 0x0 /* PF_BAR0 */
486 #define busnum_ODY_GPIO_CONST 0
487 #define arguments_ODY_GPIO_CONST -1, -1, -1, -1
488
489 /**
490 * Register (NCB) gpio_intr#
491 *
492 * GPIO Bit Interrupt Registers
493 * Each register provides interrupt information for the corresponding GPIO pin.
494 * GPIO_INTR() interrupts can be level or edge interrupts depending on GPIO_BIT_CFG()[INT_TYPE].
495 *
496 * Each index is only accessible to the requestor(s) permitted with GPIO_BIT_PERMIT().
497 *
498 * This register is not accessible through ROM scripts; see SCR_WRITE32_S[ADDR].
499 */
500 union ody_gpio_intrx {
501 uint64_t u;
502 struct ody_gpio_intrx_s {
503 uint64_t intr : 1;
504 uint64_t intr_w1s : 1;
505 uint64_t intr_ena_w1c : 1;
506 uint64_t intr_ena_w1s : 1;
507 uint64_t reserved_4_63 : 60;
508 } s;
509 /* struct ody_gpio_intrx_s cn; */
510 };
511 typedef union ody_gpio_intrx ody_gpio_intrx_t;
512
513 static inline uint64_t ODY_GPIO_INTRX(uint64_t a) __attribute__ ((pure, always_inline));
ODY_GPIO_INTRX(uint64_t a)514 static inline uint64_t ODY_GPIO_INTRX(uint64_t a)
515 {
516 if (a <= 63)
517 return 0x803000000800ll + 8ll * ((a) & 0x3f);
518 __ody_csr_fatal("GPIO_INTRX", 1, a, 0, 0, 0, 0, 0);
519 }
520
521 #define typedef_ODY_GPIO_INTRX(a) ody_gpio_intrx_t
522 #define bustype_ODY_GPIO_INTRX(a) CSR_TYPE_NCB
523 #define basename_ODY_GPIO_INTRX(a) "GPIO_INTRX"
524 #define device_bar_ODY_GPIO_INTRX(a) 0x0 /* PF_BAR0 */
525 #define busnum_ODY_GPIO_INTRX(a) (a)
526 #define arguments_ODY_GPIO_INTRX(a) (a), -1, -1, -1
527
528 /**
529 * Register (NCB) gpio_io_ctl
530 *
531 * GPIO I/O Control Register
532 * This register is only accessible to the requestor(s) permitted with GPIO_PERMIT.
533 *
534 * When permitted, this register is accessible through ROM scripts; see SCR_WRITE32_S[ADDR].
535 */
536 union ody_gpio_io_ctl {
537 uint64_t u;
538 struct ody_gpio_io_ctl_s {
539 uint64_t slew0 : 2;
540 uint64_t drive0 : 2;
541 uint64_t slew1 : 2;
542 uint64_t drive1 : 2;
543 uint64_t slew2 : 2;
544 uint64_t drive2 : 2;
545 uint64_t slew3 : 2;
546 uint64_t drive3 : 2;
547 uint64_t slew4 : 2;
548 uint64_t drive4 : 2;
549 uint64_t slew5 : 2;
550 uint64_t drive5 : 2;
551 uint64_t slew6 : 2;
552 uint64_t drive6 : 2;
553 uint64_t slew7 : 2;
554 uint64_t drive7 : 2;
555 uint64_t reserved_32_63 : 32;
556 } s;
557 /* struct ody_gpio_io_ctl_s cn; */
558 };
559 typedef union ody_gpio_io_ctl ody_gpio_io_ctl_t;
560
561 #define ODY_GPIO_IO_CTL ODY_GPIO_IO_CTL_FUNC()
562 static inline uint64_t ODY_GPIO_IO_CTL_FUNC(void) __attribute__ ((pure, always_inline));
ODY_GPIO_IO_CTL_FUNC(void)563 static inline uint64_t ODY_GPIO_IO_CTL_FUNC(void)
564 {
565 return 0x803000000080ll;
566 }
567
568 #define typedef_ODY_GPIO_IO_CTL ody_gpio_io_ctl_t
569 #define bustype_ODY_GPIO_IO_CTL CSR_TYPE_NCB
570 #define basename_ODY_GPIO_IO_CTL "GPIO_IO_CTL"
571 #define device_bar_ODY_GPIO_IO_CTL 0x0 /* PF_BAR0 */
572 #define busnum_ODY_GPIO_IO_CTL 0
573 #define arguments_ODY_GPIO_IO_CTL -1, -1, -1, -1
574
575 /**
576 * Register (NCB) gpio_mc_intr#
577 *
578 * GPIO Bit Multicast Interrupt Registers
579 * Each register provides interrupt multicasting for GPIO(4..7).
580 *
581 * This register is only accessible to the requestor(s) permitted with GPIO_PERMIT.
582 *
583 * This register is not accessible through ROM scripts; see SCR_WRITE32_S[ADDR].
584 */
585 union ody_gpio_mc_intrx {
586 uint64_t u;
587 struct ody_gpio_mc_intrx_s {
588 uint64_t intr : 64;
589 } s;
590 /* struct ody_gpio_mc_intrx_s cn; */
591 };
592 typedef union ody_gpio_mc_intrx ody_gpio_mc_intrx_t;
593
594 static inline uint64_t ODY_GPIO_MC_INTRX(uint64_t a) __attribute__ ((pure, always_inline));
ODY_GPIO_MC_INTRX(uint64_t a)595 static inline uint64_t ODY_GPIO_MC_INTRX(uint64_t a)
596 {
597 if ((a >= 4) && (a <= 7))
598 return 0x803000001000ll + 8ll * ((a) & 0x7);
599 __ody_csr_fatal("GPIO_MC_INTRX", 1, a, 0, 0, 0, 0, 0);
600 }
601
602 #define typedef_ODY_GPIO_MC_INTRX(a) ody_gpio_mc_intrx_t
603 #define bustype_ODY_GPIO_MC_INTRX(a) CSR_TYPE_NCB
604 #define basename_ODY_GPIO_MC_INTRX(a) "GPIO_MC_INTRX"
605 #define device_bar_ODY_GPIO_MC_INTRX(a) 0x0 /* PF_BAR0 */
606 #define busnum_ODY_GPIO_MC_INTRX(a) (a)
607 #define arguments_ODY_GPIO_MC_INTRX(a) (a), -1, -1, -1
608
609 /**
610 * Register (NCB) gpio_mc_intr#_ena_w1c
611 *
612 * GPIO Bit Multicast Interrupt Registers
613 * This register clears interrupt enable bits.
614 */
615 union ody_gpio_mc_intrx_ena_w1c {
616 uint64_t u;
617 struct ody_gpio_mc_intrx_ena_w1c_s {
618 uint64_t intr : 64;
619 } s;
620 /* struct ody_gpio_mc_intrx_ena_w1c_s cn; */
621 };
622 typedef union ody_gpio_mc_intrx_ena_w1c ody_gpio_mc_intrx_ena_w1c_t;
623
624 static inline uint64_t ODY_GPIO_MC_INTRX_ENA_W1C(uint64_t a) __attribute__ ((pure, always_inline));
ODY_GPIO_MC_INTRX_ENA_W1C(uint64_t a)625 static inline uint64_t ODY_GPIO_MC_INTRX_ENA_W1C(uint64_t a)
626 {
627 if ((a >= 4) && (a <= 7))
628 return 0x803000001200ll + 8ll * ((a) & 0x7);
629 __ody_csr_fatal("GPIO_MC_INTRX_ENA_W1C", 1, a, 0, 0, 0, 0, 0);
630 }
631
632 #define typedef_ODY_GPIO_MC_INTRX_ENA_W1C(a) ody_gpio_mc_intrx_ena_w1c_t
633 #define bustype_ODY_GPIO_MC_INTRX_ENA_W1C(a) CSR_TYPE_NCB
634 #define basename_ODY_GPIO_MC_INTRX_ENA_W1C(a) "GPIO_MC_INTRX_ENA_W1C"
635 #define device_bar_ODY_GPIO_MC_INTRX_ENA_W1C(a) 0x0 /* PF_BAR0 */
636 #define busnum_ODY_GPIO_MC_INTRX_ENA_W1C(a) (a)
637 #define arguments_ODY_GPIO_MC_INTRX_ENA_W1C(a) (a), -1, -1, -1
638
639 /**
640 * Register (NCB) gpio_mc_intr#_ena_w1s
641 *
642 * GPIO Bit Multicast Interrupt Registers
643 * This register sets interrupt enable bits.
644 */
645 union ody_gpio_mc_intrx_ena_w1s {
646 uint64_t u;
647 struct ody_gpio_mc_intrx_ena_w1s_s {
648 uint64_t intr : 64;
649 } s;
650 /* struct ody_gpio_mc_intrx_ena_w1s_s cn; */
651 };
652 typedef union ody_gpio_mc_intrx_ena_w1s ody_gpio_mc_intrx_ena_w1s_t;
653
654 static inline uint64_t ODY_GPIO_MC_INTRX_ENA_W1S(uint64_t a) __attribute__ ((pure, always_inline));
ODY_GPIO_MC_INTRX_ENA_W1S(uint64_t a)655 static inline uint64_t ODY_GPIO_MC_INTRX_ENA_W1S(uint64_t a)
656 {
657 if ((a >= 4) && (a <= 7))
658 return 0x803000001300ll + 8ll * ((a) & 0x7);
659 __ody_csr_fatal("GPIO_MC_INTRX_ENA_W1S", 1, a, 0, 0, 0, 0, 0);
660 }
661
662 #define typedef_ODY_GPIO_MC_INTRX_ENA_W1S(a) ody_gpio_mc_intrx_ena_w1s_t
663 #define bustype_ODY_GPIO_MC_INTRX_ENA_W1S(a) CSR_TYPE_NCB
664 #define basename_ODY_GPIO_MC_INTRX_ENA_W1S(a) "GPIO_MC_INTRX_ENA_W1S"
665 #define device_bar_ODY_GPIO_MC_INTRX_ENA_W1S(a) 0x0 /* PF_BAR0 */
666 #define busnum_ODY_GPIO_MC_INTRX_ENA_W1S(a) (a)
667 #define arguments_ODY_GPIO_MC_INTRX_ENA_W1S(a) (a), -1, -1, -1
668
669 /**
670 * Register (NCB) gpio_mc_intr#_w1s
671 *
672 * GPIO Bit Multicast Interrupt Registers
673 * This register sets interrupt bits.
674 */
675 union ody_gpio_mc_intrx_w1s {
676 uint64_t u;
677 struct ody_gpio_mc_intrx_w1s_s {
678 uint64_t intr : 64;
679 } s;
680 /* struct ody_gpio_mc_intrx_w1s_s cn; */
681 };
682 typedef union ody_gpio_mc_intrx_w1s ody_gpio_mc_intrx_w1s_t;
683
684 static inline uint64_t ODY_GPIO_MC_INTRX_W1S(uint64_t a) __attribute__ ((pure, always_inline));
ODY_GPIO_MC_INTRX_W1S(uint64_t a)685 static inline uint64_t ODY_GPIO_MC_INTRX_W1S(uint64_t a)
686 {
687 if ((a >= 4) && (a <= 7))
688 return 0x803000001100ll + 8ll * ((a) & 0x7);
689 __ody_csr_fatal("GPIO_MC_INTRX_W1S", 1, a, 0, 0, 0, 0, 0);
690 }
691
692 #define typedef_ODY_GPIO_MC_INTRX_W1S(a) ody_gpio_mc_intrx_w1s_t
693 #define bustype_ODY_GPIO_MC_INTRX_W1S(a) CSR_TYPE_NCB
694 #define basename_ODY_GPIO_MC_INTRX_W1S(a) "GPIO_MC_INTRX_W1S"
695 #define device_bar_ODY_GPIO_MC_INTRX_W1S(a) 0x0 /* PF_BAR0 */
696 #define busnum_ODY_GPIO_MC_INTRX_W1S(a) (a)
697 #define arguments_ODY_GPIO_MC_INTRX_W1S(a) (a), -1, -1, -1
698
699 /**
700 * Register (NCB) gpio_mc_intr1#
701 *
702 * GPIO Bit Multicast Interrupt Registers
703 * Each register provides interrupt multicasting for GPIO(4..7).
704 *
705 * This register is only accessible to the requestor(s) permitted with GPIO_PERMIT.
706 *
707 * This register is not accessible through ROM scripts; see SCR_WRITE32_S[ADDR].
708 */
709 union ody_gpio_mc_intr1x {
710 uint64_t u;
711 struct ody_gpio_mc_intr1x_s {
712 uint64_t intr : 18;
713 uint64_t reserved_18_63 : 46;
714 } s;
715 /* struct ody_gpio_mc_intr1x_s cn; */
716 };
717 typedef union ody_gpio_mc_intr1x ody_gpio_mc_intr1x_t;
718
719 static inline uint64_t ODY_GPIO_MC_INTR1X(uint64_t a) __attribute__ ((pure, always_inline));
ODY_GPIO_MC_INTR1X(uint64_t a)720 static inline uint64_t ODY_GPIO_MC_INTR1X(uint64_t a)
721 {
722 if ((a >= 4) && (a <= 7))
723 return 0x803000001040ll + 8ll * ((a) & 0x7);
724 __ody_csr_fatal("GPIO_MC_INTR1X", 1, a, 0, 0, 0, 0, 0);
725 }
726
727 #define typedef_ODY_GPIO_MC_INTR1X(a) ody_gpio_mc_intr1x_t
728 #define bustype_ODY_GPIO_MC_INTR1X(a) CSR_TYPE_NCB
729 #define basename_ODY_GPIO_MC_INTR1X(a) "GPIO_MC_INTR1X"
730 #define device_bar_ODY_GPIO_MC_INTR1X(a) 0x0 /* PF_BAR0 */
731 #define busnum_ODY_GPIO_MC_INTR1X(a) (a)
732 #define arguments_ODY_GPIO_MC_INTR1X(a) (a), -1, -1, -1
733
734 /**
735 * Register (NCB) gpio_mc_intr1#_ena_w1c
736 *
737 * GPIO Bit Multicast Interrupt Registers
738 * This register clears interrupt enable bits.
739 */
740 union ody_gpio_mc_intr1x_ena_w1c {
741 uint64_t u;
742 struct ody_gpio_mc_intr1x_ena_w1c_s {
743 uint64_t intr : 18;
744 uint64_t reserved_18_63 : 46;
745 } s;
746 /* struct ody_gpio_mc_intr1x_ena_w1c_s cn; */
747 };
748 typedef union ody_gpio_mc_intr1x_ena_w1c ody_gpio_mc_intr1x_ena_w1c_t;
749
750 static inline uint64_t ODY_GPIO_MC_INTR1X_ENA_W1C(uint64_t a) __attribute__ ((pure, always_inline));
ODY_GPIO_MC_INTR1X_ENA_W1C(uint64_t a)751 static inline uint64_t ODY_GPIO_MC_INTR1X_ENA_W1C(uint64_t a)
752 {
753 if ((a >= 4) && (a <= 7))
754 return 0x803000001240ll + 8ll * ((a) & 0x7);
755 __ody_csr_fatal("GPIO_MC_INTR1X_ENA_W1C", 1, a, 0, 0, 0, 0, 0);
756 }
757
758 #define typedef_ODY_GPIO_MC_INTR1X_ENA_W1C(a) ody_gpio_mc_intr1x_ena_w1c_t
759 #define bustype_ODY_GPIO_MC_INTR1X_ENA_W1C(a) CSR_TYPE_NCB
760 #define basename_ODY_GPIO_MC_INTR1X_ENA_W1C(a) "GPIO_MC_INTR1X_ENA_W1C"
761 #define device_bar_ODY_GPIO_MC_INTR1X_ENA_W1C(a) 0x0 /* PF_BAR0 */
762 #define busnum_ODY_GPIO_MC_INTR1X_ENA_W1C(a) (a)
763 #define arguments_ODY_GPIO_MC_INTR1X_ENA_W1C(a) (a), -1, -1, -1
764
765 /**
766 * Register (NCB) gpio_mc_intr1#_ena_w1s
767 *
768 * GPIO Bit Multicast Interrupt Registers
769 * This register sets interrupt enable bits.
770 */
771 union ody_gpio_mc_intr1x_ena_w1s {
772 uint64_t u;
773 struct ody_gpio_mc_intr1x_ena_w1s_s {
774 uint64_t intr : 18;
775 uint64_t reserved_18_63 : 46;
776 } s;
777 /* struct ody_gpio_mc_intr1x_ena_w1s_s cn; */
778 };
779 typedef union ody_gpio_mc_intr1x_ena_w1s ody_gpio_mc_intr1x_ena_w1s_t;
780
781 static inline uint64_t ODY_GPIO_MC_INTR1X_ENA_W1S(uint64_t a) __attribute__ ((pure, always_inline));
ODY_GPIO_MC_INTR1X_ENA_W1S(uint64_t a)782 static inline uint64_t ODY_GPIO_MC_INTR1X_ENA_W1S(uint64_t a)
783 {
784 if ((a >= 4) && (a <= 7))
785 return 0x803000001340ll + 8ll * ((a) & 0x7);
786 __ody_csr_fatal("GPIO_MC_INTR1X_ENA_W1S", 1, a, 0, 0, 0, 0, 0);
787 }
788
789 #define typedef_ODY_GPIO_MC_INTR1X_ENA_W1S(a) ody_gpio_mc_intr1x_ena_w1s_t
790 #define bustype_ODY_GPIO_MC_INTR1X_ENA_W1S(a) CSR_TYPE_NCB
791 #define basename_ODY_GPIO_MC_INTR1X_ENA_W1S(a) "GPIO_MC_INTR1X_ENA_W1S"
792 #define device_bar_ODY_GPIO_MC_INTR1X_ENA_W1S(a) 0x0 /* PF_BAR0 */
793 #define busnum_ODY_GPIO_MC_INTR1X_ENA_W1S(a) (a)
794 #define arguments_ODY_GPIO_MC_INTR1X_ENA_W1S(a) (a), -1, -1, -1
795
796 /**
797 * Register (NCB) gpio_mc_intr1#_w1s
798 *
799 * GPIO Bit Multicast Interrupt Registers
800 * This register sets interrupt bits.
801 */
802 union ody_gpio_mc_intr1x_w1s {
803 uint64_t u;
804 struct ody_gpio_mc_intr1x_w1s_s {
805 uint64_t intr : 18;
806 uint64_t reserved_18_63 : 46;
807 } s;
808 /* struct ody_gpio_mc_intr1x_w1s_s cn; */
809 };
810 typedef union ody_gpio_mc_intr1x_w1s ody_gpio_mc_intr1x_w1s_t;
811
812 static inline uint64_t ODY_GPIO_MC_INTR1X_W1S(uint64_t a) __attribute__ ((pure, always_inline));
ODY_GPIO_MC_INTR1X_W1S(uint64_t a)813 static inline uint64_t ODY_GPIO_MC_INTR1X_W1S(uint64_t a)
814 {
815 if ((a >= 4) && (a <= 7))
816 return 0x803000001140ll + 8ll * ((a) & 0x7);
817 __ody_csr_fatal("GPIO_MC_INTR1X_W1S", 1, a, 0, 0, 0, 0, 0);
818 }
819
820 #define typedef_ODY_GPIO_MC_INTR1X_W1S(a) ody_gpio_mc_intr1x_w1s_t
821 #define bustype_ODY_GPIO_MC_INTR1X_W1S(a) CSR_TYPE_NCB
822 #define basename_ODY_GPIO_MC_INTR1X_W1S(a) "GPIO_MC_INTR1X_W1S"
823 #define device_bar_ODY_GPIO_MC_INTR1X_W1S(a) 0x0 /* PF_BAR0 */
824 #define busnum_ODY_GPIO_MC_INTR1X_W1S(a) (a)
825 #define arguments_ODY_GPIO_MC_INTR1X_W1S(a) (a), -1, -1, -1
826
827 /**
828 * Register (NCB) gpio_misc_strap
829 *
830 * GPIO Misc Strap Value Register
831 * This register contains the miscellaneous strap state.
832 *
833 * Miscellaneous straps are enumerated by GPIO_MISC_STRAP_PIN_E, where the value 0x0
834 * corresponds to bit zero in this register.
835 *
836 * This register is accessible to all requestors (regardless of GPIO_PERMIT).
837 *
838 * When permitted, this register is accessible through ROM scripts; see SCR_WRITE32_S[ADDR].
839 */
840 union ody_gpio_misc_strap {
841 uint64_t u;
842 struct ody_gpio_misc_strap_s {
843 uint64_t reserved_0_15 : 16;
844 uint64_t uart0_rts : 1;
845 uint64_t uart1_rts : 1;
846 uint64_t reserved_18_63 : 46;
847 } s;
848 /* struct ody_gpio_misc_strap_s cn; */
849 };
850 typedef union ody_gpio_misc_strap ody_gpio_misc_strap_t;
851
852 #define ODY_GPIO_MISC_STRAP ODY_GPIO_MISC_STRAP_FUNC()
853 static inline uint64_t ODY_GPIO_MISC_STRAP_FUNC(void) __attribute__ ((pure, always_inline));
ODY_GPIO_MISC_STRAP_FUNC(void)854 static inline uint64_t ODY_GPIO_MISC_STRAP_FUNC(void)
855 {
856 return 0x803000000030ll;
857 }
858
859 #define typedef_ODY_GPIO_MISC_STRAP ody_gpio_misc_strap_t
860 #define bustype_ODY_GPIO_MISC_STRAP CSR_TYPE_NCB
861 #define basename_ODY_GPIO_MISC_STRAP "GPIO_MISC_STRAP"
862 #define device_bar_ODY_GPIO_MISC_STRAP 0x0 /* PF_BAR0 */
863 #define busnum_ODY_GPIO_MISC_STRAP 0
864 #define arguments_ODY_GPIO_MISC_STRAP -1, -1, -1, -1
865
866 /**
867 * Register (NCB) gpio_misc_supply
868 *
869 * GPIO Misc Supply Value Register
870 * This register contains the state of the GPIO power supplies.
871 *
872 * This register is accessible to all requestors (regardless of GPIO_PERMIT).
873 *
874 * This register is not accessible through ROM scripts; see SCR_WRITE32_S[ADDR].
875 */
876 union ody_gpio_misc_supply {
877 uint64_t u;
878 struct ody_gpio_misc_supply_s {
879 uint64_t reserved_0_63 : 64;
880 } s;
881 /* struct ody_gpio_misc_supply_s cn; */
882 };
883 typedef union ody_gpio_misc_supply ody_gpio_misc_supply_t;
884
885 #define ODY_GPIO_MISC_SUPPLY ODY_GPIO_MISC_SUPPLY_FUNC()
886 static inline uint64_t ODY_GPIO_MISC_SUPPLY_FUNC(void) __attribute__ ((pure, always_inline));
ODY_GPIO_MISC_SUPPLY_FUNC(void)887 static inline uint64_t ODY_GPIO_MISC_SUPPLY_FUNC(void)
888 {
889 return 0x803000000038ll;
890 }
891
892 #define typedef_ODY_GPIO_MISC_SUPPLY ody_gpio_misc_supply_t
893 #define bustype_ODY_GPIO_MISC_SUPPLY CSR_TYPE_NCB
894 #define basename_ODY_GPIO_MISC_SUPPLY "GPIO_MISC_SUPPLY"
895 #define device_bar_ODY_GPIO_MISC_SUPPLY 0x0 /* PF_BAR0 */
896 #define busnum_ODY_GPIO_MISC_SUPPLY 0
897 #define arguments_ODY_GPIO_MISC_SUPPLY -1, -1, -1, -1
898
899 /**
900 * Register (NCB) gpio_msix_pba#
901 *
902 * GPIO MSI-X Pending Bit Array Registers
903 * This register is the MSI-X PBA table; the bit number is indexed by the GPIO_INT_VEC_E enumeration.
904 *
905 * This register is not accessible through ROM scripts; see SCR_WRITE32_S[ADDR].
906 */
907 union ody_gpio_msix_pbax {
908 uint64_t u;
909 struct ody_gpio_msix_pbax_s {
910 uint64_t pend : 64;
911 } s;
912 /* struct ody_gpio_msix_pbax_s cn; */
913 };
914 typedef union ody_gpio_msix_pbax ody_gpio_msix_pbax_t;
915
916 static inline uint64_t ODY_GPIO_MSIX_PBAX(uint64_t a) __attribute__ ((pure, always_inline));
ODY_GPIO_MSIX_PBAX(uint64_t a)917 static inline uint64_t ODY_GPIO_MSIX_PBAX(uint64_t a)
918 {
919 if (a <= 3)
920 return 0x803000ff0000ll + 8ll * ((a) & 0x3);
921 __ody_csr_fatal("GPIO_MSIX_PBAX", 1, a, 0, 0, 0, 0, 0);
922 }
923
924 #define typedef_ODY_GPIO_MSIX_PBAX(a) ody_gpio_msix_pbax_t
925 #define bustype_ODY_GPIO_MSIX_PBAX(a) CSR_TYPE_NCB
926 #define basename_ODY_GPIO_MSIX_PBAX(a) "GPIO_MSIX_PBAX"
927 #define device_bar_ODY_GPIO_MSIX_PBAX(a) 0x4 /* PF_BAR4 */
928 #define busnum_ODY_GPIO_MSIX_PBAX(a) (a)
929 #define arguments_ODY_GPIO_MSIX_PBAX(a) (a), -1, -1, -1
930
931 /**
932 * Register (NCB) gpio_msix_vec#_addr
933 *
934 * GPIO MSI-X Vector-Table Address Register
935 * This register is the MSI-X vector table, indexed by the GPIO_INT_VEC_E enumeration.
936 *
937 * This register is not accessible through ROM scripts; see SCR_WRITE32_S[ADDR].
938 */
939 union ody_gpio_msix_vecx_addr {
940 uint64_t u;
941 struct ody_gpio_msix_vecx_addr_s {
942 uint64_t secvec : 1;
943 uint64_t reserved_1 : 1;
944 uint64_t addr : 51;
945 uint64_t reserved_53_63 : 11;
946 } s;
947 /* struct ody_gpio_msix_vecx_addr_s cn; */
948 };
949 typedef union ody_gpio_msix_vecx_addr ody_gpio_msix_vecx_addr_t;
950
951 static inline uint64_t ODY_GPIO_MSIX_VECX_ADDR(uint64_t a) __attribute__ ((pure, always_inline));
ODY_GPIO_MSIX_VECX_ADDR(uint64_t a)952 static inline uint64_t ODY_GPIO_MSIX_VECX_ADDR(uint64_t a)
953 {
954 if (a <= 209)
955 return 0x803000f00000ll + 0x10ll * ((a) & 0xff);
956 __ody_csr_fatal("GPIO_MSIX_VECX_ADDR", 1, a, 0, 0, 0, 0, 0);
957 }
958
959 #define typedef_ODY_GPIO_MSIX_VECX_ADDR(a) ody_gpio_msix_vecx_addr_t
960 #define bustype_ODY_GPIO_MSIX_VECX_ADDR(a) CSR_TYPE_NCB
961 #define basename_ODY_GPIO_MSIX_VECX_ADDR(a) "GPIO_MSIX_VECX_ADDR"
962 #define device_bar_ODY_GPIO_MSIX_VECX_ADDR(a) 0x4 /* PF_BAR4 */
963 #define busnum_ODY_GPIO_MSIX_VECX_ADDR(a) (a)
964 #define arguments_ODY_GPIO_MSIX_VECX_ADDR(a) (a), -1, -1, -1
965
966 /**
967 * Register (NCB) gpio_msix_vec#_ctl
968 *
969 * GPIO MSI-X Vector-Table Control and Data Register
970 * This register is the MSI-X vector table, indexed by the GPIO_INT_VEC_E enumeration.
971 *
972 * This register is not accessible through ROM scripts; see SCR_WRITE32_S[ADDR].
973 */
974 union ody_gpio_msix_vecx_ctl {
975 uint64_t u;
976 struct ody_gpio_msix_vecx_ctl_s {
977 uint64_t data : 32;
978 uint64_t mask : 1;
979 uint64_t reserved_33_63 : 31;
980 } s;
981 /* struct ody_gpio_msix_vecx_ctl_s cn; */
982 };
983 typedef union ody_gpio_msix_vecx_ctl ody_gpio_msix_vecx_ctl_t;
984
985 static inline uint64_t ODY_GPIO_MSIX_VECX_CTL(uint64_t a) __attribute__ ((pure, always_inline));
ODY_GPIO_MSIX_VECX_CTL(uint64_t a)986 static inline uint64_t ODY_GPIO_MSIX_VECX_CTL(uint64_t a)
987 {
988 if (a <= 209)
989 return 0x803000f00008ll + 0x10ll * ((a) & 0xff);
990 __ody_csr_fatal("GPIO_MSIX_VECX_CTL", 1, a, 0, 0, 0, 0, 0);
991 }
992
993 #define typedef_ODY_GPIO_MSIX_VECX_CTL(a) ody_gpio_msix_vecx_ctl_t
994 #define bustype_ODY_GPIO_MSIX_VECX_CTL(a) CSR_TYPE_NCB
995 #define basename_ODY_GPIO_MSIX_VECX_CTL(a) "GPIO_MSIX_VECX_CTL"
996 #define device_bar_ODY_GPIO_MSIX_VECX_CTL(a) 0x4 /* PF_BAR4 */
997 #define busnum_ODY_GPIO_MSIX_VECX_CTL(a) (a)
998 #define arguments_ODY_GPIO_MSIX_VECX_CTL(a) (a), -1, -1, -1
999
1000 /**
1001 * Register (NCB) gpio_multi_cast
1002 *
1003 * GPIO Multicast Register
1004 * This register enables multicast GPIO interrupts.
1005 *
1006 * This register is only accessible to the requestor(s) permitted with GPIO_PERMIT.
1007 *
1008 * This register is not accessible through ROM scripts; see SCR_WRITE32_S[ADDR].
1009 */
1010 union ody_gpio_multi_cast {
1011 uint64_t u;
1012 struct ody_gpio_multi_cast_s {
1013 uint64_t en : 1;
1014 uint64_t reserved_1_63 : 63;
1015 } s;
1016 /* struct ody_gpio_multi_cast_s cn; */
1017 };
1018 typedef union ody_gpio_multi_cast ody_gpio_multi_cast_t;
1019
1020 #define ODY_GPIO_MULTI_CAST ODY_GPIO_MULTI_CAST_FUNC()
1021 static inline uint64_t ODY_GPIO_MULTI_CAST_FUNC(void) __attribute__ ((pure, always_inline));
ODY_GPIO_MULTI_CAST_FUNC(void)1022 static inline uint64_t ODY_GPIO_MULTI_CAST_FUNC(void)
1023 {
1024 return 0x803000000018ll;
1025 }
1026
1027 #define typedef_ODY_GPIO_MULTI_CAST ody_gpio_multi_cast_t
1028 #define bustype_ODY_GPIO_MULTI_CAST CSR_TYPE_NCB
1029 #define basename_ODY_GPIO_MULTI_CAST "GPIO_MULTI_CAST"
1030 #define device_bar_ODY_GPIO_MULTI_CAST 0x0 /* PF_BAR0 */
1031 #define busnum_ODY_GPIO_MULTI_CAST 0
1032 #define arguments_ODY_GPIO_MULTI_CAST -1, -1, -1, -1
1033
1034 /**
1035 * Register (NCB) gpio_permit
1036 *
1037 * GPIO Permit Register
1038 * This register determines which requestor(s) are permitted to access which GPIO global
1039 * registers.
1040 *
1041 * This register is only accessible to the requestor(s) permitted with GPIO_PERMIT.
1042 * (That is, only the GPIO_PERMIT permitted agent can change the permission settings of
1043 * all requestors.)
1044 *
1045 * This register is not accessible through ROM scripts; see SCR_WRITE32_S[ADDR].
1046 */
1047 union ody_gpio_permit {
1048 uint64_t u;
1049 struct ody_gpio_permit_s {
1050 uint64_t permitdis : 5;
1051 uint64_t reserved_5_63 : 59;
1052 } s;
1053 /* struct ody_gpio_permit_s cn; */
1054 };
1055 typedef union ody_gpio_permit ody_gpio_permit_t;
1056
1057 #define ODY_GPIO_PERMIT ODY_GPIO_PERMIT_FUNC()
1058 static inline uint64_t ODY_GPIO_PERMIT_FUNC(void) __attribute__ ((pure, always_inline));
ODY_GPIO_PERMIT_FUNC(void)1059 static inline uint64_t ODY_GPIO_PERMIT_FUNC(void)
1060 {
1061 return 0x803000001500ll;
1062 }
1063
1064 #define typedef_ODY_GPIO_PERMIT ody_gpio_permit_t
1065 #define bustype_ODY_GPIO_PERMIT CSR_TYPE_NCB
1066 #define basename_ODY_GPIO_PERMIT "GPIO_PERMIT"
1067 #define device_bar_ODY_GPIO_PERMIT 0x0 /* PF_BAR0 */
1068 #define busnum_ODY_GPIO_PERMIT 0
1069 #define arguments_ODY_GPIO_PERMIT -1, -1, -1, -1
1070
1071 /**
1072 * Register (NCB) gpio_pkg_ver
1073 *
1074 * Chip Package Version Register
1075 * This register reads the package version.
1076 */
1077 union ody_gpio_pkg_ver {
1078 uint64_t u;
1079 struct ody_gpio_pkg_ver_s {
1080 uint64_t pkg_ver : 4;
1081 uint64_t reserved_4_63 : 60;
1082 } s;
1083 /* struct ody_gpio_pkg_ver_s cn; */
1084 };
1085 typedef union ody_gpio_pkg_ver ody_gpio_pkg_ver_t;
1086
1087 #define ODY_GPIO_PKG_VER ODY_GPIO_PKG_VER_FUNC()
1088 static inline uint64_t ODY_GPIO_PKG_VER_FUNC(void) __attribute__ ((pure, always_inline));
ODY_GPIO_PKG_VER_FUNC(void)1089 static inline uint64_t ODY_GPIO_PKG_VER_FUNC(void)
1090 {
1091 return 0x803000001610ll;
1092 }
1093
1094 #define typedef_ODY_GPIO_PKG_VER ody_gpio_pkg_ver_t
1095 #define bustype_ODY_GPIO_PKG_VER CSR_TYPE_NCB
1096 #define basename_ODY_GPIO_PKG_VER "GPIO_PKG_VER"
1097 #define device_bar_ODY_GPIO_PKG_VER 0x0 /* PF_BAR0 */
1098 #define busnum_ODY_GPIO_PKG_VER 0
1099 #define arguments_ODY_GPIO_PKG_VER -1, -1, -1, -1
1100
1101 /**
1102 * Register (NCB) gpio_pull_down#
1103 *
1104 * GPIO control for Pull-down Register
1105 * This register controls the pull-down for GPIOs. Each bit of this register corresponds
1106 * to a GPIO IO. These pull-downs are not replacement for proper board pull-downs.
1107 */
1108 union ody_gpio_pull_downx {
1109 uint64_t u;
1110 struct ody_gpio_pull_downx_s {
1111 uint64_t pull_down : 64;
1112 } s;
1113 /* struct ody_gpio_pull_downx_s cn; */
1114 };
1115 typedef union ody_gpio_pull_downx ody_gpio_pull_downx_t;
1116
1117 static inline uint64_t ODY_GPIO_PULL_DOWNX(uint64_t a) __attribute__ ((pure, always_inline));
ODY_GPIO_PULL_DOWNX(uint64_t a)1118 static inline uint64_t ODY_GPIO_PULL_DOWNX(uint64_t a)
1119 {
1120 if (a <= 1)
1121 return 0x803000001630ll + 8ll * ((a) & 0x1);
1122 __ody_csr_fatal("GPIO_PULL_DOWNX", 1, a, 0, 0, 0, 0, 0);
1123 }
1124
1125 #define typedef_ODY_GPIO_PULL_DOWNX(a) ody_gpio_pull_downx_t
1126 #define bustype_ODY_GPIO_PULL_DOWNX(a) CSR_TYPE_NCB
1127 #define basename_ODY_GPIO_PULL_DOWNX(a) "GPIO_PULL_DOWNX"
1128 #define device_bar_ODY_GPIO_PULL_DOWNX(a) 0x0 /* PF_BAR0 */
1129 #define busnum_ODY_GPIO_PULL_DOWNX(a) (a)
1130 #define arguments_ODY_GPIO_PULL_DOWNX(a) (a), -1, -1, -1
1131
1132 /**
1133 * Register (NCB) gpio_pull_up#
1134 *
1135 * GPIO control for Pull-up Register
1136 * This register controls the pull-up for GPIOs. Each bit of this register corresponds
1137 * to a GPIO IO. These pull-ups are not replacement for proper board pull-ups.
1138 */
1139 union ody_gpio_pull_upx {
1140 uint64_t u;
1141 struct ody_gpio_pull_upx_s {
1142 uint64_t pull_up : 64;
1143 } s;
1144 /* struct ody_gpio_pull_upx_s cn; */
1145 };
1146 typedef union ody_gpio_pull_upx ody_gpio_pull_upx_t;
1147
1148 static inline uint64_t ODY_GPIO_PULL_UPX(uint64_t a) __attribute__ ((pure, always_inline));
ODY_GPIO_PULL_UPX(uint64_t a)1149 static inline uint64_t ODY_GPIO_PULL_UPX(uint64_t a)
1150 {
1151 if (a <= 1)
1152 return 0x803000001620ll + 8ll * ((a) & 0x1);
1153 __ody_csr_fatal("GPIO_PULL_UPX", 1, a, 0, 0, 0, 0, 0);
1154 }
1155
1156 #define typedef_ODY_GPIO_PULL_UPX(a) ody_gpio_pull_upx_t
1157 #define bustype_ODY_GPIO_PULL_UPX(a) CSR_TYPE_NCB
1158 #define basename_ODY_GPIO_PULL_UPX(a) "GPIO_PULL_UPX"
1159 #define device_bar_ODY_GPIO_PULL_UPX(a) 0x0 /* PF_BAR0 */
1160 #define busnum_ODY_GPIO_PULL_UPX(a) (a)
1161 #define arguments_ODY_GPIO_PULL_UPX(a) (a), -1, -1, -1
1162
1163 /**
1164 * Register (NCB) gpio_rx_dat
1165 *
1166 * GPIO Receive Data Register
1167 * This register contains the state of the GPIO pins, which is after glitch filter and XOR
1168 * inverter (GPIO_BIT_CFG()[PIN_XOR]). GPIO inputs always report to GPIO_RX_DAT despite of
1169 * the value of GPIO_BIT_CFG()[PIN_SEL].
1170 * GPIO_RX_DAT reads GPIO input data for the first 64 GPIOs, and GPIO_RX1_DAT the remainder.
1171 *
1172 * Each bit in this register is only accessible to the requestor(s) permitted with
1173 * GPIO_BIT_PERMIT(), but error will not be reported when there are bits are not
1174 * permitted by GPIO_BIT_PERMIT().
1175 *
1176 * When permitted, this register is accessible through ROM scripts; see SCR_WRITE32_S[ADDR].
1177 */
1178 union ody_gpio_rx_dat {
1179 uint64_t u;
1180 struct ody_gpio_rx_dat_s {
1181 uint64_t dat : 64;
1182 } s;
1183 /* struct ody_gpio_rx_dat_s cn; */
1184 };
1185 typedef union ody_gpio_rx_dat ody_gpio_rx_dat_t;
1186
1187 #define ODY_GPIO_RX_DAT ODY_GPIO_RX_DAT_FUNC()
1188 static inline uint64_t ODY_GPIO_RX_DAT_FUNC(void) __attribute__ ((pure, always_inline));
ODY_GPIO_RX_DAT_FUNC(void)1189 static inline uint64_t ODY_GPIO_RX_DAT_FUNC(void)
1190 {
1191 return 0x803000000000ll;
1192 }
1193
1194 #define typedef_ODY_GPIO_RX_DAT ody_gpio_rx_dat_t
1195 #define bustype_ODY_GPIO_RX_DAT CSR_TYPE_NCB
1196 #define basename_ODY_GPIO_RX_DAT "GPIO_RX_DAT"
1197 #define device_bar_ODY_GPIO_RX_DAT 0x0 /* PF_BAR0 */
1198 #define busnum_ODY_GPIO_RX_DAT 0
1199 #define arguments_ODY_GPIO_RX_DAT -1, -1, -1, -1
1200
1201 /**
1202 * Register (NCB) gpio_strap
1203 *
1204 * GPIO Strap Value Register
1205 * This register contains the first 64 GPIO strap data captured at the rising edge of DC_OK.
1206 * GPIO_STRAP1 contains the remaining GPIOs.
1207 *
1208 * Straps are enumerated by GPIO_STRAP_PIN_E.
1209 *
1210 * This register is accessible to all requestors (regardless of GPIO_PERMIT).
1211 *
1212 * When permitted, this register is accessible through ROM scripts; see SCR_WRITE32_S[ADDR].
1213 */
1214 union ody_gpio_strap {
1215 uint64_t u;
1216 struct ody_gpio_strap_s {
1217 uint64_t strap : 64;
1218 } s;
1219 /* struct ody_gpio_strap_s cn; */
1220 };
1221 typedef union ody_gpio_strap ody_gpio_strap_t;
1222
1223 #define ODY_GPIO_STRAP ODY_GPIO_STRAP_FUNC()
1224 static inline uint64_t ODY_GPIO_STRAP_FUNC(void) __attribute__ ((pure, always_inline));
ODY_GPIO_STRAP_FUNC(void)1225 static inline uint64_t ODY_GPIO_STRAP_FUNC(void)
1226 {
1227 return 0x803000000028ll;
1228 }
1229
1230 #define typedef_ODY_GPIO_STRAP ody_gpio_strap_t
1231 #define bustype_ODY_GPIO_STRAP CSR_TYPE_NCB
1232 #define basename_ODY_GPIO_STRAP "GPIO_STRAP"
1233 #define device_bar_ODY_GPIO_STRAP 0x0 /* PF_BAR0 */
1234 #define busnum_ODY_GPIO_STRAP 0
1235 #define arguments_ODY_GPIO_STRAP -1, -1, -1, -1
1236
1237 /**
1238 * Register (NCB) gpio_thermal_hot
1239 *
1240 * Chip Thermal Hot Register
1241 * This register reads and drives the thermal hot pin (THERMAL_HOT_L).
1242 *
1243 * This register is only accessible to the requestor(s) permitted with GPIO_PERMIT.
1244 *
1245 * This register is not accessible through ROM scripts; see SCR_WRITE32_S[ADDR].
1246 */
1247 union ody_gpio_thermal_hot {
1248 uint64_t u;
1249 struct ody_gpio_thermal_hot_s {
1250 uint64_t pin : 1;
1251 uint64_t drv : 1;
1252 uint64_t reserved_2_63 : 62;
1253 } s;
1254 /* struct ody_gpio_thermal_hot_s cn; */
1255 };
1256 typedef union ody_gpio_thermal_hot ody_gpio_thermal_hot_t;
1257
1258 #define ODY_GPIO_THERMAL_HOT ODY_GPIO_THERMAL_HOT_FUNC()
1259 static inline uint64_t ODY_GPIO_THERMAL_HOT_FUNC(void) __attribute__ ((pure, always_inline));
ODY_GPIO_THERMAL_HOT_FUNC(void)1260 static inline uint64_t ODY_GPIO_THERMAL_HOT_FUNC(void)
1261 {
1262 return 0x803000001618ll;
1263 }
1264
1265 #define typedef_ODY_GPIO_THERMAL_HOT ody_gpio_thermal_hot_t
1266 #define bustype_ODY_GPIO_THERMAL_HOT CSR_TYPE_NCB
1267 #define basename_ODY_GPIO_THERMAL_HOT "GPIO_THERMAL_HOT"
1268 #define device_bar_ODY_GPIO_THERMAL_HOT 0x0 /* PF_BAR0 */
1269 #define busnum_ODY_GPIO_THERMAL_HOT 0
1270 #define arguments_ODY_GPIO_THERMAL_HOT -1, -1, -1, -1
1271
1272 /**
1273 * Register (NCB) gpio_tx_clr
1274 *
1275 * GPIO Transmit Clear Mask Register
1276 * This register clears GPIO output data for the first 64 GPIOs, and GPIO_TX1_CLR the
1277 * remainder.
1278 *
1279 * Each bit in this register is only accessible to the requestor(s) permitted with
1280 * GPIO_BIT_PERMIT(), but error will not be reported when there are bits are not
1281 * permitted by GPIO_BIT_PERMIT().
1282 *
1283 * When permitted, this register is accessible through ROM scripts; see SCR_WRITE32_S[ADDR].
1284 */
1285 union ody_gpio_tx_clr {
1286 uint64_t u;
1287 struct ody_gpio_tx_clr_s {
1288 uint64_t clr : 64;
1289 } s;
1290 /* struct ody_gpio_tx_clr_s cn; */
1291 };
1292 typedef union ody_gpio_tx_clr ody_gpio_tx_clr_t;
1293
1294 #define ODY_GPIO_TX_CLR ODY_GPIO_TX_CLR_FUNC()
1295 static inline uint64_t ODY_GPIO_TX_CLR_FUNC(void) __attribute__ ((pure, always_inline));
ODY_GPIO_TX_CLR_FUNC(void)1296 static inline uint64_t ODY_GPIO_TX_CLR_FUNC(void)
1297 {
1298 return 0x803000000010ll;
1299 }
1300
1301 #define typedef_ODY_GPIO_TX_CLR ody_gpio_tx_clr_t
1302 #define bustype_ODY_GPIO_TX_CLR CSR_TYPE_NCB
1303 #define basename_ODY_GPIO_TX_CLR "GPIO_TX_CLR"
1304 #define device_bar_ODY_GPIO_TX_CLR 0x0 /* PF_BAR0 */
1305 #define busnum_ODY_GPIO_TX_CLR 0
1306 #define arguments_ODY_GPIO_TX_CLR -1, -1, -1, -1
1307
1308 /**
1309 * Register (NCB) gpio_tx_set
1310 *
1311 * GPIO Transmit Set Mask Register
1312 * This register sets GPIO output data. GPIO_TX_SET sets the first 64 GPIOs, and
1313 * GPIO_TX1_SET the remainder.
1314 *
1315 * Each bit in this register is only accessible to the requestor(s) permitted with
1316 * GPIO_BIT_PERMIT(), but error will not be reported when there are bits are not
1317 * permitted by GPIO_BIT_PERMIT().
1318 *
1319 * When permitted, this register is accessible through ROM scripts; see SCR_WRITE32_S[ADDR].
1320 */
1321 union ody_gpio_tx_set {
1322 uint64_t u;
1323 struct ody_gpio_tx_set_s {
1324 uint64_t set : 64;
1325 } s;
1326 /* struct ody_gpio_tx_set_s cn; */
1327 };
1328 typedef union ody_gpio_tx_set ody_gpio_tx_set_t;
1329
1330 #define ODY_GPIO_TX_SET ODY_GPIO_TX_SET_FUNC()
1331 static inline uint64_t ODY_GPIO_TX_SET_FUNC(void) __attribute__ ((pure, always_inline));
ODY_GPIO_TX_SET_FUNC(void)1332 static inline uint64_t ODY_GPIO_TX_SET_FUNC(void)
1333 {
1334 return 0x803000000008ll;
1335 }
1336
1337 #define typedef_ODY_GPIO_TX_SET ody_gpio_tx_set_t
1338 #define bustype_ODY_GPIO_TX_SET CSR_TYPE_NCB
1339 #define basename_ODY_GPIO_TX_SET "GPIO_TX_SET"
1340 #define device_bar_ODY_GPIO_TX_SET 0x0 /* PF_BAR0 */
1341 #define busnum_ODY_GPIO_TX_SET 0
1342 #define arguments_ODY_GPIO_TX_SET -1, -1, -1, -1
1343
1344 #endif /* __ODY_CSRS_GPIO_H__ */
1345