1 #ifndef __ODY_CSRS_PCIERC_H__
2 #define __ODY_CSRS_PCIERC_H__
3 /* This file is auto-generated. Do not edit */
4
5 /***********************license start***********************************
6 * Copyright (C) 2021-2026 Marvell.
7 * SPDX-License-Identifier: BSD-3-Clause
8 * https://spdx.org/licenses
9 ***********************license end**************************************/
10
11
12 /**
13 * @file
14 *
15 * Configuration and status register (CSR) address and type definitions for
16 * PCIERC.
17 *
18 * This file is auto generated. Do not edit.
19 *
20 */
21
22 /**
23 * Register (PCICONFIGRC) pcierc#_ack_freq
24 *
25 * PCIe RC Ack Frequency Register
26 */
27 union ody_pciercx_ack_freq {
28 uint32_t u;
29 struct ody_pciercx_ack_freq_s {
30 uint32_t ack_freq : 8;
31 uint32_t n_fts : 8;
32 uint32_t n_fts_cc : 8;
33 uint32_t l0el : 3;
34 uint32_t l1el : 3;
35 uint32_t easpml1 : 1;
36 uint32_t aspm_timer_en : 1;
37 } s;
38 /* struct ody_pciercx_ack_freq_s cn; */
39 };
40 typedef union ody_pciercx_ack_freq ody_pciercx_ack_freq_t;
41
42 static inline uint64_t ODY_PCIERCX_ACK_FREQ(uint64_t a) __attribute__ ((pure, always_inline));
ODY_PCIERCX_ACK_FREQ(uint64_t a)43 static inline uint64_t ODY_PCIERCX_ACK_FREQ(uint64_t a)
44 {
45 if (a <= 15)
46 return 0x70c;
47 __ody_csr_fatal("PCIERCX_ACK_FREQ", 1, a, 0, 0, 0, 0, 0);
48 }
49
50 #define typedef_ODY_PCIERCX_ACK_FREQ(a) ody_pciercx_ack_freq_t
51 #define bustype_ODY_PCIERCX_ACK_FREQ(a) CSR_TYPE_PCICONFIGRC
52 #define basename_ODY_PCIERCX_ACK_FREQ(a) "PCIERCX_ACK_FREQ"
53 #define busnum_ODY_PCIERCX_ACK_FREQ(a) (a)
54 #define arguments_ODY_PCIERCX_ACK_FREQ(a) (a), -1, -1, -1
55
56 /**
57 * Register (PCICONFIGRC) pcierc#_ack_timer
58 *
59 * PCIe RC Ack Latency Timer/Replay Timer Register
60 */
61 union ody_pciercx_ack_timer {
62 uint32_t u;
63 struct ody_pciercx_ack_timer_s {
64 uint32_t rtltl : 16;
65 uint32_t rtl : 16;
66 } s;
67 /* struct ody_pciercx_ack_timer_s cn; */
68 };
69 typedef union ody_pciercx_ack_timer ody_pciercx_ack_timer_t;
70
71 static inline uint64_t ODY_PCIERCX_ACK_TIMER(uint64_t a) __attribute__ ((pure, always_inline));
ODY_PCIERCX_ACK_TIMER(uint64_t a)72 static inline uint64_t ODY_PCIERCX_ACK_TIMER(uint64_t a)
73 {
74 if (a <= 15)
75 return 0x700;
76 __ody_csr_fatal("PCIERCX_ACK_TIMER", 1, a, 0, 0, 0, 0, 0);
77 }
78
79 #define typedef_ODY_PCIERCX_ACK_TIMER(a) ody_pciercx_ack_timer_t
80 #define bustype_ODY_PCIERCX_ACK_TIMER(a) CSR_TYPE_PCICONFIGRC
81 #define basename_ODY_PCIERCX_ACK_TIMER(a) "PCIERCX_ACK_TIMER"
82 #define busnum_ODY_PCIERCX_ACK_TIMER(a) (a)
83 #define arguments_ODY_PCIERCX_ACK_TIMER(a) (a), -1, -1, -1
84
85 /**
86 * Register (PCICONFIGRC) pcierc#_acs_cap_ctl
87 *
88 * PCIe RC ACS Capability and Control Register
89 */
90 union ody_pciercx_acs_cap_ctl {
91 uint32_t u;
92 struct ody_pciercx_acs_cap_ctl_s {
93 uint32_t sv : 1;
94 uint32_t tb : 1;
95 uint32_t rr : 1;
96 uint32_t cr : 1;
97 uint32_t uf : 1;
98 uint32_t ec : 1;
99 uint32_t dt : 1;
100 uint32_t reserved_7 : 1;
101 uint32_t ecvs : 8;
102 uint32_t sve : 1;
103 uint32_t tbe : 1;
104 uint32_t rre : 1;
105 uint32_t cre : 1;
106 uint32_t ufe : 1;
107 uint32_t ece : 1;
108 uint32_t dte : 1;
109 uint32_t reserved_23_31 : 9;
110 } s;
111 /* struct ody_pciercx_acs_cap_ctl_s cn; */
112 };
113 typedef union ody_pciercx_acs_cap_ctl ody_pciercx_acs_cap_ctl_t;
114
115 static inline uint64_t ODY_PCIERCX_ACS_CAP_CTL(uint64_t a) __attribute__ ((pure, always_inline));
ODY_PCIERCX_ACS_CAP_CTL(uint64_t a)116 static inline uint64_t ODY_PCIERCX_ACS_CAP_CTL(uint64_t a)
117 {
118 if (a <= 15)
119 return 0x254;
120 __ody_csr_fatal("PCIERCX_ACS_CAP_CTL", 1, a, 0, 0, 0, 0, 0);
121 }
122
123 #define typedef_ODY_PCIERCX_ACS_CAP_CTL(a) ody_pciercx_acs_cap_ctl_t
124 #define bustype_ODY_PCIERCX_ACS_CAP_CTL(a) CSR_TYPE_PCICONFIGRC
125 #define basename_ODY_PCIERCX_ACS_CAP_CTL(a) "PCIERCX_ACS_CAP_CTL"
126 #define busnum_ODY_PCIERCX_ACS_CAP_CTL(a) (a)
127 #define arguments_ODY_PCIERCX_ACS_CAP_CTL(a) (a), -1, -1, -1
128
129 /**
130 * Register (PCICONFIGRC) pcierc#_acs_cap_hdr
131 *
132 * PCIe RC PCI Express ACS Extended Capability Header Register
133 */
134 union ody_pciercx_acs_cap_hdr {
135 uint32_t u;
136 struct ody_pciercx_acs_cap_hdr_s {
137 uint32_t pcieec : 16;
138 uint32_t cv : 4;
139 uint32_t nco : 12;
140 } s;
141 /* struct ody_pciercx_acs_cap_hdr_s cn; */
142 };
143 typedef union ody_pciercx_acs_cap_hdr ody_pciercx_acs_cap_hdr_t;
144
145 static inline uint64_t ODY_PCIERCX_ACS_CAP_HDR(uint64_t a) __attribute__ ((pure, always_inline));
ODY_PCIERCX_ACS_CAP_HDR(uint64_t a)146 static inline uint64_t ODY_PCIERCX_ACS_CAP_HDR(uint64_t a)
147 {
148 if (a <= 15)
149 return 0x250;
150 __ody_csr_fatal("PCIERCX_ACS_CAP_HDR", 1, a, 0, 0, 0, 0, 0);
151 }
152
153 #define typedef_ODY_PCIERCX_ACS_CAP_HDR(a) ody_pciercx_acs_cap_hdr_t
154 #define bustype_ODY_PCIERCX_ACS_CAP_HDR(a) CSR_TYPE_PCICONFIGRC
155 #define basename_ODY_PCIERCX_ACS_CAP_HDR(a) "PCIERCX_ACS_CAP_HDR"
156 #define busnum_ODY_PCIERCX_ACS_CAP_HDR(a) (a)
157 #define arguments_ODY_PCIERCX_ACS_CAP_HDR(a) (a), -1, -1, -1
158
159 /**
160 * Register (PCICONFIGRC) pcierc#_acs_egr_ctl_vec
161 *
162 * PCIe RC Egress Control Vector Register
163 */
164 union ody_pciercx_acs_egr_ctl_vec {
165 uint32_t u;
166 struct ody_pciercx_acs_egr_ctl_vec_s {
167 uint32_t ecv : 3;
168 uint32_t unused : 29;
169 } s;
170 /* struct ody_pciercx_acs_egr_ctl_vec_s cn; */
171 };
172 typedef union ody_pciercx_acs_egr_ctl_vec ody_pciercx_acs_egr_ctl_vec_t;
173
174 static inline uint64_t ODY_PCIERCX_ACS_EGR_CTL_VEC(uint64_t a) __attribute__ ((pure, always_inline));
ODY_PCIERCX_ACS_EGR_CTL_VEC(uint64_t a)175 static inline uint64_t ODY_PCIERCX_ACS_EGR_CTL_VEC(uint64_t a)
176 {
177 if (a <= 15)
178 return 0x258;
179 __ody_csr_fatal("PCIERCX_ACS_EGR_CTL_VEC", 1, a, 0, 0, 0, 0, 0);
180 }
181
182 #define typedef_ODY_PCIERCX_ACS_EGR_CTL_VEC(a) ody_pciercx_acs_egr_ctl_vec_t
183 #define bustype_ODY_PCIERCX_ACS_EGR_CTL_VEC(a) CSR_TYPE_PCICONFIGRC
184 #define basename_ODY_PCIERCX_ACS_EGR_CTL_VEC(a) "PCIERCX_ACS_EGR_CTL_VEC"
185 #define busnum_ODY_PCIERCX_ACS_EGR_CTL_VEC(a) (a)
186 #define arguments_ODY_PCIERCX_ACS_EGR_CTL_VEC(a) (a), -1, -1, -1
187
188 /**
189 * Register (PCICONFIGRC) pcierc#_adv_err_cap_cntrl
190 *
191 * PCIe RC Advanced Capabilities and Control Register
192 */
193 union ody_pciercx_adv_err_cap_cntrl {
194 uint32_t u;
195 struct ody_pciercx_adv_err_cap_cntrl_s {
196 uint32_t fep : 5;
197 uint32_t gc : 1;
198 uint32_t ge : 1;
199 uint32_t cc : 1;
200 uint32_t ce : 1;
201 uint32_t mult_hdr_cap : 1;
202 uint32_t mult_hdr_en : 1;
203 uint32_t tlp_plp : 1;
204 uint32_t reserved_12_31 : 20;
205 } s;
206 /* struct ody_pciercx_adv_err_cap_cntrl_s cn; */
207 };
208 typedef union ody_pciercx_adv_err_cap_cntrl ody_pciercx_adv_err_cap_cntrl_t;
209
210 static inline uint64_t ODY_PCIERCX_ADV_ERR_CAP_CNTRL(uint64_t a) __attribute__ ((pure, always_inline));
ODY_PCIERCX_ADV_ERR_CAP_CNTRL(uint64_t a)211 static inline uint64_t ODY_PCIERCX_ADV_ERR_CAP_CNTRL(uint64_t a)
212 {
213 if (a <= 15)
214 return 0x118;
215 __ody_csr_fatal("PCIERCX_ADV_ERR_CAP_CNTRL", 1, a, 0, 0, 0, 0, 0);
216 }
217
218 #define typedef_ODY_PCIERCX_ADV_ERR_CAP_CNTRL(a) ody_pciercx_adv_err_cap_cntrl_t
219 #define bustype_ODY_PCIERCX_ADV_ERR_CAP_CNTRL(a) CSR_TYPE_PCICONFIGRC
220 #define basename_ODY_PCIERCX_ADV_ERR_CAP_CNTRL(a) "PCIERCX_ADV_ERR_CAP_CNTRL"
221 #define busnum_ODY_PCIERCX_ADV_ERR_CAP_CNTRL(a) (a)
222 #define arguments_ODY_PCIERCX_ADV_ERR_CAP_CNTRL(a) (a), -1, -1, -1
223
224 /**
225 * Register (PCICONFIGRC) pcierc#_ats_cap_ctl
226 *
227 * PCIe RC PCI Express ATS Extended Capability And Control Register
228 */
229 union ody_pciercx_ats_cap_ctl {
230 uint32_t u;
231 struct ody_pciercx_ats_cap_ctl_s {
232 uint32_t iqd : 5;
233 uint32_t par : 1;
234 uint32_t gis : 1;
235 uint32_t ros : 1;
236 uint32_t reserved_8_15 : 8;
237 uint32_t stu : 5;
238 uint32_t reserved_21_30 : 10;
239 uint32_t en : 1;
240 } s;
241 /* struct ody_pciercx_ats_cap_ctl_s cn; */
242 };
243 typedef union ody_pciercx_ats_cap_ctl ody_pciercx_ats_cap_ctl_t;
244
245 static inline uint64_t ODY_PCIERCX_ATS_CAP_CTL(uint64_t a) __attribute__ ((pure, always_inline));
ODY_PCIERCX_ATS_CAP_CTL(uint64_t a)246 static inline uint64_t ODY_PCIERCX_ATS_CAP_CTL(uint64_t a)
247 {
248 if (a <= 15)
249 return 0x244;
250 __ody_csr_fatal("PCIERCX_ATS_CAP_CTL", 1, a, 0, 0, 0, 0, 0);
251 }
252
253 #define typedef_ODY_PCIERCX_ATS_CAP_CTL(a) ody_pciercx_ats_cap_ctl_t
254 #define bustype_ODY_PCIERCX_ATS_CAP_CTL(a) CSR_TYPE_PCICONFIGRC
255 #define basename_ODY_PCIERCX_ATS_CAP_CTL(a) "PCIERCX_ATS_CAP_CTL"
256 #define busnum_ODY_PCIERCX_ATS_CAP_CTL(a) (a)
257 #define arguments_ODY_PCIERCX_ATS_CAP_CTL(a) (a), -1, -1, -1
258
259 /**
260 * Register (PCICONFIGRC) pcierc#_ats_cap_hdr
261 *
262 * PCIe RC PCI Express ATS Extended Capability Header Register
263 */
264 union ody_pciercx_ats_cap_hdr {
265 uint32_t u;
266 struct ody_pciercx_ats_cap_hdr_s {
267 uint32_t pcieec : 16;
268 uint32_t cv : 4;
269 uint32_t nco : 12;
270 } s;
271 /* struct ody_pciercx_ats_cap_hdr_s cn; */
272 };
273 typedef union ody_pciercx_ats_cap_hdr ody_pciercx_ats_cap_hdr_t;
274
275 static inline uint64_t ODY_PCIERCX_ATS_CAP_HDR(uint64_t a) __attribute__ ((pure, always_inline));
ODY_PCIERCX_ATS_CAP_HDR(uint64_t a)276 static inline uint64_t ODY_PCIERCX_ATS_CAP_HDR(uint64_t a)
277 {
278 if (a <= 15)
279 return 0x240;
280 __ody_csr_fatal("PCIERCX_ATS_CAP_HDR", 1, a, 0, 0, 0, 0, 0);
281 }
282
283 #define typedef_ODY_PCIERCX_ATS_CAP_HDR(a) ody_pciercx_ats_cap_hdr_t
284 #define bustype_ODY_PCIERCX_ATS_CAP_HDR(a) CSR_TYPE_PCICONFIGRC
285 #define basename_ODY_PCIERCX_ATS_CAP_HDR(a) "PCIERCX_ATS_CAP_HDR"
286 #define busnum_ODY_PCIERCX_ATS_CAP_HDR(a) (a)
287 #define arguments_ODY_PCIERCX_ATS_CAP_HDR(a) (a), -1, -1, -1
288
289 /**
290 * Register (PCICONFIGRC) pcierc#_aux_clk_freq
291 *
292 * PCIe RC Auxiliary Clock Frequency Control Register
293 */
294 union ody_pciercx_aux_clk_freq {
295 uint32_t u;
296 struct ody_pciercx_aux_clk_freq_s {
297 uint32_t upc_supp : 10;
298 uint32_t reserved_10_31 : 22;
299 } s;
300 /* struct ody_pciercx_aux_clk_freq_s cn; */
301 };
302 typedef union ody_pciercx_aux_clk_freq ody_pciercx_aux_clk_freq_t;
303
304 static inline uint64_t ODY_PCIERCX_AUX_CLK_FREQ(uint64_t a) __attribute__ ((pure, always_inline));
ODY_PCIERCX_AUX_CLK_FREQ(uint64_t a)305 static inline uint64_t ODY_PCIERCX_AUX_CLK_FREQ(uint64_t a)
306 {
307 if (a <= 15)
308 return 0xb40;
309 __ody_csr_fatal("PCIERCX_AUX_CLK_FREQ", 1, a, 0, 0, 0, 0, 0);
310 }
311
312 #define typedef_ODY_PCIERCX_AUX_CLK_FREQ(a) ody_pciercx_aux_clk_freq_t
313 #define bustype_ODY_PCIERCX_AUX_CLK_FREQ(a) CSR_TYPE_PCICONFIGRC
314 #define basename_ODY_PCIERCX_AUX_CLK_FREQ(a) "PCIERCX_AUX_CLK_FREQ"
315 #define busnum_ODY_PCIERCX_AUX_CLK_FREQ(a) (a)
316 #define arguments_ODY_PCIERCX_AUX_CLK_FREQ(a) (a), -1, -1, -1
317
318 /**
319 * Register (PCICONFIGRC) pcierc#_bar0l
320 *
321 * PCIe RC Base Address 0 Low Register
322 */
323 union ody_pciercx_bar0l {
324 uint32_t u;
325 struct ody_pciercx_bar0l_s {
326 uint32_t reserved_0_31 : 32;
327 } s;
328 /* struct ody_pciercx_bar0l_s cn; */
329 };
330 typedef union ody_pciercx_bar0l ody_pciercx_bar0l_t;
331
332 static inline uint64_t ODY_PCIERCX_BAR0L(uint64_t a) __attribute__ ((pure, always_inline));
ODY_PCIERCX_BAR0L(uint64_t a)333 static inline uint64_t ODY_PCIERCX_BAR0L(uint64_t a)
334 {
335 if (a <= 15)
336 return 0x10;
337 __ody_csr_fatal("PCIERCX_BAR0L", 1, a, 0, 0, 0, 0, 0);
338 }
339
340 #define typedef_ODY_PCIERCX_BAR0L(a) ody_pciercx_bar0l_t
341 #define bustype_ODY_PCIERCX_BAR0L(a) CSR_TYPE_PCICONFIGRC
342 #define basename_ODY_PCIERCX_BAR0L(a) "PCIERCX_BAR0L"
343 #define busnum_ODY_PCIERCX_BAR0L(a) (a)
344 #define arguments_ODY_PCIERCX_BAR0L(a) (a), -1, -1, -1
345
346 /**
347 * Register (PCICONFIGRC) pcierc#_bar0u
348 *
349 * PCIe RC Base Address 0 High Register
350 */
351 union ody_pciercx_bar0u {
352 uint32_t u;
353 struct ody_pciercx_bar0u_s {
354 uint32_t reserved_0_31 : 32;
355 } s;
356 /* struct ody_pciercx_bar0u_s cn; */
357 };
358 typedef union ody_pciercx_bar0u ody_pciercx_bar0u_t;
359
360 static inline uint64_t ODY_PCIERCX_BAR0U(uint64_t a) __attribute__ ((pure, always_inline));
ODY_PCIERCX_BAR0U(uint64_t a)361 static inline uint64_t ODY_PCIERCX_BAR0U(uint64_t a)
362 {
363 if (a <= 15)
364 return 0x14;
365 __ody_csr_fatal("PCIERCX_BAR0U", 1, a, 0, 0, 0, 0, 0);
366 }
367
368 #define typedef_ODY_PCIERCX_BAR0U(a) ody_pciercx_bar0u_t
369 #define bustype_ODY_PCIERCX_BAR0U(a) CSR_TYPE_PCICONFIGRC
370 #define basename_ODY_PCIERCX_BAR0U(a) "PCIERCX_BAR0U"
371 #define busnum_ODY_PCIERCX_BAR0U(a) (a)
372 #define arguments_ODY_PCIERCX_BAR0U(a) (a), -1, -1, -1
373
374 /**
375 * Register (PCICONFIGRC) pcierc#_bnum
376 *
377 * PCIe RC Bus Number Register
378 */
379 union ody_pciercx_bnum {
380 uint32_t u;
381 struct ody_pciercx_bnum_s {
382 uint32_t pbnum : 8;
383 uint32_t sbnum : 8;
384 uint32_t subbnum : 8;
385 uint32_t slt : 8;
386 } s;
387 /* struct ody_pciercx_bnum_s cn; */
388 };
389 typedef union ody_pciercx_bnum ody_pciercx_bnum_t;
390
391 static inline uint64_t ODY_PCIERCX_BNUM(uint64_t a) __attribute__ ((pure, always_inline));
ODY_PCIERCX_BNUM(uint64_t a)392 static inline uint64_t ODY_PCIERCX_BNUM(uint64_t a)
393 {
394 if (a <= 15)
395 return 0x18;
396 __ody_csr_fatal("PCIERCX_BNUM", 1, a, 0, 0, 0, 0, 0);
397 }
398
399 #define typedef_ODY_PCIERCX_BNUM(a) ody_pciercx_bnum_t
400 #define bustype_ODY_PCIERCX_BNUM(a) CSR_TYPE_PCICONFIGRC
401 #define basename_ODY_PCIERCX_BNUM(a) "PCIERCX_BNUM"
402 #define busnum_ODY_PCIERCX_BNUM(a) (a)
403 #define arguments_ODY_PCIERCX_BNUM(a) (a), -1, -1, -1
404
405 /**
406 * Register (PCICONFIGRC) pcierc#_c_rcv_credit
407 *
408 * PCIe RC VC0 Completion Receive Queue Control Register
409 */
410 union ody_pciercx_c_rcv_credit {
411 uint32_t u;
412 struct ody_pciercx_c_rcv_credit_s {
413 uint32_t data_credits : 12;
414 uint32_t header_credits : 8;
415 uint32_t reserved_20 : 1;
416 uint32_t queue_mode : 3;
417 uint32_t hdr_sc : 2;
418 uint32_t data_sc : 2;
419 uint32_t reserved_28_31 : 4;
420 } s;
421 /* struct ody_pciercx_c_rcv_credit_s cn; */
422 };
423 typedef union ody_pciercx_c_rcv_credit ody_pciercx_c_rcv_credit_t;
424
425 static inline uint64_t ODY_PCIERCX_C_RCV_CREDIT(uint64_t a) __attribute__ ((pure, always_inline));
ODY_PCIERCX_C_RCV_CREDIT(uint64_t a)426 static inline uint64_t ODY_PCIERCX_C_RCV_CREDIT(uint64_t a)
427 {
428 if (a <= 15)
429 return 0x750;
430 __ody_csr_fatal("PCIERCX_C_RCV_CREDIT", 1, a, 0, 0, 0, 0, 0);
431 }
432
433 #define typedef_ODY_PCIERCX_C_RCV_CREDIT(a) ody_pciercx_c_rcv_credit_t
434 #define bustype_ODY_PCIERCX_C_RCV_CREDIT(a) CSR_TYPE_PCICONFIGRC
435 #define basename_ODY_PCIERCX_C_RCV_CREDIT(a) "PCIERCX_C_RCV_CREDIT"
436 #define busnum_ODY_PCIERCX_C_RCV_CREDIT(a) (a)
437 #define arguments_ODY_PCIERCX_C_RCV_CREDIT(a) (a), -1, -1, -1
438
439 /**
440 * Register (PCICONFIGRC) pcierc#_c_xmit_credit
441 *
442 * PCIe RC Transmit Completion FC Credit Status Register
443 */
444 union ody_pciercx_c_xmit_credit {
445 uint32_t u;
446 struct ody_pciercx_c_xmit_credit_s {
447 uint32_t tcdfcc : 16;
448 uint32_t tchfcc : 12;
449 uint32_t reserved_28_31 : 4;
450 } s;
451 /* struct ody_pciercx_c_xmit_credit_s cn; */
452 };
453 typedef union ody_pciercx_c_xmit_credit ody_pciercx_c_xmit_credit_t;
454
455 static inline uint64_t ODY_PCIERCX_C_XMIT_CREDIT(uint64_t a) __attribute__ ((pure, always_inline));
ODY_PCIERCX_C_XMIT_CREDIT(uint64_t a)456 static inline uint64_t ODY_PCIERCX_C_XMIT_CREDIT(uint64_t a)
457 {
458 if (a <= 15)
459 return 0x738;
460 __ody_csr_fatal("PCIERCX_C_XMIT_CREDIT", 1, a, 0, 0, 0, 0, 0);
461 }
462
463 #define typedef_ODY_PCIERCX_C_XMIT_CREDIT(a) ody_pciercx_c_xmit_credit_t
464 #define bustype_ODY_PCIERCX_C_XMIT_CREDIT(a) CSR_TYPE_PCICONFIGRC
465 #define basename_ODY_PCIERCX_C_XMIT_CREDIT(a) "PCIERCX_C_XMIT_CREDIT"
466 #define busnum_ODY_PCIERCX_C_XMIT_CREDIT(a) (a)
467 #define arguments_ODY_PCIERCX_C_XMIT_CREDIT(a) (a), -1, -1, -1
468
469 /**
470 * Register (PCICONFIGRC) pcierc#_cap_ptr
471 *
472 * PCIe RC Capability Pointer Register
473 */
474 union ody_pciercx_cap_ptr {
475 uint32_t u;
476 struct ody_pciercx_cap_ptr_s {
477 uint32_t cp : 8;
478 uint32_t reserved_8_31 : 24;
479 } s;
480 /* struct ody_pciercx_cap_ptr_s cn; */
481 };
482 typedef union ody_pciercx_cap_ptr ody_pciercx_cap_ptr_t;
483
484 static inline uint64_t ODY_PCIERCX_CAP_PTR(uint64_t a) __attribute__ ((pure, always_inline));
ODY_PCIERCX_CAP_PTR(uint64_t a)485 static inline uint64_t ODY_PCIERCX_CAP_PTR(uint64_t a)
486 {
487 if (a <= 15)
488 return 0x34;
489 __ody_csr_fatal("PCIERCX_CAP_PTR", 1, a, 0, 0, 0, 0, 0);
490 }
491
492 #define typedef_ODY_PCIERCX_CAP_PTR(a) ody_pciercx_cap_ptr_t
493 #define bustype_ODY_PCIERCX_CAP_PTR(a) CSR_TYPE_PCICONFIGRC
494 #define basename_ODY_PCIERCX_CAP_PTR(a) "PCIERCX_CAP_PTR"
495 #define busnum_ODY_PCIERCX_CAP_PTR(a) (a)
496 #define arguments_ODY_PCIERCX_CAP_PTR(a) (a), -1, -1, -1
497
498 /**
499 * Register (PCICONFIGRC) pcierc#_clk_gating_ctl
500 *
501 * PCIe RC RADM Clock Gating Enable Control Register
502 */
503 union ody_pciercx_clk_gating_ctl {
504 uint32_t u;
505 struct ody_pciercx_clk_gating_ctl_s {
506 uint32_t radm_clk_gating_en : 1;
507 uint32_t reserved_1_31 : 31;
508 } s;
509 /* struct ody_pciercx_clk_gating_ctl_s cn; */
510 };
511 typedef union ody_pciercx_clk_gating_ctl ody_pciercx_clk_gating_ctl_t;
512
513 static inline uint64_t ODY_PCIERCX_CLK_GATING_CTL(uint64_t a) __attribute__ ((pure, always_inline));
ODY_PCIERCX_CLK_GATING_CTL(uint64_t a)514 static inline uint64_t ODY_PCIERCX_CLK_GATING_CTL(uint64_t a)
515 {
516 if (a <= 15)
517 return 0x88c;
518 __ody_csr_fatal("PCIERCX_CLK_GATING_CTL", 1, a, 0, 0, 0, 0, 0);
519 }
520
521 #define typedef_ODY_PCIERCX_CLK_GATING_CTL(a) ody_pciercx_clk_gating_ctl_t
522 #define bustype_ODY_PCIERCX_CLK_GATING_CTL(a) CSR_TYPE_PCICONFIGRC
523 #define basename_ODY_PCIERCX_CLK_GATING_CTL(a) "PCIERCX_CLK_GATING_CTL"
524 #define busnum_ODY_PCIERCX_CLK_GATING_CTL(a) (a)
525 #define arguments_ODY_PCIERCX_CLK_GATING_CTL(a) (a), -1, -1, -1
526
527 /**
528 * Register (PCICONFIGRC) pcierc#_clsize
529 *
530 * PCIe RC BIST, Header Type, Master Latency Timer, Cache Line Size Register
531 */
532 union ody_pciercx_clsize {
533 uint32_t u;
534 struct ody_pciercx_clsize_s {
535 uint32_t cls : 8;
536 uint32_t lt : 8;
537 uint32_t chf : 7;
538 uint32_t mfd : 1;
539 uint32_t bist : 8;
540 } s;
541 /* struct ody_pciercx_clsize_s cn; */
542 };
543 typedef union ody_pciercx_clsize ody_pciercx_clsize_t;
544
545 static inline uint64_t ODY_PCIERCX_CLSIZE(uint64_t a) __attribute__ ((pure, always_inline));
ODY_PCIERCX_CLSIZE(uint64_t a)546 static inline uint64_t ODY_PCIERCX_CLSIZE(uint64_t a)
547 {
548 if (a <= 15)
549 return 0xc;
550 __ody_csr_fatal("PCIERCX_CLSIZE", 1, a, 0, 0, 0, 0, 0);
551 }
552
553 #define typedef_ODY_PCIERCX_CLSIZE(a) ody_pciercx_clsize_t
554 #define bustype_ODY_PCIERCX_CLSIZE(a) CSR_TYPE_PCICONFIGRC
555 #define basename_ODY_PCIERCX_CLSIZE(a) "PCIERCX_CLSIZE"
556 #define busnum_ODY_PCIERCX_CLSIZE(a) (a)
557 #define arguments_ODY_PCIERCX_CLSIZE(a) (a), -1, -1, -1
558
559 /**
560 * Register (PCICONFIGRC) pcierc#_cmd
561 *
562 * PCIe RC Command/Status Register
563 */
564 union ody_pciercx_cmd {
565 uint32_t u;
566 struct ody_pciercx_cmd_s {
567 uint32_t isae : 1;
568 uint32_t msae : 1;
569 uint32_t me : 1;
570 uint32_t scse : 1;
571 uint32_t mwice : 1;
572 uint32_t vps : 1;
573 uint32_t per : 1;
574 uint32_t ids_wcc : 1;
575 uint32_t see : 1;
576 uint32_t fbbe : 1;
577 uint32_t i_dis : 1;
578 uint32_t reserved_11_18 : 8;
579 uint32_t i_stat : 1;
580 uint32_t cl : 1;
581 uint32_t m66 : 1;
582 uint32_t reserved_22 : 1;
583 uint32_t fbb : 1;
584 uint32_t mdpe : 1;
585 uint32_t devt : 2;
586 uint32_t sta : 1;
587 uint32_t rta : 1;
588 uint32_t rma : 1;
589 uint32_t sse : 1;
590 uint32_t dpe : 1;
591 } s;
592 /* struct ody_pciercx_cmd_s cn; */
593 };
594 typedef union ody_pciercx_cmd ody_pciercx_cmd_t;
595
596 static inline uint64_t ODY_PCIERCX_CMD(uint64_t a) __attribute__ ((pure, always_inline));
ODY_PCIERCX_CMD(uint64_t a)597 static inline uint64_t ODY_PCIERCX_CMD(uint64_t a)
598 {
599 if (a <= 15)
600 return 4;
601 __ody_csr_fatal("PCIERCX_CMD", 1, a, 0, 0, 0, 0, 0);
602 }
603
604 #define typedef_ODY_PCIERCX_CMD(a) ody_pciercx_cmd_t
605 #define bustype_ODY_PCIERCX_CMD(a) CSR_TYPE_PCICONFIGRC
606 #define basename_ODY_PCIERCX_CMD(a) "PCIERCX_CMD"
607 #define busnum_ODY_PCIERCX_CMD(a) (a)
608 #define arguments_ODY_PCIERCX_CMD(a) (a), -1, -1, -1
609
610 /**
611 * Register (PCICONFIGRC) pcierc#_cor_err_msk
612 *
613 * PCIe RC Correctable Error Mask Register
614 */
615 union ody_pciercx_cor_err_msk {
616 uint32_t u;
617 struct ody_pciercx_cor_err_msk_s {
618 uint32_t rem : 1;
619 uint32_t reserved_1_5 : 5;
620 uint32_t btlpm : 1;
621 uint32_t bdllpm : 1;
622 uint32_t rnrm : 1;
623 uint32_t reserved_9_11 : 3;
624 uint32_t rttm : 1;
625 uint32_t anfem : 1;
626 uint32_t ciem : 1;
627 uint32_t chlom : 1;
628 uint32_t reserved_16_31 : 16;
629 } s;
630 /* struct ody_pciercx_cor_err_msk_s cn; */
631 };
632 typedef union ody_pciercx_cor_err_msk ody_pciercx_cor_err_msk_t;
633
634 static inline uint64_t ODY_PCIERCX_COR_ERR_MSK(uint64_t a) __attribute__ ((pure, always_inline));
ODY_PCIERCX_COR_ERR_MSK(uint64_t a)635 static inline uint64_t ODY_PCIERCX_COR_ERR_MSK(uint64_t a)
636 {
637 if (a <= 15)
638 return 0x114;
639 __ody_csr_fatal("PCIERCX_COR_ERR_MSK", 1, a, 0, 0, 0, 0, 0);
640 }
641
642 #define typedef_ODY_PCIERCX_COR_ERR_MSK(a) ody_pciercx_cor_err_msk_t
643 #define bustype_ODY_PCIERCX_COR_ERR_MSK(a) CSR_TYPE_PCICONFIGRC
644 #define basename_ODY_PCIERCX_COR_ERR_MSK(a) "PCIERCX_COR_ERR_MSK"
645 #define busnum_ODY_PCIERCX_COR_ERR_MSK(a) (a)
646 #define arguments_ODY_PCIERCX_COR_ERR_MSK(a) (a), -1, -1, -1
647
648 /**
649 * Register (PCICONFIGRC) pcierc#_cor_err_stat
650 *
651 * PCIe RC Correctable Error Status Register
652 */
653 union ody_pciercx_cor_err_stat {
654 uint32_t u;
655 struct ody_pciercx_cor_err_stat_s {
656 uint32_t res : 1;
657 uint32_t reserved_1_5 : 5;
658 uint32_t btlps : 1;
659 uint32_t bdllps : 1;
660 uint32_t rnrs : 1;
661 uint32_t reserved_9_11 : 3;
662 uint32_t rtts : 1;
663 uint32_t anfes : 1;
664 uint32_t cies : 1;
665 uint32_t chlo : 1;
666 uint32_t reserved_16_31 : 16;
667 } s;
668 /* struct ody_pciercx_cor_err_stat_s cn; */
669 };
670 typedef union ody_pciercx_cor_err_stat ody_pciercx_cor_err_stat_t;
671
672 static inline uint64_t ODY_PCIERCX_COR_ERR_STAT(uint64_t a) __attribute__ ((pure, always_inline));
ODY_PCIERCX_COR_ERR_STAT(uint64_t a)673 static inline uint64_t ODY_PCIERCX_COR_ERR_STAT(uint64_t a)
674 {
675 if (a <= 15)
676 return 0x110;
677 __ody_csr_fatal("PCIERCX_COR_ERR_STAT", 1, a, 0, 0, 0, 0, 0);
678 }
679
680 #define typedef_ODY_PCIERCX_COR_ERR_STAT(a) ody_pciercx_cor_err_stat_t
681 #define bustype_ODY_PCIERCX_COR_ERR_STAT(a) CSR_TYPE_PCICONFIGRC
682 #define basename_ODY_PCIERCX_COR_ERR_STAT(a) "PCIERCX_COR_ERR_STAT"
683 #define busnum_ODY_PCIERCX_COR_ERR_STAT(a) (a)
684 #define arguments_ODY_PCIERCX_COR_ERR_STAT(a) (a), -1, -1, -1
685
686 /**
687 * Register (PCICONFIGRC) pcierc#_dbg0
688 *
689 * PCIe RC Debug Register 0
690 */
691 union ody_pciercx_dbg0 {
692 uint32_t u;
693 struct ody_pciercx_dbg0_s {
694 uint32_t dbg_info_l32 : 32;
695 } s;
696 /* struct ody_pciercx_dbg0_s cn; */
697 };
698 typedef union ody_pciercx_dbg0 ody_pciercx_dbg0_t;
699
700 static inline uint64_t ODY_PCIERCX_DBG0(uint64_t a) __attribute__ ((pure, always_inline));
ODY_PCIERCX_DBG0(uint64_t a)701 static inline uint64_t ODY_PCIERCX_DBG0(uint64_t a)
702 {
703 if (a <= 15)
704 return 0x728;
705 __ody_csr_fatal("PCIERCX_DBG0", 1, a, 0, 0, 0, 0, 0);
706 }
707
708 #define typedef_ODY_PCIERCX_DBG0(a) ody_pciercx_dbg0_t
709 #define bustype_ODY_PCIERCX_DBG0(a) CSR_TYPE_PCICONFIGRC
710 #define basename_ODY_PCIERCX_DBG0(a) "PCIERCX_DBG0"
711 #define busnum_ODY_PCIERCX_DBG0(a) (a)
712 #define arguments_ODY_PCIERCX_DBG0(a) (a), -1, -1, -1
713
714 /**
715 * Register (PCICONFIGRC) pcierc#_dbg1
716 *
717 * PCIe RC Debug Register 1
718 */
719 union ody_pciercx_dbg1 {
720 uint32_t u;
721 struct ody_pciercx_dbg1_s {
722 uint32_t dbg_info_u32 : 32;
723 } s;
724 /* struct ody_pciercx_dbg1_s cn; */
725 };
726 typedef union ody_pciercx_dbg1 ody_pciercx_dbg1_t;
727
728 static inline uint64_t ODY_PCIERCX_DBG1(uint64_t a) __attribute__ ((pure, always_inline));
ODY_PCIERCX_DBG1(uint64_t a)729 static inline uint64_t ODY_PCIERCX_DBG1(uint64_t a)
730 {
731 if (a <= 15)
732 return 0x72c;
733 __ody_csr_fatal("PCIERCX_DBG1", 1, a, 0, 0, 0, 0, 0);
734 }
735
736 #define typedef_ODY_PCIERCX_DBG1(a) ody_pciercx_dbg1_t
737 #define bustype_ODY_PCIERCX_DBG1(a) CSR_TYPE_PCICONFIGRC
738 #define basename_ODY_PCIERCX_DBG1(a) "PCIERCX_DBG1"
739 #define busnum_ODY_PCIERCX_DBG1(a) (a)
740 #define arguments_ODY_PCIERCX_DBG1(a) (a), -1, -1, -1
741
742 /**
743 * Register (PCICONFIGRC) pcierc#_dev_cap
744 *
745 * PCIe RC Device Capabilities Register
746 */
747 union ody_pciercx_dev_cap {
748 uint32_t u;
749 struct ody_pciercx_dev_cap_s {
750 uint32_t mpss : 3;
751 uint32_t pfs : 2;
752 uint32_t etfs : 1;
753 uint32_t el0al : 3;
754 uint32_t el1al : 3;
755 uint32_t reserved_12_14 : 3;
756 uint32_t rber : 1;
757 uint32_t reserved_16_17 : 2;
758 uint32_t csplv : 8;
759 uint32_t cspls : 2;
760 uint32_t flr_cap : 1;
761 uint32_t reserved_29_31 : 3;
762 } s;
763 struct ody_pciercx_dev_cap_cn {
764 uint32_t mpss : 3;
765 uint32_t pfs : 2;
766 uint32_t etfs : 1;
767 uint32_t el0al : 3;
768 uint32_t el1al : 3;
769 uint32_t reserved_12 : 1;
770 uint32_t reserved_13 : 1;
771 uint32_t reserved_14 : 1;
772 uint32_t rber : 1;
773 uint32_t reserved_16_17 : 2;
774 uint32_t csplv : 8;
775 uint32_t cspls : 2;
776 uint32_t flr_cap : 1;
777 uint32_t reserved_29_31 : 3;
778 } cn;
779 };
780 typedef union ody_pciercx_dev_cap ody_pciercx_dev_cap_t;
781
782 static inline uint64_t ODY_PCIERCX_DEV_CAP(uint64_t a) __attribute__ ((pure, always_inline));
ODY_PCIERCX_DEV_CAP(uint64_t a)783 static inline uint64_t ODY_PCIERCX_DEV_CAP(uint64_t a)
784 {
785 if (a <= 15)
786 return 0x74;
787 __ody_csr_fatal("PCIERCX_DEV_CAP", 1, a, 0, 0, 0, 0, 0);
788 }
789
790 #define typedef_ODY_PCIERCX_DEV_CAP(a) ody_pciercx_dev_cap_t
791 #define bustype_ODY_PCIERCX_DEV_CAP(a) CSR_TYPE_PCICONFIGRC
792 #define basename_ODY_PCIERCX_DEV_CAP(a) "PCIERCX_DEV_CAP"
793 #define busnum_ODY_PCIERCX_DEV_CAP(a) (a)
794 #define arguments_ODY_PCIERCX_DEV_CAP(a) (a), -1, -1, -1
795
796 /**
797 * Register (PCICONFIGRC) pcierc#_dev_cap2
798 *
799 * PCIe RC Device Capabilities 2 Register
800 */
801 union ody_pciercx_dev_cap2 {
802 uint32_t u;
803 struct ody_pciercx_dev_cap2_s {
804 uint32_t ctrs : 4;
805 uint32_t ctds : 1;
806 uint32_t ari_fw : 1;
807 uint32_t atom_ops : 1;
808 uint32_t atom32s : 1;
809 uint32_t atom64s : 1;
810 uint32_t atom128s : 1;
811 uint32_t noroprpr : 1;
812 uint32_t ltrs : 1;
813 uint32_t tph : 2;
814 uint32_t ln_sys_cls : 2;
815 uint32_t tag10b_cpl_supp : 1;
816 uint32_t tag10b_req_supp : 1;
817 uint32_t obffs : 2;
818 uint32_t effs : 1;
819 uint32_t eetps : 1;
820 uint32_t meetp : 2;
821 uint32_t eprs : 2;
822 uint32_t eprir : 1;
823 uint32_t reserved_27 : 1;
824 uint32_t dwrr_cpl_sup : 1;
825 uint32_t dwrr_len_sup : 2;
826 uint32_t frs_sup : 1;
827 } s;
828 /* struct ody_pciercx_dev_cap2_s cn; */
829 };
830 typedef union ody_pciercx_dev_cap2 ody_pciercx_dev_cap2_t;
831
832 static inline uint64_t ODY_PCIERCX_DEV_CAP2(uint64_t a) __attribute__ ((pure, always_inline));
ODY_PCIERCX_DEV_CAP2(uint64_t a)833 static inline uint64_t ODY_PCIERCX_DEV_CAP2(uint64_t a)
834 {
835 if (a <= 15)
836 return 0x94;
837 __ody_csr_fatal("PCIERCX_DEV_CAP2", 1, a, 0, 0, 0, 0, 0);
838 }
839
840 #define typedef_ODY_PCIERCX_DEV_CAP2(a) ody_pciercx_dev_cap2_t
841 #define bustype_ODY_PCIERCX_DEV_CAP2(a) CSR_TYPE_PCICONFIGRC
842 #define basename_ODY_PCIERCX_DEV_CAP2(a) "PCIERCX_DEV_CAP2"
843 #define busnum_ODY_PCIERCX_DEV_CAP2(a) (a)
844 #define arguments_ODY_PCIERCX_DEV_CAP2(a) (a), -1, -1, -1
845
846 /**
847 * Register (PCICONFIGRC) pcierc#_dev_ctl
848 *
849 * PCIe RC Device Control/Device Status Register
850 */
851 union ody_pciercx_dev_ctl {
852 uint32_t u;
853 struct ody_pciercx_dev_ctl_s {
854 uint32_t ce_en : 1;
855 uint32_t nfe_en : 1;
856 uint32_t fe_en : 1;
857 uint32_t ur_en : 1;
858 uint32_t ro_en : 1;
859 uint32_t mps : 3;
860 uint32_t etf_en : 1;
861 uint32_t pf_en : 1;
862 uint32_t ap_en : 1;
863 uint32_t ns_en : 1;
864 uint32_t mrrs : 3;
865 uint32_t reserved_15 : 1;
866 uint32_t ce_d : 1;
867 uint32_t nfe_d : 1;
868 uint32_t fe_d : 1;
869 uint32_t ur_d : 1;
870 uint32_t ap_d : 1;
871 uint32_t tp : 1;
872 uint32_t reserved_22_31 : 10;
873 } s;
874 /* struct ody_pciercx_dev_ctl_s cn; */
875 };
876 typedef union ody_pciercx_dev_ctl ody_pciercx_dev_ctl_t;
877
878 static inline uint64_t ODY_PCIERCX_DEV_CTL(uint64_t a) __attribute__ ((pure, always_inline));
ODY_PCIERCX_DEV_CTL(uint64_t a)879 static inline uint64_t ODY_PCIERCX_DEV_CTL(uint64_t a)
880 {
881 if (a <= 15)
882 return 0x78;
883 __ody_csr_fatal("PCIERCX_DEV_CTL", 1, a, 0, 0, 0, 0, 0);
884 }
885
886 #define typedef_ODY_PCIERCX_DEV_CTL(a) ody_pciercx_dev_ctl_t
887 #define bustype_ODY_PCIERCX_DEV_CTL(a) CSR_TYPE_PCICONFIGRC
888 #define basename_ODY_PCIERCX_DEV_CTL(a) "PCIERCX_DEV_CTL"
889 #define busnum_ODY_PCIERCX_DEV_CTL(a) (a)
890 #define arguments_ODY_PCIERCX_DEV_CTL(a) (a), -1, -1, -1
891
892 /**
893 * Register (PCICONFIGRC) pcierc#_dev_ctl2
894 *
895 * PCIe RC Device Control 2 Register/Device Status 2 Register
896 */
897 union ody_pciercx_dev_ctl2 {
898 uint32_t u;
899 struct ody_pciercx_dev_ctl2_s {
900 uint32_t ctv : 4;
901 uint32_t ctd : 1;
902 uint32_t ari : 1;
903 uint32_t atom_op : 1;
904 uint32_t atom_op_eb : 1;
905 uint32_t id0_rq : 1;
906 uint32_t id0_cp : 1;
907 uint32_t ltre : 1;
908 uint32_t reserved_11 : 1;
909 uint32_t tag10b_req_en : 1;
910 uint32_t obffe : 2;
911 uint32_t eetpb : 1;
912 uint32_t reserved_16_31 : 16;
913 } s;
914 /* struct ody_pciercx_dev_ctl2_s cn; */
915 };
916 typedef union ody_pciercx_dev_ctl2 ody_pciercx_dev_ctl2_t;
917
918 static inline uint64_t ODY_PCIERCX_DEV_CTL2(uint64_t a) __attribute__ ((pure, always_inline));
ODY_PCIERCX_DEV_CTL2(uint64_t a)919 static inline uint64_t ODY_PCIERCX_DEV_CTL2(uint64_t a)
920 {
921 if (a <= 15)
922 return 0x98;
923 __ody_csr_fatal("PCIERCX_DEV_CTL2", 1, a, 0, 0, 0, 0, 0);
924 }
925
926 #define typedef_ODY_PCIERCX_DEV_CTL2(a) ody_pciercx_dev_ctl2_t
927 #define bustype_ODY_PCIERCX_DEV_CTL2(a) CSR_TYPE_PCICONFIGRC
928 #define basename_ODY_PCIERCX_DEV_CTL2(a) "PCIERCX_DEV_CTL2"
929 #define busnum_ODY_PCIERCX_DEV_CTL2(a) (a)
930 #define arguments_ODY_PCIERCX_DEV_CTL2(a) (a), -1, -1, -1
931
932 /**
933 * Register (PCICONFIGRC) pcierc#_dl_feature_cap
934 *
935 * PCIe RC Data Link Feature Capabilities Register
936 */
937 union ody_pciercx_dl_feature_cap {
938 uint32_t u;
939 struct ody_pciercx_dl_feature_cap_s {
940 uint32_t lsfcs : 1;
941 uint32_t lfdlfs : 22;
942 uint32_t reserved_23_30 : 8;
943 uint32_t dl_fex_en : 1;
944 } s;
945 /* struct ody_pciercx_dl_feature_cap_s cn; */
946 };
947 typedef union ody_pciercx_dl_feature_cap ody_pciercx_dl_feature_cap_t;
948
949 static inline uint64_t ODY_PCIERCX_DL_FEATURE_CAP(uint64_t a) __attribute__ ((pure, always_inline));
ODY_PCIERCX_DL_FEATURE_CAP(uint64_t a)950 static inline uint64_t ODY_PCIERCX_DL_FEATURE_CAP(uint64_t a)
951 {
952 if (a <= 15)
953 return 0x3a8;
954 __ody_csr_fatal("PCIERCX_DL_FEATURE_CAP", 1, a, 0, 0, 0, 0, 0);
955 }
956
957 #define typedef_ODY_PCIERCX_DL_FEATURE_CAP(a) ody_pciercx_dl_feature_cap_t
958 #define bustype_ODY_PCIERCX_DL_FEATURE_CAP(a) CSR_TYPE_PCICONFIGRC
959 #define basename_ODY_PCIERCX_DL_FEATURE_CAP(a) "PCIERCX_DL_FEATURE_CAP"
960 #define busnum_ODY_PCIERCX_DL_FEATURE_CAP(a) (a)
961 #define arguments_ODY_PCIERCX_DL_FEATURE_CAP(a) (a), -1, -1, -1
962
963 /**
964 * Register (PCICONFIGRC) pcierc#_dl_feature_ext_hdr
965 *
966 * PCIe RC Data Link Feature Extended Capability Header Register
967 */
968 union ody_pciercx_dl_feature_ext_hdr {
969 uint32_t u;
970 struct ody_pciercx_dl_feature_ext_hdr_s {
971 uint32_t pcieec : 16;
972 uint32_t cv : 4;
973 uint32_t nco : 12;
974 } s;
975 /* struct ody_pciercx_dl_feature_ext_hdr_s cn; */
976 };
977 typedef union ody_pciercx_dl_feature_ext_hdr ody_pciercx_dl_feature_ext_hdr_t;
978
979 static inline uint64_t ODY_PCIERCX_DL_FEATURE_EXT_HDR(uint64_t a) __attribute__ ((pure, always_inline));
ODY_PCIERCX_DL_FEATURE_EXT_HDR(uint64_t a)980 static inline uint64_t ODY_PCIERCX_DL_FEATURE_EXT_HDR(uint64_t a)
981 {
982 if (a <= 15)
983 return 0x3a4;
984 __ody_csr_fatal("PCIERCX_DL_FEATURE_EXT_HDR", 1, a, 0, 0, 0, 0, 0);
985 }
986
987 #define typedef_ODY_PCIERCX_DL_FEATURE_EXT_HDR(a) ody_pciercx_dl_feature_ext_hdr_t
988 #define bustype_ODY_PCIERCX_DL_FEATURE_EXT_HDR(a) CSR_TYPE_PCICONFIGRC
989 #define basename_ODY_PCIERCX_DL_FEATURE_EXT_HDR(a) "PCIERCX_DL_FEATURE_EXT_HDR"
990 #define busnum_ODY_PCIERCX_DL_FEATURE_EXT_HDR(a) (a)
991 #define arguments_ODY_PCIERCX_DL_FEATURE_EXT_HDR(a) (a), -1, -1, -1
992
993 /**
994 * Register (PCICONFIGRC) pcierc#_dl_feature_status
995 *
996 * PCIe RC Data Link Feature Status Register
997 */
998 union ody_pciercx_dl_feature_status {
999 uint32_t u;
1000 struct ody_pciercx_dl_feature_status_s {
1001 uint32_t rdlfs : 23;
1002 uint32_t reserved_23_30 : 8;
1003 uint32_t dlfsv : 1;
1004 } s;
1005 /* struct ody_pciercx_dl_feature_status_s cn; */
1006 };
1007 typedef union ody_pciercx_dl_feature_status ody_pciercx_dl_feature_status_t;
1008
1009 static inline uint64_t ODY_PCIERCX_DL_FEATURE_STATUS(uint64_t a) __attribute__ ((pure, always_inline));
ODY_PCIERCX_DL_FEATURE_STATUS(uint64_t a)1010 static inline uint64_t ODY_PCIERCX_DL_FEATURE_STATUS(uint64_t a)
1011 {
1012 if (a <= 15)
1013 return 0x3ac;
1014 __ody_csr_fatal("PCIERCX_DL_FEATURE_STATUS", 1, a, 0, 0, 0, 0, 0);
1015 }
1016
1017 #define typedef_ODY_PCIERCX_DL_FEATURE_STATUS(a) ody_pciercx_dl_feature_status_t
1018 #define bustype_ODY_PCIERCX_DL_FEATURE_STATUS(a) CSR_TYPE_PCICONFIGRC
1019 #define basename_ODY_PCIERCX_DL_FEATURE_STATUS(a) "PCIERCX_DL_FEATURE_STATUS"
1020 #define busnum_ODY_PCIERCX_DL_FEATURE_STATUS(a) (a)
1021 #define arguments_ODY_PCIERCX_DL_FEATURE_STATUS(a) (a), -1, -1, -1
1022
1023 /**
1024 * Register (PCICONFIGRC) pcierc#_e_cap_list
1025 *
1026 * PCIe RC PCIe Capabilities/PCIe Capabilities List Register
1027 */
1028 union ody_pciercx_e_cap_list {
1029 uint32_t u;
1030 struct ody_pciercx_e_cap_list_s {
1031 uint32_t pcieid : 8;
1032 uint32_t ncp : 8;
1033 uint32_t pciecv : 4;
1034 uint32_t dpt : 4;
1035 uint32_t si : 1;
1036 uint32_t imn : 5;
1037 uint32_t reserved_30_31 : 2;
1038 } s;
1039 /* struct ody_pciercx_e_cap_list_s cn; */
1040 };
1041 typedef union ody_pciercx_e_cap_list ody_pciercx_e_cap_list_t;
1042
1043 static inline uint64_t ODY_PCIERCX_E_CAP_LIST(uint64_t a) __attribute__ ((pure, always_inline));
ODY_PCIERCX_E_CAP_LIST(uint64_t a)1044 static inline uint64_t ODY_PCIERCX_E_CAP_LIST(uint64_t a)
1045 {
1046 if (a <= 15)
1047 return 0x70;
1048 __ody_csr_fatal("PCIERCX_E_CAP_LIST", 1, a, 0, 0, 0, 0, 0);
1049 }
1050
1051 #define typedef_ODY_PCIERCX_E_CAP_LIST(a) ody_pciercx_e_cap_list_t
1052 #define bustype_ODY_PCIERCX_E_CAP_LIST(a) CSR_TYPE_PCICONFIGRC
1053 #define basename_ODY_PCIERCX_E_CAP_LIST(a) "PCIERCX_E_CAP_LIST"
1054 #define busnum_ODY_PCIERCX_E_CAP_LIST(a) (a)
1055 #define arguments_ODY_PCIERCX_E_CAP_LIST(a) (a), -1, -1, -1
1056
1057 /**
1058 * Register (PCICONFIGRC) pcierc#_ea_cap_hdr
1059 *
1060 * PCIe RC Enhanced Allocation Capability ID Register
1061 */
1062 union ody_pciercx_ea_cap_hdr {
1063 uint32_t u;
1064 struct ody_pciercx_ea_cap_hdr_s {
1065 uint32_t eacid : 8;
1066 uint32_t ncp : 8;
1067 uint32_t num_entries : 6;
1068 uint32_t ea_rsvd : 10;
1069 } s;
1070 /* struct ody_pciercx_ea_cap_hdr_s cn; */
1071 };
1072 typedef union ody_pciercx_ea_cap_hdr ody_pciercx_ea_cap_hdr_t;
1073
1074 static inline uint64_t ODY_PCIERCX_EA_CAP_HDR(uint64_t a) __attribute__ ((pure, always_inline));
ODY_PCIERCX_EA_CAP_HDR(uint64_t a)1075 static inline uint64_t ODY_PCIERCX_EA_CAP_HDR(uint64_t a)
1076 {
1077 if (a <= 15)
1078 return 0x50;
1079 __ody_csr_fatal("PCIERCX_EA_CAP_HDR", 1, a, 0, 0, 0, 0, 0);
1080 }
1081
1082 #define typedef_ODY_PCIERCX_EA_CAP_HDR(a) ody_pciercx_ea_cap_hdr_t
1083 #define bustype_ODY_PCIERCX_EA_CAP_HDR(a) CSR_TYPE_PCICONFIGRC
1084 #define basename_ODY_PCIERCX_EA_CAP_HDR(a) "PCIERCX_EA_CAP_HDR"
1085 #define busnum_ODY_PCIERCX_EA_CAP_HDR(a) (a)
1086 #define arguments_ODY_PCIERCX_EA_CAP_HDR(a) (a), -1, -1, -1
1087
1088 /**
1089 * Register (PCICONFIGRC) pcierc#_ea_entry0
1090 *
1091 * PCIe RC Enhanced Allocation Capability Second DW Register
1092 */
1093 union ody_pciercx_ea_entry0 {
1094 uint32_t u;
1095 struct ody_pciercx_ea_entry0_s {
1096 uint32_t fixed_secnum : 8;
1097 uint32_t fixed_subnum : 8;
1098 uint32_t ea_rsvd : 16;
1099 } s;
1100 /* struct ody_pciercx_ea_entry0_s cn; */
1101 };
1102 typedef union ody_pciercx_ea_entry0 ody_pciercx_ea_entry0_t;
1103
1104 static inline uint64_t ODY_PCIERCX_EA_ENTRY0(uint64_t a) __attribute__ ((pure, always_inline));
ODY_PCIERCX_EA_ENTRY0(uint64_t a)1105 static inline uint64_t ODY_PCIERCX_EA_ENTRY0(uint64_t a)
1106 {
1107 if (a <= 15)
1108 return 0x54;
1109 __ody_csr_fatal("PCIERCX_EA_ENTRY0", 1, a, 0, 0, 0, 0, 0);
1110 }
1111
1112 #define typedef_ODY_PCIERCX_EA_ENTRY0(a) ody_pciercx_ea_entry0_t
1113 #define bustype_ODY_PCIERCX_EA_ENTRY0(a) CSR_TYPE_PCICONFIGRC
1114 #define basename_ODY_PCIERCX_EA_ENTRY0(a) "PCIERCX_EA_ENTRY0"
1115 #define busnum_ODY_PCIERCX_EA_ENTRY0(a) (a)
1116 #define arguments_ODY_PCIERCX_EA_ENTRY0(a) (a), -1, -1, -1
1117
1118 /**
1119 * Register (PCICONFIGRC) pcierc#_ea_entry1
1120 *
1121 * PCIe RC Enhanced Allocation Entry 0 First DW Register
1122 */
1123 union ody_pciercx_ea_entry1 {
1124 uint32_t u;
1125 struct ody_pciercx_ea_entry1_s {
1126 uint32_t esize : 3;
1127 uint32_t ea_rsvd_0 : 1;
1128 uint32_t bei : 4;
1129 uint32_t pprop : 8;
1130 uint32_t sprop : 8;
1131 uint32_t ea_rsvd_1 : 6;
1132 uint32_t wr : 1;
1133 uint32_t ena : 1;
1134 } s;
1135 /* struct ody_pciercx_ea_entry1_s cn; */
1136 };
1137 typedef union ody_pciercx_ea_entry1 ody_pciercx_ea_entry1_t;
1138
1139 static inline uint64_t ODY_PCIERCX_EA_ENTRY1(uint64_t a) __attribute__ ((pure, always_inline));
ODY_PCIERCX_EA_ENTRY1(uint64_t a)1140 static inline uint64_t ODY_PCIERCX_EA_ENTRY1(uint64_t a)
1141 {
1142 if (a <= 15)
1143 return 0x58;
1144 __ody_csr_fatal("PCIERCX_EA_ENTRY1", 1, a, 0, 0, 0, 0, 0);
1145 }
1146
1147 #define typedef_ODY_PCIERCX_EA_ENTRY1(a) ody_pciercx_ea_entry1_t
1148 #define bustype_ODY_PCIERCX_EA_ENTRY1(a) CSR_TYPE_PCICONFIGRC
1149 #define basename_ODY_PCIERCX_EA_ENTRY1(a) "PCIERCX_EA_ENTRY1"
1150 #define busnum_ODY_PCIERCX_EA_ENTRY1(a) (a)
1151 #define arguments_ODY_PCIERCX_EA_ENTRY1(a) (a), -1, -1, -1
1152
1153 /**
1154 * Register (PCICONFIGRC) pcierc#_ea_entry2
1155 *
1156 * PCIe RC Enhanced Allocation Entry 0 Lower Base Register
1157 */
1158 union ody_pciercx_ea_entry2 {
1159 uint32_t u;
1160 struct ody_pciercx_ea_entry2_s {
1161 uint32_t ea_rsvd : 1;
1162 uint32_t size : 1;
1163 uint32_t lbase : 30;
1164 } s;
1165 /* struct ody_pciercx_ea_entry2_s cn; */
1166 };
1167 typedef union ody_pciercx_ea_entry2 ody_pciercx_ea_entry2_t;
1168
1169 static inline uint64_t ODY_PCIERCX_EA_ENTRY2(uint64_t a) __attribute__ ((pure, always_inline));
ODY_PCIERCX_EA_ENTRY2(uint64_t a)1170 static inline uint64_t ODY_PCIERCX_EA_ENTRY2(uint64_t a)
1171 {
1172 if (a <= 15)
1173 return 0x5c;
1174 __ody_csr_fatal("PCIERCX_EA_ENTRY2", 1, a, 0, 0, 0, 0, 0);
1175 }
1176
1177 #define typedef_ODY_PCIERCX_EA_ENTRY2(a) ody_pciercx_ea_entry2_t
1178 #define bustype_ODY_PCIERCX_EA_ENTRY2(a) CSR_TYPE_PCICONFIGRC
1179 #define basename_ODY_PCIERCX_EA_ENTRY2(a) "PCIERCX_EA_ENTRY2"
1180 #define busnum_ODY_PCIERCX_EA_ENTRY2(a) (a)
1181 #define arguments_ODY_PCIERCX_EA_ENTRY2(a) (a), -1, -1, -1
1182
1183 /**
1184 * Register (PCICONFIGRC) pcierc#_ea_entry3
1185 *
1186 * PCIe RC Enhanced Allocation Entry 0 Max Offset Register
1187 */
1188 union ody_pciercx_ea_entry3 {
1189 uint32_t u;
1190 struct ody_pciercx_ea_entry3_s {
1191 uint32_t ea_rsvd : 1;
1192 uint32_t size : 1;
1193 uint32_t moffs : 30;
1194 } s;
1195 /* struct ody_pciercx_ea_entry3_s cn; */
1196 };
1197 typedef union ody_pciercx_ea_entry3 ody_pciercx_ea_entry3_t;
1198
1199 static inline uint64_t ODY_PCIERCX_EA_ENTRY3(uint64_t a) __attribute__ ((pure, always_inline));
ODY_PCIERCX_EA_ENTRY3(uint64_t a)1200 static inline uint64_t ODY_PCIERCX_EA_ENTRY3(uint64_t a)
1201 {
1202 if (a <= 15)
1203 return 0x60;
1204 __ody_csr_fatal("PCIERCX_EA_ENTRY3", 1, a, 0, 0, 0, 0, 0);
1205 }
1206
1207 #define typedef_ODY_PCIERCX_EA_ENTRY3(a) ody_pciercx_ea_entry3_t
1208 #define bustype_ODY_PCIERCX_EA_ENTRY3(a) CSR_TYPE_PCICONFIGRC
1209 #define basename_ODY_PCIERCX_EA_ENTRY3(a) "PCIERCX_EA_ENTRY3"
1210 #define busnum_ODY_PCIERCX_EA_ENTRY3(a) (a)
1211 #define arguments_ODY_PCIERCX_EA_ENTRY3(a) (a), -1, -1, -1
1212
1213 /**
1214 * Register (PCICONFIGRC) pcierc#_ea_entry4
1215 *
1216 * PCIe RC Enhanced Allocation Entry 0 Upper Base Register
1217 */
1218 union ody_pciercx_ea_entry4 {
1219 uint32_t u;
1220 struct ody_pciercx_ea_entry4_s {
1221 uint32_t ubase : 32;
1222 } s;
1223 /* struct ody_pciercx_ea_entry4_s cn; */
1224 };
1225 typedef union ody_pciercx_ea_entry4 ody_pciercx_ea_entry4_t;
1226
1227 static inline uint64_t ODY_PCIERCX_EA_ENTRY4(uint64_t a) __attribute__ ((pure, always_inline));
ODY_PCIERCX_EA_ENTRY4(uint64_t a)1228 static inline uint64_t ODY_PCIERCX_EA_ENTRY4(uint64_t a)
1229 {
1230 if (a <= 15)
1231 return 0x64;
1232 __ody_csr_fatal("PCIERCX_EA_ENTRY4", 1, a, 0, 0, 0, 0, 0);
1233 }
1234
1235 #define typedef_ODY_PCIERCX_EA_ENTRY4(a) ody_pciercx_ea_entry4_t
1236 #define bustype_ODY_PCIERCX_EA_ENTRY4(a) CSR_TYPE_PCICONFIGRC
1237 #define basename_ODY_PCIERCX_EA_ENTRY4(a) "PCIERCX_EA_ENTRY4"
1238 #define busnum_ODY_PCIERCX_EA_ENTRY4(a) (a)
1239 #define arguments_ODY_PCIERCX_EA_ENTRY4(a) (a), -1, -1, -1
1240
1241 /**
1242 * Register (PCICONFIGRC) pcierc#_ebar
1243 *
1244 * PCIe RC Expansion ROM Base Address Register
1245 */
1246 union ody_pciercx_ebar {
1247 uint32_t u;
1248 struct ody_pciercx_ebar_s {
1249 uint32_t unused : 32;
1250 } s;
1251 /* struct ody_pciercx_ebar_s cn; */
1252 };
1253 typedef union ody_pciercx_ebar ody_pciercx_ebar_t;
1254
1255 static inline uint64_t ODY_PCIERCX_EBAR(uint64_t a) __attribute__ ((pure, always_inline));
ODY_PCIERCX_EBAR(uint64_t a)1256 static inline uint64_t ODY_PCIERCX_EBAR(uint64_t a)
1257 {
1258 if (a <= 15)
1259 return 0x38;
1260 __ody_csr_fatal("PCIERCX_EBAR", 1, a, 0, 0, 0, 0, 0);
1261 }
1262
1263 #define typedef_ODY_PCIERCX_EBAR(a) ody_pciercx_ebar_t
1264 #define bustype_ODY_PCIERCX_EBAR(a) CSR_TYPE_PCICONFIGRC
1265 #define basename_ODY_PCIERCX_EBAR(a) "PCIERCX_EBAR"
1266 #define busnum_ODY_PCIERCX_EBAR(a) (a)
1267 #define arguments_ODY_PCIERCX_EBAR(a) (a), -1, -1, -1
1268
1269 /**
1270 * Register (PCICONFIGRC) pcierc#_eq_ctl01
1271 *
1272 * PCIe RC Equalization Control Lane 0/1 Register
1273 * The Equalization Control register consists of control fields required for per-Lane
1274 * 16.0 GT/s equalization.
1275 *
1276 * Equalization as an RC:
1277 * \<pre\>
1278 * - On speed change from GEN1-\>GEN3, advertise the transmitter preset hint per lane
1279 * to the EP device in the TS2s exchanged. This value comes from the per lane
1280 * upstream port transmitter preset (L*UTP).
1281 * - Upon exit from Recovery Speed, the RC will enter EQ PHASE1 and the RC's
1282 * transmitter will use the per lane downstream port transmitter preset field (L*DTP).
1283 * - While in EQ PHASE 1, the EP & RC device exchange NO presets. They do advertise
1284 * their LF & FS which are needed for the fine tuning stages to follow.
1285 * - For the RC, while in EQ PHASE 2, the EP device makes tuning requests of the RC.
1286 * The RC adjusts its transmitter settings as directed by the EP. The requests are
1287 * communicated via TS1s.
1288 * - Once the EP is satisfied with the tuning, equalization moves to PHASE 3 where
1289 * the RC tunes the EP's remote transmitter.
1290 * Again, the settings are communicated via TS1s but the feedback is provided by
1291 * the RC phy's FOM or direction change indications.
1292 * \</pre\>
1293 */
1294 union ody_pciercx_eq_ctl01 {
1295 uint32_t u;
1296 struct ody_pciercx_eq_ctl01_s {
1297 uint32_t l0dtp : 4;
1298 uint32_t l0drph : 3;
1299 uint32_t reserved_7 : 1;
1300 uint32_t l0utp : 4;
1301 uint32_t l0urph : 3;
1302 uint32_t reserved_15 : 1;
1303 uint32_t l1dtp : 4;
1304 uint32_t l1drph : 3;
1305 uint32_t reserved_23 : 1;
1306 uint32_t l1utp : 4;
1307 uint32_t l1urph : 3;
1308 uint32_t reserved_31 : 1;
1309 } s;
1310 /* struct ody_pciercx_eq_ctl01_s cn; */
1311 };
1312 typedef union ody_pciercx_eq_ctl01 ody_pciercx_eq_ctl01_t;
1313
1314 static inline uint64_t ODY_PCIERCX_EQ_CTL01(uint64_t a) __attribute__ ((pure, always_inline));
ODY_PCIERCX_EQ_CTL01(uint64_t a)1315 static inline uint64_t ODY_PCIERCX_EQ_CTL01(uint64_t a)
1316 {
1317 if (a <= 15)
1318 return 0x174;
1319 __ody_csr_fatal("PCIERCX_EQ_CTL01", 1, a, 0, 0, 0, 0, 0);
1320 }
1321
1322 #define typedef_ODY_PCIERCX_EQ_CTL01(a) ody_pciercx_eq_ctl01_t
1323 #define bustype_ODY_PCIERCX_EQ_CTL01(a) CSR_TYPE_PCICONFIGRC
1324 #define basename_ODY_PCIERCX_EQ_CTL01(a) "PCIERCX_EQ_CTL01"
1325 #define busnum_ODY_PCIERCX_EQ_CTL01(a) (a)
1326 #define arguments_ODY_PCIERCX_EQ_CTL01(a) (a), -1, -1, -1
1327
1328 /**
1329 * Register (PCICONFIGRC) pcierc#_eq_ctl1011
1330 *
1331 * PCIe RC Equalization Control Lane 10/11 Register
1332 * Not supported in QPEM/HPEM.
1333 *
1334 * The Equalization Control register consists of control fields required for per-Lane
1335 * 16.0 GT/s equalization.
1336 *
1337 * Equalization as an RC:
1338 * \<pre\>
1339 * - On speed change from GEN1-\>GEN3, advertise the transmitter preset hint per lane
1340 * to the EP device in the TS2s exchanged. This value comes from the per lane
1341 * upstream port transmitter preset (L*UTP).
1342 * - Upon exit from Recovery Speed, the RC will enter EQ PHASE1 and the RC's
1343 * transmitter will use the per lane downstream port transmitter preset field (L*DTP).
1344 * - While in EQ PHASE 1, the EP & RC device exchange NO presets. They do advertise
1345 * their LF & FS which are needed for the fine tuning stages to follow.
1346 * - For the RC, while in EQ PHASE 2, the EP device makes tuning requests of the RC.
1347 * The RC adjusts its transmitter settings as directed by the EP. The requests are
1348 * communicated via TS1s.
1349 * - Once the EP is satisfied with the tuning, equalization moves to PHASE 3 where
1350 * the RC tunes the EP's remote transmitter.
1351 * Again, the settings are communicated via TS1s but the feedback is provided by
1352 * the RC phy's FOM or direction change indications.
1353 * \</pre\>
1354 */
1355 union ody_pciercx_eq_ctl1011 {
1356 uint32_t u;
1357 struct ody_pciercx_eq_ctl1011_s {
1358 uint32_t l10dtp : 4;
1359 uint32_t l10drph : 3;
1360 uint32_t reserved_7 : 1;
1361 uint32_t l10utp : 4;
1362 uint32_t l10urph : 3;
1363 uint32_t reserved_15 : 1;
1364 uint32_t l11dtp : 4;
1365 uint32_t l11drph : 3;
1366 uint32_t reserved_23 : 1;
1367 uint32_t l11utp : 4;
1368 uint32_t l11urph : 3;
1369 uint32_t reserved_31 : 1;
1370 } s;
1371 /* struct ody_pciercx_eq_ctl1011_s cn; */
1372 };
1373 typedef union ody_pciercx_eq_ctl1011 ody_pciercx_eq_ctl1011_t;
1374
1375 static inline uint64_t ODY_PCIERCX_EQ_CTL1011(uint64_t a) __attribute__ ((pure, always_inline));
ODY_PCIERCX_EQ_CTL1011(uint64_t a)1376 static inline uint64_t ODY_PCIERCX_EQ_CTL1011(uint64_t a)
1377 {
1378 if (a <= 15)
1379 return 0x188;
1380 __ody_csr_fatal("PCIERCX_EQ_CTL1011", 1, a, 0, 0, 0, 0, 0);
1381 }
1382
1383 #define typedef_ODY_PCIERCX_EQ_CTL1011(a) ody_pciercx_eq_ctl1011_t
1384 #define bustype_ODY_PCIERCX_EQ_CTL1011(a) CSR_TYPE_PCICONFIGRC
1385 #define basename_ODY_PCIERCX_EQ_CTL1011(a) "PCIERCX_EQ_CTL1011"
1386 #define busnum_ODY_PCIERCX_EQ_CTL1011(a) (a)
1387 #define arguments_ODY_PCIERCX_EQ_CTL1011(a) (a), -1, -1, -1
1388
1389 /**
1390 * Register (PCICONFIGRC) pcierc#_eq_ctl1213
1391 *
1392 * PCIe RC Equalization Control Lane 12/13 Register
1393 * Not supported in QPEM/HPEM.
1394 *
1395 * The Equalization Control register consists of control fields required for per-Lane
1396 * 16.0 GT/s equalization.
1397 *
1398 * Equalization as an RC:
1399 * \<pre\>
1400 * - On speed change from GEN1-\>GEN3, advertise the transmitter preset hint per lane
1401 * to the EP device in the TS2s exchanged. This value comes from the per lane
1402 * upstream port transmitter preset (L*UTP).
1403 * - Upon exit from Recovery Speed, the RC will enter EQ PHASE1 and the RC's
1404 * transmitter will use the per lane downstream port transmitter preset field (L*DTP).
1405 * - While in EQ PHASE 1, the EP & RC device exchange NO presets. They do advertise
1406 * their LF & FS which are needed for the fine tuning stages to follow.
1407 * - For the RC, while in EQ PHASE 2, the EP device makes tuning requests of the RC.
1408 * The RC adjusts its transmitter settings as directed by the EP. The requests are
1409 * communicated via TS1s.
1410 * - Once the EP is satisfied with the tuning, equalization moves to PHASE 3 where
1411 * the RC tunes the EP's remote transmitter.
1412 * Again, the settings are communicated via TS1s but the feedback is provided by
1413 * the RC phy's FOM or direction change indications.
1414 * \</pre\>
1415 */
1416 union ody_pciercx_eq_ctl1213 {
1417 uint32_t u;
1418 struct ody_pciercx_eq_ctl1213_s {
1419 uint32_t l12dtp : 4;
1420 uint32_t l12drph : 3;
1421 uint32_t reserved_7 : 1;
1422 uint32_t l12utp : 4;
1423 uint32_t l12urph : 3;
1424 uint32_t reserved_15 : 1;
1425 uint32_t l13dtp : 4;
1426 uint32_t l13drph : 3;
1427 uint32_t reserved_23 : 1;
1428 uint32_t l13utp : 4;
1429 uint32_t l13urph : 3;
1430 uint32_t reserved_31 : 1;
1431 } s;
1432 /* struct ody_pciercx_eq_ctl1213_s cn; */
1433 };
1434 typedef union ody_pciercx_eq_ctl1213 ody_pciercx_eq_ctl1213_t;
1435
1436 static inline uint64_t ODY_PCIERCX_EQ_CTL1213(uint64_t a) __attribute__ ((pure, always_inline));
ODY_PCIERCX_EQ_CTL1213(uint64_t a)1437 static inline uint64_t ODY_PCIERCX_EQ_CTL1213(uint64_t a)
1438 {
1439 if (a <= 15)
1440 return 0x18c;
1441 __ody_csr_fatal("PCIERCX_EQ_CTL1213", 1, a, 0, 0, 0, 0, 0);
1442 }
1443
1444 #define typedef_ODY_PCIERCX_EQ_CTL1213(a) ody_pciercx_eq_ctl1213_t
1445 #define bustype_ODY_PCIERCX_EQ_CTL1213(a) CSR_TYPE_PCICONFIGRC
1446 #define basename_ODY_PCIERCX_EQ_CTL1213(a) "PCIERCX_EQ_CTL1213"
1447 #define busnum_ODY_PCIERCX_EQ_CTL1213(a) (a)
1448 #define arguments_ODY_PCIERCX_EQ_CTL1213(a) (a), -1, -1, -1
1449
1450 /**
1451 * Register (PCICONFIGRC) pcierc#_eq_ctl1415
1452 *
1453 * PCIe RC Equalization Control Lane 14/15 Register
1454 * Not supported in QPEM/HPEM.
1455 *
1456 * The Equalization Control register consists of control fields required for per-Lane
1457 * 16.0 GT/s equalization.
1458 *
1459 * Equalization as an RC:
1460 * \<pre\>
1461 * - On speed change from GEN1-\>GEN3, advertise the transmitter preset hint per lane
1462 * to the EP device in the TS2s exchanged. This value comes from the per lane
1463 * upstream port transmitter preset (L*UTP).
1464 * - Upon exit from Recovery Speed, the RC will enter EQ PHASE1 and the RC's
1465 * transmitter will use the per lane downstream port transmitter preset field (L*DTP).
1466 * - While in EQ PHASE 1, the EP & RC device exchange NO presets. They do advertise
1467 * their LF & FS which are needed for the fine tuning stages to follow.
1468 * - For the RC, while in EQ PHASE 2, the EP device makes tuning requests of the RC.
1469 * The RC adjusts its transmitter settings as directed by the EP. The requests are
1470 * communicated via TS1s.
1471 * - Once the EP is satisfied with the tuning, equalization moves to PHASE 3 where
1472 * the RC tunes the EP's remote transmitter.
1473 * Again, the settings are communicated via TS1s but the feedback is provided by
1474 * the RC phy's FOM or direction change indications.
1475 * \</pre\>
1476 */
1477 union ody_pciercx_eq_ctl1415 {
1478 uint32_t u;
1479 struct ody_pciercx_eq_ctl1415_s {
1480 uint32_t l14dtp : 4;
1481 uint32_t l14drph : 3;
1482 uint32_t reserved_7 : 1;
1483 uint32_t l14utp : 4;
1484 uint32_t l14urph : 3;
1485 uint32_t reserved_15 : 1;
1486 uint32_t l15dtp : 4;
1487 uint32_t l15drph : 3;
1488 uint32_t reserved_23 : 1;
1489 uint32_t l15utp : 4;
1490 uint32_t l15urph : 3;
1491 uint32_t reserved_31 : 1;
1492 } s;
1493 /* struct ody_pciercx_eq_ctl1415_s cn; */
1494 };
1495 typedef union ody_pciercx_eq_ctl1415 ody_pciercx_eq_ctl1415_t;
1496
1497 static inline uint64_t ODY_PCIERCX_EQ_CTL1415(uint64_t a) __attribute__ ((pure, always_inline));
ODY_PCIERCX_EQ_CTL1415(uint64_t a)1498 static inline uint64_t ODY_PCIERCX_EQ_CTL1415(uint64_t a)
1499 {
1500 if (a <= 15)
1501 return 0x190;
1502 __ody_csr_fatal("PCIERCX_EQ_CTL1415", 1, a, 0, 0, 0, 0, 0);
1503 }
1504
1505 #define typedef_ODY_PCIERCX_EQ_CTL1415(a) ody_pciercx_eq_ctl1415_t
1506 #define bustype_ODY_PCIERCX_EQ_CTL1415(a) CSR_TYPE_PCICONFIGRC
1507 #define basename_ODY_PCIERCX_EQ_CTL1415(a) "PCIERCX_EQ_CTL1415"
1508 #define busnum_ODY_PCIERCX_EQ_CTL1415(a) (a)
1509 #define arguments_ODY_PCIERCX_EQ_CTL1415(a) (a), -1, -1, -1
1510
1511 /**
1512 * Register (PCICONFIGRC) pcierc#_eq_ctl23
1513 *
1514 * PCIe RC Equalization Control Lane 2/3 Register
1515 * The Equalization Control register consists of control fields required for per-Lane
1516 * 16.0 GT/s equalization.
1517 *
1518 * Equalization as an RC:
1519 * \<pre\>
1520 * - On speed change from GEN1-\>GEN3, advertise the transmitter preset hint per lane
1521 * to the EP device in the TS2s exchanged. This value comes from the per lane
1522 * upstream port transmitter preset (L*UTP).
1523 * - Upon exit from Recovery Speed, the RC will enter EQ PHASE1 and the RC's
1524 * transmitter will use the per lane downstream port transmitter preset field (L*DTP).
1525 * - While in EQ PHASE 1, the EP & RC device exchange NO presets. They do advertise
1526 * their LF & FS which are needed for the fine tuning stages to follow.
1527 * - For the RC, while in EQ PHASE 2, the EP device makes tuning requests of the RC.
1528 * The RC adjusts its transmitter settings as directed by the EP. The requests are
1529 * communicated via TS1s.
1530 * - Once the EP is satisfied with the tuning, equalization moves to PHASE 3 where
1531 * the RC tunes the EP's remote transmitter.
1532 * Again, the settings are communicated via TS1s but the feedback is provided by
1533 * the RC phy's FOM or direction change indications.
1534 * \</pre\>
1535 */
1536 union ody_pciercx_eq_ctl23 {
1537 uint32_t u;
1538 struct ody_pciercx_eq_ctl23_s {
1539 uint32_t l2dtp : 4;
1540 uint32_t l2drph : 3;
1541 uint32_t reserved_7 : 1;
1542 uint32_t l2utp : 4;
1543 uint32_t l2urph : 3;
1544 uint32_t reserved_15 : 1;
1545 uint32_t l3dtp : 4;
1546 uint32_t l3drph : 3;
1547 uint32_t reserved_23 : 1;
1548 uint32_t l3utp : 4;
1549 uint32_t l3urph : 3;
1550 uint32_t reserved_31 : 1;
1551 } s;
1552 /* struct ody_pciercx_eq_ctl23_s cn; */
1553 };
1554 typedef union ody_pciercx_eq_ctl23 ody_pciercx_eq_ctl23_t;
1555
1556 static inline uint64_t ODY_PCIERCX_EQ_CTL23(uint64_t a) __attribute__ ((pure, always_inline));
ODY_PCIERCX_EQ_CTL23(uint64_t a)1557 static inline uint64_t ODY_PCIERCX_EQ_CTL23(uint64_t a)
1558 {
1559 if (a <= 15)
1560 return 0x178;
1561 __ody_csr_fatal("PCIERCX_EQ_CTL23", 1, a, 0, 0, 0, 0, 0);
1562 }
1563
1564 #define typedef_ODY_PCIERCX_EQ_CTL23(a) ody_pciercx_eq_ctl23_t
1565 #define bustype_ODY_PCIERCX_EQ_CTL23(a) CSR_TYPE_PCICONFIGRC
1566 #define basename_ODY_PCIERCX_EQ_CTL23(a) "PCIERCX_EQ_CTL23"
1567 #define busnum_ODY_PCIERCX_EQ_CTL23(a) (a)
1568 #define arguments_ODY_PCIERCX_EQ_CTL23(a) (a), -1, -1, -1
1569
1570 /**
1571 * Register (PCICONFIGRC) pcierc#_eq_ctl45
1572 *
1573 * PCIe RC Equalization Control Lane 2/3 Register
1574 * Not supported in QPEM.
1575 *
1576 * The Equalization Control register consists of control fields required for per-Lane
1577 * 16.0 GT/s equalization.
1578 *
1579 * Equalization as an RC:
1580 * \<pre\>
1581 * - On speed change from GEN1-\>GEN3, advertise the transmitter preset hint per lane
1582 * to the EP device in the TS2s exchanged. This value comes from the per lane
1583 * upstream port transmitter preset (L*UTP).
1584 * - Upon exit from Recovery Speed, the RC will enter EQ PHASE1 and the RC's
1585 * transmitter will use the per lane downstream port transmitter preset field (L*DTP).
1586 * - While in EQ PHASE 1, the EP & RC device exchange NO presets. They do advertise
1587 * their LF & FS which are needed for the fine tuning stages to follow.
1588 * - For the RC, while in EQ PHASE 2, the EP device makes tuning requests of the RC.
1589 * The RC adjusts its transmitter settings as directed by the EP. The requests are
1590 * communicated via TS1s.
1591 * - Once the EP is satisfied with the tuning, equalization moves to PHASE 3 where
1592 * the RC tunes the EP's remote transmitter.
1593 * Again, the settings are communicated via TS1s but the feedback is provided by
1594 * the RC phy's FOM or direction change indications.
1595 * \</pre\>
1596 */
1597 union ody_pciercx_eq_ctl45 {
1598 uint32_t u;
1599 struct ody_pciercx_eq_ctl45_s {
1600 uint32_t l4dtp : 4;
1601 uint32_t l4drph : 3;
1602 uint32_t reserved_7 : 1;
1603 uint32_t l4utp : 4;
1604 uint32_t l4urph : 3;
1605 uint32_t reserved_15 : 1;
1606 uint32_t l5dtp : 4;
1607 uint32_t l5drph : 3;
1608 uint32_t reserved_23 : 1;
1609 uint32_t l5utp : 4;
1610 uint32_t l5urph : 3;
1611 uint32_t reserved_31 : 1;
1612 } s;
1613 /* struct ody_pciercx_eq_ctl45_s cn; */
1614 };
1615 typedef union ody_pciercx_eq_ctl45 ody_pciercx_eq_ctl45_t;
1616
1617 static inline uint64_t ODY_PCIERCX_EQ_CTL45(uint64_t a) __attribute__ ((pure, always_inline));
ODY_PCIERCX_EQ_CTL45(uint64_t a)1618 static inline uint64_t ODY_PCIERCX_EQ_CTL45(uint64_t a)
1619 {
1620 if (a <= 15)
1621 return 0x17c;
1622 __ody_csr_fatal("PCIERCX_EQ_CTL45", 1, a, 0, 0, 0, 0, 0);
1623 }
1624
1625 #define typedef_ODY_PCIERCX_EQ_CTL45(a) ody_pciercx_eq_ctl45_t
1626 #define bustype_ODY_PCIERCX_EQ_CTL45(a) CSR_TYPE_PCICONFIGRC
1627 #define basename_ODY_PCIERCX_EQ_CTL45(a) "PCIERCX_EQ_CTL45"
1628 #define busnum_ODY_PCIERCX_EQ_CTL45(a) (a)
1629 #define arguments_ODY_PCIERCX_EQ_CTL45(a) (a), -1, -1, -1
1630
1631 /**
1632 * Register (PCICONFIGRC) pcierc#_eq_ctl67
1633 *
1634 * PCIe RC Equalization Control Lane 6/7 Register
1635 * Not supported in QPEM.
1636 *
1637 * The Equalization Control register consists of control fields required for per-Lane
1638 * 16.0 GT/s equalization.
1639 *
1640 * Equalization as an RC:
1641 * \<pre\>
1642 * - On speed change from GEN1-\>GEN3, advertise the transmitter preset hint per lane
1643 * to the EP device in the TS2s exchanged. This value comes from the per lane
1644 * upstream port transmitter preset (L*UTP).
1645 * - Upon exit from Recovery Speed, the RC will enter EQ PHASE1 and the RC's
1646 * transmitter will use the per lane downstream port transmitter preset field (L*DTP).
1647 * - While in EQ PHASE 1, the EP & RC device exchange NO presets. They do advertise
1648 * their LF & FS which are needed for the fine tuning stages to follow.
1649 * - For the RC, while in EQ PHASE 2, the EP device makes tuning requests of the RC.
1650 * The RC adjusts its transmitter settings as directed by the EP. The requests are
1651 * communicated via TS1s.
1652 * - Once the EP is satisfied with the tuning, equalization moves to PHASE 3 where
1653 * the RC tunes the EP's remote transmitter.
1654 * Again, the settings are communicated via TS1s but the feedback is provided by
1655 * the RC phy's FOM or direction change indications.
1656 * \</pre\>
1657 */
1658 union ody_pciercx_eq_ctl67 {
1659 uint32_t u;
1660 struct ody_pciercx_eq_ctl67_s {
1661 uint32_t l6dtp : 4;
1662 uint32_t l6drph : 3;
1663 uint32_t reserved_7 : 1;
1664 uint32_t l6utp : 4;
1665 uint32_t l6urph : 3;
1666 uint32_t reserved_15 : 1;
1667 uint32_t l7dtp : 4;
1668 uint32_t l7drph : 3;
1669 uint32_t reserved_23 : 1;
1670 uint32_t l7utp : 4;
1671 uint32_t l7urph : 3;
1672 uint32_t reserved_31 : 1;
1673 } s;
1674 /* struct ody_pciercx_eq_ctl67_s cn; */
1675 };
1676 typedef union ody_pciercx_eq_ctl67 ody_pciercx_eq_ctl67_t;
1677
1678 static inline uint64_t ODY_PCIERCX_EQ_CTL67(uint64_t a) __attribute__ ((pure, always_inline));
ODY_PCIERCX_EQ_CTL67(uint64_t a)1679 static inline uint64_t ODY_PCIERCX_EQ_CTL67(uint64_t a)
1680 {
1681 if (a <= 15)
1682 return 0x180;
1683 __ody_csr_fatal("PCIERCX_EQ_CTL67", 1, a, 0, 0, 0, 0, 0);
1684 }
1685
1686 #define typedef_ODY_PCIERCX_EQ_CTL67(a) ody_pciercx_eq_ctl67_t
1687 #define bustype_ODY_PCIERCX_EQ_CTL67(a) CSR_TYPE_PCICONFIGRC
1688 #define basename_ODY_PCIERCX_EQ_CTL67(a) "PCIERCX_EQ_CTL67"
1689 #define busnum_ODY_PCIERCX_EQ_CTL67(a) (a)
1690 #define arguments_ODY_PCIERCX_EQ_CTL67(a) (a), -1, -1, -1
1691
1692 /**
1693 * Register (PCICONFIGRC) pcierc#_eq_ctl89
1694 *
1695 * PCIe RC Equalization Control Lane 8/9 Register
1696 * Not supported in QPEM/HPEM.
1697 *
1698 * The Equalization Control register consists of control fields required for per-Lane
1699 * 16.0 GT/s equalization.
1700 *
1701 * Equalization as an RC:
1702 * \<pre\>
1703 * - On speed change from GEN1-\>GEN3, advertise the transmitter preset hint per lane
1704 * to the EP device in the TS2s exchanged. This value comes from the per lane
1705 * upstream port transmitter preset (L*UTP).
1706 * - Upon exit from Recovery Speed, the RC will enter EQ PHASE1 and the RC's
1707 * transmitter will use the per lane downstream port transmitter preset field (L*DTP).
1708 * - While in EQ PHASE 1, the EP & RC device exchange NO presets. They do advertise
1709 * their LF & FS which are needed for the fine tuning stages to follow.
1710 * - For the RC, while in EQ PHASE 2, the EP device makes tuning requests of the RC.
1711 * The RC adjusts its transmitter settings as directed by the EP. The requests are
1712 * communicated via TS1s.
1713 * - Once the EP is satisfied with the tuning, equalization moves to PHASE 3 where
1714 * the RC tunes the EP's remote transmitter.
1715 * Again, the settings are communicated via TS1s but the feedback is provided by
1716 * the RC phy's FOM or direction change indications.
1717 * \</pre\>
1718 */
1719 union ody_pciercx_eq_ctl89 {
1720 uint32_t u;
1721 struct ody_pciercx_eq_ctl89_s {
1722 uint32_t l8dtp : 4;
1723 uint32_t l8drph : 3;
1724 uint32_t reserved_7 : 1;
1725 uint32_t l8utp : 4;
1726 uint32_t l8urph : 3;
1727 uint32_t reserved_15 : 1;
1728 uint32_t l9dtp : 4;
1729 uint32_t l9drph : 3;
1730 uint32_t reserved_23 : 1;
1731 uint32_t l9utp : 4;
1732 uint32_t l9urph : 3;
1733 uint32_t reserved_31 : 1;
1734 } s;
1735 /* struct ody_pciercx_eq_ctl89_s cn; */
1736 };
1737 typedef union ody_pciercx_eq_ctl89 ody_pciercx_eq_ctl89_t;
1738
1739 static inline uint64_t ODY_PCIERCX_EQ_CTL89(uint64_t a) __attribute__ ((pure, always_inline));
ODY_PCIERCX_EQ_CTL89(uint64_t a)1740 static inline uint64_t ODY_PCIERCX_EQ_CTL89(uint64_t a)
1741 {
1742 if (a <= 15)
1743 return 0x184;
1744 __ody_csr_fatal("PCIERCX_EQ_CTL89", 1, a, 0, 0, 0, 0, 0);
1745 }
1746
1747 #define typedef_ODY_PCIERCX_EQ_CTL89(a) ody_pciercx_eq_ctl89_t
1748 #define bustype_ODY_PCIERCX_EQ_CTL89(a) CSR_TYPE_PCICONFIGRC
1749 #define basename_ODY_PCIERCX_EQ_CTL89(a) "PCIERCX_EQ_CTL89"
1750 #define busnum_ODY_PCIERCX_EQ_CTL89(a) (a)
1751 #define arguments_ODY_PCIERCX_EQ_CTL89(a) (a), -1, -1, -1
1752
1753 /**
1754 * Register (PCICONFIGRC) pcierc#_err_source
1755 *
1756 * PCIe RC Error Source Identification Register
1757 */
1758 union ody_pciercx_err_source {
1759 uint32_t u;
1760 struct ody_pciercx_err_source_s {
1761 uint32_t ecsi : 16;
1762 uint32_t efnfsi : 16;
1763 } s;
1764 /* struct ody_pciercx_err_source_s cn; */
1765 };
1766 typedef union ody_pciercx_err_source ody_pciercx_err_source_t;
1767
1768 static inline uint64_t ODY_PCIERCX_ERR_SOURCE(uint64_t a) __attribute__ ((pure, always_inline));
ODY_PCIERCX_ERR_SOURCE(uint64_t a)1769 static inline uint64_t ODY_PCIERCX_ERR_SOURCE(uint64_t a)
1770 {
1771 if (a <= 15)
1772 return 0x134;
1773 __ody_csr_fatal("PCIERCX_ERR_SOURCE", 1, a, 0, 0, 0, 0, 0);
1774 }
1775
1776 #define typedef_ODY_PCIERCX_ERR_SOURCE(a) ody_pciercx_err_source_t
1777 #define bustype_ODY_PCIERCX_ERR_SOURCE(a) CSR_TYPE_PCICONFIGRC
1778 #define basename_ODY_PCIERCX_ERR_SOURCE(a) "PCIERCX_ERR_SOURCE"
1779 #define busnum_ODY_PCIERCX_ERR_SOURCE(a) (a)
1780 #define arguments_ODY_PCIERCX_ERR_SOURCE(a) (a), -1, -1, -1
1781
1782 /**
1783 * Register (PCICONFIGRC) pcierc#_ext_cap
1784 *
1785 * PCIe RC PCI Express Extended Capability Header Register
1786 */
1787 union ody_pciercx_ext_cap {
1788 uint32_t u;
1789 struct ody_pciercx_ext_cap_s {
1790 uint32_t pcieec : 16;
1791 uint32_t cv : 4;
1792 uint32_t nco : 12;
1793 } s;
1794 /* struct ody_pciercx_ext_cap_s cn; */
1795 };
1796 typedef union ody_pciercx_ext_cap ody_pciercx_ext_cap_t;
1797
1798 static inline uint64_t ODY_PCIERCX_EXT_CAP(uint64_t a) __attribute__ ((pure, always_inline));
ODY_PCIERCX_EXT_CAP(uint64_t a)1799 static inline uint64_t ODY_PCIERCX_EXT_CAP(uint64_t a)
1800 {
1801 if (a <= 15)
1802 return 0x100;
1803 __ody_csr_fatal("PCIERCX_EXT_CAP", 1, a, 0, 0, 0, 0, 0);
1804 }
1805
1806 #define typedef_ODY_PCIERCX_EXT_CAP(a) ody_pciercx_ext_cap_t
1807 #define bustype_ODY_PCIERCX_EXT_CAP(a) CSR_TYPE_PCICONFIGRC
1808 #define basename_ODY_PCIERCX_EXT_CAP(a) "PCIERCX_EXT_CAP"
1809 #define busnum_ODY_PCIERCX_EXT_CAP(a) (a)
1810 #define arguments_ODY_PCIERCX_EXT_CAP(a) (a), -1, -1, -1
1811
1812 /**
1813 * Register (PCICONFIGRC) pcierc#_filt_msk2
1814 *
1815 * PCIe RC Filter Mask Register 2
1816 */
1817 union ody_pciercx_filt_msk2 {
1818 uint32_t u;
1819 struct ody_pciercx_filt_msk2_s {
1820 uint32_t m_vend0_drp : 1;
1821 uint32_t m_vend1_drp : 1;
1822 uint32_t m_dabort_4ucpl : 1;
1823 uint32_t m_handle_flush : 1;
1824 uint32_t m_ln_vend1_drop : 1;
1825 uint32_t m_unmask_ur_pois : 1;
1826 uint32_t m_unmask_td : 1;
1827 uint32_t m_prs : 1;
1828 uint32_t m_pois_rpt : 1;
1829 uint32_t m_cpl_lut_chk : 1;
1830 uint32_t m_umsk_ats_rules : 1;
1831 uint32_t m_umsk_atomic_rules : 1;
1832 uint32_t reserved_12_31 : 20;
1833 } s;
1834 /* struct ody_pciercx_filt_msk2_s cn; */
1835 };
1836 typedef union ody_pciercx_filt_msk2 ody_pciercx_filt_msk2_t;
1837
1838 static inline uint64_t ODY_PCIERCX_FILT_MSK2(uint64_t a) __attribute__ ((pure, always_inline));
ODY_PCIERCX_FILT_MSK2(uint64_t a)1839 static inline uint64_t ODY_PCIERCX_FILT_MSK2(uint64_t a)
1840 {
1841 if (a <= 15)
1842 return 0x720;
1843 __ody_csr_fatal("PCIERCX_FILT_MSK2", 1, a, 0, 0, 0, 0, 0);
1844 }
1845
1846 #define typedef_ODY_PCIERCX_FILT_MSK2(a) ody_pciercx_filt_msk2_t
1847 #define bustype_ODY_PCIERCX_FILT_MSK2(a) CSR_TYPE_PCICONFIGRC
1848 #define basename_ODY_PCIERCX_FILT_MSK2(a) "PCIERCX_FILT_MSK2"
1849 #define busnum_ODY_PCIERCX_FILT_MSK2(a) (a)
1850 #define arguments_ODY_PCIERCX_FILT_MSK2(a) (a), -1, -1, -1
1851
1852 /**
1853 * Register (PCICONFIGRC) pcierc#_gen2_port
1854 *
1855 * PCIe RC Gen2 Port Logic Register
1856 */
1857 union ody_pciercx_gen2_port {
1858 uint32_t u;
1859 struct ody_pciercx_gen2_port_s {
1860 uint32_t n_fts : 8;
1861 uint32_t nlanes : 5;
1862 uint32_t pdetlane : 3;
1863 uint32_t alaneflip : 1;
1864 uint32_t dsc : 1;
1865 uint32_t cpyts : 1;
1866 uint32_t ctcrb : 1;
1867 uint32_t s_d_e : 1;
1868 uint32_t gen1_ei_inf : 1;
1869 uint32_t sel_deemph_var : 1;
1870 uint32_t sel_deemph_bit : 1;
1871 uint32_t lane_utest : 4;
1872 uint32_t eq_for_lpbk : 1;
1873 uint32_t tx_mcmpl_pat_for_lpbk : 1;
1874 uint32_t force_lflip : 1;
1875 uint32_t mod_ts_en : 1;
1876 } s;
1877 /* struct ody_pciercx_gen2_port_s cn; */
1878 };
1879 typedef union ody_pciercx_gen2_port ody_pciercx_gen2_port_t;
1880
1881 static inline uint64_t ODY_PCIERCX_GEN2_PORT(uint64_t a) __attribute__ ((pure, always_inline));
ODY_PCIERCX_GEN2_PORT(uint64_t a)1882 static inline uint64_t ODY_PCIERCX_GEN2_PORT(uint64_t a)
1883 {
1884 if (a <= 15)
1885 return 0x80c;
1886 __ody_csr_fatal("PCIERCX_GEN2_PORT", 1, a, 0, 0, 0, 0, 0);
1887 }
1888
1889 #define typedef_ODY_PCIERCX_GEN2_PORT(a) ody_pciercx_gen2_port_t
1890 #define bustype_ODY_PCIERCX_GEN2_PORT(a) CSR_TYPE_PCICONFIGRC
1891 #define basename_ODY_PCIERCX_GEN2_PORT(a) "PCIERCX_GEN2_PORT"
1892 #define busnum_ODY_PCIERCX_GEN2_PORT(a) (a)
1893 #define arguments_ODY_PCIERCX_GEN2_PORT(a) (a), -1, -1, -1
1894
1895 /**
1896 * Register (PCICONFIGRC) pcierc#_gen3_eq_ctl
1897 *
1898 * PCIe RC Gen3 EQ Control Register
1899 */
1900 union ody_pciercx_gen3_eq_ctl {
1901 uint32_t u;
1902 struct ody_pciercx_gen3_eq_ctl_s {
1903 uint32_t fm : 4;
1904 uint32_t bt : 1;
1905 uint32_t p23td : 1;
1906 uint32_t eq_redo_en : 1;
1907 uint32_t reserved_7 : 1;
1908 uint32_t prv : 16;
1909 uint32_t iif : 1;
1910 uint32_t eq_pset_req : 1;
1911 uint32_t scefpm : 1;
1912 uint32_t eq_req_num : 3;
1913 uint32_t fin_eq_req : 1;
1914 uint32_t reserved_31 : 1;
1915 } s;
1916 /* struct ody_pciercx_gen3_eq_ctl_s cn; */
1917 };
1918 typedef union ody_pciercx_gen3_eq_ctl ody_pciercx_gen3_eq_ctl_t;
1919
1920 static inline uint64_t ODY_PCIERCX_GEN3_EQ_CTL(uint64_t a) __attribute__ ((pure, always_inline));
ODY_PCIERCX_GEN3_EQ_CTL(uint64_t a)1921 static inline uint64_t ODY_PCIERCX_GEN3_EQ_CTL(uint64_t a)
1922 {
1923 if (a <= 15)
1924 return 0x8a8;
1925 __ody_csr_fatal("PCIERCX_GEN3_EQ_CTL", 1, a, 0, 0, 0, 0, 0);
1926 }
1927
1928 #define typedef_ODY_PCIERCX_GEN3_EQ_CTL(a) ody_pciercx_gen3_eq_ctl_t
1929 #define bustype_ODY_PCIERCX_GEN3_EQ_CTL(a) CSR_TYPE_PCICONFIGRC
1930 #define basename_ODY_PCIERCX_GEN3_EQ_CTL(a) "PCIERCX_GEN3_EQ_CTL"
1931 #define busnum_ODY_PCIERCX_GEN3_EQ_CTL(a) (a)
1932 #define arguments_ODY_PCIERCX_GEN3_EQ_CTL(a) (a), -1, -1, -1
1933
1934 /**
1935 * Register (PCICONFIGRC) pcierc#_gen3_pipe_lb
1936 *
1937 * PCIe RC Gen3 PIPE Loopback Register
1938 */
1939 union ody_pciercx_gen3_pipe_lb {
1940 uint32_t u;
1941 struct ody_pciercx_gen3_pipe_lb_s {
1942 uint32_t lpbk_rxvalid : 16;
1943 uint32_t rxstat_ln : 6;
1944 uint32_t reserved_22_23 : 2;
1945 uint32_t rx_stat : 3;
1946 uint32_t reserved_27_30 : 4;
1947 uint32_t ple : 1;
1948 } s;
1949 /* struct ody_pciercx_gen3_pipe_lb_s cn; */
1950 };
1951 typedef union ody_pciercx_gen3_pipe_lb ody_pciercx_gen3_pipe_lb_t;
1952
1953 static inline uint64_t ODY_PCIERCX_GEN3_PIPE_LB(uint64_t a) __attribute__ ((pure, always_inline));
ODY_PCIERCX_GEN3_PIPE_LB(uint64_t a)1954 static inline uint64_t ODY_PCIERCX_GEN3_PIPE_LB(uint64_t a)
1955 {
1956 if (a <= 15)
1957 return 0x8b8;
1958 __ody_csr_fatal("PCIERCX_GEN3_PIPE_LB", 1, a, 0, 0, 0, 0, 0);
1959 }
1960
1961 #define typedef_ODY_PCIERCX_GEN3_PIPE_LB(a) ody_pciercx_gen3_pipe_lb_t
1962 #define bustype_ODY_PCIERCX_GEN3_PIPE_LB(a) CSR_TYPE_PCICONFIGRC
1963 #define basename_ODY_PCIERCX_GEN3_PIPE_LB(a) "PCIERCX_GEN3_PIPE_LB"
1964 #define busnum_ODY_PCIERCX_GEN3_PIPE_LB(a) (a)
1965 #define arguments_ODY_PCIERCX_GEN3_PIPE_LB(a) (a), -1, -1, -1
1966
1967 /**
1968 * Register (PCICONFIGRC) pcierc#_gen4_lane_margining_1
1969 *
1970 * PCIe RC Gen4 Lane Margining Register 1
1971 */
1972 union ody_pciercx_gen4_lane_margining_1 {
1973 uint32_t u;
1974 struct ody_pciercx_gen4_lane_margining_1_s {
1975 uint32_t nts : 6;
1976 uint32_t reserved_6_7 : 2;
1977 uint32_t mto : 6;
1978 uint32_t reserved_14_15 : 2;
1979 uint32_t nvs : 7;
1980 uint32_t reserved_23 : 1;
1981 uint32_t mvo : 6;
1982 uint32_t reserved_30_31 : 2;
1983 } s;
1984 /* struct ody_pciercx_gen4_lane_margining_1_s cn; */
1985 };
1986 typedef union ody_pciercx_gen4_lane_margining_1 ody_pciercx_gen4_lane_margining_1_t;
1987
1988 static inline uint64_t ODY_PCIERCX_GEN4_LANE_MARGINING_1(uint64_t a) __attribute__ ((pure, always_inline));
ODY_PCIERCX_GEN4_LANE_MARGINING_1(uint64_t a)1989 static inline uint64_t ODY_PCIERCX_GEN4_LANE_MARGINING_1(uint64_t a)
1990 {
1991 if (a <= 15)
1992 return 0xb80;
1993 __ody_csr_fatal("PCIERCX_GEN4_LANE_MARGINING_1", 1, a, 0, 0, 0, 0, 0);
1994 }
1995
1996 #define typedef_ODY_PCIERCX_GEN4_LANE_MARGINING_1(a) ody_pciercx_gen4_lane_margining_1_t
1997 #define bustype_ODY_PCIERCX_GEN4_LANE_MARGINING_1(a) CSR_TYPE_PCICONFIGRC
1998 #define basename_ODY_PCIERCX_GEN4_LANE_MARGINING_1(a) "PCIERCX_GEN4_LANE_MARGINING_1"
1999 #define busnum_ODY_PCIERCX_GEN4_LANE_MARGINING_1(a) (a)
2000 #define arguments_ODY_PCIERCX_GEN4_LANE_MARGINING_1(a) (a), -1, -1, -1
2001
2002 /**
2003 * Register (PCICONFIGRC) pcierc#_gen4_lane_margining_2
2004 *
2005 * PCIe RC Gen4 Lane Margining Register 2
2006 */
2007 union ody_pciercx_gen4_lane_margining_2 {
2008 uint32_t u;
2009 struct ody_pciercx_gen4_lane_margining_2_s {
2010 uint32_t srv : 6;
2011 uint32_t reserved_6_7 : 2;
2012 uint32_t srt : 6;
2013 uint32_t reserved_14_15 : 2;
2014 uint32_t max_lanes : 5;
2015 uint32_t reserved_21_23 : 3;
2016 uint32_t volt_sup : 1;
2017 uint32_t iudv : 1;
2018 uint32_t ilrt : 1;
2019 uint32_t srm : 1;
2020 uint32_t ies : 1;
2021 uint32_t reserved_29_31 : 3;
2022 } s;
2023 /* struct ody_pciercx_gen4_lane_margining_2_s cn; */
2024 };
2025 typedef union ody_pciercx_gen4_lane_margining_2 ody_pciercx_gen4_lane_margining_2_t;
2026
2027 static inline uint64_t ODY_PCIERCX_GEN4_LANE_MARGINING_2(uint64_t a) __attribute__ ((pure, always_inline));
ODY_PCIERCX_GEN4_LANE_MARGINING_2(uint64_t a)2028 static inline uint64_t ODY_PCIERCX_GEN4_LANE_MARGINING_2(uint64_t a)
2029 {
2030 if (a <= 15)
2031 return 0xb84;
2032 __ody_csr_fatal("PCIERCX_GEN4_LANE_MARGINING_2", 1, a, 0, 0, 0, 0, 0);
2033 }
2034
2035 #define typedef_ODY_PCIERCX_GEN4_LANE_MARGINING_2(a) ody_pciercx_gen4_lane_margining_2_t
2036 #define bustype_ODY_PCIERCX_GEN4_LANE_MARGINING_2(a) CSR_TYPE_PCICONFIGRC
2037 #define basename_ODY_PCIERCX_GEN4_LANE_MARGINING_2(a) "PCIERCX_GEN4_LANE_MARGINING_2"
2038 #define busnum_ODY_PCIERCX_GEN4_LANE_MARGINING_2(a) (a)
2039 #define arguments_ODY_PCIERCX_GEN4_LANE_MARGINING_2(a) (a), -1, -1, -1
2040
2041 /**
2042 * Register (PCICONFIGRC) pcierc#_gen5_lane_margining_1
2043 *
2044 * PCIe RC Gen5 Lane Margining Register 1
2045 */
2046 union ody_pciercx_gen5_lane_margining_1 {
2047 uint32_t u;
2048 struct ody_pciercx_gen5_lane_margining_1_s {
2049 uint32_t nts : 6;
2050 uint32_t reserved_6_7 : 2;
2051 uint32_t mto : 6;
2052 uint32_t reserved_14_15 : 2;
2053 uint32_t nvs : 7;
2054 uint32_t reserved_23 : 1;
2055 uint32_t mvo : 6;
2056 uint32_t reserved_30_31 : 2;
2057 } s;
2058 /* struct ody_pciercx_gen5_lane_margining_1_s cn; */
2059 };
2060 typedef union ody_pciercx_gen5_lane_margining_1 ody_pciercx_gen5_lane_margining_1_t;
2061
2062 static inline uint64_t ODY_PCIERCX_GEN5_LANE_MARGINING_1(uint64_t a) __attribute__ ((pure, always_inline));
ODY_PCIERCX_GEN5_LANE_MARGINING_1(uint64_t a)2063 static inline uint64_t ODY_PCIERCX_GEN5_LANE_MARGINING_1(uint64_t a)
2064 {
2065 if (a <= 15)
2066 return 0xb88;
2067 __ody_csr_fatal("PCIERCX_GEN5_LANE_MARGINING_1", 1, a, 0, 0, 0, 0, 0);
2068 }
2069
2070 #define typedef_ODY_PCIERCX_GEN5_LANE_MARGINING_1(a) ody_pciercx_gen5_lane_margining_1_t
2071 #define bustype_ODY_PCIERCX_GEN5_LANE_MARGINING_1(a) CSR_TYPE_PCICONFIGRC
2072 #define basename_ODY_PCIERCX_GEN5_LANE_MARGINING_1(a) "PCIERCX_GEN5_LANE_MARGINING_1"
2073 #define busnum_ODY_PCIERCX_GEN5_LANE_MARGINING_1(a) (a)
2074 #define arguments_ODY_PCIERCX_GEN5_LANE_MARGINING_1(a) (a), -1, -1, -1
2075
2076 /**
2077 * Register (PCICONFIGRC) pcierc#_gen5_lane_margining_2
2078 *
2079 * PCIe RC Gen5 Lane Margining Register 2
2080 */
2081 union ody_pciercx_gen5_lane_margining_2 {
2082 uint32_t u;
2083 struct ody_pciercx_gen5_lane_margining_2_s {
2084 uint32_t srv : 6;
2085 uint32_t reserved_6_7 : 2;
2086 uint32_t srt : 6;
2087 uint32_t reserved_14_15 : 2;
2088 uint32_t max_lanes : 5;
2089 uint32_t reserved_21_23 : 3;
2090 uint32_t volt_sup : 1;
2091 uint32_t iudv : 1;
2092 uint32_t ilrt : 1;
2093 uint32_t srm : 1;
2094 uint32_t ies : 1;
2095 uint32_t reserved_29_31 : 3;
2096 } s;
2097 /* struct ody_pciercx_gen5_lane_margining_2_s cn; */
2098 };
2099 typedef union ody_pciercx_gen5_lane_margining_2 ody_pciercx_gen5_lane_margining_2_t;
2100
2101 static inline uint64_t ODY_PCIERCX_GEN5_LANE_MARGINING_2(uint64_t a) __attribute__ ((pure, always_inline));
ODY_PCIERCX_GEN5_LANE_MARGINING_2(uint64_t a)2102 static inline uint64_t ODY_PCIERCX_GEN5_LANE_MARGINING_2(uint64_t a)
2103 {
2104 if (a <= 15)
2105 return 0xb8c;
2106 __ody_csr_fatal("PCIERCX_GEN5_LANE_MARGINING_2", 1, a, 0, 0, 0, 0, 0);
2107 }
2108
2109 #define typedef_ODY_PCIERCX_GEN5_LANE_MARGINING_2(a) ody_pciercx_gen5_lane_margining_2_t
2110 #define bustype_ODY_PCIERCX_GEN5_LANE_MARGINING_2(a) CSR_TYPE_PCICONFIGRC
2111 #define basename_ODY_PCIERCX_GEN5_LANE_MARGINING_2(a) "PCIERCX_GEN5_LANE_MARGINING_2"
2112 #define busnum_ODY_PCIERCX_GEN5_LANE_MARGINING_2(a) (a)
2113 #define arguments_ODY_PCIERCX_GEN5_LANE_MARGINING_2(a) (a), -1, -1, -1
2114
2115 /**
2116 * Register (PCICONFIGRC) pcierc#_hdr_log1
2117 *
2118 * PCIe RC Header Log Register 1
2119 * The header log registers collect the header for the TLP corresponding to a detected error.
2120 */
2121 union ody_pciercx_hdr_log1 {
2122 uint32_t u;
2123 struct ody_pciercx_hdr_log1_s {
2124 uint32_t dword1 : 32;
2125 } s;
2126 /* struct ody_pciercx_hdr_log1_s cn; */
2127 };
2128 typedef union ody_pciercx_hdr_log1 ody_pciercx_hdr_log1_t;
2129
2130 static inline uint64_t ODY_PCIERCX_HDR_LOG1(uint64_t a) __attribute__ ((pure, always_inline));
ODY_PCIERCX_HDR_LOG1(uint64_t a)2131 static inline uint64_t ODY_PCIERCX_HDR_LOG1(uint64_t a)
2132 {
2133 if (a <= 15)
2134 return 0x11c;
2135 __ody_csr_fatal("PCIERCX_HDR_LOG1", 1, a, 0, 0, 0, 0, 0);
2136 }
2137
2138 #define typedef_ODY_PCIERCX_HDR_LOG1(a) ody_pciercx_hdr_log1_t
2139 #define bustype_ODY_PCIERCX_HDR_LOG1(a) CSR_TYPE_PCICONFIGRC
2140 #define basename_ODY_PCIERCX_HDR_LOG1(a) "PCIERCX_HDR_LOG1"
2141 #define busnum_ODY_PCIERCX_HDR_LOG1(a) (a)
2142 #define arguments_ODY_PCIERCX_HDR_LOG1(a) (a), -1, -1, -1
2143
2144 /**
2145 * Register (PCICONFIGRC) pcierc#_hdr_log2
2146 *
2147 * PCIe RC Header Log Register 2
2148 * The header log registers collect the header for the TLP corresponding to a detected error.
2149 */
2150 union ody_pciercx_hdr_log2 {
2151 uint32_t u;
2152 struct ody_pciercx_hdr_log2_s {
2153 uint32_t dword2 : 32;
2154 } s;
2155 /* struct ody_pciercx_hdr_log2_s cn; */
2156 };
2157 typedef union ody_pciercx_hdr_log2 ody_pciercx_hdr_log2_t;
2158
2159 static inline uint64_t ODY_PCIERCX_HDR_LOG2(uint64_t a) __attribute__ ((pure, always_inline));
ODY_PCIERCX_HDR_LOG2(uint64_t a)2160 static inline uint64_t ODY_PCIERCX_HDR_LOG2(uint64_t a)
2161 {
2162 if (a <= 15)
2163 return 0x120;
2164 __ody_csr_fatal("PCIERCX_HDR_LOG2", 1, a, 0, 0, 0, 0, 0);
2165 }
2166
2167 #define typedef_ODY_PCIERCX_HDR_LOG2(a) ody_pciercx_hdr_log2_t
2168 #define bustype_ODY_PCIERCX_HDR_LOG2(a) CSR_TYPE_PCICONFIGRC
2169 #define basename_ODY_PCIERCX_HDR_LOG2(a) "PCIERCX_HDR_LOG2"
2170 #define busnum_ODY_PCIERCX_HDR_LOG2(a) (a)
2171 #define arguments_ODY_PCIERCX_HDR_LOG2(a) (a), -1, -1, -1
2172
2173 /**
2174 * Register (PCICONFIGRC) pcierc#_hdr_log3
2175 *
2176 * PCIe RC Header Log Register 3
2177 * The header log registers collect the header for the TLP corresponding to a detected error.
2178 */
2179 union ody_pciercx_hdr_log3 {
2180 uint32_t u;
2181 struct ody_pciercx_hdr_log3_s {
2182 uint32_t dword3 : 32;
2183 } s;
2184 /* struct ody_pciercx_hdr_log3_s cn; */
2185 };
2186 typedef union ody_pciercx_hdr_log3 ody_pciercx_hdr_log3_t;
2187
2188 static inline uint64_t ODY_PCIERCX_HDR_LOG3(uint64_t a) __attribute__ ((pure, always_inline));
ODY_PCIERCX_HDR_LOG3(uint64_t a)2189 static inline uint64_t ODY_PCIERCX_HDR_LOG3(uint64_t a)
2190 {
2191 if (a <= 15)
2192 return 0x124;
2193 __ody_csr_fatal("PCIERCX_HDR_LOG3", 1, a, 0, 0, 0, 0, 0);
2194 }
2195
2196 #define typedef_ODY_PCIERCX_HDR_LOG3(a) ody_pciercx_hdr_log3_t
2197 #define bustype_ODY_PCIERCX_HDR_LOG3(a) CSR_TYPE_PCICONFIGRC
2198 #define basename_ODY_PCIERCX_HDR_LOG3(a) "PCIERCX_HDR_LOG3"
2199 #define busnum_ODY_PCIERCX_HDR_LOG3(a) (a)
2200 #define arguments_ODY_PCIERCX_HDR_LOG3(a) (a), -1, -1, -1
2201
2202 /**
2203 * Register (PCICONFIGRC) pcierc#_hdr_log4
2204 *
2205 * PCIe RC Header Log Register 4
2206 * The header log registers collect the header for the TLP corresponding to a detected error.
2207 */
2208 union ody_pciercx_hdr_log4 {
2209 uint32_t u;
2210 struct ody_pciercx_hdr_log4_s {
2211 uint32_t dword4 : 32;
2212 } s;
2213 /* struct ody_pciercx_hdr_log4_s cn; */
2214 };
2215 typedef union ody_pciercx_hdr_log4 ody_pciercx_hdr_log4_t;
2216
2217 static inline uint64_t ODY_PCIERCX_HDR_LOG4(uint64_t a) __attribute__ ((pure, always_inline));
ODY_PCIERCX_HDR_LOG4(uint64_t a)2218 static inline uint64_t ODY_PCIERCX_HDR_LOG4(uint64_t a)
2219 {
2220 if (a <= 15)
2221 return 0x128;
2222 __ody_csr_fatal("PCIERCX_HDR_LOG4", 1, a, 0, 0, 0, 0, 0);
2223 }
2224
2225 #define typedef_ODY_PCIERCX_HDR_LOG4(a) ody_pciercx_hdr_log4_t
2226 #define bustype_ODY_PCIERCX_HDR_LOG4(a) CSR_TYPE_PCICONFIGRC
2227 #define basename_ODY_PCIERCX_HDR_LOG4(a) "PCIERCX_HDR_LOG4"
2228 #define busnum_ODY_PCIERCX_HDR_LOG4(a) (a)
2229 #define arguments_ODY_PCIERCX_HDR_LOG4(a) (a), -1, -1, -1
2230
2231 /**
2232 * Register (PCICONFIGRC) pcierc#_id
2233 *
2234 * PCIe RC Device ID and Vendor ID Register
2235 */
2236 union ody_pciercx_id {
2237 uint32_t u;
2238 struct ody_pciercx_id_s {
2239 uint32_t vendid : 16;
2240 uint32_t devid : 16;
2241 } s;
2242 /* struct ody_pciercx_id_s cn; */
2243 };
2244 typedef union ody_pciercx_id ody_pciercx_id_t;
2245
2246 static inline uint64_t ODY_PCIERCX_ID(uint64_t a) __attribute__ ((pure, always_inline));
ODY_PCIERCX_ID(uint64_t a)2247 static inline uint64_t ODY_PCIERCX_ID(uint64_t a)
2248 {
2249 if (a <= 15)
2250 return 0;
2251 __ody_csr_fatal("PCIERCX_ID", 1, a, 0, 0, 0, 0, 0);
2252 }
2253
2254 #define typedef_ODY_PCIERCX_ID(a) ody_pciercx_id_t
2255 #define bustype_ODY_PCIERCX_ID(a) CSR_TYPE_PCICONFIGRC
2256 #define basename_ODY_PCIERCX_ID(a) "PCIERCX_ID"
2257 #define busnum_ODY_PCIERCX_ID(a) (a)
2258 #define arguments_ODY_PCIERCX_ID(a) (a), -1, -1, -1
2259
2260 /**
2261 * Register (PCICONFIGRC) pcierc#_ide_cap
2262 *
2263 * PCIe IDE Capability Register
2264 * This register provides access to the PCIe extended capability
2265 * register in the IDE encryption block. This register
2266 * is used in PEM configurations which support PCIe IDE encryption.
2267 */
2268 union ody_pciercx_ide_cap {
2269 uint32_t u;
2270 struct ody_pciercx_ide_cap_s {
2271 uint32_t liss : 1;
2272 uint32_t siss : 1;
2273 uint32_t fiss : 1;
2274 uint32_t reserved_3 : 1;
2275 uint32_t agg_sup : 1;
2276 uint32_t pcrc_sup : 1;
2277 uint32_t ikps : 1;
2278 uint32_t sicrs : 1;
2279 uint32_t sup_alg : 5;
2280 uint32_t nts : 3;
2281 uint32_t reserved_16_31 : 16;
2282 } s;
2283 /* struct ody_pciercx_ide_cap_s cn; */
2284 };
2285 typedef union ody_pciercx_ide_cap ody_pciercx_ide_cap_t;
2286
2287 static inline uint64_t ODY_PCIERCX_IDE_CAP(uint64_t a) __attribute__ ((pure, always_inline));
ODY_PCIERCX_IDE_CAP(uint64_t a)2288 static inline uint64_t ODY_PCIERCX_IDE_CAP(uint64_t a)
2289 {
2290 if (a <= 15)
2291 return 0x428;
2292 __ody_csr_fatal("PCIERCX_IDE_CAP", 1, a, 0, 0, 0, 0, 0);
2293 }
2294
2295 #define typedef_ODY_PCIERCX_IDE_CAP(a) ody_pciercx_ide_cap_t
2296 #define bustype_ODY_PCIERCX_IDE_CAP(a) CSR_TYPE_PCICONFIGRC
2297 #define basename_ODY_PCIERCX_IDE_CAP(a) "PCIERCX_IDE_CAP"
2298 #define busnum_ODY_PCIERCX_IDE_CAP(a) (a)
2299 #define arguments_ODY_PCIERCX_IDE_CAP(a) (a), -1, -1, -1
2300
2301 /**
2302 * Register (PCICONFIGRC) pcierc#_ide_ctrl
2303 *
2304 * PCIe IDE Control Register
2305 * This register provides access to the PCIe IDE control register
2306 * in the IDE encryption block. This register is used in
2307 * PEM configurations which support PCIe IDE encryption.
2308 */
2309 union ody_pciercx_ide_ctrl {
2310 uint32_t u;
2311 struct ody_pciercx_ide_ctrl_s {
2312 uint32_t reserved_0_1 : 2;
2313 uint32_t fis_en : 1;
2314 uint32_t reserved_3_31 : 29;
2315 } s;
2316 /* struct ody_pciercx_ide_ctrl_s cn; */
2317 };
2318 typedef union ody_pciercx_ide_ctrl ody_pciercx_ide_ctrl_t;
2319
2320 static inline uint64_t ODY_PCIERCX_IDE_CTRL(uint64_t a) __attribute__ ((pure, always_inline));
ODY_PCIERCX_IDE_CTRL(uint64_t a)2321 static inline uint64_t ODY_PCIERCX_IDE_CTRL(uint64_t a)
2322 {
2323 if (a <= 15)
2324 return 0x42c;
2325 __ody_csr_fatal("PCIERCX_IDE_CTRL", 1, a, 0, 0, 0, 0, 0);
2326 }
2327
2328 #define typedef_ODY_PCIERCX_IDE_CTRL(a) ody_pciercx_ide_ctrl_t
2329 #define bustype_ODY_PCIERCX_IDE_CTRL(a) CSR_TYPE_PCICONFIGRC
2330 #define basename_ODY_PCIERCX_IDE_CTRL(a) "PCIERCX_IDE_CTRL"
2331 #define busnum_ODY_PCIERCX_IDE_CTRL(a) (a)
2332 #define arguments_ODY_PCIERCX_IDE_CTRL(a) (a), -1, -1, -1
2333
2334 /**
2335 * Register (PCICONFIGRC) pcierc#_ide_ext_cap_hdr
2336 *
2337 * PCIe IDE Extended Capability Header Register
2338 * This register provides access to the PCIe extended capability
2339 * header register in the IDE encryption block. This register
2340 * is used in PEM configurations which support PCIe IDE encryption.
2341 */
2342 union ody_pciercx_ide_ext_cap_hdr {
2343 uint32_t u;
2344 struct ody_pciercx_ide_ext_cap_hdr_s {
2345 uint32_t pcieec : 16;
2346 uint32_t cv : 4;
2347 uint32_t nco : 12;
2348 } s;
2349 /* struct ody_pciercx_ide_ext_cap_hdr_s cn; */
2350 };
2351 typedef union ody_pciercx_ide_ext_cap_hdr ody_pciercx_ide_ext_cap_hdr_t;
2352
2353 static inline uint64_t ODY_PCIERCX_IDE_EXT_CAP_HDR(uint64_t a) __attribute__ ((pure, always_inline));
ODY_PCIERCX_IDE_EXT_CAP_HDR(uint64_t a)2354 static inline uint64_t ODY_PCIERCX_IDE_EXT_CAP_HDR(uint64_t a)
2355 {
2356 if (a <= 15)
2357 return 0x424;
2358 __ody_csr_fatal("PCIERCX_IDE_EXT_CAP_HDR", 1, a, 0, 0, 0, 0, 0);
2359 }
2360
2361 #define typedef_ODY_PCIERCX_IDE_EXT_CAP_HDR(a) ody_pciercx_ide_ext_cap_hdr_t
2362 #define bustype_ODY_PCIERCX_IDE_EXT_CAP_HDR(a) CSR_TYPE_PCICONFIGRC
2363 #define basename_ODY_PCIERCX_IDE_EXT_CAP_HDR(a) "PCIERCX_IDE_EXT_CAP_HDR"
2364 #define busnum_ODY_PCIERCX_IDE_EXT_CAP_HDR(a) (a)
2365 #define arguments_ODY_PCIERCX_IDE_EXT_CAP_HDR(a) (a), -1, -1, -1
2366
2367 /**
2368 * Register (PCICONFIGRC) pcierc#_ide_link_ctrl_0
2369 *
2370 * PCIe IDE Link Stream 0 Control Register
2371 * This register provides access to the PCIe IDE link stream 0 control
2372 * register in the IDE encryption block. This register is used
2373 * in PEM configurations which support PCIe IDE encryption.
2374 */
2375 union ody_pciercx_ide_link_ctrl_0 {
2376 uint32_t u;
2377 struct ody_pciercx_ide_link_ctrl_0_s {
2378 uint32_t lis_en : 1;
2379 uint32_t reserved_1_7 : 7;
2380 uint32_t pcrc_en : 1;
2381 uint32_t reserved_9_13 : 5;
2382 uint32_t sel_alg : 5;
2383 uint32_t tc : 3;
2384 uint32_t reserved_22_23 : 2;
2385 uint32_t strm_id : 8;
2386 } s;
2387 /* struct ody_pciercx_ide_link_ctrl_0_s cn; */
2388 };
2389 typedef union ody_pciercx_ide_link_ctrl_0 ody_pciercx_ide_link_ctrl_0_t;
2390
2391 static inline uint64_t ODY_PCIERCX_IDE_LINK_CTRL_0(uint64_t a) __attribute__ ((pure, always_inline));
ODY_PCIERCX_IDE_LINK_CTRL_0(uint64_t a)2392 static inline uint64_t ODY_PCIERCX_IDE_LINK_CTRL_0(uint64_t a)
2393 {
2394 if (a <= 15)
2395 return 0x430;
2396 __ody_csr_fatal("PCIERCX_IDE_LINK_CTRL_0", 1, a, 0, 0, 0, 0, 0);
2397 }
2398
2399 #define typedef_ODY_PCIERCX_IDE_LINK_CTRL_0(a) ody_pciercx_ide_link_ctrl_0_t
2400 #define bustype_ODY_PCIERCX_IDE_LINK_CTRL_0(a) CSR_TYPE_PCICONFIGRC
2401 #define basename_ODY_PCIERCX_IDE_LINK_CTRL_0(a) "PCIERCX_IDE_LINK_CTRL_0"
2402 #define busnum_ODY_PCIERCX_IDE_LINK_CTRL_0(a) (a)
2403 #define arguments_ODY_PCIERCX_IDE_LINK_CTRL_0(a) (a), -1, -1, -1
2404
2405 /**
2406 * Register (PCICONFIGRC) pcierc#_ide_link_status_0
2407 *
2408 * PCIe IDE Link Stream 0 Status Register
2409 * This register provides access to the PCIe IDE link stream 0
2410 * status register in the IDE encryption block. This register is
2411 * used in PEM configurations which support PCIe IDE encryption.
2412 */
2413 union ody_pciercx_ide_link_status_0 {
2414 uint32_t u;
2415 struct ody_pciercx_ide_link_status_0_s {
2416 uint32_t liss : 4;
2417 uint32_t reserved_4_30 : 27;
2418 uint32_t ricfm : 1;
2419 } s;
2420 /* struct ody_pciercx_ide_link_status_0_s cn; */
2421 };
2422 typedef union ody_pciercx_ide_link_status_0 ody_pciercx_ide_link_status_0_t;
2423
2424 static inline uint64_t ODY_PCIERCX_IDE_LINK_STATUS_0(uint64_t a) __attribute__ ((pure, always_inline));
ODY_PCIERCX_IDE_LINK_STATUS_0(uint64_t a)2425 static inline uint64_t ODY_PCIERCX_IDE_LINK_STATUS_0(uint64_t a)
2426 {
2427 if (a <= 15)
2428 return 0x434;
2429 __ody_csr_fatal("PCIERCX_IDE_LINK_STATUS_0", 1, a, 0, 0, 0, 0, 0);
2430 }
2431
2432 #define typedef_ODY_PCIERCX_IDE_LINK_STATUS_0(a) ody_pciercx_ide_link_status_0_t
2433 #define bustype_ODY_PCIERCX_IDE_LINK_STATUS_0(a) CSR_TYPE_PCICONFIGRC
2434 #define basename_ODY_PCIERCX_IDE_LINK_STATUS_0(a) "PCIERCX_IDE_LINK_STATUS_0"
2435 #define busnum_ODY_PCIERCX_IDE_LINK_STATUS_0(a) (a)
2436 #define arguments_ODY_PCIERCX_IDE_LINK_STATUS_0(a) (a), -1, -1, -1
2437
2438 /**
2439 * Register (PCICONFIGRC) pcierc#_int
2440 *
2441 * PCIe RC Interrupt Line Register/Interrupt Pin/Bridge Control Register
2442 */
2443 union ody_pciercx_int {
2444 uint32_t u;
2445 struct ody_pciercx_int_s {
2446 uint32_t il : 8;
2447 uint32_t inta : 8;
2448 uint32_t pere : 1;
2449 uint32_t see : 1;
2450 uint32_t isae : 1;
2451 uint32_t vgae : 1;
2452 uint32_t vga16d : 1;
2453 uint32_t mam : 1;
2454 uint32_t sbrst : 1;
2455 uint32_t fbbe : 1;
2456 uint32_t pdt : 1;
2457 uint32_t sdt : 1;
2458 uint32_t dts : 1;
2459 uint32_t dtsees : 1;
2460 uint32_t reserved_28_31 : 4;
2461 } s;
2462 /* struct ody_pciercx_int_s cn; */
2463 };
2464 typedef union ody_pciercx_int ody_pciercx_int_t;
2465
2466 static inline uint64_t ODY_PCIERCX_INT(uint64_t a) __attribute__ ((pure, always_inline));
ODY_PCIERCX_INT(uint64_t a)2467 static inline uint64_t ODY_PCIERCX_INT(uint64_t a)
2468 {
2469 if (a <= 15)
2470 return 0x3c;
2471 __ody_csr_fatal("PCIERCX_INT", 1, a, 0, 0, 0, 0, 0);
2472 }
2473
2474 #define typedef_ODY_PCIERCX_INT(a) ody_pciercx_int_t
2475 #define bustype_ODY_PCIERCX_INT(a) CSR_TYPE_PCICONFIGRC
2476 #define basename_ODY_PCIERCX_INT(a) "PCIERCX_INT"
2477 #define busnum_ODY_PCIERCX_INT(a) (a)
2478 #define arguments_ODY_PCIERCX_INT(a) (a), -1, -1, -1
2479
2480 /**
2481 * Register (PCICONFIGRC) pcierc#_iobasel
2482 *
2483 * PCIe RC I/O Base and I/O Limit/Secondary Status Register
2484 */
2485 union ody_pciercx_iobasel {
2486 uint32_t u;
2487 struct ody_pciercx_iobasel_s {
2488 uint32_t io32a : 1;
2489 uint32_t reserved_1_3 : 3;
2490 uint32_t lio_base : 4;
2491 uint32_t io32b : 1;
2492 uint32_t reserved_9_11 : 3;
2493 uint32_t lio_limi : 4;
2494 uint32_t reserved_16_20 : 5;
2495 uint32_t m66 : 1;
2496 uint32_t reserved_22 : 1;
2497 uint32_t fbb : 1;
2498 uint32_t mdpe : 1;
2499 uint32_t devt : 2;
2500 uint32_t sta : 1;
2501 uint32_t rta : 1;
2502 uint32_t rma : 1;
2503 uint32_t sse : 1;
2504 uint32_t dpe : 1;
2505 } s;
2506 /* struct ody_pciercx_iobasel_s cn; */
2507 };
2508 typedef union ody_pciercx_iobasel ody_pciercx_iobasel_t;
2509
2510 static inline uint64_t ODY_PCIERCX_IOBASEL(uint64_t a) __attribute__ ((pure, always_inline));
ODY_PCIERCX_IOBASEL(uint64_t a)2511 static inline uint64_t ODY_PCIERCX_IOBASEL(uint64_t a)
2512 {
2513 if (a <= 15)
2514 return 0x1c;
2515 __ody_csr_fatal("PCIERCX_IOBASEL", 1, a, 0, 0, 0, 0, 0);
2516 }
2517
2518 #define typedef_ODY_PCIERCX_IOBASEL(a) ody_pciercx_iobasel_t
2519 #define bustype_ODY_PCIERCX_IOBASEL(a) CSR_TYPE_PCICONFIGRC
2520 #define basename_ODY_PCIERCX_IOBASEL(a) "PCIERCX_IOBASEL"
2521 #define busnum_ODY_PCIERCX_IOBASEL(a) (a)
2522 #define arguments_ODY_PCIERCX_IOBASEL(a) (a), -1, -1, -1
2523
2524 /**
2525 * Register (PCICONFIGRC) pcierc#_iobaseu
2526 *
2527 * PCIe RC I/O Base and Limit Upper 16 Bits Register
2528 */
2529 union ody_pciercx_iobaseu {
2530 uint32_t u;
2531 struct ody_pciercx_iobaseu_s {
2532 uint32_t uio_base : 16;
2533 uint32_t uio_limit : 16;
2534 } s;
2535 /* struct ody_pciercx_iobaseu_s cn; */
2536 };
2537 typedef union ody_pciercx_iobaseu ody_pciercx_iobaseu_t;
2538
2539 static inline uint64_t ODY_PCIERCX_IOBASEU(uint64_t a) __attribute__ ((pure, always_inline));
ODY_PCIERCX_IOBASEU(uint64_t a)2540 static inline uint64_t ODY_PCIERCX_IOBASEU(uint64_t a)
2541 {
2542 if (a <= 15)
2543 return 0x30;
2544 __ody_csr_fatal("PCIERCX_IOBASEU", 1, a, 0, 0, 0, 0, 0);
2545 }
2546
2547 #define typedef_ODY_PCIERCX_IOBASEU(a) ody_pciercx_iobaseu_t
2548 #define bustype_ODY_PCIERCX_IOBASEU(a) CSR_TYPE_PCICONFIGRC
2549 #define basename_ODY_PCIERCX_IOBASEU(a) "PCIERCX_IOBASEU"
2550 #define busnum_ODY_PCIERCX_IOBASEU(a) (a)
2551 #define arguments_ODY_PCIERCX_IOBASEU(a) (a), -1, -1, -1
2552
2553 /**
2554 * Register (PCICONFIGRC) pcierc#_lane_err
2555 *
2556 * Lane Error Status Register
2557 */
2558 union ody_pciercx_lane_err {
2559 uint32_t u;
2560 struct ody_pciercx_lane_err_s {
2561 uint32_t les : 4;
2562 uint32_t reserved_4_31 : 28;
2563 } s;
2564 /* struct ody_pciercx_lane_err_s cn; */
2565 };
2566 typedef union ody_pciercx_lane_err ody_pciercx_lane_err_t;
2567
2568 static inline uint64_t ODY_PCIERCX_LANE_ERR(uint64_t a) __attribute__ ((pure, always_inline));
ODY_PCIERCX_LANE_ERR(uint64_t a)2569 static inline uint64_t ODY_PCIERCX_LANE_ERR(uint64_t a)
2570 {
2571 if (a <= 15)
2572 return 0x170;
2573 __ody_csr_fatal("PCIERCX_LANE_ERR", 1, a, 0, 0, 0, 0, 0);
2574 }
2575
2576 #define typedef_ODY_PCIERCX_LANE_ERR(a) ody_pciercx_lane_err_t
2577 #define bustype_ODY_PCIERCX_LANE_ERR(a) CSR_TYPE_PCICONFIGRC
2578 #define basename_ODY_PCIERCX_LANE_ERR(a) "PCIERCX_LANE_ERR"
2579 #define busnum_ODY_PCIERCX_LANE_ERR(a) (a)
2580 #define arguments_ODY_PCIERCX_LANE_ERR(a) (a), -1, -1, -1
2581
2582 /**
2583 * Register (PCICONFIGRC) pcierc#_lane_skew
2584 *
2585 * PCIe RC Lane Skew Register
2586 */
2587 union ody_pciercx_lane_skew {
2588 uint32_t u;
2589 struct ody_pciercx_lane_skew_s {
2590 uint32_t ilst : 24;
2591 uint32_t fcd : 1;
2592 uint32_t ack_nak : 1;
2593 uint32_t ebm : 1;
2594 uint32_t inuml : 4;
2595 uint32_t dlld : 1;
2596 } s;
2597 /* struct ody_pciercx_lane_skew_s cn; */
2598 };
2599 typedef union ody_pciercx_lane_skew ody_pciercx_lane_skew_t;
2600
2601 static inline uint64_t ODY_PCIERCX_LANE_SKEW(uint64_t a) __attribute__ ((pure, always_inline));
ODY_PCIERCX_LANE_SKEW(uint64_t a)2602 static inline uint64_t ODY_PCIERCX_LANE_SKEW(uint64_t a)
2603 {
2604 if (a <= 15)
2605 return 0x714;
2606 __ody_csr_fatal("PCIERCX_LANE_SKEW", 1, a, 0, 0, 0, 0, 0);
2607 }
2608
2609 #define typedef_ODY_PCIERCX_LANE_SKEW(a) ody_pciercx_lane_skew_t
2610 #define bustype_ODY_PCIERCX_LANE_SKEW(a) CSR_TYPE_PCICONFIGRC
2611 #define basename_ODY_PCIERCX_LANE_SKEW(a) "PCIERCX_LANE_SKEW"
2612 #define busnum_ODY_PCIERCX_LANE_SKEW(a) (a)
2613 #define arguments_ODY_PCIERCX_LANE_SKEW(a) (a), -1, -1, -1
2614
2615 /**
2616 * Register (PCICONFIGRC) pcierc#_link_cap
2617 *
2618 * PCIe RC Link Capabilities Register
2619 */
2620 union ody_pciercx_link_cap {
2621 uint32_t u;
2622 struct ody_pciercx_link_cap_s {
2623 uint32_t mls : 4;
2624 uint32_t mlw : 6;
2625 uint32_t aslpms : 2;
2626 uint32_t l0el : 3;
2627 uint32_t l1el : 3;
2628 uint32_t cpm : 1;
2629 uint32_t sderc : 1;
2630 uint32_t dllarc : 1;
2631 uint32_t lbnc : 1;
2632 uint32_t aspm : 1;
2633 uint32_t reserved_23 : 1;
2634 uint32_t pnum : 8;
2635 } s;
2636 /* struct ody_pciercx_link_cap_s cn; */
2637 };
2638 typedef union ody_pciercx_link_cap ody_pciercx_link_cap_t;
2639
2640 static inline uint64_t ODY_PCIERCX_LINK_CAP(uint64_t a) __attribute__ ((pure, always_inline));
ODY_PCIERCX_LINK_CAP(uint64_t a)2641 static inline uint64_t ODY_PCIERCX_LINK_CAP(uint64_t a)
2642 {
2643 if (a <= 15)
2644 return 0x7c;
2645 __ody_csr_fatal("PCIERCX_LINK_CAP", 1, a, 0, 0, 0, 0, 0);
2646 }
2647
2648 #define typedef_ODY_PCIERCX_LINK_CAP(a) ody_pciercx_link_cap_t
2649 #define bustype_ODY_PCIERCX_LINK_CAP(a) CSR_TYPE_PCICONFIGRC
2650 #define basename_ODY_PCIERCX_LINK_CAP(a) "PCIERCX_LINK_CAP"
2651 #define busnum_ODY_PCIERCX_LINK_CAP(a) (a)
2652 #define arguments_ODY_PCIERCX_LINK_CAP(a) (a), -1, -1, -1
2653
2654 /**
2655 * Register (PCICONFIGRC) pcierc#_link_cap2
2656 *
2657 * PCIe RC Link Capabilities 2 Register
2658 */
2659 union ody_pciercx_link_cap2 {
2660 uint32_t u;
2661 struct ody_pciercx_link_cap2_s {
2662 uint32_t reserved_0 : 1;
2663 uint32_t slsv : 7;
2664 uint32_t cls : 1;
2665 uint32_t reserved_9_22 : 14;
2666 uint32_t rtds : 1;
2667 uint32_t trtds : 1;
2668 uint32_t reserved_25_31 : 7;
2669 } s;
2670 /* struct ody_pciercx_link_cap2_s cn; */
2671 };
2672 typedef union ody_pciercx_link_cap2 ody_pciercx_link_cap2_t;
2673
2674 static inline uint64_t ODY_PCIERCX_LINK_CAP2(uint64_t a) __attribute__ ((pure, always_inline));
ODY_PCIERCX_LINK_CAP2(uint64_t a)2675 static inline uint64_t ODY_PCIERCX_LINK_CAP2(uint64_t a)
2676 {
2677 if (a <= 15)
2678 return 0x9c;
2679 __ody_csr_fatal("PCIERCX_LINK_CAP2", 1, a, 0, 0, 0, 0, 0);
2680 }
2681
2682 #define typedef_ODY_PCIERCX_LINK_CAP2(a) ody_pciercx_link_cap2_t
2683 #define bustype_ODY_PCIERCX_LINK_CAP2(a) CSR_TYPE_PCICONFIGRC
2684 #define basename_ODY_PCIERCX_LINK_CAP2(a) "PCIERCX_LINK_CAP2"
2685 #define busnum_ODY_PCIERCX_LINK_CAP2(a) (a)
2686 #define arguments_ODY_PCIERCX_LINK_CAP2(a) (a), -1, -1, -1
2687
2688 /**
2689 * Register (PCICONFIGRC) pcierc#_link_ctl
2690 *
2691 * PCIe RC Link Control/Link Status Register
2692 */
2693 union ody_pciercx_link_ctl {
2694 uint32_t u;
2695 struct ody_pciercx_link_ctl_s {
2696 uint32_t aslpc : 2;
2697 uint32_t reserved_2 : 1;
2698 uint32_t rcb : 1;
2699 uint32_t ld : 1;
2700 uint32_t rl : 1;
2701 uint32_t ccc : 1;
2702 uint32_t es : 1;
2703 uint32_t ecpm : 1;
2704 uint32_t hawd : 1;
2705 uint32_t lbm_int_enb : 1;
2706 uint32_t lab_int_enb : 1;
2707 uint32_t reserved_12_13 : 2;
2708 uint32_t drs_ctl : 2;
2709 uint32_t ls : 4;
2710 uint32_t nlw : 6;
2711 uint32_t reserved_26 : 1;
2712 uint32_t lt : 1;
2713 uint32_t scc : 1;
2714 uint32_t dlla : 1;
2715 uint32_t lbm : 1;
2716 uint32_t lab : 1;
2717 } s;
2718 /* struct ody_pciercx_link_ctl_s cn; */
2719 };
2720 typedef union ody_pciercx_link_ctl ody_pciercx_link_ctl_t;
2721
2722 static inline uint64_t ODY_PCIERCX_LINK_CTL(uint64_t a) __attribute__ ((pure, always_inline));
ODY_PCIERCX_LINK_CTL(uint64_t a)2723 static inline uint64_t ODY_PCIERCX_LINK_CTL(uint64_t a)
2724 {
2725 if (a <= 15)
2726 return 0x80;
2727 __ody_csr_fatal("PCIERCX_LINK_CTL", 1, a, 0, 0, 0, 0, 0);
2728 }
2729
2730 #define typedef_ODY_PCIERCX_LINK_CTL(a) ody_pciercx_link_ctl_t
2731 #define bustype_ODY_PCIERCX_LINK_CTL(a) CSR_TYPE_PCICONFIGRC
2732 #define basename_ODY_PCIERCX_LINK_CTL(a) "PCIERCX_LINK_CTL"
2733 #define busnum_ODY_PCIERCX_LINK_CTL(a) (a)
2734 #define arguments_ODY_PCIERCX_LINK_CTL(a) (a), -1, -1, -1
2735
2736 /**
2737 * Register (PCICONFIGRC) pcierc#_link_ctl2
2738 *
2739 * PCIe RC Link Control 2 Register/Link Status 2 Register
2740 */
2741 union ody_pciercx_link_ctl2 {
2742 uint32_t u;
2743 struct ody_pciercx_link_ctl2_s {
2744 uint32_t tls : 4;
2745 uint32_t ec : 1;
2746 uint32_t hasd : 1;
2747 uint32_t sde : 1;
2748 uint32_t tm : 3;
2749 uint32_t emc : 1;
2750 uint32_t csos : 1;
2751 uint32_t cde : 4;
2752 uint32_t cdl : 1;
2753 uint32_t eqc : 1;
2754 uint32_t ep1s : 1;
2755 uint32_t ep2s : 1;
2756 uint32_t ep3s : 1;
2757 uint32_t ler : 1;
2758 uint32_t rtd : 1;
2759 uint32_t trtd : 1;
2760 uint32_t crossl : 2;
2761 uint32_t reserved_26_27 : 2;
2762 uint32_t dcp : 3;
2763 uint32_t drs_mr : 1;
2764 } s;
2765 /* struct ody_pciercx_link_ctl2_s cn; */
2766 };
2767 typedef union ody_pciercx_link_ctl2 ody_pciercx_link_ctl2_t;
2768
2769 static inline uint64_t ODY_PCIERCX_LINK_CTL2(uint64_t a) __attribute__ ((pure, always_inline));
ODY_PCIERCX_LINK_CTL2(uint64_t a)2770 static inline uint64_t ODY_PCIERCX_LINK_CTL2(uint64_t a)
2771 {
2772 if (a <= 15)
2773 return 0xa0;
2774 __ody_csr_fatal("PCIERCX_LINK_CTL2", 1, a, 0, 0, 0, 0, 0);
2775 }
2776
2777 #define typedef_ODY_PCIERCX_LINK_CTL2(a) ody_pciercx_link_ctl2_t
2778 #define bustype_ODY_PCIERCX_LINK_CTL2(a) CSR_TYPE_PCICONFIGRC
2779 #define basename_ODY_PCIERCX_LINK_CTL2(a) "PCIERCX_LINK_CTL2"
2780 #define busnum_ODY_PCIERCX_LINK_CTL2(a) (a)
2781 #define arguments_ODY_PCIERCX_LINK_CTL2(a) (a), -1, -1, -1
2782
2783 /**
2784 * Register (PCICONFIGRC) pcierc#_link_ctl3
2785 *
2786 * PCIe RC Link Control 3 Register
2787 */
2788 union ody_pciercx_link_ctl3 {
2789 uint32_t u;
2790 struct ody_pciercx_link_ctl3_s {
2791 uint32_t pe : 1;
2792 uint32_t ler : 1;
2793 uint32_t reserved_2_31 : 30;
2794 } s;
2795 /* struct ody_pciercx_link_ctl3_s cn; */
2796 };
2797 typedef union ody_pciercx_link_ctl3 ody_pciercx_link_ctl3_t;
2798
2799 static inline uint64_t ODY_PCIERCX_LINK_CTL3(uint64_t a) __attribute__ ((pure, always_inline));
ODY_PCIERCX_LINK_CTL3(uint64_t a)2800 static inline uint64_t ODY_PCIERCX_LINK_CTL3(uint64_t a)
2801 {
2802 if (a <= 15)
2803 return 0x16c;
2804 __ody_csr_fatal("PCIERCX_LINK_CTL3", 1, a, 0, 0, 0, 0, 0);
2805 }
2806
2807 #define typedef_ODY_PCIERCX_LINK_CTL3(a) ody_pciercx_link_ctl3_t
2808 #define bustype_ODY_PCIERCX_LINK_CTL3(a) CSR_TYPE_PCICONFIGRC
2809 #define basename_ODY_PCIERCX_LINK_CTL3(a) "PCIERCX_LINK_CTL3"
2810 #define busnum_ODY_PCIERCX_LINK_CTL3(a) (a)
2811 #define arguments_ODY_PCIERCX_LINK_CTL3(a) (a), -1, -1, -1
2812
2813 /**
2814 * Register (PCICONFIGRC) pcierc#_margin_ext_cap_hdr
2815 *
2816 * PCIe RC Margining Extended Capability Header Register
2817 */
2818 union ody_pciercx_margin_ext_cap_hdr {
2819 uint32_t u;
2820 struct ody_pciercx_margin_ext_cap_hdr_s {
2821 uint32_t pcieec : 16;
2822 uint32_t cv : 4;
2823 uint32_t nco : 12;
2824 } s;
2825 /* struct ody_pciercx_margin_ext_cap_hdr_s cn; */
2826 };
2827 typedef union ody_pciercx_margin_ext_cap_hdr ody_pciercx_margin_ext_cap_hdr_t;
2828
2829 static inline uint64_t ODY_PCIERCX_MARGIN_EXT_CAP_HDR(uint64_t a) __attribute__ ((pure, always_inline));
ODY_PCIERCX_MARGIN_EXT_CAP_HDR(uint64_t a)2830 static inline uint64_t ODY_PCIERCX_MARGIN_EXT_CAP_HDR(uint64_t a)
2831 {
2832 if (a <= 15)
2833 return 0x1c8;
2834 __ody_csr_fatal("PCIERCX_MARGIN_EXT_CAP_HDR", 1, a, 0, 0, 0, 0, 0);
2835 }
2836
2837 #define typedef_ODY_PCIERCX_MARGIN_EXT_CAP_HDR(a) ody_pciercx_margin_ext_cap_hdr_t
2838 #define bustype_ODY_PCIERCX_MARGIN_EXT_CAP_HDR(a) CSR_TYPE_PCICONFIGRC
2839 #define basename_ODY_PCIERCX_MARGIN_EXT_CAP_HDR(a) "PCIERCX_MARGIN_EXT_CAP_HDR"
2840 #define busnum_ODY_PCIERCX_MARGIN_EXT_CAP_HDR(a) (a)
2841 #define arguments_ODY_PCIERCX_MARGIN_EXT_CAP_HDR(a) (a), -1, -1, -1
2842
2843 /**
2844 * Register (PCICONFIGRC) pcierc#_mem
2845 *
2846 * PCIe RC Memory Base and Memory Limit Register
2847 */
2848 union ody_pciercx_mem {
2849 uint32_t u;
2850 struct ody_pciercx_mem_s {
2851 uint32_t reserved_0_3 : 4;
2852 uint32_t mb_addr : 12;
2853 uint32_t reserved_16_19 : 4;
2854 uint32_t ml_addr : 12;
2855 } s;
2856 /* struct ody_pciercx_mem_s cn; */
2857 };
2858 typedef union ody_pciercx_mem ody_pciercx_mem_t;
2859
2860 static inline uint64_t ODY_PCIERCX_MEM(uint64_t a) __attribute__ ((pure, always_inline));
ODY_PCIERCX_MEM(uint64_t a)2861 static inline uint64_t ODY_PCIERCX_MEM(uint64_t a)
2862 {
2863 if (a <= 15)
2864 return 0x20;
2865 __ody_csr_fatal("PCIERCX_MEM", 1, a, 0, 0, 0, 0, 0);
2866 }
2867
2868 #define typedef_ODY_PCIERCX_MEM(a) ody_pciercx_mem_t
2869 #define bustype_ODY_PCIERCX_MEM(a) CSR_TYPE_PCICONFIGRC
2870 #define basename_ODY_PCIERCX_MEM(a) "PCIERCX_MEM"
2871 #define busnum_ODY_PCIERCX_MEM(a) (a)
2872 #define arguments_ODY_PCIERCX_MEM(a) (a), -1, -1, -1
2873
2874 /**
2875 * Register (PCICONFIGRC) pcierc#_misc_ctl1
2876 *
2877 * PCIe RC Miscellaneous Control 1 Register
2878 */
2879 union ody_pciercx_misc_ctl1 {
2880 uint32_t u;
2881 struct ody_pciercx_misc_ctl1_s {
2882 uint32_t dbi_ro_wr_en : 1;
2883 uint32_t def_target : 1;
2884 uint32_t ur_c4_mask_4_trgt1 : 1;
2885 uint32_t simp_replay_timer : 1;
2886 uint32_t dis_auto_ltr_clr : 1;
2887 uint32_t ari_devn : 1;
2888 uint32_t cplq_mng_en : 1;
2889 uint32_t cfg_tlp_byp_en : 1;
2890 uint32_t cfg_limit : 10;
2891 uint32_t trgt_above_cfg_limit : 2;
2892 uint32_t p2p_track_cpl : 1;
2893 uint32_t p2p_err_rpt : 1;
2894 uint32_t port_logic_wr_dis : 1;
2895 uint32_t ras_reg_pf0_only : 1;
2896 uint32_t rasdes_reg_pf0_only : 1;
2897 uint32_t err_inj_wr_dis : 1;
2898 uint32_t reserved_26_31 : 6;
2899 } s;
2900 /* struct ody_pciercx_misc_ctl1_s cn; */
2901 };
2902 typedef union ody_pciercx_misc_ctl1 ody_pciercx_misc_ctl1_t;
2903
2904 static inline uint64_t ODY_PCIERCX_MISC_CTL1(uint64_t a) __attribute__ ((pure, always_inline));
ODY_PCIERCX_MISC_CTL1(uint64_t a)2905 static inline uint64_t ODY_PCIERCX_MISC_CTL1(uint64_t a)
2906 {
2907 if (a <= 15)
2908 return 0x8bc;
2909 __ody_csr_fatal("PCIERCX_MISC_CTL1", 1, a, 0, 0, 0, 0, 0);
2910 }
2911
2912 #define typedef_ODY_PCIERCX_MISC_CTL1(a) ody_pciercx_misc_ctl1_t
2913 #define bustype_ODY_PCIERCX_MISC_CTL1(a) CSR_TYPE_PCICONFIGRC
2914 #define basename_ODY_PCIERCX_MISC_CTL1(a) "PCIERCX_MISC_CTL1"
2915 #define busnum_ODY_PCIERCX_MISC_CTL1(a) (a)
2916 #define arguments_ODY_PCIERCX_MISC_CTL1(a) (a), -1, -1, -1
2917
2918 /**
2919 * Register (PCICONFIGRC) pcierc#_mrg_lane_ctl_stat0
2920 *
2921 * PCIe RC Margining Lane Control and Status Register 0
2922 */
2923 union ody_pciercx_mrg_lane_ctl_stat0 {
2924 uint32_t u;
2925 struct ody_pciercx_mrg_lane_ctl_stat0_s {
2926 uint32_t rnum : 3;
2927 uint32_t mt : 3;
2928 uint32_t um : 1;
2929 uint32_t reserved_7 : 1;
2930 uint32_t mpl : 8;
2931 uint32_t rnum_stat : 3;
2932 uint32_t mt_stat : 3;
2933 uint32_t um_stat : 1;
2934 uint32_t reserved_23 : 1;
2935 uint32_t pl_stat : 8;
2936 } s;
2937 /* struct ody_pciercx_mrg_lane_ctl_stat0_s cn; */
2938 };
2939 typedef union ody_pciercx_mrg_lane_ctl_stat0 ody_pciercx_mrg_lane_ctl_stat0_t;
2940
2941 static inline uint64_t ODY_PCIERCX_MRG_LANE_CTL_STAT0(uint64_t a) __attribute__ ((pure, always_inline));
ODY_PCIERCX_MRG_LANE_CTL_STAT0(uint64_t a)2942 static inline uint64_t ODY_PCIERCX_MRG_LANE_CTL_STAT0(uint64_t a)
2943 {
2944 if (a <= 15)
2945 return 0x1d0;
2946 __ody_csr_fatal("PCIERCX_MRG_LANE_CTL_STAT0", 1, a, 0, 0, 0, 0, 0);
2947 }
2948
2949 #define typedef_ODY_PCIERCX_MRG_LANE_CTL_STAT0(a) ody_pciercx_mrg_lane_ctl_stat0_t
2950 #define bustype_ODY_PCIERCX_MRG_LANE_CTL_STAT0(a) CSR_TYPE_PCICONFIGRC
2951 #define basename_ODY_PCIERCX_MRG_LANE_CTL_STAT0(a) "PCIERCX_MRG_LANE_CTL_STAT0"
2952 #define busnum_ODY_PCIERCX_MRG_LANE_CTL_STAT0(a) (a)
2953 #define arguments_ODY_PCIERCX_MRG_LANE_CTL_STAT0(a) (a), -1, -1, -1
2954
2955 /**
2956 * Register (PCICONFIGRC) pcierc#_mrg_lane_ctl_stat1
2957 *
2958 * PCIe RC Margining Lane Control and Status Register 1
2959 */
2960 union ody_pciercx_mrg_lane_ctl_stat1 {
2961 uint32_t u;
2962 struct ody_pciercx_mrg_lane_ctl_stat1_s {
2963 uint32_t rnum : 3;
2964 uint32_t mt : 3;
2965 uint32_t um : 1;
2966 uint32_t reserved_7 : 1;
2967 uint32_t mpl : 8;
2968 uint32_t rnum_stat : 3;
2969 uint32_t mt_stat : 3;
2970 uint32_t um_stat : 1;
2971 uint32_t reserved_23 : 1;
2972 uint32_t pl_stat : 8;
2973 } s;
2974 /* struct ody_pciercx_mrg_lane_ctl_stat1_s cn; */
2975 };
2976 typedef union ody_pciercx_mrg_lane_ctl_stat1 ody_pciercx_mrg_lane_ctl_stat1_t;
2977
2978 static inline uint64_t ODY_PCIERCX_MRG_LANE_CTL_STAT1(uint64_t a) __attribute__ ((pure, always_inline));
ODY_PCIERCX_MRG_LANE_CTL_STAT1(uint64_t a)2979 static inline uint64_t ODY_PCIERCX_MRG_LANE_CTL_STAT1(uint64_t a)
2980 {
2981 if (a <= 15)
2982 return 0x1d4;
2983 __ody_csr_fatal("PCIERCX_MRG_LANE_CTL_STAT1", 1, a, 0, 0, 0, 0, 0);
2984 }
2985
2986 #define typedef_ODY_PCIERCX_MRG_LANE_CTL_STAT1(a) ody_pciercx_mrg_lane_ctl_stat1_t
2987 #define bustype_ODY_PCIERCX_MRG_LANE_CTL_STAT1(a) CSR_TYPE_PCICONFIGRC
2988 #define basename_ODY_PCIERCX_MRG_LANE_CTL_STAT1(a) "PCIERCX_MRG_LANE_CTL_STAT1"
2989 #define busnum_ODY_PCIERCX_MRG_LANE_CTL_STAT1(a) (a)
2990 #define arguments_ODY_PCIERCX_MRG_LANE_CTL_STAT1(a) (a), -1, -1, -1
2991
2992 /**
2993 * Register (PCICONFIGRC) pcierc#_mrg_lane_ctl_stat10
2994 *
2995 * PCIe RC Margining Lane Control and Status Register 10
2996 */
2997 union ody_pciercx_mrg_lane_ctl_stat10 {
2998 uint32_t u;
2999 struct ody_pciercx_mrg_lane_ctl_stat10_s {
3000 uint32_t rnum : 3;
3001 uint32_t mt : 3;
3002 uint32_t um : 1;
3003 uint32_t reserved_7 : 1;
3004 uint32_t mpl : 8;
3005 uint32_t rnum_stat : 3;
3006 uint32_t mt_stat : 3;
3007 uint32_t um_stat : 1;
3008 uint32_t reserved_23 : 1;
3009 uint32_t pl_stat : 8;
3010 } s;
3011 /* struct ody_pciercx_mrg_lane_ctl_stat10_s cn; */
3012 };
3013 typedef union ody_pciercx_mrg_lane_ctl_stat10 ody_pciercx_mrg_lane_ctl_stat10_t;
3014
3015 static inline uint64_t ODY_PCIERCX_MRG_LANE_CTL_STAT10(uint64_t a) __attribute__ ((pure, always_inline));
ODY_PCIERCX_MRG_LANE_CTL_STAT10(uint64_t a)3016 static inline uint64_t ODY_PCIERCX_MRG_LANE_CTL_STAT10(uint64_t a)
3017 {
3018 if (a <= 15)
3019 return 0x1f8;
3020 __ody_csr_fatal("PCIERCX_MRG_LANE_CTL_STAT10", 1, a, 0, 0, 0, 0, 0);
3021 }
3022
3023 #define typedef_ODY_PCIERCX_MRG_LANE_CTL_STAT10(a) ody_pciercx_mrg_lane_ctl_stat10_t
3024 #define bustype_ODY_PCIERCX_MRG_LANE_CTL_STAT10(a) CSR_TYPE_PCICONFIGRC
3025 #define basename_ODY_PCIERCX_MRG_LANE_CTL_STAT10(a) "PCIERCX_MRG_LANE_CTL_STAT10"
3026 #define busnum_ODY_PCIERCX_MRG_LANE_CTL_STAT10(a) (a)
3027 #define arguments_ODY_PCIERCX_MRG_LANE_CTL_STAT10(a) (a), -1, -1, -1
3028
3029 /**
3030 * Register (PCICONFIGRC) pcierc#_mrg_lane_ctl_stat11
3031 *
3032 * PCIe RC Margining Lane Control and Status Register 11
3033 */
3034 union ody_pciercx_mrg_lane_ctl_stat11 {
3035 uint32_t u;
3036 struct ody_pciercx_mrg_lane_ctl_stat11_s {
3037 uint32_t rnum : 3;
3038 uint32_t mt : 3;
3039 uint32_t um : 1;
3040 uint32_t reserved_7 : 1;
3041 uint32_t mpl : 8;
3042 uint32_t rnum_stat : 3;
3043 uint32_t mt_stat : 3;
3044 uint32_t um_stat : 1;
3045 uint32_t reserved_23 : 1;
3046 uint32_t pl_stat : 8;
3047 } s;
3048 /* struct ody_pciercx_mrg_lane_ctl_stat11_s cn; */
3049 };
3050 typedef union ody_pciercx_mrg_lane_ctl_stat11 ody_pciercx_mrg_lane_ctl_stat11_t;
3051
3052 static inline uint64_t ODY_PCIERCX_MRG_LANE_CTL_STAT11(uint64_t a) __attribute__ ((pure, always_inline));
ODY_PCIERCX_MRG_LANE_CTL_STAT11(uint64_t a)3053 static inline uint64_t ODY_PCIERCX_MRG_LANE_CTL_STAT11(uint64_t a)
3054 {
3055 if (a <= 15)
3056 return 0x1fc;
3057 __ody_csr_fatal("PCIERCX_MRG_LANE_CTL_STAT11", 1, a, 0, 0, 0, 0, 0);
3058 }
3059
3060 #define typedef_ODY_PCIERCX_MRG_LANE_CTL_STAT11(a) ody_pciercx_mrg_lane_ctl_stat11_t
3061 #define bustype_ODY_PCIERCX_MRG_LANE_CTL_STAT11(a) CSR_TYPE_PCICONFIGRC
3062 #define basename_ODY_PCIERCX_MRG_LANE_CTL_STAT11(a) "PCIERCX_MRG_LANE_CTL_STAT11"
3063 #define busnum_ODY_PCIERCX_MRG_LANE_CTL_STAT11(a) (a)
3064 #define arguments_ODY_PCIERCX_MRG_LANE_CTL_STAT11(a) (a), -1, -1, -1
3065
3066 /**
3067 * Register (PCICONFIGRC) pcierc#_mrg_lane_ctl_stat12
3068 *
3069 * PCIe RC Margining Lane Control and Status Register 12
3070 */
3071 union ody_pciercx_mrg_lane_ctl_stat12 {
3072 uint32_t u;
3073 struct ody_pciercx_mrg_lane_ctl_stat12_s {
3074 uint32_t rnum : 3;
3075 uint32_t mt : 3;
3076 uint32_t um : 1;
3077 uint32_t reserved_7 : 1;
3078 uint32_t mpl : 8;
3079 uint32_t rnum_stat : 3;
3080 uint32_t mt_stat : 3;
3081 uint32_t um_stat : 1;
3082 uint32_t reserved_23 : 1;
3083 uint32_t pl_stat : 8;
3084 } s;
3085 /* struct ody_pciercx_mrg_lane_ctl_stat12_s cn; */
3086 };
3087 typedef union ody_pciercx_mrg_lane_ctl_stat12 ody_pciercx_mrg_lane_ctl_stat12_t;
3088
3089 static inline uint64_t ODY_PCIERCX_MRG_LANE_CTL_STAT12(uint64_t a) __attribute__ ((pure, always_inline));
ODY_PCIERCX_MRG_LANE_CTL_STAT12(uint64_t a)3090 static inline uint64_t ODY_PCIERCX_MRG_LANE_CTL_STAT12(uint64_t a)
3091 {
3092 if (a <= 15)
3093 return 0x200;
3094 __ody_csr_fatal("PCIERCX_MRG_LANE_CTL_STAT12", 1, a, 0, 0, 0, 0, 0);
3095 }
3096
3097 #define typedef_ODY_PCIERCX_MRG_LANE_CTL_STAT12(a) ody_pciercx_mrg_lane_ctl_stat12_t
3098 #define bustype_ODY_PCIERCX_MRG_LANE_CTL_STAT12(a) CSR_TYPE_PCICONFIGRC
3099 #define basename_ODY_PCIERCX_MRG_LANE_CTL_STAT12(a) "PCIERCX_MRG_LANE_CTL_STAT12"
3100 #define busnum_ODY_PCIERCX_MRG_LANE_CTL_STAT12(a) (a)
3101 #define arguments_ODY_PCIERCX_MRG_LANE_CTL_STAT12(a) (a), -1, -1, -1
3102
3103 /**
3104 * Register (PCICONFIGRC) pcierc#_mrg_lane_ctl_stat13
3105 *
3106 * PCIe RC Margining Lane Control and Status Register 13
3107 */
3108 union ody_pciercx_mrg_lane_ctl_stat13 {
3109 uint32_t u;
3110 struct ody_pciercx_mrg_lane_ctl_stat13_s {
3111 uint32_t rnum : 3;
3112 uint32_t mt : 3;
3113 uint32_t um : 1;
3114 uint32_t reserved_7 : 1;
3115 uint32_t mpl : 8;
3116 uint32_t rnum_stat : 3;
3117 uint32_t mt_stat : 3;
3118 uint32_t um_stat : 1;
3119 uint32_t reserved_23 : 1;
3120 uint32_t pl_stat : 8;
3121 } s;
3122 /* struct ody_pciercx_mrg_lane_ctl_stat13_s cn; */
3123 };
3124 typedef union ody_pciercx_mrg_lane_ctl_stat13 ody_pciercx_mrg_lane_ctl_stat13_t;
3125
3126 static inline uint64_t ODY_PCIERCX_MRG_LANE_CTL_STAT13(uint64_t a) __attribute__ ((pure, always_inline));
ODY_PCIERCX_MRG_LANE_CTL_STAT13(uint64_t a)3127 static inline uint64_t ODY_PCIERCX_MRG_LANE_CTL_STAT13(uint64_t a)
3128 {
3129 if (a <= 15)
3130 return 0x204;
3131 __ody_csr_fatal("PCIERCX_MRG_LANE_CTL_STAT13", 1, a, 0, 0, 0, 0, 0);
3132 }
3133
3134 #define typedef_ODY_PCIERCX_MRG_LANE_CTL_STAT13(a) ody_pciercx_mrg_lane_ctl_stat13_t
3135 #define bustype_ODY_PCIERCX_MRG_LANE_CTL_STAT13(a) CSR_TYPE_PCICONFIGRC
3136 #define basename_ODY_PCIERCX_MRG_LANE_CTL_STAT13(a) "PCIERCX_MRG_LANE_CTL_STAT13"
3137 #define busnum_ODY_PCIERCX_MRG_LANE_CTL_STAT13(a) (a)
3138 #define arguments_ODY_PCIERCX_MRG_LANE_CTL_STAT13(a) (a), -1, -1, -1
3139
3140 /**
3141 * Register (PCICONFIGRC) pcierc#_mrg_lane_ctl_stat14
3142 *
3143 * PCIe RC Margining Lane Control and Status Register 14
3144 */
3145 union ody_pciercx_mrg_lane_ctl_stat14 {
3146 uint32_t u;
3147 struct ody_pciercx_mrg_lane_ctl_stat14_s {
3148 uint32_t rnum : 3;
3149 uint32_t mt : 3;
3150 uint32_t um : 1;
3151 uint32_t reserved_7 : 1;
3152 uint32_t mpl : 8;
3153 uint32_t rnum_stat : 3;
3154 uint32_t mt_stat : 3;
3155 uint32_t um_stat : 1;
3156 uint32_t reserved_23 : 1;
3157 uint32_t pl_stat : 8;
3158 } s;
3159 /* struct ody_pciercx_mrg_lane_ctl_stat14_s cn; */
3160 };
3161 typedef union ody_pciercx_mrg_lane_ctl_stat14 ody_pciercx_mrg_lane_ctl_stat14_t;
3162
3163 static inline uint64_t ODY_PCIERCX_MRG_LANE_CTL_STAT14(uint64_t a) __attribute__ ((pure, always_inline));
ODY_PCIERCX_MRG_LANE_CTL_STAT14(uint64_t a)3164 static inline uint64_t ODY_PCIERCX_MRG_LANE_CTL_STAT14(uint64_t a)
3165 {
3166 if (a <= 15)
3167 return 0x208;
3168 __ody_csr_fatal("PCIERCX_MRG_LANE_CTL_STAT14", 1, a, 0, 0, 0, 0, 0);
3169 }
3170
3171 #define typedef_ODY_PCIERCX_MRG_LANE_CTL_STAT14(a) ody_pciercx_mrg_lane_ctl_stat14_t
3172 #define bustype_ODY_PCIERCX_MRG_LANE_CTL_STAT14(a) CSR_TYPE_PCICONFIGRC
3173 #define basename_ODY_PCIERCX_MRG_LANE_CTL_STAT14(a) "PCIERCX_MRG_LANE_CTL_STAT14"
3174 #define busnum_ODY_PCIERCX_MRG_LANE_CTL_STAT14(a) (a)
3175 #define arguments_ODY_PCIERCX_MRG_LANE_CTL_STAT14(a) (a), -1, -1, -1
3176
3177 /**
3178 * Register (PCICONFIGRC) pcierc#_mrg_lane_ctl_stat15
3179 *
3180 * PCIe RC Margining Lane Control and Status Register 15
3181 */
3182 union ody_pciercx_mrg_lane_ctl_stat15 {
3183 uint32_t u;
3184 struct ody_pciercx_mrg_lane_ctl_stat15_s {
3185 uint32_t rnum : 3;
3186 uint32_t mt : 3;
3187 uint32_t um : 1;
3188 uint32_t reserved_7 : 1;
3189 uint32_t mpl : 8;
3190 uint32_t rnum_stat : 3;
3191 uint32_t mt_stat : 3;
3192 uint32_t um_stat : 1;
3193 uint32_t reserved_23 : 1;
3194 uint32_t pl_stat : 8;
3195 } s;
3196 /* struct ody_pciercx_mrg_lane_ctl_stat15_s cn; */
3197 };
3198 typedef union ody_pciercx_mrg_lane_ctl_stat15 ody_pciercx_mrg_lane_ctl_stat15_t;
3199
3200 static inline uint64_t ODY_PCIERCX_MRG_LANE_CTL_STAT15(uint64_t a) __attribute__ ((pure, always_inline));
ODY_PCIERCX_MRG_LANE_CTL_STAT15(uint64_t a)3201 static inline uint64_t ODY_PCIERCX_MRG_LANE_CTL_STAT15(uint64_t a)
3202 {
3203 if (a <= 15)
3204 return 0x20c;
3205 __ody_csr_fatal("PCIERCX_MRG_LANE_CTL_STAT15", 1, a, 0, 0, 0, 0, 0);
3206 }
3207
3208 #define typedef_ODY_PCIERCX_MRG_LANE_CTL_STAT15(a) ody_pciercx_mrg_lane_ctl_stat15_t
3209 #define bustype_ODY_PCIERCX_MRG_LANE_CTL_STAT15(a) CSR_TYPE_PCICONFIGRC
3210 #define basename_ODY_PCIERCX_MRG_LANE_CTL_STAT15(a) "PCIERCX_MRG_LANE_CTL_STAT15"
3211 #define busnum_ODY_PCIERCX_MRG_LANE_CTL_STAT15(a) (a)
3212 #define arguments_ODY_PCIERCX_MRG_LANE_CTL_STAT15(a) (a), -1, -1, -1
3213
3214 /**
3215 * Register (PCICONFIGRC) pcierc#_mrg_lane_ctl_stat2
3216 *
3217 * PCIe RC Margining Lane Control and Status Register 2
3218 */
3219 union ody_pciercx_mrg_lane_ctl_stat2 {
3220 uint32_t u;
3221 struct ody_pciercx_mrg_lane_ctl_stat2_s {
3222 uint32_t rnum : 3;
3223 uint32_t mt : 3;
3224 uint32_t um : 1;
3225 uint32_t reserved_7 : 1;
3226 uint32_t mpl : 8;
3227 uint32_t rnum_stat : 3;
3228 uint32_t mt_stat : 3;
3229 uint32_t um_stat : 1;
3230 uint32_t reserved_23 : 1;
3231 uint32_t pl_stat : 8;
3232 } s;
3233 /* struct ody_pciercx_mrg_lane_ctl_stat2_s cn; */
3234 };
3235 typedef union ody_pciercx_mrg_lane_ctl_stat2 ody_pciercx_mrg_lane_ctl_stat2_t;
3236
3237 static inline uint64_t ODY_PCIERCX_MRG_LANE_CTL_STAT2(uint64_t a) __attribute__ ((pure, always_inline));
ODY_PCIERCX_MRG_LANE_CTL_STAT2(uint64_t a)3238 static inline uint64_t ODY_PCIERCX_MRG_LANE_CTL_STAT2(uint64_t a)
3239 {
3240 if (a <= 15)
3241 return 0x1d8;
3242 __ody_csr_fatal("PCIERCX_MRG_LANE_CTL_STAT2", 1, a, 0, 0, 0, 0, 0);
3243 }
3244
3245 #define typedef_ODY_PCIERCX_MRG_LANE_CTL_STAT2(a) ody_pciercx_mrg_lane_ctl_stat2_t
3246 #define bustype_ODY_PCIERCX_MRG_LANE_CTL_STAT2(a) CSR_TYPE_PCICONFIGRC
3247 #define basename_ODY_PCIERCX_MRG_LANE_CTL_STAT2(a) "PCIERCX_MRG_LANE_CTL_STAT2"
3248 #define busnum_ODY_PCIERCX_MRG_LANE_CTL_STAT2(a) (a)
3249 #define arguments_ODY_PCIERCX_MRG_LANE_CTL_STAT2(a) (a), -1, -1, -1
3250
3251 /**
3252 * Register (PCICONFIGRC) pcierc#_mrg_lane_ctl_stat3
3253 *
3254 * PCIe RC Margining Lane Control and Status Register 3
3255 */
3256 union ody_pciercx_mrg_lane_ctl_stat3 {
3257 uint32_t u;
3258 struct ody_pciercx_mrg_lane_ctl_stat3_s {
3259 uint32_t rnum : 3;
3260 uint32_t mt : 3;
3261 uint32_t um : 1;
3262 uint32_t reserved_7 : 1;
3263 uint32_t mpl : 8;
3264 uint32_t rnum_stat : 3;
3265 uint32_t mt_stat : 3;
3266 uint32_t um_stat : 1;
3267 uint32_t reserved_23 : 1;
3268 uint32_t pl_stat : 8;
3269 } s;
3270 /* struct ody_pciercx_mrg_lane_ctl_stat3_s cn; */
3271 };
3272 typedef union ody_pciercx_mrg_lane_ctl_stat3 ody_pciercx_mrg_lane_ctl_stat3_t;
3273
3274 static inline uint64_t ODY_PCIERCX_MRG_LANE_CTL_STAT3(uint64_t a) __attribute__ ((pure, always_inline));
ODY_PCIERCX_MRG_LANE_CTL_STAT3(uint64_t a)3275 static inline uint64_t ODY_PCIERCX_MRG_LANE_CTL_STAT3(uint64_t a)
3276 {
3277 if (a <= 15)
3278 return 0x1dc;
3279 __ody_csr_fatal("PCIERCX_MRG_LANE_CTL_STAT3", 1, a, 0, 0, 0, 0, 0);
3280 }
3281
3282 #define typedef_ODY_PCIERCX_MRG_LANE_CTL_STAT3(a) ody_pciercx_mrg_lane_ctl_stat3_t
3283 #define bustype_ODY_PCIERCX_MRG_LANE_CTL_STAT3(a) CSR_TYPE_PCICONFIGRC
3284 #define basename_ODY_PCIERCX_MRG_LANE_CTL_STAT3(a) "PCIERCX_MRG_LANE_CTL_STAT3"
3285 #define busnum_ODY_PCIERCX_MRG_LANE_CTL_STAT3(a) (a)
3286 #define arguments_ODY_PCIERCX_MRG_LANE_CTL_STAT3(a) (a), -1, -1, -1
3287
3288 /**
3289 * Register (PCICONFIGRC) pcierc#_mrg_lane_ctl_stat4
3290 *
3291 * PCIe RC Margining Lane Control and Status Register 4
3292 */
3293 union ody_pciercx_mrg_lane_ctl_stat4 {
3294 uint32_t u;
3295 struct ody_pciercx_mrg_lane_ctl_stat4_s {
3296 uint32_t rnum : 3;
3297 uint32_t mt : 3;
3298 uint32_t um : 1;
3299 uint32_t reserved_7 : 1;
3300 uint32_t mpl : 8;
3301 uint32_t rnum_stat : 3;
3302 uint32_t mt_stat : 3;
3303 uint32_t um_stat : 1;
3304 uint32_t reserved_23 : 1;
3305 uint32_t pl_stat : 8;
3306 } s;
3307 /* struct ody_pciercx_mrg_lane_ctl_stat4_s cn; */
3308 };
3309 typedef union ody_pciercx_mrg_lane_ctl_stat4 ody_pciercx_mrg_lane_ctl_stat4_t;
3310
3311 static inline uint64_t ODY_PCIERCX_MRG_LANE_CTL_STAT4(uint64_t a) __attribute__ ((pure, always_inline));
ODY_PCIERCX_MRG_LANE_CTL_STAT4(uint64_t a)3312 static inline uint64_t ODY_PCIERCX_MRG_LANE_CTL_STAT4(uint64_t a)
3313 {
3314 if (a <= 15)
3315 return 0x1e0;
3316 __ody_csr_fatal("PCIERCX_MRG_LANE_CTL_STAT4", 1, a, 0, 0, 0, 0, 0);
3317 }
3318
3319 #define typedef_ODY_PCIERCX_MRG_LANE_CTL_STAT4(a) ody_pciercx_mrg_lane_ctl_stat4_t
3320 #define bustype_ODY_PCIERCX_MRG_LANE_CTL_STAT4(a) CSR_TYPE_PCICONFIGRC
3321 #define basename_ODY_PCIERCX_MRG_LANE_CTL_STAT4(a) "PCIERCX_MRG_LANE_CTL_STAT4"
3322 #define busnum_ODY_PCIERCX_MRG_LANE_CTL_STAT4(a) (a)
3323 #define arguments_ODY_PCIERCX_MRG_LANE_CTL_STAT4(a) (a), -1, -1, -1
3324
3325 /**
3326 * Register (PCICONFIGRC) pcierc#_mrg_lane_ctl_stat5
3327 *
3328 * PCIe RC Margining Lane Control and Status Register 5
3329 */
3330 union ody_pciercx_mrg_lane_ctl_stat5 {
3331 uint32_t u;
3332 struct ody_pciercx_mrg_lane_ctl_stat5_s {
3333 uint32_t rnum : 3;
3334 uint32_t mt : 3;
3335 uint32_t um : 1;
3336 uint32_t reserved_7 : 1;
3337 uint32_t mpl : 8;
3338 uint32_t rnum_stat : 3;
3339 uint32_t mt_stat : 3;
3340 uint32_t um_stat : 1;
3341 uint32_t reserved_23 : 1;
3342 uint32_t pl_stat : 8;
3343 } s;
3344 /* struct ody_pciercx_mrg_lane_ctl_stat5_s cn; */
3345 };
3346 typedef union ody_pciercx_mrg_lane_ctl_stat5 ody_pciercx_mrg_lane_ctl_stat5_t;
3347
3348 static inline uint64_t ODY_PCIERCX_MRG_LANE_CTL_STAT5(uint64_t a) __attribute__ ((pure, always_inline));
ODY_PCIERCX_MRG_LANE_CTL_STAT5(uint64_t a)3349 static inline uint64_t ODY_PCIERCX_MRG_LANE_CTL_STAT5(uint64_t a)
3350 {
3351 if (a <= 15)
3352 return 0x1e4;
3353 __ody_csr_fatal("PCIERCX_MRG_LANE_CTL_STAT5", 1, a, 0, 0, 0, 0, 0);
3354 }
3355
3356 #define typedef_ODY_PCIERCX_MRG_LANE_CTL_STAT5(a) ody_pciercx_mrg_lane_ctl_stat5_t
3357 #define bustype_ODY_PCIERCX_MRG_LANE_CTL_STAT5(a) CSR_TYPE_PCICONFIGRC
3358 #define basename_ODY_PCIERCX_MRG_LANE_CTL_STAT5(a) "PCIERCX_MRG_LANE_CTL_STAT5"
3359 #define busnum_ODY_PCIERCX_MRG_LANE_CTL_STAT5(a) (a)
3360 #define arguments_ODY_PCIERCX_MRG_LANE_CTL_STAT5(a) (a), -1, -1, -1
3361
3362 /**
3363 * Register (PCICONFIGRC) pcierc#_mrg_lane_ctl_stat6
3364 *
3365 * PCIe RC Margining Lane Control and Status Register 6
3366 */
3367 union ody_pciercx_mrg_lane_ctl_stat6 {
3368 uint32_t u;
3369 struct ody_pciercx_mrg_lane_ctl_stat6_s {
3370 uint32_t rnum : 3;
3371 uint32_t mt : 3;
3372 uint32_t um : 1;
3373 uint32_t reserved_7 : 1;
3374 uint32_t mpl : 8;
3375 uint32_t rnum_stat : 3;
3376 uint32_t mt_stat : 3;
3377 uint32_t um_stat : 1;
3378 uint32_t reserved_23 : 1;
3379 uint32_t pl_stat : 8;
3380 } s;
3381 /* struct ody_pciercx_mrg_lane_ctl_stat6_s cn; */
3382 };
3383 typedef union ody_pciercx_mrg_lane_ctl_stat6 ody_pciercx_mrg_lane_ctl_stat6_t;
3384
3385 static inline uint64_t ODY_PCIERCX_MRG_LANE_CTL_STAT6(uint64_t a) __attribute__ ((pure, always_inline));
ODY_PCIERCX_MRG_LANE_CTL_STAT6(uint64_t a)3386 static inline uint64_t ODY_PCIERCX_MRG_LANE_CTL_STAT6(uint64_t a)
3387 {
3388 if (a <= 15)
3389 return 0x1e8;
3390 __ody_csr_fatal("PCIERCX_MRG_LANE_CTL_STAT6", 1, a, 0, 0, 0, 0, 0);
3391 }
3392
3393 #define typedef_ODY_PCIERCX_MRG_LANE_CTL_STAT6(a) ody_pciercx_mrg_lane_ctl_stat6_t
3394 #define bustype_ODY_PCIERCX_MRG_LANE_CTL_STAT6(a) CSR_TYPE_PCICONFIGRC
3395 #define basename_ODY_PCIERCX_MRG_LANE_CTL_STAT6(a) "PCIERCX_MRG_LANE_CTL_STAT6"
3396 #define busnum_ODY_PCIERCX_MRG_LANE_CTL_STAT6(a) (a)
3397 #define arguments_ODY_PCIERCX_MRG_LANE_CTL_STAT6(a) (a), -1, -1, -1
3398
3399 /**
3400 * Register (PCICONFIGRC) pcierc#_mrg_lane_ctl_stat7
3401 *
3402 * PCIe RC Margining Lane Control and Status Register 7
3403 */
3404 union ody_pciercx_mrg_lane_ctl_stat7 {
3405 uint32_t u;
3406 struct ody_pciercx_mrg_lane_ctl_stat7_s {
3407 uint32_t rnum : 3;
3408 uint32_t mt : 3;
3409 uint32_t um : 1;
3410 uint32_t reserved_7 : 1;
3411 uint32_t mpl : 8;
3412 uint32_t rnum_stat : 3;
3413 uint32_t mt_stat : 3;
3414 uint32_t um_stat : 1;
3415 uint32_t reserved_23 : 1;
3416 uint32_t pl_stat : 8;
3417 } s;
3418 /* struct ody_pciercx_mrg_lane_ctl_stat7_s cn; */
3419 };
3420 typedef union ody_pciercx_mrg_lane_ctl_stat7 ody_pciercx_mrg_lane_ctl_stat7_t;
3421
3422 static inline uint64_t ODY_PCIERCX_MRG_LANE_CTL_STAT7(uint64_t a) __attribute__ ((pure, always_inline));
ODY_PCIERCX_MRG_LANE_CTL_STAT7(uint64_t a)3423 static inline uint64_t ODY_PCIERCX_MRG_LANE_CTL_STAT7(uint64_t a)
3424 {
3425 if (a <= 15)
3426 return 0x1ec;
3427 __ody_csr_fatal("PCIERCX_MRG_LANE_CTL_STAT7", 1, a, 0, 0, 0, 0, 0);
3428 }
3429
3430 #define typedef_ODY_PCIERCX_MRG_LANE_CTL_STAT7(a) ody_pciercx_mrg_lane_ctl_stat7_t
3431 #define bustype_ODY_PCIERCX_MRG_LANE_CTL_STAT7(a) CSR_TYPE_PCICONFIGRC
3432 #define basename_ODY_PCIERCX_MRG_LANE_CTL_STAT7(a) "PCIERCX_MRG_LANE_CTL_STAT7"
3433 #define busnum_ODY_PCIERCX_MRG_LANE_CTL_STAT7(a) (a)
3434 #define arguments_ODY_PCIERCX_MRG_LANE_CTL_STAT7(a) (a), -1, -1, -1
3435
3436 /**
3437 * Register (PCICONFIGRC) pcierc#_mrg_lane_ctl_stat8
3438 *
3439 * PCIe RC Margining Lane Control and Status Register 8
3440 */
3441 union ody_pciercx_mrg_lane_ctl_stat8 {
3442 uint32_t u;
3443 struct ody_pciercx_mrg_lane_ctl_stat8_s {
3444 uint32_t rnum : 3;
3445 uint32_t mt : 3;
3446 uint32_t um : 1;
3447 uint32_t reserved_7 : 1;
3448 uint32_t mpl : 8;
3449 uint32_t rnum_stat : 3;
3450 uint32_t mt_stat : 3;
3451 uint32_t um_stat : 1;
3452 uint32_t reserved_23 : 1;
3453 uint32_t pl_stat : 8;
3454 } s;
3455 /* struct ody_pciercx_mrg_lane_ctl_stat8_s cn; */
3456 };
3457 typedef union ody_pciercx_mrg_lane_ctl_stat8 ody_pciercx_mrg_lane_ctl_stat8_t;
3458
3459 static inline uint64_t ODY_PCIERCX_MRG_LANE_CTL_STAT8(uint64_t a) __attribute__ ((pure, always_inline));
ODY_PCIERCX_MRG_LANE_CTL_STAT8(uint64_t a)3460 static inline uint64_t ODY_PCIERCX_MRG_LANE_CTL_STAT8(uint64_t a)
3461 {
3462 if (a <= 15)
3463 return 0x1f0;
3464 __ody_csr_fatal("PCIERCX_MRG_LANE_CTL_STAT8", 1, a, 0, 0, 0, 0, 0);
3465 }
3466
3467 #define typedef_ODY_PCIERCX_MRG_LANE_CTL_STAT8(a) ody_pciercx_mrg_lane_ctl_stat8_t
3468 #define bustype_ODY_PCIERCX_MRG_LANE_CTL_STAT8(a) CSR_TYPE_PCICONFIGRC
3469 #define basename_ODY_PCIERCX_MRG_LANE_CTL_STAT8(a) "PCIERCX_MRG_LANE_CTL_STAT8"
3470 #define busnum_ODY_PCIERCX_MRG_LANE_CTL_STAT8(a) (a)
3471 #define arguments_ODY_PCIERCX_MRG_LANE_CTL_STAT8(a) (a), -1, -1, -1
3472
3473 /**
3474 * Register (PCICONFIGRC) pcierc#_mrg_lane_ctl_stat9
3475 *
3476 * PCIe RC Margining Lane Control and Status Register 9
3477 */
3478 union ody_pciercx_mrg_lane_ctl_stat9 {
3479 uint32_t u;
3480 struct ody_pciercx_mrg_lane_ctl_stat9_s {
3481 uint32_t rnum : 3;
3482 uint32_t mt : 3;
3483 uint32_t um : 1;
3484 uint32_t reserved_7 : 1;
3485 uint32_t mpl : 8;
3486 uint32_t rnum_stat : 3;
3487 uint32_t mt_stat : 3;
3488 uint32_t um_stat : 1;
3489 uint32_t reserved_23 : 1;
3490 uint32_t pl_stat : 8;
3491 } s;
3492 /* struct ody_pciercx_mrg_lane_ctl_stat9_s cn; */
3493 };
3494 typedef union ody_pciercx_mrg_lane_ctl_stat9 ody_pciercx_mrg_lane_ctl_stat9_t;
3495
3496 static inline uint64_t ODY_PCIERCX_MRG_LANE_CTL_STAT9(uint64_t a) __attribute__ ((pure, always_inline));
ODY_PCIERCX_MRG_LANE_CTL_STAT9(uint64_t a)3497 static inline uint64_t ODY_PCIERCX_MRG_LANE_CTL_STAT9(uint64_t a)
3498 {
3499 if (a <= 15)
3500 return 0x1f4;
3501 __ody_csr_fatal("PCIERCX_MRG_LANE_CTL_STAT9", 1, a, 0, 0, 0, 0, 0);
3502 }
3503
3504 #define typedef_ODY_PCIERCX_MRG_LANE_CTL_STAT9(a) ody_pciercx_mrg_lane_ctl_stat9_t
3505 #define bustype_ODY_PCIERCX_MRG_LANE_CTL_STAT9(a) CSR_TYPE_PCICONFIGRC
3506 #define basename_ODY_PCIERCX_MRG_LANE_CTL_STAT9(a) "PCIERCX_MRG_LANE_CTL_STAT9"
3507 #define busnum_ODY_PCIERCX_MRG_LANE_CTL_STAT9(a) (a)
3508 #define arguments_ODY_PCIERCX_MRG_LANE_CTL_STAT9(a) (a), -1, -1, -1
3509
3510 /**
3511 * Register (PCICONFIGRC) pcierc#_mrg_port_cap_stat
3512 *
3513 * PCIe RC Margining Port Capabilities and Status Register
3514 */
3515 union ody_pciercx_mrg_port_cap_stat {
3516 uint32_t u;
3517 struct ody_pciercx_mrg_port_cap_stat_s {
3518 uint32_t m_drv : 1;
3519 uint32_t reserved_1_15 : 15;
3520 uint32_t m_rdy : 1;
3521 uint32_t m_swrdy : 1;
3522 uint32_t reserved_18_31 : 14;
3523 } s;
3524 /* struct ody_pciercx_mrg_port_cap_stat_s cn; */
3525 };
3526 typedef union ody_pciercx_mrg_port_cap_stat ody_pciercx_mrg_port_cap_stat_t;
3527
3528 static inline uint64_t ODY_PCIERCX_MRG_PORT_CAP_STAT(uint64_t a) __attribute__ ((pure, always_inline));
ODY_PCIERCX_MRG_PORT_CAP_STAT(uint64_t a)3529 static inline uint64_t ODY_PCIERCX_MRG_PORT_CAP_STAT(uint64_t a)
3530 {
3531 if (a <= 15)
3532 return 0x1cc;
3533 __ody_csr_fatal("PCIERCX_MRG_PORT_CAP_STAT", 1, a, 0, 0, 0, 0, 0);
3534 }
3535
3536 #define typedef_ODY_PCIERCX_MRG_PORT_CAP_STAT(a) ody_pciercx_mrg_port_cap_stat_t
3537 #define bustype_ODY_PCIERCX_MRG_PORT_CAP_STAT(a) CSR_TYPE_PCICONFIGRC
3538 #define basename_ODY_PCIERCX_MRG_PORT_CAP_STAT(a) "PCIERCX_MRG_PORT_CAP_STAT"
3539 #define busnum_ODY_PCIERCX_MRG_PORT_CAP_STAT(a) (a)
3540 #define arguments_ODY_PCIERCX_MRG_PORT_CAP_STAT(a) (a), -1, -1, -1
3541
3542 /**
3543 * Register (PCICONFIGRC) pcierc#_msix_cap_cntrl
3544 *
3545 * PCIe RC PCI Express MSI-X Capability ID/MSI-X Next Item Pointer/MSI-X Control Register
3546 */
3547 union ody_pciercx_msix_cap_cntrl {
3548 uint32_t u;
3549 struct ody_pciercx_msix_cap_cntrl_s {
3550 uint32_t msixcid : 8;
3551 uint32_t ncp : 8;
3552 uint32_t msixts : 11;
3553 uint32_t reserved_27_29 : 3;
3554 uint32_t funm : 1;
3555 uint32_t msixen : 1;
3556 } s;
3557 /* struct ody_pciercx_msix_cap_cntrl_s cn; */
3558 };
3559 typedef union ody_pciercx_msix_cap_cntrl ody_pciercx_msix_cap_cntrl_t;
3560
3561 static inline uint64_t ODY_PCIERCX_MSIX_CAP_CNTRL(uint64_t a) __attribute__ ((pure, always_inline));
ODY_PCIERCX_MSIX_CAP_CNTRL(uint64_t a)3562 static inline uint64_t ODY_PCIERCX_MSIX_CAP_CNTRL(uint64_t a)
3563 {
3564 if (a <= 15)
3565 return 0xb0;
3566 __ody_csr_fatal("PCIERCX_MSIX_CAP_CNTRL", 1, a, 0, 0, 0, 0, 0);
3567 }
3568
3569 #define typedef_ODY_PCIERCX_MSIX_CAP_CNTRL(a) ody_pciercx_msix_cap_cntrl_t
3570 #define bustype_ODY_PCIERCX_MSIX_CAP_CNTRL(a) CSR_TYPE_PCICONFIGRC
3571 #define basename_ODY_PCIERCX_MSIX_CAP_CNTRL(a) "PCIERCX_MSIX_CAP_CNTRL"
3572 #define busnum_ODY_PCIERCX_MSIX_CAP_CNTRL(a) (a)
3573 #define arguments_ODY_PCIERCX_MSIX_CAP_CNTRL(a) (a), -1, -1, -1
3574
3575 /**
3576 * Register (PCICONFIGRC) pcierc#_msix_pba
3577 *
3578 * PCIe RC PCI Express MSI-X PBA Offset and BIR Register
3579 */
3580 union ody_pciercx_msix_pba {
3581 uint32_t u;
3582 struct ody_pciercx_msix_pba_s {
3583 uint32_t msixpbir : 3;
3584 uint32_t msixpoffs : 29;
3585 } s;
3586 /* struct ody_pciercx_msix_pba_s cn; */
3587 };
3588 typedef union ody_pciercx_msix_pba ody_pciercx_msix_pba_t;
3589
3590 static inline uint64_t ODY_PCIERCX_MSIX_PBA(uint64_t a) __attribute__ ((pure, always_inline));
ODY_PCIERCX_MSIX_PBA(uint64_t a)3591 static inline uint64_t ODY_PCIERCX_MSIX_PBA(uint64_t a)
3592 {
3593 if (a <= 15)
3594 return 0xb8;
3595 __ody_csr_fatal("PCIERCX_MSIX_PBA", 1, a, 0, 0, 0, 0, 0);
3596 }
3597
3598 #define typedef_ODY_PCIERCX_MSIX_PBA(a) ody_pciercx_msix_pba_t
3599 #define bustype_ODY_PCIERCX_MSIX_PBA(a) CSR_TYPE_PCICONFIGRC
3600 #define basename_ODY_PCIERCX_MSIX_PBA(a) "PCIERCX_MSIX_PBA"
3601 #define busnum_ODY_PCIERCX_MSIX_PBA(a) (a)
3602 #define arguments_ODY_PCIERCX_MSIX_PBA(a) (a), -1, -1, -1
3603
3604 /**
3605 * Register (PCICONFIGRC) pcierc#_msix_table
3606 *
3607 * PCIe RC PCI Express MSI-X Table Offset and BIR Register
3608 */
3609 union ody_pciercx_msix_table {
3610 uint32_t u;
3611 struct ody_pciercx_msix_table_s {
3612 uint32_t msixtbir : 3;
3613 uint32_t msixtoffs : 29;
3614 } s;
3615 /* struct ody_pciercx_msix_table_s cn; */
3616 };
3617 typedef union ody_pciercx_msix_table ody_pciercx_msix_table_t;
3618
3619 static inline uint64_t ODY_PCIERCX_MSIX_TABLE(uint64_t a) __attribute__ ((pure, always_inline));
ODY_PCIERCX_MSIX_TABLE(uint64_t a)3620 static inline uint64_t ODY_PCIERCX_MSIX_TABLE(uint64_t a)
3621 {
3622 if (a <= 15)
3623 return 0xb4;
3624 __ody_csr_fatal("PCIERCX_MSIX_TABLE", 1, a, 0, 0, 0, 0, 0);
3625 }
3626
3627 #define typedef_ODY_PCIERCX_MSIX_TABLE(a) ody_pciercx_msix_table_t
3628 #define bustype_ODY_PCIERCX_MSIX_TABLE(a) CSR_TYPE_PCICONFIGRC
3629 #define basename_ODY_PCIERCX_MSIX_TABLE(a) "PCIERCX_MSIX_TABLE"
3630 #define busnum_ODY_PCIERCX_MSIX_TABLE(a) (a)
3631 #define arguments_ODY_PCIERCX_MSIX_TABLE(a) (a), -1, -1, -1
3632
3633 /**
3634 * Register (PCICONFIGRC) pcierc#_np_rcv_credit
3635 *
3636 * PCIe RC VC0 Nonposted Receive Queue Control Register
3637 */
3638 union ody_pciercx_np_rcv_credit {
3639 uint32_t u;
3640 struct ody_pciercx_np_rcv_credit_s {
3641 uint32_t data_credits : 12;
3642 uint32_t header_credits : 8;
3643 uint32_t reserved_20 : 1;
3644 uint32_t queue_mode : 3;
3645 uint32_t hdr_sc : 2;
3646 uint32_t data_sc : 2;
3647 uint32_t reserved_28_31 : 4;
3648 } s;
3649 /* struct ody_pciercx_np_rcv_credit_s cn; */
3650 };
3651 typedef union ody_pciercx_np_rcv_credit ody_pciercx_np_rcv_credit_t;
3652
3653 static inline uint64_t ODY_PCIERCX_NP_RCV_CREDIT(uint64_t a) __attribute__ ((pure, always_inline));
ODY_PCIERCX_NP_RCV_CREDIT(uint64_t a)3654 static inline uint64_t ODY_PCIERCX_NP_RCV_CREDIT(uint64_t a)
3655 {
3656 if (a <= 15)
3657 return 0x74c;
3658 __ody_csr_fatal("PCIERCX_NP_RCV_CREDIT", 1, a, 0, 0, 0, 0, 0);
3659 }
3660
3661 #define typedef_ODY_PCIERCX_NP_RCV_CREDIT(a) ody_pciercx_np_rcv_credit_t
3662 #define bustype_ODY_PCIERCX_NP_RCV_CREDIT(a) CSR_TYPE_PCICONFIGRC
3663 #define basename_ODY_PCIERCX_NP_RCV_CREDIT(a) "PCIERCX_NP_RCV_CREDIT"
3664 #define busnum_ODY_PCIERCX_NP_RCV_CREDIT(a) (a)
3665 #define arguments_ODY_PCIERCX_NP_RCV_CREDIT(a) (a), -1, -1, -1
3666
3667 /**
3668 * Register (PCICONFIGRC) pcierc#_np_xmit_credit
3669 *
3670 * PCIe RC Transmit Nonposted FC Credit Status Register
3671 */
3672 union ody_pciercx_np_xmit_credit {
3673 uint32_t u;
3674 struct ody_pciercx_np_xmit_credit_s {
3675 uint32_t tcdfcc : 16;
3676 uint32_t tchfcc : 12;
3677 uint32_t reserved_28_31 : 4;
3678 } s;
3679 /* struct ody_pciercx_np_xmit_credit_s cn; */
3680 };
3681 typedef union ody_pciercx_np_xmit_credit ody_pciercx_np_xmit_credit_t;
3682
3683 static inline uint64_t ODY_PCIERCX_NP_XMIT_CREDIT(uint64_t a) __attribute__ ((pure, always_inline));
ODY_PCIERCX_NP_XMIT_CREDIT(uint64_t a)3684 static inline uint64_t ODY_PCIERCX_NP_XMIT_CREDIT(uint64_t a)
3685 {
3686 if (a <= 15)
3687 return 0x734;
3688 __ody_csr_fatal("PCIERCX_NP_XMIT_CREDIT", 1, a, 0, 0, 0, 0, 0);
3689 }
3690
3691 #define typedef_ODY_PCIERCX_NP_XMIT_CREDIT(a) ody_pciercx_np_xmit_credit_t
3692 #define bustype_ODY_PCIERCX_NP_XMIT_CREDIT(a) CSR_TYPE_PCICONFIGRC
3693 #define basename_ODY_PCIERCX_NP_XMIT_CREDIT(a) "PCIERCX_NP_XMIT_CREDIT"
3694 #define busnum_ODY_PCIERCX_NP_XMIT_CREDIT(a) (a)
3695 #define arguments_ODY_PCIERCX_NP_XMIT_CREDIT(a) (a), -1, -1, -1
3696
3697 /**
3698 * Register (PCICONFIGRC) pcierc#_omsg_ptr
3699 *
3700 * PCIe RC Other Message Register
3701 */
3702 union ody_pciercx_omsg_ptr {
3703 uint32_t u;
3704 struct ody_pciercx_omsg_ptr_s {
3705 uint32_t omr : 32;
3706 } s;
3707 /* struct ody_pciercx_omsg_ptr_s cn; */
3708 };
3709 typedef union ody_pciercx_omsg_ptr ody_pciercx_omsg_ptr_t;
3710
3711 static inline uint64_t ODY_PCIERCX_OMSG_PTR(uint64_t a) __attribute__ ((pure, always_inline));
ODY_PCIERCX_OMSG_PTR(uint64_t a)3712 static inline uint64_t ODY_PCIERCX_OMSG_PTR(uint64_t a)
3713 {
3714 if (a <= 15)
3715 return 0x704;
3716 __ody_csr_fatal("PCIERCX_OMSG_PTR", 1, a, 0, 0, 0, 0, 0);
3717 }
3718
3719 #define typedef_ODY_PCIERCX_OMSG_PTR(a) ody_pciercx_omsg_ptr_t
3720 #define bustype_ODY_PCIERCX_OMSG_PTR(a) CSR_TYPE_PCICONFIGRC
3721 #define basename_ODY_PCIERCX_OMSG_PTR(a) "PCIERCX_OMSG_PTR"
3722 #define busnum_ODY_PCIERCX_OMSG_PTR(a) (a)
3723 #define arguments_ODY_PCIERCX_OMSG_PTR(a) (a), -1, -1, -1
3724
3725 /**
3726 * Register (PCICONFIGRC) pcierc#_ord_rule_ctrl
3727 *
3728 * PCIe RC Order Rule Control Register
3729 */
3730 union ody_pciercx_ord_rule_ctrl {
3731 uint32_t u;
3732 struct ody_pciercx_ord_rule_ctrl_s {
3733 uint32_t np_pass_p : 8;
3734 uint32_t cpl_pass_p : 8;
3735 uint32_t reserved_16_31 : 16;
3736 } s;
3737 /* struct ody_pciercx_ord_rule_ctrl_s cn; */
3738 };
3739 typedef union ody_pciercx_ord_rule_ctrl ody_pciercx_ord_rule_ctrl_t;
3740
3741 static inline uint64_t ODY_PCIERCX_ORD_RULE_CTRL(uint64_t a) __attribute__ ((pure, always_inline));
ODY_PCIERCX_ORD_RULE_CTRL(uint64_t a)3742 static inline uint64_t ODY_PCIERCX_ORD_RULE_CTRL(uint64_t a)
3743 {
3744 if (a <= 15)
3745 return 0x8b4;
3746 __ody_csr_fatal("PCIERCX_ORD_RULE_CTRL", 1, a, 0, 0, 0, 0, 0);
3747 }
3748
3749 #define typedef_ODY_PCIERCX_ORD_RULE_CTRL(a) ody_pciercx_ord_rule_ctrl_t
3750 #define bustype_ODY_PCIERCX_ORD_RULE_CTRL(a) CSR_TYPE_PCICONFIGRC
3751 #define basename_ODY_PCIERCX_ORD_RULE_CTRL(a) "PCIERCX_ORD_RULE_CTRL"
3752 #define busnum_ODY_PCIERCX_ORD_RULE_CTRL(a) (a)
3753 #define arguments_ODY_PCIERCX_ORD_RULE_CTRL(a) (a), -1, -1, -1
3754
3755 /**
3756 * Register (PCICONFIGRC) pcierc#_p_rcv_credit
3757 *
3758 * PCIe RC VC0 Posted Receive Queue Control Register
3759 */
3760 union ody_pciercx_p_rcv_credit {
3761 uint32_t u;
3762 struct ody_pciercx_p_rcv_credit_s {
3763 uint32_t data_credits : 12;
3764 uint32_t header_credits : 8;
3765 uint32_t reserved_20 : 1;
3766 uint32_t queue_mode : 3;
3767 uint32_t hdr_sc : 2;
3768 uint32_t data_sc : 2;
3769 uint32_t reserved_28_29 : 2;
3770 uint32_t type_ordering : 1;
3771 uint32_t rx_queue_order : 1;
3772 } s;
3773 /* struct ody_pciercx_p_rcv_credit_s cn; */
3774 };
3775 typedef union ody_pciercx_p_rcv_credit ody_pciercx_p_rcv_credit_t;
3776
3777 static inline uint64_t ODY_PCIERCX_P_RCV_CREDIT(uint64_t a) __attribute__ ((pure, always_inline));
ODY_PCIERCX_P_RCV_CREDIT(uint64_t a)3778 static inline uint64_t ODY_PCIERCX_P_RCV_CREDIT(uint64_t a)
3779 {
3780 if (a <= 15)
3781 return 0x748;
3782 __ody_csr_fatal("PCIERCX_P_RCV_CREDIT", 1, a, 0, 0, 0, 0, 0);
3783 }
3784
3785 #define typedef_ODY_PCIERCX_P_RCV_CREDIT(a) ody_pciercx_p_rcv_credit_t
3786 #define bustype_ODY_PCIERCX_P_RCV_CREDIT(a) CSR_TYPE_PCICONFIGRC
3787 #define basename_ODY_PCIERCX_P_RCV_CREDIT(a) "PCIERCX_P_RCV_CREDIT"
3788 #define busnum_ODY_PCIERCX_P_RCV_CREDIT(a) (a)
3789 #define arguments_ODY_PCIERCX_P_RCV_CREDIT(a) (a), -1, -1, -1
3790
3791 /**
3792 * Register (PCICONFIGRC) pcierc#_p_xmit_credit
3793 *
3794 * PCIe RC Transmit Posted FC Credit Status Register
3795 */
3796 union ody_pciercx_p_xmit_credit {
3797 uint32_t u;
3798 struct ody_pciercx_p_xmit_credit_s {
3799 uint32_t tpdfcc : 16;
3800 uint32_t tphfcc : 12;
3801 uint32_t reserved_28_31 : 4;
3802 } s;
3803 /* struct ody_pciercx_p_xmit_credit_s cn; */
3804 };
3805 typedef union ody_pciercx_p_xmit_credit ody_pciercx_p_xmit_credit_t;
3806
3807 static inline uint64_t ODY_PCIERCX_P_XMIT_CREDIT(uint64_t a) __attribute__ ((pure, always_inline));
ODY_PCIERCX_P_XMIT_CREDIT(uint64_t a)3808 static inline uint64_t ODY_PCIERCX_P_XMIT_CREDIT(uint64_t a)
3809 {
3810 if (a <= 15)
3811 return 0x730;
3812 __ody_csr_fatal("PCIERCX_P_XMIT_CREDIT", 1, a, 0, 0, 0, 0, 0);
3813 }
3814
3815 #define typedef_ODY_PCIERCX_P_XMIT_CREDIT(a) ody_pciercx_p_xmit_credit_t
3816 #define bustype_ODY_PCIERCX_P_XMIT_CREDIT(a) CSR_TYPE_PCICONFIGRC
3817 #define basename_ODY_PCIERCX_P_XMIT_CREDIT(a) "PCIERCX_P_XMIT_CREDIT"
3818 #define busnum_ODY_PCIERCX_P_XMIT_CREDIT(a) (a)
3819 #define arguments_ODY_PCIERCX_P_XMIT_CREDIT(a) (a), -1, -1, -1
3820
3821 /**
3822 * Register (PCICONFIGRC) pcierc#_pb_base
3823 *
3824 * PCIe RC Power Budgeting Extended Capability Header Register
3825 */
3826 union ody_pciercx_pb_base {
3827 uint32_t u;
3828 struct ody_pciercx_pb_base_s {
3829 uint32_t pcieec : 16;
3830 uint32_t cv : 4;
3831 uint32_t nco : 12;
3832 } s;
3833 /* struct ody_pciercx_pb_base_s cn; */
3834 };
3835 typedef union ody_pciercx_pb_base ody_pciercx_pb_base_t;
3836
3837 static inline uint64_t ODY_PCIERCX_PB_BASE(uint64_t a) __attribute__ ((pure, always_inline));
ODY_PCIERCX_PB_BASE(uint64_t a)3838 static inline uint64_t ODY_PCIERCX_PB_BASE(uint64_t a)
3839 {
3840 if (a <= 15)
3841 return 0x158;
3842 __ody_csr_fatal("PCIERCX_PB_BASE", 1, a, 0, 0, 0, 0, 0);
3843 }
3844
3845 #define typedef_ODY_PCIERCX_PB_BASE(a) ody_pciercx_pb_base_t
3846 #define bustype_ODY_PCIERCX_PB_BASE(a) CSR_TYPE_PCICONFIGRC
3847 #define basename_ODY_PCIERCX_PB_BASE(a) "PCIERCX_PB_BASE"
3848 #define busnum_ODY_PCIERCX_PB_BASE(a) (a)
3849 #define arguments_ODY_PCIERCX_PB_BASE(a) (a), -1, -1, -1
3850
3851 /**
3852 * Register (PCICONFIGRC) pcierc#_pb_cap
3853 *
3854 * PCIe RC Power Budgeting Capability Register
3855 */
3856 union ody_pciercx_pb_cap {
3857 uint32_t u;
3858 struct ody_pciercx_pb_cap_s {
3859 uint32_t sys_alloc : 1;
3860 uint32_t ext_pwr_budget_sup : 1;
3861 uint32_t pwr_budget_det_sup : 1;
3862 uint32_t pwr_lim_sup : 1;
3863 uint32_t pwr_loss_dis_sup : 2;
3864 uint32_t pwr_loss_notif_sup : 2;
3865 uint32_t reserved_8_31 : 24;
3866 } s;
3867 /* struct ody_pciercx_pb_cap_s cn; */
3868 };
3869 typedef union ody_pciercx_pb_cap ody_pciercx_pb_cap_t;
3870
3871 static inline uint64_t ODY_PCIERCX_PB_CAP(uint64_t a) __attribute__ ((pure, always_inline));
ODY_PCIERCX_PB_CAP(uint64_t a)3872 static inline uint64_t ODY_PCIERCX_PB_CAP(uint64_t a)
3873 {
3874 if (a <= 15)
3875 return 0x164;
3876 __ody_csr_fatal("PCIERCX_PB_CAP", 1, a, 0, 0, 0, 0, 0);
3877 }
3878
3879 #define typedef_ODY_PCIERCX_PB_CAP(a) ody_pciercx_pb_cap_t
3880 #define bustype_ODY_PCIERCX_PB_CAP(a) CSR_TYPE_PCICONFIGRC
3881 #define basename_ODY_PCIERCX_PB_CAP(a) "PCIERCX_PB_CAP"
3882 #define busnum_ODY_PCIERCX_PB_CAP(a) (a)
3883 #define arguments_ODY_PCIERCX_PB_CAP(a) (a), -1, -1, -1
3884
3885 /**
3886 * Register (PCICONFIGRC) pcierc#_pb_data_reg
3887 *
3888 * PCIe RC Power Budgeting Data Register
3889 */
3890 union ody_pciercx_pb_data_reg {
3891 uint32_t u;
3892 struct ody_pciercx_pb_data_reg_s {
3893 uint32_t pb_data_reg : 32;
3894 } s;
3895 /* struct ody_pciercx_pb_data_reg_s cn; */
3896 };
3897 typedef union ody_pciercx_pb_data_reg ody_pciercx_pb_data_reg_t;
3898
3899 static inline uint64_t ODY_PCIERCX_PB_DATA_REG(uint64_t a) __attribute__ ((pure, always_inline));
ODY_PCIERCX_PB_DATA_REG(uint64_t a)3900 static inline uint64_t ODY_PCIERCX_PB_DATA_REG(uint64_t a)
3901 {
3902 if (a <= 15)
3903 return 0x160;
3904 __ody_csr_fatal("PCIERCX_PB_DATA_REG", 1, a, 0, 0, 0, 0, 0);
3905 }
3906
3907 #define typedef_ODY_PCIERCX_PB_DATA_REG(a) ody_pciercx_pb_data_reg_t
3908 #define bustype_ODY_PCIERCX_PB_DATA_REG(a) CSR_TYPE_PCICONFIGRC
3909 #define basename_ODY_PCIERCX_PB_DATA_REG(a) "PCIERCX_PB_DATA_REG"
3910 #define busnum_ODY_PCIERCX_PB_DATA_REG(a) (a)
3911 #define arguments_ODY_PCIERCX_PB_DATA_REG(a) (a), -1, -1, -1
3912
3913 /**
3914 * Register (PCICONFIGRC) pcierc#_pb_data_sel
3915 *
3916 * PCIe RC Power Budgeting Data Select Register
3917 */
3918 union ody_pciercx_pb_data_sel {
3919 uint32_t u;
3920 struct ody_pciercx_pb_data_sel_s {
3921 uint32_t pb_data_sel : 8;
3922 uint32_t reserved_8_31 : 24;
3923 } s;
3924 /* struct ody_pciercx_pb_data_sel_s cn; */
3925 };
3926 typedef union ody_pciercx_pb_data_sel ody_pciercx_pb_data_sel_t;
3927
3928 static inline uint64_t ODY_PCIERCX_PB_DATA_SEL(uint64_t a) __attribute__ ((pure, always_inline));
ODY_PCIERCX_PB_DATA_SEL(uint64_t a)3929 static inline uint64_t ODY_PCIERCX_PB_DATA_SEL(uint64_t a)
3930 {
3931 if (a <= 15)
3932 return 0x15c;
3933 __ody_csr_fatal("PCIERCX_PB_DATA_SEL", 1, a, 0, 0, 0, 0, 0);
3934 }
3935
3936 #define typedef_ODY_PCIERCX_PB_DATA_SEL(a) ody_pciercx_pb_data_sel_t
3937 #define bustype_ODY_PCIERCX_PB_DATA_SEL(a) CSR_TYPE_PCICONFIGRC
3938 #define basename_ODY_PCIERCX_PB_DATA_SEL(a) "PCIERCX_PB_DATA_SEL"
3939 #define busnum_ODY_PCIERCX_PB_DATA_SEL(a) (a)
3940 #define arguments_ODY_PCIERCX_PB_DATA_SEL(a) (a), -1, -1, -1
3941
3942 /**
3943 * Register (PCICONFIGRC) pcierc#_phy_ctl
3944 *
3945 * PCIe RC PHY Control Register
3946 */
3947 union ody_pciercx_phy_ctl {
3948 uint32_t u;
3949 struct ody_pciercx_phy_ctl_s {
3950 uint32_t phy_ctrl : 32;
3951 } s;
3952 /* struct ody_pciercx_phy_ctl_s cn; */
3953 };
3954 typedef union ody_pciercx_phy_ctl ody_pciercx_phy_ctl_t;
3955
3956 static inline uint64_t ODY_PCIERCX_PHY_CTL(uint64_t a) __attribute__ ((pure, always_inline));
ODY_PCIERCX_PHY_CTL(uint64_t a)3957 static inline uint64_t ODY_PCIERCX_PHY_CTL(uint64_t a)
3958 {
3959 if (a <= 15)
3960 return 0x814;
3961 __ody_csr_fatal("PCIERCX_PHY_CTL", 1, a, 0, 0, 0, 0, 0);
3962 }
3963
3964 #define typedef_ODY_PCIERCX_PHY_CTL(a) ody_pciercx_phy_ctl_t
3965 #define bustype_ODY_PCIERCX_PHY_CTL(a) CSR_TYPE_PCICONFIGRC
3966 #define basename_ODY_PCIERCX_PHY_CTL(a) "PCIERCX_PHY_CTL"
3967 #define busnum_ODY_PCIERCX_PHY_CTL(a) (a)
3968 #define arguments_ODY_PCIERCX_PHY_CTL(a) (a), -1, -1, -1
3969
3970 /**
3971 * Register (PCICONFIGRC) pcierc#_phy_gen3_ctl
3972 *
3973 * PCIe RC Gen3 Control Register
3974 */
3975 union ody_pciercx_phy_gen3_ctl {
3976 uint32_t u;
3977 struct ody_pciercx_phy_gen3_ctl_s {
3978 uint32_t grizdnc : 1;
3979 uint32_t no_seed_value_change : 1;
3980 uint32_t reserved_2_7 : 6;
3981 uint32_t dsg3 : 1;
3982 uint32_t ep2p3d : 1;
3983 uint32_t ecrd : 1;
3984 uint32_t erd : 1;
3985 uint32_t rxeq_ph01_en : 1;
3986 uint32_t rxeq_rgrdless_rsts : 1;
3987 uint32_t reserved_14_15 : 2;
3988 uint32_t ed : 1;
3989 uint32_t dtdd : 1;
3990 uint32_t dcbd : 1;
3991 uint32_t reserved_19_20 : 2;
3992 uint32_t aed : 1;
3993 uint32_t us8etd : 1;
3994 uint32_t eiedd : 1;
3995 uint32_t rss : 2;
3996 uint32_t reserved_26_31 : 6;
3997 } s;
3998 /* struct ody_pciercx_phy_gen3_ctl_s cn; */
3999 };
4000 typedef union ody_pciercx_phy_gen3_ctl ody_pciercx_phy_gen3_ctl_t;
4001
4002 static inline uint64_t ODY_PCIERCX_PHY_GEN3_CTL(uint64_t a) __attribute__ ((pure, always_inline));
ODY_PCIERCX_PHY_GEN3_CTL(uint64_t a)4003 static inline uint64_t ODY_PCIERCX_PHY_GEN3_CTL(uint64_t a)
4004 {
4005 if (a <= 15)
4006 return 0x890;
4007 __ody_csr_fatal("PCIERCX_PHY_GEN3_CTL", 1, a, 0, 0, 0, 0, 0);
4008 }
4009
4010 #define typedef_ODY_PCIERCX_PHY_GEN3_CTL(a) ody_pciercx_phy_gen3_ctl_t
4011 #define bustype_ODY_PCIERCX_PHY_GEN3_CTL(a) CSR_TYPE_PCICONFIGRC
4012 #define basename_ODY_PCIERCX_PHY_GEN3_CTL(a) "PCIERCX_PHY_GEN3_CTL"
4013 #define busnum_ODY_PCIERCX_PHY_GEN3_CTL(a) (a)
4014 #define arguments_ODY_PCIERCX_PHY_GEN3_CTL(a) (a), -1, -1, -1
4015
4016 /**
4017 * Register (PCICONFIGRC) pcierc#_phy_intop_ctl
4018 *
4019 * PCIe RC PHY Interoperability Control Register
4020 */
4021 union ody_pciercx_phy_intop_ctl {
4022 uint32_t u;
4023 struct ody_pciercx_phy_intop_ctl_s {
4024 uint32_t rxstby_ctl : 7;
4025 uint32_t reserved_7_8 : 2;
4026 uint32_t l1_nowait_p1 : 1;
4027 uint32_t l1_clk_sel : 1;
4028 uint32_t p2nobeacon_en : 1;
4029 uint32_t phy_rst_timer : 18;
4030 uint32_t phy_perst_on_warm_r : 1;
4031 uint32_t pipe_opt_pclkchg_hs : 1;
4032 } s;
4033 /* struct ody_pciercx_phy_intop_ctl_s cn; */
4034 };
4035 typedef union ody_pciercx_phy_intop_ctl ody_pciercx_phy_intop_ctl_t;
4036
4037 static inline uint64_t ODY_PCIERCX_PHY_INTOP_CTL(uint64_t a) __attribute__ ((pure, always_inline));
ODY_PCIERCX_PHY_INTOP_CTL(uint64_t a)4038 static inline uint64_t ODY_PCIERCX_PHY_INTOP_CTL(uint64_t a)
4039 {
4040 if (a <= 15)
4041 return 0x8c4;
4042 __ody_csr_fatal("PCIERCX_PHY_INTOP_CTL", 1, a, 0, 0, 0, 0, 0);
4043 }
4044
4045 #define typedef_ODY_PCIERCX_PHY_INTOP_CTL(a) ody_pciercx_phy_intop_ctl_t
4046 #define bustype_ODY_PCIERCX_PHY_INTOP_CTL(a) CSR_TYPE_PCICONFIGRC
4047 #define basename_ODY_PCIERCX_PHY_INTOP_CTL(a) "PCIERCX_PHY_INTOP_CTL"
4048 #define busnum_ODY_PCIERCX_PHY_INTOP_CTL(a) (a)
4049 #define arguments_ODY_PCIERCX_PHY_INTOP_CTL(a) (a), -1, -1, -1
4050
4051 /**
4052 * Register (PCICONFIGRC) pcierc#_phy_status
4053 *
4054 * PCIe RC PHY Status Register
4055 */
4056 union ody_pciercx_phy_status {
4057 uint32_t u;
4058 struct ody_pciercx_phy_status_s {
4059 uint32_t phy_stat : 32;
4060 } s;
4061 /* struct ody_pciercx_phy_status_s cn; */
4062 };
4063 typedef union ody_pciercx_phy_status ody_pciercx_phy_status_t;
4064
4065 static inline uint64_t ODY_PCIERCX_PHY_STATUS(uint64_t a) __attribute__ ((pure, always_inline));
ODY_PCIERCX_PHY_STATUS(uint64_t a)4066 static inline uint64_t ODY_PCIERCX_PHY_STATUS(uint64_t a)
4067 {
4068 if (a <= 15)
4069 return 0x810;
4070 __ody_csr_fatal("PCIERCX_PHY_STATUS", 1, a, 0, 0, 0, 0, 0);
4071 }
4072
4073 #define typedef_ODY_PCIERCX_PHY_STATUS(a) ody_pciercx_phy_status_t
4074 #define bustype_ODY_PCIERCX_PHY_STATUS(a) CSR_TYPE_PCICONFIGRC
4075 #define basename_ODY_PCIERCX_PHY_STATUS(a) "PCIERCX_PHY_STATUS"
4076 #define busnum_ODY_PCIERCX_PHY_STATUS(a) (a)
4077 #define arguments_ODY_PCIERCX_PHY_STATUS(a) (a), -1, -1, -1
4078
4079 /**
4080 * Register (PCICONFIGRC) pcierc#_pipe_rel
4081 *
4082 * PCIe RC Pipe Related Register
4083 */
4084 union ody_pciercx_pipe_rel {
4085 uint32_t u;
4086 struct ody_pciercx_pipe_rel_s {
4087 uint32_t rx_msg_wbuf_depth : 4;
4088 uint32_t tx_msg_wbuf_depth : 4;
4089 uint32_t pipe_garbage_dm : 1;
4090 uint32_t reserved_9_31 : 23;
4091 } s;
4092 /* struct ody_pciercx_pipe_rel_s cn; */
4093 };
4094 typedef union ody_pciercx_pipe_rel ody_pciercx_pipe_rel_t;
4095
4096 static inline uint64_t ODY_PCIERCX_PIPE_REL(uint64_t a) __attribute__ ((pure, always_inline));
ODY_PCIERCX_PIPE_REL(uint64_t a)4097 static inline uint64_t ODY_PCIERCX_PIPE_REL(uint64_t a)
4098 {
4099 if (a <= 15)
4100 return 0xb90;
4101 __ody_csr_fatal("PCIERCX_PIPE_REL", 1, a, 0, 0, 0, 0, 0);
4102 }
4103
4104 #define typedef_ODY_PCIERCX_PIPE_REL(a) ody_pciercx_pipe_rel_t
4105 #define bustype_ODY_PCIERCX_PIPE_REL(a) CSR_TYPE_PCICONFIGRC
4106 #define basename_ODY_PCIERCX_PIPE_REL(a) "PCIERCX_PIPE_REL"
4107 #define busnum_ODY_PCIERCX_PIPE_REL(a) (a)
4108 #define arguments_ODY_PCIERCX_PIPE_REL(a) (a), -1, -1, -1
4109
4110 /**
4111 * Register (PCICONFIGRC) pcierc#_pl16g_cap
4112 *
4113 * PCIe RC 16.0 GT/s Capabilities Register
4114 */
4115 union ody_pciercx_pl16g_cap {
4116 uint32_t u;
4117 struct ody_pciercx_pl16g_cap_s {
4118 uint32_t reserved_0_31 : 32;
4119 } s;
4120 /* struct ody_pciercx_pl16g_cap_s cn; */
4121 };
4122 typedef union ody_pciercx_pl16g_cap ody_pciercx_pl16g_cap_t;
4123
4124 static inline uint64_t ODY_PCIERCX_PL16G_CAP(uint64_t a) __attribute__ ((pure, always_inline));
ODY_PCIERCX_PL16G_CAP(uint64_t a)4125 static inline uint64_t ODY_PCIERCX_PL16G_CAP(uint64_t a)
4126 {
4127 if (a <= 15)
4128 return 0x19c;
4129 __ody_csr_fatal("PCIERCX_PL16G_CAP", 1, a, 0, 0, 0, 0, 0);
4130 }
4131
4132 #define typedef_ODY_PCIERCX_PL16G_CAP(a) ody_pciercx_pl16g_cap_t
4133 #define bustype_ODY_PCIERCX_PL16G_CAP(a) CSR_TYPE_PCICONFIGRC
4134 #define basename_ODY_PCIERCX_PL16G_CAP(a) "PCIERCX_PL16G_CAP"
4135 #define busnum_ODY_PCIERCX_PL16G_CAP(a) (a)
4136 #define arguments_ODY_PCIERCX_PL16G_CAP(a) (a), -1, -1, -1
4137
4138 /**
4139 * Register (PCICONFIGRC) pcierc#_pl16g_ctl
4140 *
4141 * PCIe RC 16.0 GT/s Control Register
4142 */
4143 union ody_pciercx_pl16g_ctl {
4144 uint32_t u;
4145 struct ody_pciercx_pl16g_ctl_s {
4146 uint32_t reserved_0_31 : 32;
4147 } s;
4148 /* struct ody_pciercx_pl16g_ctl_s cn; */
4149 };
4150 typedef union ody_pciercx_pl16g_ctl ody_pciercx_pl16g_ctl_t;
4151
4152 static inline uint64_t ODY_PCIERCX_PL16G_CTL(uint64_t a) __attribute__ ((pure, always_inline));
ODY_PCIERCX_PL16G_CTL(uint64_t a)4153 static inline uint64_t ODY_PCIERCX_PL16G_CTL(uint64_t a)
4154 {
4155 if (a <= 15)
4156 return 0x1a0;
4157 __ody_csr_fatal("PCIERCX_PL16G_CTL", 1, a, 0, 0, 0, 0, 0);
4158 }
4159
4160 #define typedef_ODY_PCIERCX_PL16G_CTL(a) ody_pciercx_pl16g_ctl_t
4161 #define bustype_ODY_PCIERCX_PL16G_CTL(a) CSR_TYPE_PCICONFIGRC
4162 #define basename_ODY_PCIERCX_PL16G_CTL(a) "PCIERCX_PL16G_CTL"
4163 #define busnum_ODY_PCIERCX_PL16G_CTL(a) (a)
4164 #define arguments_ODY_PCIERCX_PL16G_CTL(a) (a), -1, -1, -1
4165
4166 /**
4167 * Register (PCICONFIGRC) pcierc#_pl16g_eq_ctl0123
4168 *
4169 * PCIe RC 16.0 GT/s Lane Equalization Control for Lane 0-3 Register
4170 * The Equalization Control register consists of control fields required for per-Lane
4171 * 16.0 GT/s equalization.
4172 *
4173 * Equalization as an RC:
4174 * \<pre\>
4175 * - On speed change from GEN1-\>GEN3, advertise the transmitter preset hint per lane
4176 * to the EP device in the TS2s exchanged. This value comes from the per lane
4177 * upstream port transmitter preset (L*UTP).
4178 * - Upon exit from Recovery Speed, the RC will enter EQ PHASE1 and the RC's
4179 * transmitter will use the per lane downstream port transmitter preset field (L*DTP).
4180 * - While in EQ PHASE 1, the EP & RC device exchange NO presets. They do advertise
4181 * their LF & FS which are needed for the fine tuning stages to follow.
4182 * - For the RC, while in EQ PHASE 2, the EP device makes tuning requests of the RC.
4183 * The RC adjusts its transmitter settings as directed by the EP. The requests are
4184 * communicated via TS1s.
4185 * - Once the EP is satisfied with the tuning, equalization moves to PHASE 3 where
4186 * the RC tunes the EP's remote transmitter.
4187 * Again, the settings are communicated via TS1s but the feedback is provided by
4188 * the RC phy's FOM or direction change indications.
4189 * \</pre\>
4190 */
4191 union ody_pciercx_pl16g_eq_ctl0123 {
4192 uint32_t u;
4193 struct ody_pciercx_pl16g_eq_ctl0123_s {
4194 uint32_t l0dtp : 4;
4195 uint32_t l0utp : 4;
4196 uint32_t l1dtp : 4;
4197 uint32_t l1utp : 4;
4198 uint32_t l2dtp : 4;
4199 uint32_t l2utp : 4;
4200 uint32_t l3dtp : 4;
4201 uint32_t l3utp : 4;
4202 } s;
4203 /* struct ody_pciercx_pl16g_eq_ctl0123_s cn; */
4204 };
4205 typedef union ody_pciercx_pl16g_eq_ctl0123 ody_pciercx_pl16g_eq_ctl0123_t;
4206
4207 static inline uint64_t ODY_PCIERCX_PL16G_EQ_CTL0123(uint64_t a) __attribute__ ((pure, always_inline));
ODY_PCIERCX_PL16G_EQ_CTL0123(uint64_t a)4208 static inline uint64_t ODY_PCIERCX_PL16G_EQ_CTL0123(uint64_t a)
4209 {
4210 if (a <= 15)
4211 return 0x1b8;
4212 __ody_csr_fatal("PCIERCX_PL16G_EQ_CTL0123", 1, a, 0, 0, 0, 0, 0);
4213 }
4214
4215 #define typedef_ODY_PCIERCX_PL16G_EQ_CTL0123(a) ody_pciercx_pl16g_eq_ctl0123_t
4216 #define bustype_ODY_PCIERCX_PL16G_EQ_CTL0123(a) CSR_TYPE_PCICONFIGRC
4217 #define basename_ODY_PCIERCX_PL16G_EQ_CTL0123(a) "PCIERCX_PL16G_EQ_CTL0123"
4218 #define busnum_ODY_PCIERCX_PL16G_EQ_CTL0123(a) (a)
4219 #define arguments_ODY_PCIERCX_PL16G_EQ_CTL0123(a) (a), -1, -1, -1
4220
4221 /**
4222 * Register (PCICONFIGRC) pcierc#_pl16g_eq_ctl12131415
4223 *
4224 * PCIe RC 16.0 GT/s Lane Equalization Control for Lane 12-15 Register
4225 * Not supported in QPEM/HPEM.
4226 *
4227 * The Equalization Control register consists of control fields required for per-Lane
4228 * 16.0 GT/s equalization.
4229 *
4230 * Equalization as an RC:
4231 * \<pre\>
4232 * - On speed change from GEN1-\>GEN3, advertise the transmitter preset hint per lane
4233 * to the EP device in the TS2s exchanged. This value comes from the per lane
4234 * upstream port transmitter preset (L*UTP).
4235 * - Upon exit from Recovery Speed, the RC will enter EQ PHASE1 and the RC's
4236 * transmitter will use the per lane downstream port transmitter preset field (L*DTP).
4237 * - While in EQ PHASE 1, the EP & RC device exchange NO presets. They do advertise
4238 * their LF & FS which are needed for the fine tuning stages to follow.
4239 * - For the RC, while in EQ PHASE 2, the EP device makes tuning requests of the RC.
4240 * The RC adjusts its transmitter settings as directed by the EP. The requests are
4241 * communicated via TS1s.
4242 * - Once the EP is satisfied with the tuning, equalization moves to PHASE 3 where
4243 * the RC tunes the EP's remote transmitter.
4244 * Again, the settings are communicated via TS1s but the feedback is provided by
4245 * the RC phy's FOM or direction change indications.
4246 * \</pre\>
4247 */
4248 union ody_pciercx_pl16g_eq_ctl12131415 {
4249 uint32_t u;
4250 struct ody_pciercx_pl16g_eq_ctl12131415_s {
4251 uint32_t l12dtp : 4;
4252 uint32_t l12utp : 4;
4253 uint32_t l13dtp : 4;
4254 uint32_t l13utp : 4;
4255 uint32_t l14dtp : 4;
4256 uint32_t l14utp : 4;
4257 uint32_t l15dtp : 4;
4258 uint32_t l15utp : 4;
4259 } s;
4260 /* struct ody_pciercx_pl16g_eq_ctl12131415_s cn; */
4261 };
4262 typedef union ody_pciercx_pl16g_eq_ctl12131415 ody_pciercx_pl16g_eq_ctl12131415_t;
4263
4264 static inline uint64_t ODY_PCIERCX_PL16G_EQ_CTL12131415(uint64_t a) __attribute__ ((pure, always_inline));
ODY_PCIERCX_PL16G_EQ_CTL12131415(uint64_t a)4265 static inline uint64_t ODY_PCIERCX_PL16G_EQ_CTL12131415(uint64_t a)
4266 {
4267 if (a <= 15)
4268 return 0x1c4;
4269 __ody_csr_fatal("PCIERCX_PL16G_EQ_CTL12131415", 1, a, 0, 0, 0, 0, 0);
4270 }
4271
4272 #define typedef_ODY_PCIERCX_PL16G_EQ_CTL12131415(a) ody_pciercx_pl16g_eq_ctl12131415_t
4273 #define bustype_ODY_PCIERCX_PL16G_EQ_CTL12131415(a) CSR_TYPE_PCICONFIGRC
4274 #define basename_ODY_PCIERCX_PL16G_EQ_CTL12131415(a) "PCIERCX_PL16G_EQ_CTL12131415"
4275 #define busnum_ODY_PCIERCX_PL16G_EQ_CTL12131415(a) (a)
4276 #define arguments_ODY_PCIERCX_PL16G_EQ_CTL12131415(a) (a), -1, -1, -1
4277
4278 /**
4279 * Register (PCICONFIGRC) pcierc#_pl16g_eq_ctl4567
4280 *
4281 * PCIe RC 16.0 GT/s Lane Equalization Control for Lane 4-7 Register
4282 * Not supported in QPEM.
4283 *
4284 * The Equalization Control register consists of control fields required for per-Lane
4285 * 16.0 GT/s equalization.
4286 *
4287 * Equalization as an RC:
4288 * \<pre\>
4289 * - On speed change from GEN1-\>GEN3, advertise the transmitter preset hint per lane
4290 * to the EP device in the TS2s exchanged. This value comes from the per lane
4291 * upstream port transmitter preset (L*UTP).
4292 * - Upon exit from Recovery Speed, the RC will enter EQ PHASE1 and the RC's
4293 * transmitter will use the per lane downstream port transmitter preset field (L*DTP).
4294 * - While in EQ PHASE 1, the EP & RC device exchange NO presets. They do advertise
4295 * their LF & FS which are needed for the fine tuning stages to follow.
4296 * - For the RC, while in EQ PHASE 2, the EP device makes tuning requests of the RC.
4297 * The RC adjusts its transmitter settings as directed by the EP. The requests are
4298 * communicated via TS1s.
4299 * - Once the EP is satisfied with the tuning, equalization moves to PHASE 3 where
4300 * the RC tunes the EP's remote transmitter.
4301 * Again, the settings are communicated via TS1s but the feedback is provided by
4302 * the RC phy's FOM or direction change indications.
4303 * \</pre\>
4304 */
4305 union ody_pciercx_pl16g_eq_ctl4567 {
4306 uint32_t u;
4307 struct ody_pciercx_pl16g_eq_ctl4567_s {
4308 uint32_t l4dtp : 4;
4309 uint32_t l4utp : 4;
4310 uint32_t l5dtp : 4;
4311 uint32_t l5utp : 4;
4312 uint32_t l6dtp : 4;
4313 uint32_t l6utp : 4;
4314 uint32_t l7dtp : 4;
4315 uint32_t l7utp : 4;
4316 } s;
4317 /* struct ody_pciercx_pl16g_eq_ctl4567_s cn; */
4318 };
4319 typedef union ody_pciercx_pl16g_eq_ctl4567 ody_pciercx_pl16g_eq_ctl4567_t;
4320
4321 static inline uint64_t ODY_PCIERCX_PL16G_EQ_CTL4567(uint64_t a) __attribute__ ((pure, always_inline));
ODY_PCIERCX_PL16G_EQ_CTL4567(uint64_t a)4322 static inline uint64_t ODY_PCIERCX_PL16G_EQ_CTL4567(uint64_t a)
4323 {
4324 if (a <= 15)
4325 return 0x1bc;
4326 __ody_csr_fatal("PCIERCX_PL16G_EQ_CTL4567", 1, a, 0, 0, 0, 0, 0);
4327 }
4328
4329 #define typedef_ODY_PCIERCX_PL16G_EQ_CTL4567(a) ody_pciercx_pl16g_eq_ctl4567_t
4330 #define bustype_ODY_PCIERCX_PL16G_EQ_CTL4567(a) CSR_TYPE_PCICONFIGRC
4331 #define basename_ODY_PCIERCX_PL16G_EQ_CTL4567(a) "PCIERCX_PL16G_EQ_CTL4567"
4332 #define busnum_ODY_PCIERCX_PL16G_EQ_CTL4567(a) (a)
4333 #define arguments_ODY_PCIERCX_PL16G_EQ_CTL4567(a) (a), -1, -1, -1
4334
4335 /**
4336 * Register (PCICONFIGRC) pcierc#_pl16g_eq_ctl891011
4337 *
4338 * PCIe RC 16.0 GT/s Lane Equalization Control for Lane 8-11 Register
4339 * Not supported in QPEM/HPEM.
4340 *
4341 * The Equalization Control register consists of control fields required for per-Lane
4342 * 16.0 GT/s equalization.
4343 *
4344 * Equalization as an RC:
4345 * \<pre\>
4346 * - On speed change from GEN1-\>GEN3, advertise the transmitter preset hint per lane
4347 * to the EP device in the TS2s exchanged. This value comes from the per lane
4348 * upstream port transmitter preset (L*UTP).
4349 * - Upon exit from Recovery Speed, the RC will enter EQ PHASE1 and the RC's
4350 * transmitter will use the per lane downstream port transmitter preset field (L*DTP).
4351 * - While in EQ PHASE 1, the EP & RC device exchange NO presets. They do advertise
4352 * their LF & FS which are needed for the fine tuning stages to follow.
4353 * - For the RC, while in EQ PHASE 2, the EP device makes tuning requests of the RC.
4354 * The RC adjusts its transmitter settings as directed by the EP. The requests are
4355 * communicated via TS1s.
4356 * - Once the EP is satisfied with the tuning, equalization moves to PHASE 3 where
4357 * the RC tunes the EP's remote transmitter.
4358 * Again, the settings are communicated via TS1s but the feedback is provided by
4359 * the RC phy's FOM or direction change indications.
4360 * \</pre\>
4361 */
4362 union ody_pciercx_pl16g_eq_ctl891011 {
4363 uint32_t u;
4364 struct ody_pciercx_pl16g_eq_ctl891011_s {
4365 uint32_t l8dtp : 4;
4366 uint32_t l8utp : 4;
4367 uint32_t l9dtp : 4;
4368 uint32_t l9utp : 4;
4369 uint32_t l10dtp : 4;
4370 uint32_t l10utp : 4;
4371 uint32_t l11dtp : 4;
4372 uint32_t l11utp : 4;
4373 } s;
4374 /* struct ody_pciercx_pl16g_eq_ctl891011_s cn; */
4375 };
4376 typedef union ody_pciercx_pl16g_eq_ctl891011 ody_pciercx_pl16g_eq_ctl891011_t;
4377
4378 static inline uint64_t ODY_PCIERCX_PL16G_EQ_CTL891011(uint64_t a) __attribute__ ((pure, always_inline));
ODY_PCIERCX_PL16G_EQ_CTL891011(uint64_t a)4379 static inline uint64_t ODY_PCIERCX_PL16G_EQ_CTL891011(uint64_t a)
4380 {
4381 if (a <= 15)
4382 return 0x1c0;
4383 __ody_csr_fatal("PCIERCX_PL16G_EQ_CTL891011", 1, a, 0, 0, 0, 0, 0);
4384 }
4385
4386 #define typedef_ODY_PCIERCX_PL16G_EQ_CTL891011(a) ody_pciercx_pl16g_eq_ctl891011_t
4387 #define bustype_ODY_PCIERCX_PL16G_EQ_CTL891011(a) CSR_TYPE_PCICONFIGRC
4388 #define basename_ODY_PCIERCX_PL16G_EQ_CTL891011(a) "PCIERCX_PL16G_EQ_CTL891011"
4389 #define busnum_ODY_PCIERCX_PL16G_EQ_CTL891011(a) (a)
4390 #define arguments_ODY_PCIERCX_PL16G_EQ_CTL891011(a) (a), -1, -1, -1
4391
4392 /**
4393 * Register (PCICONFIGRC) pcierc#_pl16g_ext_cap_hdr
4394 *
4395 * PCIe RC Pysical Layer 16.0 GT/s Extended Capability Header Register
4396 */
4397 union ody_pciercx_pl16g_ext_cap_hdr {
4398 uint32_t u;
4399 struct ody_pciercx_pl16g_ext_cap_hdr_s {
4400 uint32_t pcieec : 16;
4401 uint32_t cv : 4;
4402 uint32_t nco : 12;
4403 } s;
4404 /* struct ody_pciercx_pl16g_ext_cap_hdr_s cn; */
4405 };
4406 typedef union ody_pciercx_pl16g_ext_cap_hdr ody_pciercx_pl16g_ext_cap_hdr_t;
4407
4408 static inline uint64_t ODY_PCIERCX_PL16G_EXT_CAP_HDR(uint64_t a) __attribute__ ((pure, always_inline));
ODY_PCIERCX_PL16G_EXT_CAP_HDR(uint64_t a)4409 static inline uint64_t ODY_PCIERCX_PL16G_EXT_CAP_HDR(uint64_t a)
4410 {
4411 if (a <= 15)
4412 return 0x198;
4413 __ody_csr_fatal("PCIERCX_PL16G_EXT_CAP_HDR", 1, a, 0, 0, 0, 0, 0);
4414 }
4415
4416 #define typedef_ODY_PCIERCX_PL16G_EXT_CAP_HDR(a) ody_pciercx_pl16g_ext_cap_hdr_t
4417 #define bustype_ODY_PCIERCX_PL16G_EXT_CAP_HDR(a) CSR_TYPE_PCICONFIGRC
4418 #define basename_ODY_PCIERCX_PL16G_EXT_CAP_HDR(a) "PCIERCX_PL16G_EXT_CAP_HDR"
4419 #define busnum_ODY_PCIERCX_PL16G_EXT_CAP_HDR(a) (a)
4420 #define arguments_ODY_PCIERCX_PL16G_EXT_CAP_HDR(a) (a), -1, -1, -1
4421
4422 /**
4423 * Register (PCICONFIGRC) pcierc#_pl16g_fret_dpar_stat
4424 *
4425 * PCIe RC 16.0 GT/s First Retimer Data Parity Mismatch Status Register
4426 */
4427 union ody_pciercx_pl16g_fret_dpar_stat {
4428 uint32_t u;
4429 struct ody_pciercx_pl16g_fret_dpar_stat_s {
4430 uint32_t frt_dp_status : 16;
4431 uint32_t reserved_16_31 : 16;
4432 } s;
4433 /* struct ody_pciercx_pl16g_fret_dpar_stat_s cn; */
4434 };
4435 typedef union ody_pciercx_pl16g_fret_dpar_stat ody_pciercx_pl16g_fret_dpar_stat_t;
4436
4437 static inline uint64_t ODY_PCIERCX_PL16G_FRET_DPAR_STAT(uint64_t a) __attribute__ ((pure, always_inline));
ODY_PCIERCX_PL16G_FRET_DPAR_STAT(uint64_t a)4438 static inline uint64_t ODY_PCIERCX_PL16G_FRET_DPAR_STAT(uint64_t a)
4439 {
4440 if (a <= 15)
4441 return 0x1ac;
4442 __ody_csr_fatal("PCIERCX_PL16G_FRET_DPAR_STAT", 1, a, 0, 0, 0, 0, 0);
4443 }
4444
4445 #define typedef_ODY_PCIERCX_PL16G_FRET_DPAR_STAT(a) ody_pciercx_pl16g_fret_dpar_stat_t
4446 #define bustype_ODY_PCIERCX_PL16G_FRET_DPAR_STAT(a) CSR_TYPE_PCICONFIGRC
4447 #define basename_ODY_PCIERCX_PL16G_FRET_DPAR_STAT(a) "PCIERCX_PL16G_FRET_DPAR_STAT"
4448 #define busnum_ODY_PCIERCX_PL16G_FRET_DPAR_STAT(a) (a)
4449 #define arguments_ODY_PCIERCX_PL16G_FRET_DPAR_STAT(a) (a), -1, -1, -1
4450
4451 /**
4452 * Register (PCICONFIGRC) pcierc#_pl16g_lc_dpar_stat
4453 *
4454 * PCIe RC 16.0 GT/s Local Data Parity Mismatch Status Register
4455 */
4456 union ody_pciercx_pl16g_lc_dpar_stat {
4457 uint32_t u;
4458 struct ody_pciercx_pl16g_lc_dpar_stat_s {
4459 uint32_t ldp_status : 16;
4460 uint32_t reserved_16_31 : 16;
4461 } s;
4462 /* struct ody_pciercx_pl16g_lc_dpar_stat_s cn; */
4463 };
4464 typedef union ody_pciercx_pl16g_lc_dpar_stat ody_pciercx_pl16g_lc_dpar_stat_t;
4465
4466 static inline uint64_t ODY_PCIERCX_PL16G_LC_DPAR_STAT(uint64_t a) __attribute__ ((pure, always_inline));
ODY_PCIERCX_PL16G_LC_DPAR_STAT(uint64_t a)4467 static inline uint64_t ODY_PCIERCX_PL16G_LC_DPAR_STAT(uint64_t a)
4468 {
4469 if (a <= 15)
4470 return 0x1a8;
4471 __ody_csr_fatal("PCIERCX_PL16G_LC_DPAR_STAT", 1, a, 0, 0, 0, 0, 0);
4472 }
4473
4474 #define typedef_ODY_PCIERCX_PL16G_LC_DPAR_STAT(a) ody_pciercx_pl16g_lc_dpar_stat_t
4475 #define bustype_ODY_PCIERCX_PL16G_LC_DPAR_STAT(a) CSR_TYPE_PCICONFIGRC
4476 #define basename_ODY_PCIERCX_PL16G_LC_DPAR_STAT(a) "PCIERCX_PL16G_LC_DPAR_STAT"
4477 #define busnum_ODY_PCIERCX_PL16G_LC_DPAR_STAT(a) (a)
4478 #define arguments_ODY_PCIERCX_PL16G_LC_DPAR_STAT(a) (a), -1, -1, -1
4479
4480 /**
4481 * Register (PCICONFIGRC) pcierc#_pl16g_sret_dpar_stat
4482 *
4483 * PCIe RC 16.0 GT/s Second Retimer Data Parity Mismatch Status Register
4484 */
4485 union ody_pciercx_pl16g_sret_dpar_stat {
4486 uint32_t u;
4487 struct ody_pciercx_pl16g_sret_dpar_stat_s {
4488 uint32_t srt_dp_status : 16;
4489 uint32_t reserved_16_31 : 16;
4490 } s;
4491 /* struct ody_pciercx_pl16g_sret_dpar_stat_s cn; */
4492 };
4493 typedef union ody_pciercx_pl16g_sret_dpar_stat ody_pciercx_pl16g_sret_dpar_stat_t;
4494
4495 static inline uint64_t ODY_PCIERCX_PL16G_SRET_DPAR_STAT(uint64_t a) __attribute__ ((pure, always_inline));
ODY_PCIERCX_PL16G_SRET_DPAR_STAT(uint64_t a)4496 static inline uint64_t ODY_PCIERCX_PL16G_SRET_DPAR_STAT(uint64_t a)
4497 {
4498 if (a <= 15)
4499 return 0x1b0;
4500 __ody_csr_fatal("PCIERCX_PL16G_SRET_DPAR_STAT", 1, a, 0, 0, 0, 0, 0);
4501 }
4502
4503 #define typedef_ODY_PCIERCX_PL16G_SRET_DPAR_STAT(a) ody_pciercx_pl16g_sret_dpar_stat_t
4504 #define bustype_ODY_PCIERCX_PL16G_SRET_DPAR_STAT(a) CSR_TYPE_PCICONFIGRC
4505 #define basename_ODY_PCIERCX_PL16G_SRET_DPAR_STAT(a) "PCIERCX_PL16G_SRET_DPAR_STAT"
4506 #define busnum_ODY_PCIERCX_PL16G_SRET_DPAR_STAT(a) (a)
4507 #define arguments_ODY_PCIERCX_PL16G_SRET_DPAR_STAT(a) (a), -1, -1, -1
4508
4509 /**
4510 * Register (PCICONFIGRC) pcierc#_pl16g_status
4511 *
4512 * PCIe RC 16.0 GT/s Status Register
4513 */
4514 union ody_pciercx_pl16g_status {
4515 uint32_t u;
4516 struct ody_pciercx_pl16g_status_s {
4517 uint32_t eq_cpl : 1;
4518 uint32_t eq_cpl_p1 : 1;
4519 uint32_t eq_cpl_p2 : 1;
4520 uint32_t eq_cpl_p3 : 1;
4521 uint32_t leq_req : 1;
4522 uint32_t reserved_5_31 : 27;
4523 } s;
4524 /* struct ody_pciercx_pl16g_status_s cn; */
4525 };
4526 typedef union ody_pciercx_pl16g_status ody_pciercx_pl16g_status_t;
4527
4528 static inline uint64_t ODY_PCIERCX_PL16G_STATUS(uint64_t a) __attribute__ ((pure, always_inline));
ODY_PCIERCX_PL16G_STATUS(uint64_t a)4529 static inline uint64_t ODY_PCIERCX_PL16G_STATUS(uint64_t a)
4530 {
4531 if (a <= 15)
4532 return 0x1a4;
4533 __ody_csr_fatal("PCIERCX_PL16G_STATUS", 1, a, 0, 0, 0, 0, 0);
4534 }
4535
4536 #define typedef_ODY_PCIERCX_PL16G_STATUS(a) ody_pciercx_pl16g_status_t
4537 #define bustype_ODY_PCIERCX_PL16G_STATUS(a) CSR_TYPE_PCICONFIGRC
4538 #define basename_ODY_PCIERCX_PL16G_STATUS(a) "PCIERCX_PL16G_STATUS"
4539 #define busnum_ODY_PCIERCX_PL16G_STATUS(a) (a)
4540 #define arguments_ODY_PCIERCX_PL16G_STATUS(a) (a), -1, -1, -1
4541
4542 /**
4543 * Register (PCICONFIGRC) pcierc#_pl32g_cap
4544 *
4545 * PCIe RC 32.0 GT/s Capabilities Register
4546 */
4547 union ody_pciercx_pl32g_cap {
4548 uint32_t u;
4549 struct ody_pciercx_pl32g_cap_s {
4550 uint32_t eq_byp_hirate : 1;
4551 uint32_t no_eq_need_supp : 1;
4552 uint32_t reserved_2_7 : 6;
4553 uint32_t mod_ts_pcie_supp : 1;
4554 uint32_t mod_ts_tset_msg_supp : 1;
4555 uint32_t mod_ts_alt_prot_supp : 1;
4556 uint32_t mod_ts_rsvd_use_supp : 5;
4557 uint32_t reserved_16_31 : 16;
4558 } s;
4559 /* struct ody_pciercx_pl32g_cap_s cn; */
4560 };
4561 typedef union ody_pciercx_pl32g_cap ody_pciercx_pl32g_cap_t;
4562
4563 static inline uint64_t ODY_PCIERCX_PL32G_CAP(uint64_t a) __attribute__ ((pure, always_inline));
ODY_PCIERCX_PL32G_CAP(uint64_t a)4564 static inline uint64_t ODY_PCIERCX_PL32G_CAP(uint64_t a)
4565 {
4566 if (a <= 15)
4567 return 0x214;
4568 __ody_csr_fatal("PCIERCX_PL32G_CAP", 1, a, 0, 0, 0, 0, 0);
4569 }
4570
4571 #define typedef_ODY_PCIERCX_PL32G_CAP(a) ody_pciercx_pl32g_cap_t
4572 #define bustype_ODY_PCIERCX_PL32G_CAP(a) CSR_TYPE_PCICONFIGRC
4573 #define basename_ODY_PCIERCX_PL32G_CAP(a) "PCIERCX_PL32G_CAP"
4574 #define busnum_ODY_PCIERCX_PL32G_CAP(a) (a)
4575 #define arguments_ODY_PCIERCX_PL32G_CAP(a) (a), -1, -1, -1
4576
4577 /**
4578 * Register (PCICONFIGRC) pcierc#_pl32g_ctl
4579 *
4580 * PCIe RC 32.0 GT/s Control Register
4581 */
4582 union ody_pciercx_pl32g_ctl {
4583 uint32_t u;
4584 struct ody_pciercx_pl32g_ctl_s {
4585 uint32_t eq_byp_hirate_dis : 1;
4586 uint32_t no_eq_need_dis : 1;
4587 uint32_t reserved_2_7 : 6;
4588 uint32_t mod_ts_use_mode_sel : 3;
4589 uint32_t reserved_11_31 : 21;
4590 } s;
4591 /* struct ody_pciercx_pl32g_ctl_s cn; */
4592 };
4593 typedef union ody_pciercx_pl32g_ctl ody_pciercx_pl32g_ctl_t;
4594
4595 static inline uint64_t ODY_PCIERCX_PL32G_CTL(uint64_t a) __attribute__ ((pure, always_inline));
ODY_PCIERCX_PL32G_CTL(uint64_t a)4596 static inline uint64_t ODY_PCIERCX_PL32G_CTL(uint64_t a)
4597 {
4598 if (a <= 15)
4599 return 0x218;
4600 __ody_csr_fatal("PCIERCX_PL32G_CTL", 1, a, 0, 0, 0, 0, 0);
4601 }
4602
4603 #define typedef_ODY_PCIERCX_PL32G_CTL(a) ody_pciercx_pl32g_ctl_t
4604 #define bustype_ODY_PCIERCX_PL32G_CTL(a) CSR_TYPE_PCICONFIGRC
4605 #define basename_ODY_PCIERCX_PL32G_CTL(a) "PCIERCX_PL32G_CTL"
4606 #define busnum_ODY_PCIERCX_PL32G_CTL(a) (a)
4607 #define arguments_ODY_PCIERCX_PL32G_CTL(a) (a), -1, -1, -1
4608
4609 /**
4610 * Register (PCICONFIGRC) pcierc#_pl32g_eq_ctl0123
4611 *
4612 * PCIe RC 32.0 GT/s Equalization Control Lane 0/1/2/3 Register
4613 * The Equalization Control register consists of control fields required for per-Lane
4614 * 32.0 GT/s equalization.
4615 *
4616 * Equalization as an RC:
4617 * \<pre\>
4618 * - On speed change from GEN1-\>GEN3, advertise the transmitter preset hint per lane
4619 * to the EP device in the TS2s exchanged. This value comes from the per lane
4620 * upstream port transmitter preset (L*UTP).
4621 * - Upon exit from Recovery Speed, the RC will enter EQ PHASE1 and the RC's
4622 * transmitter will use the per lane downstream port transmitter preset field (L*DTP).
4623 * - While in EQ PHASE 1, the EP & RC device exchange NO presets. They do advertise
4624 * their LF & FS which are needed for the fine tuning stages to follow.
4625 * - For the RC, while in EQ PHASE 2, the EP device makes tuning requests of the RC.
4626 * The RC adjusts its transmitter settings as directed by the EP. The requests are
4627 * communicated via TS1s.
4628 * - Once the EP is satisfied with the tuning, equalization moves to PHASE 3 where
4629 * the RC tunes the EP's remote transmitter.
4630 * Again, the settings are communicated via TS1s but the feedback is provided by
4631 * the RC phy's FOM or direction change indications.
4632 * \</pre\>
4633 */
4634 union ody_pciercx_pl32g_eq_ctl0123 {
4635 uint32_t u;
4636 struct ody_pciercx_pl32g_eq_ctl0123_s {
4637 uint32_t l0dtp : 4;
4638 uint32_t l0utp : 4;
4639 uint32_t l1dtp : 4;
4640 uint32_t l1utp : 4;
4641 uint32_t l2dtp : 4;
4642 uint32_t l2utp : 4;
4643 uint32_t l3dtp : 4;
4644 uint32_t l3utp : 4;
4645 } s;
4646 /* struct ody_pciercx_pl32g_eq_ctl0123_s cn; */
4647 };
4648 typedef union ody_pciercx_pl32g_eq_ctl0123 ody_pciercx_pl32g_eq_ctl0123_t;
4649
4650 static inline uint64_t ODY_PCIERCX_PL32G_EQ_CTL0123(uint64_t a) __attribute__ ((pure, always_inline));
ODY_PCIERCX_PL32G_EQ_CTL0123(uint64_t a)4651 static inline uint64_t ODY_PCIERCX_PL32G_EQ_CTL0123(uint64_t a)
4652 {
4653 if (a <= 15)
4654 return 0x230;
4655 __ody_csr_fatal("PCIERCX_PL32G_EQ_CTL0123", 1, a, 0, 0, 0, 0, 0);
4656 }
4657
4658 #define typedef_ODY_PCIERCX_PL32G_EQ_CTL0123(a) ody_pciercx_pl32g_eq_ctl0123_t
4659 #define bustype_ODY_PCIERCX_PL32G_EQ_CTL0123(a) CSR_TYPE_PCICONFIGRC
4660 #define basename_ODY_PCIERCX_PL32G_EQ_CTL0123(a) "PCIERCX_PL32G_EQ_CTL0123"
4661 #define busnum_ODY_PCIERCX_PL32G_EQ_CTL0123(a) (a)
4662 #define arguments_ODY_PCIERCX_PL32G_EQ_CTL0123(a) (a), -1, -1, -1
4663
4664 /**
4665 * Register (PCICONFIGRC) pcierc#_pl32g_eq_ctl12131415
4666 *
4667 * PCIe RC 32.0 GT/s Equalization Control Lane 12/13/14/15 Register
4668 * Not supported in QPEM/HPEM.
4669 *
4670 * The Equalization Control register consists of control fields required for per-Lane
4671 * 32.0 GT/s equalization.
4672 *
4673 * Equalization as an RC:
4674 * \<pre\>
4675 * - On speed change from GEN1-\>GEN3, advertise the transmitter preset hint per lane
4676 * to the EP device in the TS2s exchanged. This value comes from the per lane
4677 * upstream port transmitter preset (L*UTP).
4678 * - Upon exit from Recovery Speed, the RC will enter EQ PHASE1 and the RC's
4679 * transmitter will use the per lane downstream port transmitter preset field (L*DTP).
4680 * - While in EQ PHASE 1, the EP & RC device exchange NO presets. They do advertise
4681 * their LF & FS which are needed for the fine tuning stages to follow.
4682 * - For the RC, while in EQ PHASE 2, the EP device makes tuning requests of the RC.
4683 * The RC adjusts its transmitter settings as directed by the EP. The requests are
4684 * communicated via TS1s.
4685 * - Once the EP is satisfied with the tuning, equalization moves to PHASE 3 where
4686 * the RC tunes the EP's remote transmitter.
4687 * Again, the settings are communicated via TS1s but the feedback is provided by
4688 * the RC phy's FOM or direction change indications.
4689 * \</pre\>
4690 */
4691 union ody_pciercx_pl32g_eq_ctl12131415 {
4692 uint32_t u;
4693 struct ody_pciercx_pl32g_eq_ctl12131415_s {
4694 uint32_t l12dtp : 4;
4695 uint32_t l12utp : 4;
4696 uint32_t l13dtp : 4;
4697 uint32_t l13utp : 4;
4698 uint32_t l14dtp : 4;
4699 uint32_t l14utp : 4;
4700 uint32_t l15dtp : 4;
4701 uint32_t l15utp : 4;
4702 } s;
4703 /* struct ody_pciercx_pl32g_eq_ctl12131415_s cn; */
4704 };
4705 typedef union ody_pciercx_pl32g_eq_ctl12131415 ody_pciercx_pl32g_eq_ctl12131415_t;
4706
4707 static inline uint64_t ODY_PCIERCX_PL32G_EQ_CTL12131415(uint64_t a) __attribute__ ((pure, always_inline));
ODY_PCIERCX_PL32G_EQ_CTL12131415(uint64_t a)4708 static inline uint64_t ODY_PCIERCX_PL32G_EQ_CTL12131415(uint64_t a)
4709 {
4710 if (a <= 15)
4711 return 0x23c;
4712 __ody_csr_fatal("PCIERCX_PL32G_EQ_CTL12131415", 1, a, 0, 0, 0, 0, 0);
4713 }
4714
4715 #define typedef_ODY_PCIERCX_PL32G_EQ_CTL12131415(a) ody_pciercx_pl32g_eq_ctl12131415_t
4716 #define bustype_ODY_PCIERCX_PL32G_EQ_CTL12131415(a) CSR_TYPE_PCICONFIGRC
4717 #define basename_ODY_PCIERCX_PL32G_EQ_CTL12131415(a) "PCIERCX_PL32G_EQ_CTL12131415"
4718 #define busnum_ODY_PCIERCX_PL32G_EQ_CTL12131415(a) (a)
4719 #define arguments_ODY_PCIERCX_PL32G_EQ_CTL12131415(a) (a), -1, -1, -1
4720
4721 /**
4722 * Register (PCICONFIGRC) pcierc#_pl32g_eq_ctl4567
4723 *
4724 * PCIe RC 32.0 GT/s Equalization Control Lane 4/5/6/7 Register
4725 * Not supported in QPEM.
4726 *
4727 * The Equalization Control register consists of control fields required for per-Lane
4728 * 32.0 GT/s equalization.
4729 *
4730 * Equalization as an RC:
4731 * \<pre\>
4732 * - On speed change from GEN1-\>GEN3, advertise the transmitter preset hint per lane
4733 * to the EP device in the TS2s exchanged. This value comes from the per lane
4734 * upstream port transmitter preset (L*UTP).
4735 * - Upon exit from Recovery Speed, the RC will enter EQ PHASE1 and the RC's
4736 * transmitter will use the per lane downstream port transmitter preset field (L*DTP).
4737 * - While in EQ PHASE 1, the EP & RC device exchange NO presets. They do advertise
4738 * their LF & FS which are needed for the fine tuning stages to follow.
4739 * - For the RC, while in EQ PHASE 2, the EP device makes tuning requests of the RC.
4740 * The RC adjusts its transmitter settings as directed by the EP. The requests are
4741 * communicated via TS1s.
4742 * - Once the EP is satisfied with the tuning, equalization moves to PHASE 3 where
4743 * the RC tunes the EP's remote transmitter.
4744 * Again, the settings are communicated via TS1s but the feedback is provided by
4745 * the RC phy's FOM or direction change indications.
4746 * \</pre\>
4747 */
4748 union ody_pciercx_pl32g_eq_ctl4567 {
4749 uint32_t u;
4750 struct ody_pciercx_pl32g_eq_ctl4567_s {
4751 uint32_t l4dtp : 4;
4752 uint32_t l4utp : 4;
4753 uint32_t l5dtp : 4;
4754 uint32_t l5utp : 4;
4755 uint32_t l6dtp : 4;
4756 uint32_t l6utp : 4;
4757 uint32_t l7dtp : 4;
4758 uint32_t l7utp : 4;
4759 } s;
4760 /* struct ody_pciercx_pl32g_eq_ctl4567_s cn; */
4761 };
4762 typedef union ody_pciercx_pl32g_eq_ctl4567 ody_pciercx_pl32g_eq_ctl4567_t;
4763
4764 static inline uint64_t ODY_PCIERCX_PL32G_EQ_CTL4567(uint64_t a) __attribute__ ((pure, always_inline));
ODY_PCIERCX_PL32G_EQ_CTL4567(uint64_t a)4765 static inline uint64_t ODY_PCIERCX_PL32G_EQ_CTL4567(uint64_t a)
4766 {
4767 if (a <= 15)
4768 return 0x234;
4769 __ody_csr_fatal("PCIERCX_PL32G_EQ_CTL4567", 1, a, 0, 0, 0, 0, 0);
4770 }
4771
4772 #define typedef_ODY_PCIERCX_PL32G_EQ_CTL4567(a) ody_pciercx_pl32g_eq_ctl4567_t
4773 #define bustype_ODY_PCIERCX_PL32G_EQ_CTL4567(a) CSR_TYPE_PCICONFIGRC
4774 #define basename_ODY_PCIERCX_PL32G_EQ_CTL4567(a) "PCIERCX_PL32G_EQ_CTL4567"
4775 #define busnum_ODY_PCIERCX_PL32G_EQ_CTL4567(a) (a)
4776 #define arguments_ODY_PCIERCX_PL32G_EQ_CTL4567(a) (a), -1, -1, -1
4777
4778 /**
4779 * Register (PCICONFIGRC) pcierc#_pl32g_eq_ctl891011
4780 *
4781 * PCIe RC 32.0 GT/s Equalization Control Lane 8/9/1011 Register
4782 * Not supported in QPEM/HPEM.
4783 *
4784 * The Equalization Control register consists of control fields required for per-Lane
4785 * 32.0 GT/s equalization.
4786 *
4787 * Equalization as an RC:
4788 * \<pre\>
4789 * - On speed change from GEN1-\>GEN3, advertise the transmitter preset hint per lane
4790 * to the EP device in the TS2s exchanged. This value comes from the per lane
4791 * upstream port transmitter preset (L*UTP).
4792 * - Upon exit from Recovery Speed, the RC will enter EQ PHASE1 and the RC's
4793 * transmitter will use the per lane downstream port transmitter preset field (L*DTP).
4794 * - While in EQ PHASE 1, the EP & RC device exchange NO presets. They do advertise
4795 * their LF & FS which are needed for the fine tuning stages to follow.
4796 * - For the RC, while in EQ PHASE 2, the EP device makes tuning requests of the RC.
4797 * The RC adjusts its transmitter settings as directed by the EP. The requests are
4798 * communicated via TS1s.
4799 * - Once the EP is satisfied with the tuning, equalization moves to PHASE 3 where
4800 * the RC tunes the EP's remote transmitter.
4801 * Again, the settings are communicated via TS1s but the feedback is provided by
4802 * the RC phy's FOM or direction change indications.
4803 * \</pre\>
4804 */
4805 union ody_pciercx_pl32g_eq_ctl891011 {
4806 uint32_t u;
4807 struct ody_pciercx_pl32g_eq_ctl891011_s {
4808 uint32_t l8dtp : 4;
4809 uint32_t l8utp : 4;
4810 uint32_t l9dtp : 4;
4811 uint32_t l9utp : 4;
4812 uint32_t l10dtp : 4;
4813 uint32_t l10utp : 4;
4814 uint32_t l11dtp : 4;
4815 uint32_t l11utp : 4;
4816 } s;
4817 /* struct ody_pciercx_pl32g_eq_ctl891011_s cn; */
4818 };
4819 typedef union ody_pciercx_pl32g_eq_ctl891011 ody_pciercx_pl32g_eq_ctl891011_t;
4820
4821 static inline uint64_t ODY_PCIERCX_PL32G_EQ_CTL891011(uint64_t a) __attribute__ ((pure, always_inline));
ODY_PCIERCX_PL32G_EQ_CTL891011(uint64_t a)4822 static inline uint64_t ODY_PCIERCX_PL32G_EQ_CTL891011(uint64_t a)
4823 {
4824 if (a <= 15)
4825 return 0x238;
4826 __ody_csr_fatal("PCIERCX_PL32G_EQ_CTL891011", 1, a, 0, 0, 0, 0, 0);
4827 }
4828
4829 #define typedef_ODY_PCIERCX_PL32G_EQ_CTL891011(a) ody_pciercx_pl32g_eq_ctl891011_t
4830 #define bustype_ODY_PCIERCX_PL32G_EQ_CTL891011(a) CSR_TYPE_PCICONFIGRC
4831 #define basename_ODY_PCIERCX_PL32G_EQ_CTL891011(a) "PCIERCX_PL32G_EQ_CTL891011"
4832 #define busnum_ODY_PCIERCX_PL32G_EQ_CTL891011(a) (a)
4833 #define arguments_ODY_PCIERCX_PL32G_EQ_CTL891011(a) (a), -1, -1, -1
4834
4835 /**
4836 * Register (PCICONFIGRC) pcierc#_pl32g_ext_cap_hdr
4837 *
4838 * PCIe RC Pysical Layer 32.0 GT/s Extended Capability Header Register
4839 */
4840 union ody_pciercx_pl32g_ext_cap_hdr {
4841 uint32_t u;
4842 struct ody_pciercx_pl32g_ext_cap_hdr_s {
4843 uint32_t pcieec : 16;
4844 uint32_t cv : 4;
4845 uint32_t nco : 12;
4846 } s;
4847 /* struct ody_pciercx_pl32g_ext_cap_hdr_s cn; */
4848 };
4849 typedef union ody_pciercx_pl32g_ext_cap_hdr ody_pciercx_pl32g_ext_cap_hdr_t;
4850
4851 static inline uint64_t ODY_PCIERCX_PL32G_EXT_CAP_HDR(uint64_t a) __attribute__ ((pure, always_inline));
ODY_PCIERCX_PL32G_EXT_CAP_HDR(uint64_t a)4852 static inline uint64_t ODY_PCIERCX_PL32G_EXT_CAP_HDR(uint64_t a)
4853 {
4854 if (a <= 15)
4855 return 0x210;
4856 __ody_csr_fatal("PCIERCX_PL32G_EXT_CAP_HDR", 1, a, 0, 0, 0, 0, 0);
4857 }
4858
4859 #define typedef_ODY_PCIERCX_PL32G_EXT_CAP_HDR(a) ody_pciercx_pl32g_ext_cap_hdr_t
4860 #define bustype_ODY_PCIERCX_PL32G_EXT_CAP_HDR(a) CSR_TYPE_PCICONFIGRC
4861 #define basename_ODY_PCIERCX_PL32G_EXT_CAP_HDR(a) "PCIERCX_PL32G_EXT_CAP_HDR"
4862 #define busnum_ODY_PCIERCX_PL32G_EXT_CAP_HDR(a) (a)
4863 #define arguments_ODY_PCIERCX_PL32G_EXT_CAP_HDR(a) (a), -1, -1, -1
4864
4865 /**
4866 * Register (PCICONFIGRC) pcierc#_pl32g_rmod_ts_data1
4867 *
4868 * PCIe RC 32.0 GT/s Received Modified TS Data 1 Register
4869 */
4870 union ody_pciercx_pl32g_rmod_ts_data1 {
4871 uint32_t u;
4872 struct ody_pciercx_pl32g_rmod_ts_data1_s {
4873 uint32_t rcvd_mod_ts_use_mode : 3;
4874 uint32_t rcvd_mod_ts_info1 : 13;
4875 uint32_t rcvd_mod_ts_vend_id : 16;
4876 } s;
4877 /* struct ody_pciercx_pl32g_rmod_ts_data1_s cn; */
4878 };
4879 typedef union ody_pciercx_pl32g_rmod_ts_data1 ody_pciercx_pl32g_rmod_ts_data1_t;
4880
4881 static inline uint64_t ODY_PCIERCX_PL32G_RMOD_TS_DATA1(uint64_t a) __attribute__ ((pure, always_inline));
ODY_PCIERCX_PL32G_RMOD_TS_DATA1(uint64_t a)4882 static inline uint64_t ODY_PCIERCX_PL32G_RMOD_TS_DATA1(uint64_t a)
4883 {
4884 if (a <= 15)
4885 return 0x220;
4886 __ody_csr_fatal("PCIERCX_PL32G_RMOD_TS_DATA1", 1, a, 0, 0, 0, 0, 0);
4887 }
4888
4889 #define typedef_ODY_PCIERCX_PL32G_RMOD_TS_DATA1(a) ody_pciercx_pl32g_rmod_ts_data1_t
4890 #define bustype_ODY_PCIERCX_PL32G_RMOD_TS_DATA1(a) CSR_TYPE_PCICONFIGRC
4891 #define basename_ODY_PCIERCX_PL32G_RMOD_TS_DATA1(a) "PCIERCX_PL32G_RMOD_TS_DATA1"
4892 #define busnum_ODY_PCIERCX_PL32G_RMOD_TS_DATA1(a) (a)
4893 #define arguments_ODY_PCIERCX_PL32G_RMOD_TS_DATA1(a) (a), -1, -1, -1
4894
4895 /**
4896 * Register (PCICONFIGRC) pcierc#_pl32g_rmod_ts_data2
4897 *
4898 * PCIe RC 32.0 GT/s Received Modified TS Data 2 Register
4899 */
4900 union ody_pciercx_pl32g_rmod_ts_data2 {
4901 uint32_t u;
4902 struct ody_pciercx_pl32g_rmod_ts_data2_s {
4903 uint32_t rcvd_mod_ts_info2 : 24;
4904 uint32_t rcvd_alt_prot_neg_stat : 2;
4905 uint32_t reserved_26_31 : 6;
4906 } s;
4907 /* struct ody_pciercx_pl32g_rmod_ts_data2_s cn; */
4908 };
4909 typedef union ody_pciercx_pl32g_rmod_ts_data2 ody_pciercx_pl32g_rmod_ts_data2_t;
4910
4911 static inline uint64_t ODY_PCIERCX_PL32G_RMOD_TS_DATA2(uint64_t a) __attribute__ ((pure, always_inline));
ODY_PCIERCX_PL32G_RMOD_TS_DATA2(uint64_t a)4912 static inline uint64_t ODY_PCIERCX_PL32G_RMOD_TS_DATA2(uint64_t a)
4913 {
4914 if (a <= 15)
4915 return 0x224;
4916 __ody_csr_fatal("PCIERCX_PL32G_RMOD_TS_DATA2", 1, a, 0, 0, 0, 0, 0);
4917 }
4918
4919 #define typedef_ODY_PCIERCX_PL32G_RMOD_TS_DATA2(a) ody_pciercx_pl32g_rmod_ts_data2_t
4920 #define bustype_ODY_PCIERCX_PL32G_RMOD_TS_DATA2(a) CSR_TYPE_PCICONFIGRC
4921 #define basename_ODY_PCIERCX_PL32G_RMOD_TS_DATA2(a) "PCIERCX_PL32G_RMOD_TS_DATA2"
4922 #define busnum_ODY_PCIERCX_PL32G_RMOD_TS_DATA2(a) (a)
4923 #define arguments_ODY_PCIERCX_PL32G_RMOD_TS_DATA2(a) (a), -1, -1, -1
4924
4925 /**
4926 * Register (PCICONFIGRC) pcierc#_pl32g_status
4927 *
4928 * PCIe RC 32.0 GT/s Status Register
4929 */
4930 union ody_pciercx_pl32g_status {
4931 uint32_t u;
4932 struct ody_pciercx_pl32g_status_s {
4933 uint32_t eq_32g_cpl : 1;
4934 uint32_t eq_32g_cpl_p1 : 1;
4935 uint32_t eq_32g_cpl_p2 : 1;
4936 uint32_t eq_32g_cpl_p3 : 1;
4937 uint32_t leq_32g_req : 1;
4938 uint32_t mod_ts_rcvd : 1;
4939 uint32_t rcvd_elbc : 2;
4940 uint32_t tx_precode_on : 1;
4941 uint32_t tx_precode_req : 1;
4942 uint32_t no_eq_needed_rcvd : 1;
4943 uint32_t reserved_11_31 : 21;
4944 } s;
4945 /* struct ody_pciercx_pl32g_status_s cn; */
4946 };
4947 typedef union ody_pciercx_pl32g_status ody_pciercx_pl32g_status_t;
4948
4949 static inline uint64_t ODY_PCIERCX_PL32G_STATUS(uint64_t a) __attribute__ ((pure, always_inline));
ODY_PCIERCX_PL32G_STATUS(uint64_t a)4950 static inline uint64_t ODY_PCIERCX_PL32G_STATUS(uint64_t a)
4951 {
4952 if (a <= 15)
4953 return 0x21c;
4954 __ody_csr_fatal("PCIERCX_PL32G_STATUS", 1, a, 0, 0, 0, 0, 0);
4955 }
4956
4957 #define typedef_ODY_PCIERCX_PL32G_STATUS(a) ody_pciercx_pl32g_status_t
4958 #define bustype_ODY_PCIERCX_PL32G_STATUS(a) CSR_TYPE_PCICONFIGRC
4959 #define basename_ODY_PCIERCX_PL32G_STATUS(a) "PCIERCX_PL32G_STATUS"
4960 #define busnum_ODY_PCIERCX_PL32G_STATUS(a) (a)
4961 #define arguments_ODY_PCIERCX_PL32G_STATUS(a) (a), -1, -1, -1
4962
4963 /**
4964 * Register (PCICONFIGRC) pcierc#_pl32g_tmod_ts_data1
4965 *
4966 * PCIe RC 32.0 GT/s Transmitted Modified TS Data 1 Register
4967 */
4968 union ody_pciercx_pl32g_tmod_ts_data1 {
4969 uint32_t u;
4970 struct ody_pciercx_pl32g_tmod_ts_data1_s {
4971 uint32_t tx_mod_ts_use_mode : 3;
4972 uint32_t tx_mod_ts_info1 : 13;
4973 uint32_t tx_mod_ts_vend_id : 16;
4974 } s;
4975 /* struct ody_pciercx_pl32g_tmod_ts_data1_s cn; */
4976 };
4977 typedef union ody_pciercx_pl32g_tmod_ts_data1 ody_pciercx_pl32g_tmod_ts_data1_t;
4978
4979 static inline uint64_t ODY_PCIERCX_PL32G_TMOD_TS_DATA1(uint64_t a) __attribute__ ((pure, always_inline));
ODY_PCIERCX_PL32G_TMOD_TS_DATA1(uint64_t a)4980 static inline uint64_t ODY_PCIERCX_PL32G_TMOD_TS_DATA1(uint64_t a)
4981 {
4982 if (a <= 15)
4983 return 0x228;
4984 __ody_csr_fatal("PCIERCX_PL32G_TMOD_TS_DATA1", 1, a, 0, 0, 0, 0, 0);
4985 }
4986
4987 #define typedef_ODY_PCIERCX_PL32G_TMOD_TS_DATA1(a) ody_pciercx_pl32g_tmod_ts_data1_t
4988 #define bustype_ODY_PCIERCX_PL32G_TMOD_TS_DATA1(a) CSR_TYPE_PCICONFIGRC
4989 #define basename_ODY_PCIERCX_PL32G_TMOD_TS_DATA1(a) "PCIERCX_PL32G_TMOD_TS_DATA1"
4990 #define busnum_ODY_PCIERCX_PL32G_TMOD_TS_DATA1(a) (a)
4991 #define arguments_ODY_PCIERCX_PL32G_TMOD_TS_DATA1(a) (a), -1, -1, -1
4992
4993 /**
4994 * Register (PCICONFIGRC) pcierc#_pl32g_tmod_ts_data2
4995 *
4996 * PCIe RC 32.0 GT/s Transmitted Modified TS Data 2 Register
4997 */
4998 union ody_pciercx_pl32g_tmod_ts_data2 {
4999 uint32_t u;
5000 struct ody_pciercx_pl32g_tmod_ts_data2_s {
5001 uint32_t tx_mod_ts_info2 : 24;
5002 uint32_t tx_alt_prot_neg_stat : 2;
5003 uint32_t reserved_26_31 : 6;
5004 } s;
5005 /* struct ody_pciercx_pl32g_tmod_ts_data2_s cn; */
5006 };
5007 typedef union ody_pciercx_pl32g_tmod_ts_data2 ody_pciercx_pl32g_tmod_ts_data2_t;
5008
5009 static inline uint64_t ODY_PCIERCX_PL32G_TMOD_TS_DATA2(uint64_t a) __attribute__ ((pure, always_inline));
ODY_PCIERCX_PL32G_TMOD_TS_DATA2(uint64_t a)5010 static inline uint64_t ODY_PCIERCX_PL32G_TMOD_TS_DATA2(uint64_t a)
5011 {
5012 if (a <= 15)
5013 return 0x22c;
5014 __ody_csr_fatal("PCIERCX_PL32G_TMOD_TS_DATA2", 1, a, 0, 0, 0, 0, 0);
5015 }
5016
5017 #define typedef_ODY_PCIERCX_PL32G_TMOD_TS_DATA2(a) ody_pciercx_pl32g_tmod_ts_data2_t
5018 #define bustype_ODY_PCIERCX_PL32G_TMOD_TS_DATA2(a) CSR_TYPE_PCICONFIGRC
5019 #define basename_ODY_PCIERCX_PL32G_TMOD_TS_DATA2(a) "PCIERCX_PL32G_TMOD_TS_DATA2"
5020 #define busnum_ODY_PCIERCX_PL32G_TMOD_TS_DATA2(a) (a)
5021 #define arguments_ODY_PCIERCX_PL32G_TMOD_TS_DATA2(a) (a), -1, -1, -1
5022
5023 /**
5024 * Register (PCICONFIGRC) pcierc#_pm_cap_id
5025 *
5026 * PCIe RC Power Management Capability ID Register
5027 */
5028 union ody_pciercx_pm_cap_id {
5029 uint32_t u;
5030 struct ody_pciercx_pm_cap_id_s {
5031 uint32_t pmcid : 8;
5032 uint32_t ncp : 8;
5033 uint32_t pmsv : 3;
5034 uint32_t pme_clock : 1;
5035 uint32_t reserved_20 : 1;
5036 uint32_t dsi : 1;
5037 uint32_t auxc : 3;
5038 uint32_t d1s : 1;
5039 uint32_t d2s : 1;
5040 uint32_t pmes : 5;
5041 } s;
5042 /* struct ody_pciercx_pm_cap_id_s cn; */
5043 };
5044 typedef union ody_pciercx_pm_cap_id ody_pciercx_pm_cap_id_t;
5045
5046 static inline uint64_t ODY_PCIERCX_PM_CAP_ID(uint64_t a) __attribute__ ((pure, always_inline));
ODY_PCIERCX_PM_CAP_ID(uint64_t a)5047 static inline uint64_t ODY_PCIERCX_PM_CAP_ID(uint64_t a)
5048 {
5049 if (a <= 15)
5050 return 0x40;
5051 __ody_csr_fatal("PCIERCX_PM_CAP_ID", 1, a, 0, 0, 0, 0, 0);
5052 }
5053
5054 #define typedef_ODY_PCIERCX_PM_CAP_ID(a) ody_pciercx_pm_cap_id_t
5055 #define bustype_ODY_PCIERCX_PM_CAP_ID(a) CSR_TYPE_PCICONFIGRC
5056 #define basename_ODY_PCIERCX_PM_CAP_ID(a) "PCIERCX_PM_CAP_ID"
5057 #define busnum_ODY_PCIERCX_PM_CAP_ID(a) (a)
5058 #define arguments_ODY_PCIERCX_PM_CAP_ID(a) (a), -1, -1, -1
5059
5060 /**
5061 * Register (PCICONFIGRC) pcierc#_pm_ctl
5062 *
5063 * PCIe RC Power Management Control and Status Register
5064 */
5065 union ody_pciercx_pm_ctl {
5066 uint32_t u;
5067 struct ody_pciercx_pm_ctl_s {
5068 uint32_t ps : 2;
5069 uint32_t reserved_2 : 1;
5070 uint32_t nsr : 1;
5071 uint32_t reserved_4_7 : 4;
5072 uint32_t pmeens : 1;
5073 uint32_t pmds : 4;
5074 uint32_t pmedsia : 2;
5075 uint32_t pmess : 1;
5076 uint32_t reserved_16_21 : 6;
5077 uint32_t bd3h : 1;
5078 uint32_t bpccee : 1;
5079 uint32_t pmdia : 8;
5080 } s;
5081 /* struct ody_pciercx_pm_ctl_s cn; */
5082 };
5083 typedef union ody_pciercx_pm_ctl ody_pciercx_pm_ctl_t;
5084
5085 static inline uint64_t ODY_PCIERCX_PM_CTL(uint64_t a) __attribute__ ((pure, always_inline));
ODY_PCIERCX_PM_CTL(uint64_t a)5086 static inline uint64_t ODY_PCIERCX_PM_CTL(uint64_t a)
5087 {
5088 if (a <= 15)
5089 return 0x44;
5090 __ody_csr_fatal("PCIERCX_PM_CTL", 1, a, 0, 0, 0, 0, 0);
5091 }
5092
5093 #define typedef_ODY_PCIERCX_PM_CTL(a) ody_pciercx_pm_ctl_t
5094 #define bustype_ODY_PCIERCX_PM_CTL(a) CSR_TYPE_PCICONFIGRC
5095 #define basename_ODY_PCIERCX_PM_CTL(a) "PCIERCX_PM_CTL"
5096 #define busnum_ODY_PCIERCX_PM_CTL(a) (a)
5097 #define arguments_ODY_PCIERCX_PM_CTL(a) (a), -1, -1, -1
5098
5099 /**
5100 * Register (PCICONFIGRC) pcierc#_pmem
5101 *
5102 * PCIe RC Prefetchable Memory and Limit Register
5103 */
5104 union ody_pciercx_pmem {
5105 uint32_t u;
5106 struct ody_pciercx_pmem_s {
5107 uint32_t mem64a : 1;
5108 uint32_t reserved_1_3 : 3;
5109 uint32_t lmem_base : 12;
5110 uint32_t mem64b : 1;
5111 uint32_t reserved_17_19 : 3;
5112 uint32_t lmem_limit : 12;
5113 } s;
5114 /* struct ody_pciercx_pmem_s cn; */
5115 };
5116 typedef union ody_pciercx_pmem ody_pciercx_pmem_t;
5117
5118 static inline uint64_t ODY_PCIERCX_PMEM(uint64_t a) __attribute__ ((pure, always_inline));
ODY_PCIERCX_PMEM(uint64_t a)5119 static inline uint64_t ODY_PCIERCX_PMEM(uint64_t a)
5120 {
5121 if (a <= 15)
5122 return 0x24;
5123 __ody_csr_fatal("PCIERCX_PMEM", 1, a, 0, 0, 0, 0, 0);
5124 }
5125
5126 #define typedef_ODY_PCIERCX_PMEM(a) ody_pciercx_pmem_t
5127 #define bustype_ODY_PCIERCX_PMEM(a) CSR_TYPE_PCICONFIGRC
5128 #define basename_ODY_PCIERCX_PMEM(a) "PCIERCX_PMEM"
5129 #define busnum_ODY_PCIERCX_PMEM(a) (a)
5130 #define arguments_ODY_PCIERCX_PMEM(a) (a), -1, -1, -1
5131
5132 /**
5133 * Register (PCICONFIGRC) pcierc#_port_ctl
5134 *
5135 * PCIe RC Port Link Control Register
5136 */
5137 union ody_pciercx_port_ctl {
5138 uint32_t u;
5139 struct ody_pciercx_port_ctl_s {
5140 uint32_t omr : 1;
5141 uint32_t sd : 1;
5142 uint32_t le : 1;
5143 uint32_t ra : 1;
5144 uint32_t reserved_4 : 1;
5145 uint32_t dllle : 1;
5146 uint32_t ldis : 1;
5147 uint32_t flm : 1;
5148 uint32_t link_rate : 4;
5149 uint32_t reserved_12_15 : 4;
5150 uint32_t lme : 6;
5151 uint32_t cle : 2;
5152 uint32_t beacon_en : 1;
5153 uint32_t clcrc_en : 1;
5154 uint32_t ex_synch : 1;
5155 uint32_t xlr_en : 1;
5156 uint32_t reserved_28_31 : 4;
5157 } s;
5158 /* struct ody_pciercx_port_ctl_s cn; */
5159 };
5160 typedef union ody_pciercx_port_ctl ody_pciercx_port_ctl_t;
5161
5162 static inline uint64_t ODY_PCIERCX_PORT_CTL(uint64_t a) __attribute__ ((pure, always_inline));
ODY_PCIERCX_PORT_CTL(uint64_t a)5163 static inline uint64_t ODY_PCIERCX_PORT_CTL(uint64_t a)
5164 {
5165 if (a <= 15)
5166 return 0x710;
5167 __ody_csr_fatal("PCIERCX_PORT_CTL", 1, a, 0, 0, 0, 0, 0);
5168 }
5169
5170 #define typedef_ODY_PCIERCX_PORT_CTL(a) ody_pciercx_port_ctl_t
5171 #define bustype_ODY_PCIERCX_PORT_CTL(a) CSR_TYPE_PCICONFIGRC
5172 #define basename_ODY_PCIERCX_PORT_CTL(a) "PCIERCX_PORT_CTL"
5173 #define busnum_ODY_PCIERCX_PORT_CTL(a) (a)
5174 #define arguments_ODY_PCIERCX_PORT_CTL(a) (a), -1, -1, -1
5175
5176 /**
5177 * Register (PCICONFIGRC) pcierc#_port_flink
5178 *
5179 * PCIe RC Port Force Link Register
5180 */
5181 union ody_pciercx_port_flink {
5182 uint32_t u;
5183 struct ody_pciercx_port_flink_s {
5184 uint32_t link_num : 8;
5185 uint32_t forced_ltssm : 4;
5186 uint32_t reserved_12_14 : 3;
5187 uint32_t force_link : 1;
5188 uint32_t link_state : 6;
5189 uint32_t supp_planes_rxei_exit : 1;
5190 uint32_t deskew_for_sris : 1;
5191 uint32_t reserved_24_31 : 8;
5192 } s;
5193 /* struct ody_pciercx_port_flink_s cn; */
5194 };
5195 typedef union ody_pciercx_port_flink ody_pciercx_port_flink_t;
5196
5197 static inline uint64_t ODY_PCIERCX_PORT_FLINK(uint64_t a) __attribute__ ((pure, always_inline));
ODY_PCIERCX_PORT_FLINK(uint64_t a)5198 static inline uint64_t ODY_PCIERCX_PORT_FLINK(uint64_t a)
5199 {
5200 if (a <= 15)
5201 return 0x708;
5202 __ody_csr_fatal("PCIERCX_PORT_FLINK", 1, a, 0, 0, 0, 0, 0);
5203 }
5204
5205 #define typedef_ODY_PCIERCX_PORT_FLINK(a) ody_pciercx_port_flink_t
5206 #define bustype_ODY_PCIERCX_PORT_FLINK(a) CSR_TYPE_PCICONFIGRC
5207 #define basename_ODY_PCIERCX_PORT_FLINK(a) "PCIERCX_PORT_FLINK"
5208 #define busnum_ODY_PCIERCX_PORT_FLINK(a) (a)
5209 #define arguments_ODY_PCIERCX_PORT_FLINK(a) (a), -1, -1, -1
5210
5211 /**
5212 * Register (PCICONFIGRC) pcierc#_pre_base
5213 *
5214 * PCIe RC Prefetchable Base Upper 32 Bits Register
5215 */
5216 union ody_pciercx_pre_base {
5217 uint32_t u;
5218 struct ody_pciercx_pre_base_s {
5219 uint32_t umem_base : 32;
5220 } s;
5221 /* struct ody_pciercx_pre_base_s cn; */
5222 };
5223 typedef union ody_pciercx_pre_base ody_pciercx_pre_base_t;
5224
5225 static inline uint64_t ODY_PCIERCX_PRE_BASE(uint64_t a) __attribute__ ((pure, always_inline));
ODY_PCIERCX_PRE_BASE(uint64_t a)5226 static inline uint64_t ODY_PCIERCX_PRE_BASE(uint64_t a)
5227 {
5228 if (a <= 15)
5229 return 0x28;
5230 __ody_csr_fatal("PCIERCX_PRE_BASE", 1, a, 0, 0, 0, 0, 0);
5231 }
5232
5233 #define typedef_ODY_PCIERCX_PRE_BASE(a) ody_pciercx_pre_base_t
5234 #define bustype_ODY_PCIERCX_PRE_BASE(a) CSR_TYPE_PCICONFIGRC
5235 #define basename_ODY_PCIERCX_PRE_BASE(a) "PCIERCX_PRE_BASE"
5236 #define busnum_ODY_PCIERCX_PRE_BASE(a) (a)
5237 #define arguments_ODY_PCIERCX_PRE_BASE(a) (a), -1, -1, -1
5238
5239 /**
5240 * Register (PCICONFIGRC) pcierc#_pre_limit
5241 *
5242 * PCIe RC Prefetchable Limit Upper 32 Bits Register
5243 */
5244 union ody_pciercx_pre_limit {
5245 uint32_t u;
5246 struct ody_pciercx_pre_limit_s {
5247 uint32_t umem_limit : 32;
5248 } s;
5249 /* struct ody_pciercx_pre_limit_s cn; */
5250 };
5251 typedef union ody_pciercx_pre_limit ody_pciercx_pre_limit_t;
5252
5253 static inline uint64_t ODY_PCIERCX_PRE_LIMIT(uint64_t a) __attribute__ ((pure, always_inline));
ODY_PCIERCX_PRE_LIMIT(uint64_t a)5254 static inline uint64_t ODY_PCIERCX_PRE_LIMIT(uint64_t a)
5255 {
5256 if (a <= 15)
5257 return 0x2c;
5258 __ody_csr_fatal("PCIERCX_PRE_LIMIT", 1, a, 0, 0, 0, 0, 0);
5259 }
5260
5261 #define typedef_ODY_PCIERCX_PRE_LIMIT(a) ody_pciercx_pre_limit_t
5262 #define bustype_ODY_PCIERCX_PRE_LIMIT(a) CSR_TYPE_PCICONFIGRC
5263 #define basename_ODY_PCIERCX_PRE_LIMIT(a) "PCIERCX_PRE_LIMIT"
5264 #define busnum_ODY_PCIERCX_PRE_LIMIT(a) (a)
5265 #define arguments_ODY_PCIERCX_PRE_LIMIT(a) (a), -1, -1, -1
5266
5267 /**
5268 * Register (PCICONFIGRC) pcierc#_ptm_cap
5269 *
5270 * PCIe RC Precision Time Measurement Capabilities Register
5271 */
5272 union ody_pciercx_ptm_cap {
5273 uint32_t u;
5274 struct ody_pciercx_ptm_cap_s {
5275 uint32_t rqc : 1;
5276 uint32_t rsc : 1;
5277 uint32_t rtc : 1;
5278 uint32_t eptm : 1;
5279 uint32_t reserved_4_7 : 4;
5280 uint32_t clkg : 8;
5281 uint32_t reserved_16_31 : 16;
5282 } s;
5283 /* struct ody_pciercx_ptm_cap_s cn; */
5284 };
5285 typedef union ody_pciercx_ptm_cap ody_pciercx_ptm_cap_t;
5286
5287 static inline uint64_t ODY_PCIERCX_PTM_CAP(uint64_t a) __attribute__ ((pure, always_inline));
ODY_PCIERCX_PTM_CAP(uint64_t a)5288 static inline uint64_t ODY_PCIERCX_PTM_CAP(uint64_t a)
5289 {
5290 if (a <= 15)
5291 return 0x3b4;
5292 __ody_csr_fatal("PCIERCX_PTM_CAP", 1, a, 0, 0, 0, 0, 0);
5293 }
5294
5295 #define typedef_ODY_PCIERCX_PTM_CAP(a) ody_pciercx_ptm_cap_t
5296 #define bustype_ODY_PCIERCX_PTM_CAP(a) CSR_TYPE_PCICONFIGRC
5297 #define basename_ODY_PCIERCX_PTM_CAP(a) "PCIERCX_PTM_CAP"
5298 #define busnum_ODY_PCIERCX_PTM_CAP(a) (a)
5299 #define arguments_ODY_PCIERCX_PTM_CAP(a) (a), -1, -1, -1
5300
5301 /**
5302 * Register (PCICONFIGRC) pcierc#_ptm_ctl
5303 *
5304 * PCIe RC Precision Time Measurement Control Register
5305 */
5306 union ody_pciercx_ptm_ctl {
5307 uint32_t u;
5308 struct ody_pciercx_ptm_ctl_s {
5309 uint32_t en : 1;
5310 uint32_t rt_sel : 1;
5311 uint32_t reserved_2_7 : 6;
5312 uint32_t eff_gran : 8;
5313 uint32_t reserved_16_31 : 16;
5314 } s;
5315 /* struct ody_pciercx_ptm_ctl_s cn; */
5316 };
5317 typedef union ody_pciercx_ptm_ctl ody_pciercx_ptm_ctl_t;
5318
5319 static inline uint64_t ODY_PCIERCX_PTM_CTL(uint64_t a) __attribute__ ((pure, always_inline));
ODY_PCIERCX_PTM_CTL(uint64_t a)5320 static inline uint64_t ODY_PCIERCX_PTM_CTL(uint64_t a)
5321 {
5322 if (a <= 15)
5323 return 0x3b8;
5324 __ody_csr_fatal("PCIERCX_PTM_CTL", 1, a, 0, 0, 0, 0, 0);
5325 }
5326
5327 #define typedef_ODY_PCIERCX_PTM_CTL(a) ody_pciercx_ptm_ctl_t
5328 #define bustype_ODY_PCIERCX_PTM_CTL(a) CSR_TYPE_PCICONFIGRC
5329 #define basename_ODY_PCIERCX_PTM_CTL(a) "PCIERCX_PTM_CTL"
5330 #define busnum_ODY_PCIERCX_PTM_CTL(a) (a)
5331 #define arguments_ODY_PCIERCX_PTM_CTL(a) (a), -1, -1, -1
5332
5333 /**
5334 * Register (PCICONFIGRC) pcierc#_ptm_ext_cap_hdr
5335 *
5336 * PCIe RC Precision Time Measurement Capability Header Register
5337 */
5338 union ody_pciercx_ptm_ext_cap_hdr {
5339 uint32_t u;
5340 struct ody_pciercx_ptm_ext_cap_hdr_s {
5341 uint32_t pcieec : 16;
5342 uint32_t cv : 4;
5343 uint32_t nco : 12;
5344 } s;
5345 /* struct ody_pciercx_ptm_ext_cap_hdr_s cn; */
5346 };
5347 typedef union ody_pciercx_ptm_ext_cap_hdr ody_pciercx_ptm_ext_cap_hdr_t;
5348
5349 static inline uint64_t ODY_PCIERCX_PTM_EXT_CAP_HDR(uint64_t a) __attribute__ ((pure, always_inline));
ODY_PCIERCX_PTM_EXT_CAP_HDR(uint64_t a)5350 static inline uint64_t ODY_PCIERCX_PTM_EXT_CAP_HDR(uint64_t a)
5351 {
5352 if (a <= 15)
5353 return 0x3b0;
5354 __ody_csr_fatal("PCIERCX_PTM_EXT_CAP_HDR", 1, a, 0, 0, 0, 0, 0);
5355 }
5356
5357 #define typedef_ODY_PCIERCX_PTM_EXT_CAP_HDR(a) ody_pciercx_ptm_ext_cap_hdr_t
5358 #define bustype_ODY_PCIERCX_PTM_EXT_CAP_HDR(a) CSR_TYPE_PCICONFIGRC
5359 #define basename_ODY_PCIERCX_PTM_EXT_CAP_HDR(a) "PCIERCX_PTM_EXT_CAP_HDR"
5360 #define busnum_ODY_PCIERCX_PTM_EXT_CAP_HDR(a) (a)
5361 #define arguments_ODY_PCIERCX_PTM_EXT_CAP_HDR(a) (a), -1, -1, -1
5362
5363 /**
5364 * Register (PCICONFIGRC) pcierc#_ptm_res_cap_hdr
5365 *
5366 * PCIe RC Precision Time Measurement Responder Capability Header Register
5367 */
5368 union ody_pciercx_ptm_res_cap_hdr {
5369 uint32_t u;
5370 struct ody_pciercx_ptm_res_cap_hdr_s {
5371 uint32_t pcieec : 16;
5372 uint32_t cv : 4;
5373 uint32_t nco : 12;
5374 } s;
5375 /* struct ody_pciercx_ptm_res_cap_hdr_s cn; */
5376 };
5377 typedef union ody_pciercx_ptm_res_cap_hdr ody_pciercx_ptm_res_cap_hdr_t;
5378
5379 static inline uint64_t ODY_PCIERCX_PTM_RES_CAP_HDR(uint64_t a) __attribute__ ((pure, always_inline));
ODY_PCIERCX_PTM_RES_CAP_HDR(uint64_t a)5380 static inline uint64_t ODY_PCIERCX_PTM_RES_CAP_HDR(uint64_t a)
5381 {
5382 if (a <= 15)
5383 return 0x3bc;
5384 __ody_csr_fatal("PCIERCX_PTM_RES_CAP_HDR", 1, a, 0, 0, 0, 0, 0);
5385 }
5386
5387 #define typedef_ODY_PCIERCX_PTM_RES_CAP_HDR(a) ody_pciercx_ptm_res_cap_hdr_t
5388 #define bustype_ODY_PCIERCX_PTM_RES_CAP_HDR(a) CSR_TYPE_PCICONFIGRC
5389 #define basename_ODY_PCIERCX_PTM_RES_CAP_HDR(a) "PCIERCX_PTM_RES_CAP_HDR"
5390 #define busnum_ODY_PCIERCX_PTM_RES_CAP_HDR(a) (a)
5391 #define arguments_ODY_PCIERCX_PTM_RES_CAP_HDR(a) (a), -1, -1, -1
5392
5393 /**
5394 * Register (PCICONFIGRC) pcierc#_ptm_res_ctl
5395 *
5396 * PCIe RC Precision Time Measurement Responder Control Register
5397 */
5398 union ody_pciercx_ptm_res_ctl {
5399 uint32_t u;
5400 struct ody_pciercx_ptm_res_ctl_s {
5401 uint32_t pres_ctx_vld : 1;
5402 uint32_t pd_byterev : 1;
5403 uint32_t reserved_2_31 : 30;
5404 } s;
5405 /* struct ody_pciercx_ptm_res_ctl_s cn; */
5406 };
5407 typedef union ody_pciercx_ptm_res_ctl ody_pciercx_ptm_res_ctl_t;
5408
5409 static inline uint64_t ODY_PCIERCX_PTM_RES_CTL(uint64_t a) __attribute__ ((pure, always_inline));
ODY_PCIERCX_PTM_RES_CTL(uint64_t a)5410 static inline uint64_t ODY_PCIERCX_PTM_RES_CTL(uint64_t a)
5411 {
5412 if (a <= 15)
5413 return 0x3c4;
5414 __ody_csr_fatal("PCIERCX_PTM_RES_CTL", 1, a, 0, 0, 0, 0, 0);
5415 }
5416
5417 #define typedef_ODY_PCIERCX_PTM_RES_CTL(a) ody_pciercx_ptm_res_ctl_t
5418 #define bustype_ODY_PCIERCX_PTM_RES_CTL(a) CSR_TYPE_PCICONFIGRC
5419 #define basename_ODY_PCIERCX_PTM_RES_CTL(a) "PCIERCX_PTM_RES_CTL"
5420 #define busnum_ODY_PCIERCX_PTM_RES_CTL(a) (a)
5421 #define arguments_ODY_PCIERCX_PTM_RES_CTL(a) (a), -1, -1, -1
5422
5423 /**
5424 * Register (PCICONFIGRC) pcierc#_ptm_res_hdr
5425 *
5426 * PCIe RC Precision Time Measurement Responder Vendor Specific Header Register
5427 */
5428 union ody_pciercx_ptm_res_hdr {
5429 uint32_t u;
5430 struct ody_pciercx_ptm_res_hdr_s {
5431 uint32_t vid : 16;
5432 uint32_t vrev : 4;
5433 uint32_t vlen : 12;
5434 } s;
5435 /* struct ody_pciercx_ptm_res_hdr_s cn; */
5436 };
5437 typedef union ody_pciercx_ptm_res_hdr ody_pciercx_ptm_res_hdr_t;
5438
5439 static inline uint64_t ODY_PCIERCX_PTM_RES_HDR(uint64_t a) __attribute__ ((pure, always_inline));
ODY_PCIERCX_PTM_RES_HDR(uint64_t a)5440 static inline uint64_t ODY_PCIERCX_PTM_RES_HDR(uint64_t a)
5441 {
5442 if (a <= 15)
5443 return 0x3c0;
5444 __ody_csr_fatal("PCIERCX_PTM_RES_HDR", 1, a, 0, 0, 0, 0, 0);
5445 }
5446
5447 #define typedef_ODY_PCIERCX_PTM_RES_HDR(a) ody_pciercx_ptm_res_hdr_t
5448 #define bustype_ODY_PCIERCX_PTM_RES_HDR(a) CSR_TYPE_PCICONFIGRC
5449 #define basename_ODY_PCIERCX_PTM_RES_HDR(a) "PCIERCX_PTM_RES_HDR"
5450 #define busnum_ODY_PCIERCX_PTM_RES_HDR(a) (a)
5451 #define arguments_ODY_PCIERCX_PTM_RES_HDR(a) (a), -1, -1, -1
5452
5453 /**
5454 * Register (PCICONFIGRC) pcierc#_ptm_res_latency_sel
5455 *
5456 * PCIe RC PTM Responder Latency Register Select Register
5457 */
5458 union ody_pciercx_ptm_res_latency_sel {
5459 uint32_t u;
5460 struct ody_pciercx_ptm_res_latency_sel_s {
5461 uint32_t lat_reg_sel : 4;
5462 uint32_t reserved_4_31 : 28;
5463 } s;
5464 /* struct ody_pciercx_ptm_res_latency_sel_s cn; */
5465 };
5466 typedef union ody_pciercx_ptm_res_latency_sel ody_pciercx_ptm_res_latency_sel_t;
5467
5468 static inline uint64_t ODY_PCIERCX_PTM_RES_LATENCY_SEL(uint64_t a) __attribute__ ((pure, always_inline));
ODY_PCIERCX_PTM_RES_LATENCY_SEL(uint64_t a)5469 static inline uint64_t ODY_PCIERCX_PTM_RES_LATENCY_SEL(uint64_t a)
5470 {
5471 if (a <= 15)
5472 return 0x404;
5473 __ody_csr_fatal("PCIERCX_PTM_RES_LATENCY_SEL", 1, a, 0, 0, 0, 0, 0);
5474 }
5475
5476 #define typedef_ODY_PCIERCX_PTM_RES_LATENCY_SEL(a) ody_pciercx_ptm_res_latency_sel_t
5477 #define bustype_ODY_PCIERCX_PTM_RES_LATENCY_SEL(a) CSR_TYPE_PCICONFIGRC
5478 #define basename_ODY_PCIERCX_PTM_RES_LATENCY_SEL(a) "PCIERCX_PTM_RES_LATENCY_SEL"
5479 #define busnum_ODY_PCIERCX_PTM_RES_LATENCY_SEL(a) (a)
5480 #define arguments_ODY_PCIERCX_PTM_RES_LATENCY_SEL(a) (a), -1, -1, -1
5481
5482 /**
5483 * Register (PCICONFIGRC) pcierc#_ptm_res_local_lsb
5484 *
5485 * PCIe RC PTM Responder Local Clock LSB Register
5486 */
5487 union ody_pciercx_ptm_res_local_lsb {
5488 uint32_t u;
5489 struct ody_pciercx_ptm_res_local_lsb_s {
5490 uint32_t clk_lsb : 32;
5491 } s;
5492 /* struct ody_pciercx_ptm_res_local_lsb_s cn; */
5493 };
5494 typedef union ody_pciercx_ptm_res_local_lsb ody_pciercx_ptm_res_local_lsb_t;
5495
5496 static inline uint64_t ODY_PCIERCX_PTM_RES_LOCAL_LSB(uint64_t a) __attribute__ ((pure, always_inline));
ODY_PCIERCX_PTM_RES_LOCAL_LSB(uint64_t a)5497 static inline uint64_t ODY_PCIERCX_PTM_RES_LOCAL_LSB(uint64_t a)
5498 {
5499 if (a <= 15)
5500 return 0x3cc;
5501 __ody_csr_fatal("PCIERCX_PTM_RES_LOCAL_LSB", 1, a, 0, 0, 0, 0, 0);
5502 }
5503
5504 #define typedef_ODY_PCIERCX_PTM_RES_LOCAL_LSB(a) ody_pciercx_ptm_res_local_lsb_t
5505 #define bustype_ODY_PCIERCX_PTM_RES_LOCAL_LSB(a) CSR_TYPE_PCICONFIGRC
5506 #define basename_ODY_PCIERCX_PTM_RES_LOCAL_LSB(a) "PCIERCX_PTM_RES_LOCAL_LSB"
5507 #define busnum_ODY_PCIERCX_PTM_RES_LOCAL_LSB(a) (a)
5508 #define arguments_ODY_PCIERCX_PTM_RES_LOCAL_LSB(a) (a), -1, -1, -1
5509
5510 /**
5511 * Register (PCICONFIGRC) pcierc#_ptm_res_local_msb
5512 *
5513 * PCIe RC PTM Responder Local Clock MSB Register
5514 */
5515 union ody_pciercx_ptm_res_local_msb {
5516 uint32_t u;
5517 struct ody_pciercx_ptm_res_local_msb_s {
5518 uint32_t clk_msb : 32;
5519 } s;
5520 /* struct ody_pciercx_ptm_res_local_msb_s cn; */
5521 };
5522 typedef union ody_pciercx_ptm_res_local_msb ody_pciercx_ptm_res_local_msb_t;
5523
5524 static inline uint64_t ODY_PCIERCX_PTM_RES_LOCAL_MSB(uint64_t a) __attribute__ ((pure, always_inline));
ODY_PCIERCX_PTM_RES_LOCAL_MSB(uint64_t a)5525 static inline uint64_t ODY_PCIERCX_PTM_RES_LOCAL_MSB(uint64_t a)
5526 {
5527 if (a <= 15)
5528 return 0x3d0;
5529 __ody_csr_fatal("PCIERCX_PTM_RES_LOCAL_MSB", 1, a, 0, 0, 0, 0, 0);
5530 }
5531
5532 #define typedef_ODY_PCIERCX_PTM_RES_LOCAL_MSB(a) ody_pciercx_ptm_res_local_msb_t
5533 #define bustype_ODY_PCIERCX_PTM_RES_LOCAL_MSB(a) CSR_TYPE_PCICONFIGRC
5534 #define basename_ODY_PCIERCX_PTM_RES_LOCAL_MSB(a) "PCIERCX_PTM_RES_LOCAL_MSB"
5535 #define busnum_ODY_PCIERCX_PTM_RES_LOCAL_MSB(a) (a)
5536 #define arguments_ODY_PCIERCX_PTM_RES_LOCAL_MSB(a) (a), -1, -1, -1
5537
5538 /**
5539 * Register (PCICONFIGRC) pcierc#_ptm_res_nom_clk_t
5540 *
5541 * PCIe RC PTM Responder Nominal Clock Period Register
5542 */
5543 union ody_pciercx_ptm_res_nom_clk_t {
5544 uint32_t u;
5545 struct ody_pciercx_ptm_res_nom_clk_t_s {
5546 uint32_t clk_t_frac : 16;
5547 uint32_t clk_t_int : 8;
5548 uint32_t reserved_24_31 : 8;
5549 } s;
5550 /* struct ody_pciercx_ptm_res_nom_clk_t_s cn; */
5551 };
5552 typedef union ody_pciercx_ptm_res_nom_clk_t ody_pciercx_ptm_res_nom_clk_t_t;
5553
5554 static inline uint64_t ODY_PCIERCX_PTM_RES_NOM_CLK_T(uint64_t a) __attribute__ ((pure, always_inline));
ODY_PCIERCX_PTM_RES_NOM_CLK_T(uint64_t a)5555 static inline uint64_t ODY_PCIERCX_PTM_RES_NOM_CLK_T(uint64_t a)
5556 {
5557 if (a <= 15)
5558 return 0x3fc;
5559 __ody_csr_fatal("PCIERCX_PTM_RES_NOM_CLK_T", 1, a, 0, 0, 0, 0, 0);
5560 }
5561
5562 #define typedef_ODY_PCIERCX_PTM_RES_NOM_CLK_T(a) ody_pciercx_ptm_res_nom_clk_t_t
5563 #define bustype_ODY_PCIERCX_PTM_RES_NOM_CLK_T(a) CSR_TYPE_PCICONFIGRC
5564 #define basename_ODY_PCIERCX_PTM_RES_NOM_CLK_T(a) "PCIERCX_PTM_RES_NOM_CLK_T"
5565 #define busnum_ODY_PCIERCX_PTM_RES_NOM_CLK_T(a) (a)
5566 #define arguments_ODY_PCIERCX_PTM_RES_NOM_CLK_T(a) (a), -1, -1, -1
5567
5568 /**
5569 * Register (PCICONFIGRC) pcierc#_ptm_res_rx_latency
5570 *
5571 * PCIe RC PTM Responder RX Latency Register
5572 */
5573 union ody_pciercx_ptm_res_rx_latency {
5574 uint32_t u;
5575 struct ody_pciercx_ptm_res_rx_latency_s {
5576 uint32_t rx_lat : 12;
5577 uint32_t reserved_12_31 : 20;
5578 } s;
5579 /* struct ody_pciercx_ptm_res_rx_latency_s cn; */
5580 };
5581 typedef union ody_pciercx_ptm_res_rx_latency ody_pciercx_ptm_res_rx_latency_t;
5582
5583 static inline uint64_t ODY_PCIERCX_PTM_RES_RX_LATENCY(uint64_t a) __attribute__ ((pure, always_inline));
ODY_PCIERCX_PTM_RES_RX_LATENCY(uint64_t a)5584 static inline uint64_t ODY_PCIERCX_PTM_RES_RX_LATENCY(uint64_t a)
5585 {
5586 if (a <= 15)
5587 return 0x3f8;
5588 __ody_csr_fatal("PCIERCX_PTM_RES_RX_LATENCY", 1, a, 0, 0, 0, 0, 0);
5589 }
5590
5591 #define typedef_ODY_PCIERCX_PTM_RES_RX_LATENCY(a) ody_pciercx_ptm_res_rx_latency_t
5592 #define bustype_ODY_PCIERCX_PTM_RES_RX_LATENCY(a) CSR_TYPE_PCICONFIGRC
5593 #define basename_ODY_PCIERCX_PTM_RES_RX_LATENCY(a) "PCIERCX_PTM_RES_RX_LATENCY"
5594 #define busnum_ODY_PCIERCX_PTM_RES_RX_LATENCY(a) (a)
5595 #define arguments_ODY_PCIERCX_PTM_RES_RX_LATENCY(a) (a), -1, -1, -1
5596
5597 /**
5598 * Register (PCICONFIGRC) pcierc#_ptm_res_scaled_clk_t
5599 *
5600 * PCIe RC PTM Responder Scaled Clock Period Register
5601 */
5602 union ody_pciercx_ptm_res_scaled_clk_t {
5603 uint32_t u;
5604 struct ody_pciercx_ptm_res_scaled_clk_t_s {
5605 uint32_t sclk_t_frac : 16;
5606 uint32_t sclk_t_int : 8;
5607 uint32_t reserved_24_30 : 7;
5608 uint32_t sclk_t_en : 1;
5609 } s;
5610 /* struct ody_pciercx_ptm_res_scaled_clk_t_s cn; */
5611 };
5612 typedef union ody_pciercx_ptm_res_scaled_clk_t ody_pciercx_ptm_res_scaled_clk_t_t;
5613
5614 static inline uint64_t ODY_PCIERCX_PTM_RES_SCALED_CLK_T(uint64_t a) __attribute__ ((pure, always_inline));
ODY_PCIERCX_PTM_RES_SCALED_CLK_T(uint64_t a)5615 static inline uint64_t ODY_PCIERCX_PTM_RES_SCALED_CLK_T(uint64_t a)
5616 {
5617 if (a <= 15)
5618 return 0x400;
5619 __ody_csr_fatal("PCIERCX_PTM_RES_SCALED_CLK_T", 1, a, 0, 0, 0, 0, 0);
5620 }
5621
5622 #define typedef_ODY_PCIERCX_PTM_RES_SCALED_CLK_T(a) ody_pciercx_ptm_res_scaled_clk_t_t
5623 #define bustype_ODY_PCIERCX_PTM_RES_SCALED_CLK_T(a) CSR_TYPE_PCICONFIGRC
5624 #define basename_ODY_PCIERCX_PTM_RES_SCALED_CLK_T(a) "PCIERCX_PTM_RES_SCALED_CLK_T"
5625 #define busnum_ODY_PCIERCX_PTM_RES_SCALED_CLK_T(a) (a)
5626 #define arguments_ODY_PCIERCX_PTM_RES_SCALED_CLK_T(a) (a), -1, -1, -1
5627
5628 /**
5629 * Register (PCICONFIGRC) pcierc#_ptm_res_status
5630 *
5631 * PCIe RC PTM Responder Status Register
5632 */
5633 union ody_pciercx_ptm_res_status {
5634 uint32_t u;
5635 struct ody_pciercx_ptm_res_status_s {
5636 uint32_t ctxt_vld : 1;
5637 uint32_t first_req_rcv : 1;
5638 uint32_t reserved_2_31 : 30;
5639 } s;
5640 /* struct ody_pciercx_ptm_res_status_s cn; */
5641 };
5642 typedef union ody_pciercx_ptm_res_status ody_pciercx_ptm_res_status_t;
5643
5644 static inline uint64_t ODY_PCIERCX_PTM_RES_STATUS(uint64_t a) __attribute__ ((pure, always_inline));
ODY_PCIERCX_PTM_RES_STATUS(uint64_t a)5645 static inline uint64_t ODY_PCIERCX_PTM_RES_STATUS(uint64_t a)
5646 {
5647 if (a <= 15)
5648 return 0x3c8;
5649 __ody_csr_fatal("PCIERCX_PTM_RES_STATUS", 1, a, 0, 0, 0, 0, 0);
5650 }
5651
5652 #define typedef_ODY_PCIERCX_PTM_RES_STATUS(a) ody_pciercx_ptm_res_status_t
5653 #define bustype_ODY_PCIERCX_PTM_RES_STATUS(a) CSR_TYPE_PCICONFIGRC
5654 #define basename_ODY_PCIERCX_PTM_RES_STATUS(a) "PCIERCX_PTM_RES_STATUS"
5655 #define busnum_ODY_PCIERCX_PTM_RES_STATUS(a) (a)
5656 #define arguments_ODY_PCIERCX_PTM_RES_STATUS(a) (a), -1, -1, -1
5657
5658 /**
5659 * Register (PCICONFIGRC) pcierc#_ptm_res_t2_lsb
5660 *
5661 * PCIe RC PTM Responder T2 Timestamp LSB Register
5662 */
5663 union ody_pciercx_ptm_res_t2_lsb {
5664 uint32_t u;
5665 struct ody_pciercx_ptm_res_t2_lsb_s {
5666 uint32_t ts_lsb : 32;
5667 } s;
5668 /* struct ody_pciercx_ptm_res_t2_lsb_s cn; */
5669 };
5670 typedef union ody_pciercx_ptm_res_t2_lsb ody_pciercx_ptm_res_t2_lsb_t;
5671
5672 static inline uint64_t ODY_PCIERCX_PTM_RES_T2_LSB(uint64_t a) __attribute__ ((pure, always_inline));
ODY_PCIERCX_PTM_RES_T2_LSB(uint64_t a)5673 static inline uint64_t ODY_PCIERCX_PTM_RES_T2_LSB(uint64_t a)
5674 {
5675 if (a <= 15)
5676 return 0x3d4;
5677 __ody_csr_fatal("PCIERCX_PTM_RES_T2_LSB", 1, a, 0, 0, 0, 0, 0);
5678 }
5679
5680 #define typedef_ODY_PCIERCX_PTM_RES_T2_LSB(a) ody_pciercx_ptm_res_t2_lsb_t
5681 #define bustype_ODY_PCIERCX_PTM_RES_T2_LSB(a) CSR_TYPE_PCICONFIGRC
5682 #define basename_ODY_PCIERCX_PTM_RES_T2_LSB(a) "PCIERCX_PTM_RES_T2_LSB"
5683 #define busnum_ODY_PCIERCX_PTM_RES_T2_LSB(a) (a)
5684 #define arguments_ODY_PCIERCX_PTM_RES_T2_LSB(a) (a), -1, -1, -1
5685
5686 /**
5687 * Register (PCICONFIGRC) pcierc#_ptm_res_t2_msb
5688 *
5689 * PCIe RC PTM Responder T2 Timestamp MSB Register
5690 */
5691 union ody_pciercx_ptm_res_t2_msb {
5692 uint32_t u;
5693 struct ody_pciercx_ptm_res_t2_msb_s {
5694 uint32_t ts_msb : 32;
5695 } s;
5696 /* struct ody_pciercx_ptm_res_t2_msb_s cn; */
5697 };
5698 typedef union ody_pciercx_ptm_res_t2_msb ody_pciercx_ptm_res_t2_msb_t;
5699
5700 static inline uint64_t ODY_PCIERCX_PTM_RES_T2_MSB(uint64_t a) __attribute__ ((pure, always_inline));
ODY_PCIERCX_PTM_RES_T2_MSB(uint64_t a)5701 static inline uint64_t ODY_PCIERCX_PTM_RES_T2_MSB(uint64_t a)
5702 {
5703 if (a <= 15)
5704 return 0x3d8;
5705 __ody_csr_fatal("PCIERCX_PTM_RES_T2_MSB", 1, a, 0, 0, 0, 0, 0);
5706 }
5707
5708 #define typedef_ODY_PCIERCX_PTM_RES_T2_MSB(a) ody_pciercx_ptm_res_t2_msb_t
5709 #define bustype_ODY_PCIERCX_PTM_RES_T2_MSB(a) CSR_TYPE_PCICONFIGRC
5710 #define basename_ODY_PCIERCX_PTM_RES_T2_MSB(a) "PCIERCX_PTM_RES_T2_MSB"
5711 #define busnum_ODY_PCIERCX_PTM_RES_T2_MSB(a) (a)
5712 #define arguments_ODY_PCIERCX_PTM_RES_T2_MSB(a) (a), -1, -1, -1
5713
5714 /**
5715 * Register (PCICONFIGRC) pcierc#_ptm_res_t2p_lsb
5716 *
5717 * PCIe RC PTM Responder T2 Previous Timestamp LSB Register
5718 */
5719 union ody_pciercx_ptm_res_t2p_lsb {
5720 uint32_t u;
5721 struct ody_pciercx_ptm_res_t2p_lsb_s {
5722 uint32_t t2p_lsb : 32;
5723 } s;
5724 /* struct ody_pciercx_ptm_res_t2p_lsb_s cn; */
5725 };
5726 typedef union ody_pciercx_ptm_res_t2p_lsb ody_pciercx_ptm_res_t2p_lsb_t;
5727
5728 static inline uint64_t ODY_PCIERCX_PTM_RES_T2P_LSB(uint64_t a) __attribute__ ((pure, always_inline));
ODY_PCIERCX_PTM_RES_T2P_LSB(uint64_t a)5729 static inline uint64_t ODY_PCIERCX_PTM_RES_T2P_LSB(uint64_t a)
5730 {
5731 if (a <= 15)
5732 return 0x3dc;
5733 __ody_csr_fatal("PCIERCX_PTM_RES_T2P_LSB", 1, a, 0, 0, 0, 0, 0);
5734 }
5735
5736 #define typedef_ODY_PCIERCX_PTM_RES_T2P_LSB(a) ody_pciercx_ptm_res_t2p_lsb_t
5737 #define bustype_ODY_PCIERCX_PTM_RES_T2P_LSB(a) CSR_TYPE_PCICONFIGRC
5738 #define basename_ODY_PCIERCX_PTM_RES_T2P_LSB(a) "PCIERCX_PTM_RES_T2P_LSB"
5739 #define busnum_ODY_PCIERCX_PTM_RES_T2P_LSB(a) (a)
5740 #define arguments_ODY_PCIERCX_PTM_RES_T2P_LSB(a) (a), -1, -1, -1
5741
5742 /**
5743 * Register (PCICONFIGRC) pcierc#_ptm_res_t2p_msb
5744 *
5745 * PCIe RC PTM Responder T2 Previous Timestamp MSB Register
5746 */
5747 union ody_pciercx_ptm_res_t2p_msb {
5748 uint32_t u;
5749 struct ody_pciercx_ptm_res_t2p_msb_s {
5750 uint32_t t2p_msb : 32;
5751 } s;
5752 /* struct ody_pciercx_ptm_res_t2p_msb_s cn; */
5753 };
5754 typedef union ody_pciercx_ptm_res_t2p_msb ody_pciercx_ptm_res_t2p_msb_t;
5755
5756 static inline uint64_t ODY_PCIERCX_PTM_RES_T2P_MSB(uint64_t a) __attribute__ ((pure, always_inline));
ODY_PCIERCX_PTM_RES_T2P_MSB(uint64_t a)5757 static inline uint64_t ODY_PCIERCX_PTM_RES_T2P_MSB(uint64_t a)
5758 {
5759 if (a <= 15)
5760 return 0x3e0;
5761 __ody_csr_fatal("PCIERCX_PTM_RES_T2P_MSB", 1, a, 0, 0, 0, 0, 0);
5762 }
5763
5764 #define typedef_ODY_PCIERCX_PTM_RES_T2P_MSB(a) ody_pciercx_ptm_res_t2p_msb_t
5765 #define bustype_ODY_PCIERCX_PTM_RES_T2P_MSB(a) CSR_TYPE_PCICONFIGRC
5766 #define basename_ODY_PCIERCX_PTM_RES_T2P_MSB(a) "PCIERCX_PTM_RES_T2P_MSB"
5767 #define busnum_ODY_PCIERCX_PTM_RES_T2P_MSB(a) (a)
5768 #define arguments_ODY_PCIERCX_PTM_RES_T2P_MSB(a) (a), -1, -1, -1
5769
5770 /**
5771 * Register (PCICONFIGRC) pcierc#_ptm_res_t3_lsb
5772 *
5773 * PCIe RC PTM Responder T3 Timestamp LSB Register
5774 */
5775 union ody_pciercx_ptm_res_t3_lsb {
5776 uint32_t u;
5777 struct ody_pciercx_ptm_res_t3_lsb_s {
5778 uint32_t t3_lsb : 32;
5779 } s;
5780 /* struct ody_pciercx_ptm_res_t3_lsb_s cn; */
5781 };
5782 typedef union ody_pciercx_ptm_res_t3_lsb ody_pciercx_ptm_res_t3_lsb_t;
5783
5784 static inline uint64_t ODY_PCIERCX_PTM_RES_T3_LSB(uint64_t a) __attribute__ ((pure, always_inline));
ODY_PCIERCX_PTM_RES_T3_LSB(uint64_t a)5785 static inline uint64_t ODY_PCIERCX_PTM_RES_T3_LSB(uint64_t a)
5786 {
5787 if (a <= 15)
5788 return 0x3e4;
5789 __ody_csr_fatal("PCIERCX_PTM_RES_T3_LSB", 1, a, 0, 0, 0, 0, 0);
5790 }
5791
5792 #define typedef_ODY_PCIERCX_PTM_RES_T3_LSB(a) ody_pciercx_ptm_res_t3_lsb_t
5793 #define bustype_ODY_PCIERCX_PTM_RES_T3_LSB(a) CSR_TYPE_PCICONFIGRC
5794 #define basename_ODY_PCIERCX_PTM_RES_T3_LSB(a) "PCIERCX_PTM_RES_T3_LSB"
5795 #define busnum_ODY_PCIERCX_PTM_RES_T3_LSB(a) (a)
5796 #define arguments_ODY_PCIERCX_PTM_RES_T3_LSB(a) (a), -1, -1, -1
5797
5798 /**
5799 * Register (PCICONFIGRC) pcierc#_ptm_res_t3_msb
5800 *
5801 * PCIe RC PTM Responder T3 Timestamp MSB Register
5802 */
5803 union ody_pciercx_ptm_res_t3_msb {
5804 uint32_t u;
5805 struct ody_pciercx_ptm_res_t3_msb_s {
5806 uint32_t t3 : 32;
5807 } s;
5808 /* struct ody_pciercx_ptm_res_t3_msb_s cn; */
5809 };
5810 typedef union ody_pciercx_ptm_res_t3_msb ody_pciercx_ptm_res_t3_msb_t;
5811
5812 static inline uint64_t ODY_PCIERCX_PTM_RES_T3_MSB(uint64_t a) __attribute__ ((pure, always_inline));
ODY_PCIERCX_PTM_RES_T3_MSB(uint64_t a)5813 static inline uint64_t ODY_PCIERCX_PTM_RES_T3_MSB(uint64_t a)
5814 {
5815 if (a <= 15)
5816 return 0x3e8;
5817 __ody_csr_fatal("PCIERCX_PTM_RES_T3_MSB", 1, a, 0, 0, 0, 0, 0);
5818 }
5819
5820 #define typedef_ODY_PCIERCX_PTM_RES_T3_MSB(a) ody_pciercx_ptm_res_t3_msb_t
5821 #define bustype_ODY_PCIERCX_PTM_RES_T3_MSB(a) CSR_TYPE_PCICONFIGRC
5822 #define basename_ODY_PCIERCX_PTM_RES_T3_MSB(a) "PCIERCX_PTM_RES_T3_MSB"
5823 #define busnum_ODY_PCIERCX_PTM_RES_T3_MSB(a) (a)
5824 #define arguments_ODY_PCIERCX_PTM_RES_T3_MSB(a) (a), -1, -1, -1
5825
5826 /**
5827 * Register (PCICONFIGRC) pcierc#_ptm_res_t3p_lsb
5828 *
5829 * PCIe RC PTM Responder T3 Previous Timestamp LSB Register
5830 */
5831 union ody_pciercx_ptm_res_t3p_lsb {
5832 uint32_t u;
5833 struct ody_pciercx_ptm_res_t3p_lsb_s {
5834 uint32_t t3p_lsb : 32;
5835 } s;
5836 /* struct ody_pciercx_ptm_res_t3p_lsb_s cn; */
5837 };
5838 typedef union ody_pciercx_ptm_res_t3p_lsb ody_pciercx_ptm_res_t3p_lsb_t;
5839
5840 static inline uint64_t ODY_PCIERCX_PTM_RES_T3P_LSB(uint64_t a) __attribute__ ((pure, always_inline));
ODY_PCIERCX_PTM_RES_T3P_LSB(uint64_t a)5841 static inline uint64_t ODY_PCIERCX_PTM_RES_T3P_LSB(uint64_t a)
5842 {
5843 if (a <= 15)
5844 return 0x3ec;
5845 __ody_csr_fatal("PCIERCX_PTM_RES_T3P_LSB", 1, a, 0, 0, 0, 0, 0);
5846 }
5847
5848 #define typedef_ODY_PCIERCX_PTM_RES_T3P_LSB(a) ody_pciercx_ptm_res_t3p_lsb_t
5849 #define bustype_ODY_PCIERCX_PTM_RES_T3P_LSB(a) CSR_TYPE_PCICONFIGRC
5850 #define basename_ODY_PCIERCX_PTM_RES_T3P_LSB(a) "PCIERCX_PTM_RES_T3P_LSB"
5851 #define busnum_ODY_PCIERCX_PTM_RES_T3P_LSB(a) (a)
5852 #define arguments_ODY_PCIERCX_PTM_RES_T3P_LSB(a) (a), -1, -1, -1
5853
5854 /**
5855 * Register (PCICONFIGRC) pcierc#_ptm_res_t3p_msb
5856 *
5857 * PCIe RC PTM Responder T3 Previous Timestamp MSB Register
5858 */
5859 union ody_pciercx_ptm_res_t3p_msb {
5860 uint32_t u;
5861 struct ody_pciercx_ptm_res_t3p_msb_s {
5862 uint32_t t3p_msb : 32;
5863 } s;
5864 /* struct ody_pciercx_ptm_res_t3p_msb_s cn; */
5865 };
5866 typedef union ody_pciercx_ptm_res_t3p_msb ody_pciercx_ptm_res_t3p_msb_t;
5867
5868 static inline uint64_t ODY_PCIERCX_PTM_RES_T3P_MSB(uint64_t a) __attribute__ ((pure, always_inline));
ODY_PCIERCX_PTM_RES_T3P_MSB(uint64_t a)5869 static inline uint64_t ODY_PCIERCX_PTM_RES_T3P_MSB(uint64_t a)
5870 {
5871 if (a <= 15)
5872 return 0x3f0;
5873 __ody_csr_fatal("PCIERCX_PTM_RES_T3P_MSB", 1, a, 0, 0, 0, 0, 0);
5874 }
5875
5876 #define typedef_ODY_PCIERCX_PTM_RES_T3P_MSB(a) ody_pciercx_ptm_res_t3p_msb_t
5877 #define bustype_ODY_PCIERCX_PTM_RES_T3P_MSB(a) CSR_TYPE_PCICONFIGRC
5878 #define basename_ODY_PCIERCX_PTM_RES_T3P_MSB(a) "PCIERCX_PTM_RES_T3P_MSB"
5879 #define busnum_ODY_PCIERCX_PTM_RES_T3P_MSB(a) (a)
5880 #define arguments_ODY_PCIERCX_PTM_RES_T3P_MSB(a) (a), -1, -1, -1
5881
5882 /**
5883 * Register (PCICONFIGRC) pcierc#_ptm_res_tx_latency
5884 *
5885 * PCIe RC PTM Responder TX Latency Register
5886 */
5887 union ody_pciercx_ptm_res_tx_latency {
5888 uint32_t u;
5889 struct ody_pciercx_ptm_res_tx_latency_s {
5890 uint32_t tx_lat : 12;
5891 uint32_t reserved_12_31 : 20;
5892 } s;
5893 /* struct ody_pciercx_ptm_res_tx_latency_s cn; */
5894 };
5895 typedef union ody_pciercx_ptm_res_tx_latency ody_pciercx_ptm_res_tx_latency_t;
5896
5897 static inline uint64_t ODY_PCIERCX_PTM_RES_TX_LATENCY(uint64_t a) __attribute__ ((pure, always_inline));
ODY_PCIERCX_PTM_RES_TX_LATENCY(uint64_t a)5898 static inline uint64_t ODY_PCIERCX_PTM_RES_TX_LATENCY(uint64_t a)
5899 {
5900 if (a <= 15)
5901 return 0x3f4;
5902 __ody_csr_fatal("PCIERCX_PTM_RES_TX_LATENCY", 1, a, 0, 0, 0, 0, 0);
5903 }
5904
5905 #define typedef_ODY_PCIERCX_PTM_RES_TX_LATENCY(a) ody_pciercx_ptm_res_tx_latency_t
5906 #define bustype_ODY_PCIERCX_PTM_RES_TX_LATENCY(a) CSR_TYPE_PCICONFIGRC
5907 #define basename_ODY_PCIERCX_PTM_RES_TX_LATENCY(a) "PCIERCX_PTM_RES_TX_LATENCY"
5908 #define busnum_ODY_PCIERCX_PTM_RES_TX_LATENCY(a) (a)
5909 #define arguments_ODY_PCIERCX_PTM_RES_TX_LATENCY(a) (a), -1, -1, -1
5910
5911 /**
5912 * Register (PCICONFIGRC) pcierc#_queue_status
5913 *
5914 * PCIe RC Queue Status Register
5915 */
5916 union ody_pciercx_queue_status {
5917 uint32_t u;
5918 struct ody_pciercx_queue_status_s {
5919 uint32_t rtlpfccnr : 1;
5920 uint32_t trbne : 1;
5921 uint32_t rqne : 1;
5922 uint32_t rqof : 1;
5923 uint32_t reserved_4_12 : 9;
5924 uint32_t rsqne : 1;
5925 uint32_t rsqwe : 1;
5926 uint32_t rsqre : 1;
5927 uint32_t fcltov : 13;
5928 uint32_t reserved_29_30 : 2;
5929 uint32_t fcltoe : 1;
5930 } s;
5931 /* struct ody_pciercx_queue_status_s cn; */
5932 };
5933 typedef union ody_pciercx_queue_status ody_pciercx_queue_status_t;
5934
5935 static inline uint64_t ODY_PCIERCX_QUEUE_STATUS(uint64_t a) __attribute__ ((pure, always_inline));
ODY_PCIERCX_QUEUE_STATUS(uint64_t a)5936 static inline uint64_t ODY_PCIERCX_QUEUE_STATUS(uint64_t a)
5937 {
5938 if (a <= 15)
5939 return 0x73c;
5940 __ody_csr_fatal("PCIERCX_QUEUE_STATUS", 1, a, 0, 0, 0, 0, 0);
5941 }
5942
5943 #define typedef_ODY_PCIERCX_QUEUE_STATUS(a) ody_pciercx_queue_status_t
5944 #define bustype_ODY_PCIERCX_QUEUE_STATUS(a) CSR_TYPE_PCICONFIGRC
5945 #define basename_ODY_PCIERCX_QUEUE_STATUS(a) "PCIERCX_QUEUE_STATUS"
5946 #define busnum_ODY_PCIERCX_QUEUE_STATUS(a) (a)
5947 #define arguments_ODY_PCIERCX_QUEUE_STATUS(a) (a), -1, -1, -1
5948
5949 /**
5950 * Register (PCICONFIGRC) pcierc#_ras_des_cap_hdr
5951 *
5952 * PCIe RC Vendor Specific RAS DES Capability Header Register
5953 */
5954 union ody_pciercx_ras_des_cap_hdr {
5955 uint32_t u;
5956 struct ody_pciercx_ras_des_cap_hdr_s {
5957 uint32_t pcieec : 16;
5958 uint32_t cv : 4;
5959 uint32_t nco : 12;
5960 } s;
5961 /* struct ody_pciercx_ras_des_cap_hdr_s cn; */
5962 };
5963 typedef union ody_pciercx_ras_des_cap_hdr ody_pciercx_ras_des_cap_hdr_t;
5964
5965 static inline uint64_t ODY_PCIERCX_RAS_DES_CAP_HDR(uint64_t a) __attribute__ ((pure, always_inline));
ODY_PCIERCX_RAS_DES_CAP_HDR(uint64_t a)5966 static inline uint64_t ODY_PCIERCX_RAS_DES_CAP_HDR(uint64_t a)
5967 {
5968 if (a <= 15)
5969 return 0x26c;
5970 __ody_csr_fatal("PCIERCX_RAS_DES_CAP_HDR", 1, a, 0, 0, 0, 0, 0);
5971 }
5972
5973 #define typedef_ODY_PCIERCX_RAS_DES_CAP_HDR(a) ody_pciercx_ras_des_cap_hdr_t
5974 #define bustype_ODY_PCIERCX_RAS_DES_CAP_HDR(a) CSR_TYPE_PCICONFIGRC
5975 #define basename_ODY_PCIERCX_RAS_DES_CAP_HDR(a) "PCIERCX_RAS_DES_CAP_HDR"
5976 #define busnum_ODY_PCIERCX_RAS_DES_CAP_HDR(a) (a)
5977 #define arguments_ODY_PCIERCX_RAS_DES_CAP_HDR(a) (a), -1, -1, -1
5978
5979 /**
5980 * Register (PCICONFIGRC) pcierc#_ras_ec_ctl
5981 *
5982 * PCIe RC Vendor RAS DES Event Counter Control Register
5983 */
5984 union ody_pciercx_ras_ec_ctl {
5985 uint32_t u;
5986 struct ody_pciercx_ras_ec_ctl_s {
5987 uint32_t ev_cntr_clr : 2;
5988 uint32_t ev_cntr_en : 3;
5989 uint32_t reserved_5_6 : 2;
5990 uint32_t ev_cntr_stat : 1;
5991 uint32_t ev_cntr_lane_sel : 4;
5992 uint32_t reserved_12_15 : 4;
5993 uint32_t ev_cntr_data_sel : 12;
5994 uint32_t reserved_28_31 : 4;
5995 } s;
5996 /* struct ody_pciercx_ras_ec_ctl_s cn; */
5997 };
5998 typedef union ody_pciercx_ras_ec_ctl ody_pciercx_ras_ec_ctl_t;
5999
6000 static inline uint64_t ODY_PCIERCX_RAS_EC_CTL(uint64_t a) __attribute__ ((pure, always_inline));
ODY_PCIERCX_RAS_EC_CTL(uint64_t a)6001 static inline uint64_t ODY_PCIERCX_RAS_EC_CTL(uint64_t a)
6002 {
6003 if (a <= 15)
6004 return 0x274;
6005 __ody_csr_fatal("PCIERCX_RAS_EC_CTL", 1, a, 0, 0, 0, 0, 0);
6006 }
6007
6008 #define typedef_ODY_PCIERCX_RAS_EC_CTL(a) ody_pciercx_ras_ec_ctl_t
6009 #define bustype_ODY_PCIERCX_RAS_EC_CTL(a) CSR_TYPE_PCICONFIGRC
6010 #define basename_ODY_PCIERCX_RAS_EC_CTL(a) "PCIERCX_RAS_EC_CTL"
6011 #define busnum_ODY_PCIERCX_RAS_EC_CTL(a) (a)
6012 #define arguments_ODY_PCIERCX_RAS_EC_CTL(a) (a), -1, -1, -1
6013
6014 /**
6015 * Register (PCICONFIGRC) pcierc#_ras_ec_data
6016 *
6017 * PCIe RC Vendor RAS DES Data Register
6018 */
6019 union ody_pciercx_ras_ec_data {
6020 uint32_t u;
6021 struct ody_pciercx_ras_ec_data_s {
6022 uint32_t ev_cntr_data : 32;
6023 } s;
6024 /* struct ody_pciercx_ras_ec_data_s cn; */
6025 };
6026 typedef union ody_pciercx_ras_ec_data ody_pciercx_ras_ec_data_t;
6027
6028 static inline uint64_t ODY_PCIERCX_RAS_EC_DATA(uint64_t a) __attribute__ ((pure, always_inline));
ODY_PCIERCX_RAS_EC_DATA(uint64_t a)6029 static inline uint64_t ODY_PCIERCX_RAS_EC_DATA(uint64_t a)
6030 {
6031 if (a <= 15)
6032 return 0x278;
6033 __ody_csr_fatal("PCIERCX_RAS_EC_DATA", 1, a, 0, 0, 0, 0, 0);
6034 }
6035
6036 #define typedef_ODY_PCIERCX_RAS_EC_DATA(a) ody_pciercx_ras_ec_data_t
6037 #define bustype_ODY_PCIERCX_RAS_EC_DATA(a) CSR_TYPE_PCICONFIGRC
6038 #define basename_ODY_PCIERCX_RAS_EC_DATA(a) "PCIERCX_RAS_EC_DATA"
6039 #define busnum_ODY_PCIERCX_RAS_EC_DATA(a) (a)
6040 #define arguments_ODY_PCIERCX_RAS_EC_DATA(a) (a), -1, -1, -1
6041
6042 /**
6043 * Register (PCICONFIGRC) pcierc#_ras_einj_ctl0
6044 *
6045 * PCIe RC Vendor RAS DES Error Injection Control 0 (CRC) Register
6046 */
6047 union ody_pciercx_ras_einj_ctl0 {
6048 uint32_t u;
6049 struct ody_pciercx_ras_einj_ctl0_s {
6050 uint32_t einj0_cnt : 8;
6051 uint32_t einj0_crc_type : 4;
6052 uint32_t reserved_12_31 : 20;
6053 } s;
6054 /* struct ody_pciercx_ras_einj_ctl0_s cn; */
6055 };
6056 typedef union ody_pciercx_ras_einj_ctl0 ody_pciercx_ras_einj_ctl0_t;
6057
6058 static inline uint64_t ODY_PCIERCX_RAS_EINJ_CTL0(uint64_t a) __attribute__ ((pure, always_inline));
ODY_PCIERCX_RAS_EINJ_CTL0(uint64_t a)6059 static inline uint64_t ODY_PCIERCX_RAS_EINJ_CTL0(uint64_t a)
6060 {
6061 if (a <= 15)
6062 return 0x2a0;
6063 __ody_csr_fatal("PCIERCX_RAS_EINJ_CTL0", 1, a, 0, 0, 0, 0, 0);
6064 }
6065
6066 #define typedef_ODY_PCIERCX_RAS_EINJ_CTL0(a) ody_pciercx_ras_einj_ctl0_t
6067 #define bustype_ODY_PCIERCX_RAS_EINJ_CTL0(a) CSR_TYPE_PCICONFIGRC
6068 #define basename_ODY_PCIERCX_RAS_EINJ_CTL0(a) "PCIERCX_RAS_EINJ_CTL0"
6069 #define busnum_ODY_PCIERCX_RAS_EINJ_CTL0(a) (a)
6070 #define arguments_ODY_PCIERCX_RAS_EINJ_CTL0(a) (a), -1, -1, -1
6071
6072 /**
6073 * Register (PCICONFIGRC) pcierc#_ras_einj_ctl1
6074 *
6075 * PCIe RC Vendor RAS DES Error Injection Control 1 (SEQNUM) Register
6076 */
6077 union ody_pciercx_ras_einj_ctl1 {
6078 uint32_t u;
6079 struct ody_pciercx_ras_einj_ctl1_s {
6080 uint32_t einj1_cnt : 8;
6081 uint32_t einj1_seqnum_type : 1;
6082 uint32_t reserved_9_15 : 7;
6083 uint32_t einj1_bad_seqnum : 13;
6084 uint32_t reserved_29_31 : 3;
6085 } s;
6086 /* struct ody_pciercx_ras_einj_ctl1_s cn; */
6087 };
6088 typedef union ody_pciercx_ras_einj_ctl1 ody_pciercx_ras_einj_ctl1_t;
6089
6090 static inline uint64_t ODY_PCIERCX_RAS_EINJ_CTL1(uint64_t a) __attribute__ ((pure, always_inline));
ODY_PCIERCX_RAS_EINJ_CTL1(uint64_t a)6091 static inline uint64_t ODY_PCIERCX_RAS_EINJ_CTL1(uint64_t a)
6092 {
6093 if (a <= 15)
6094 return 0x2a4;
6095 __ody_csr_fatal("PCIERCX_RAS_EINJ_CTL1", 1, a, 0, 0, 0, 0, 0);
6096 }
6097
6098 #define typedef_ODY_PCIERCX_RAS_EINJ_CTL1(a) ody_pciercx_ras_einj_ctl1_t
6099 #define bustype_ODY_PCIERCX_RAS_EINJ_CTL1(a) CSR_TYPE_PCICONFIGRC
6100 #define basename_ODY_PCIERCX_RAS_EINJ_CTL1(a) "PCIERCX_RAS_EINJ_CTL1"
6101 #define busnum_ODY_PCIERCX_RAS_EINJ_CTL1(a) (a)
6102 #define arguments_ODY_PCIERCX_RAS_EINJ_CTL1(a) (a), -1, -1, -1
6103
6104 /**
6105 * Register (PCICONFIGRC) pcierc#_ras_einj_ctl2
6106 *
6107 * PCIe RC Vendor RAS DES Error Injection Control 2 (DLLP) Register
6108 */
6109 union ody_pciercx_ras_einj_ctl2 {
6110 uint32_t u;
6111 struct ody_pciercx_ras_einj_ctl2_s {
6112 uint32_t einj2_cnt : 8;
6113 uint32_t einj2_dllp_type : 2;
6114 uint32_t reserved_10_31 : 22;
6115 } s;
6116 /* struct ody_pciercx_ras_einj_ctl2_s cn; */
6117 };
6118 typedef union ody_pciercx_ras_einj_ctl2 ody_pciercx_ras_einj_ctl2_t;
6119
6120 static inline uint64_t ODY_PCIERCX_RAS_EINJ_CTL2(uint64_t a) __attribute__ ((pure, always_inline));
ODY_PCIERCX_RAS_EINJ_CTL2(uint64_t a)6121 static inline uint64_t ODY_PCIERCX_RAS_EINJ_CTL2(uint64_t a)
6122 {
6123 if (a <= 15)
6124 return 0x2a8;
6125 __ody_csr_fatal("PCIERCX_RAS_EINJ_CTL2", 1, a, 0, 0, 0, 0, 0);
6126 }
6127
6128 #define typedef_ODY_PCIERCX_RAS_EINJ_CTL2(a) ody_pciercx_ras_einj_ctl2_t
6129 #define bustype_ODY_PCIERCX_RAS_EINJ_CTL2(a) CSR_TYPE_PCICONFIGRC
6130 #define basename_ODY_PCIERCX_RAS_EINJ_CTL2(a) "PCIERCX_RAS_EINJ_CTL2"
6131 #define busnum_ODY_PCIERCX_RAS_EINJ_CTL2(a) (a)
6132 #define arguments_ODY_PCIERCX_RAS_EINJ_CTL2(a) (a), -1, -1, -1
6133
6134 /**
6135 * Register (PCICONFIGRC) pcierc#_ras_einj_ctl3
6136 *
6137 * PCIe RC Vendor RAS DES Error Injection Control 3 (Symbol) Register
6138 */
6139 union ody_pciercx_ras_einj_ctl3 {
6140 uint32_t u;
6141 struct ody_pciercx_ras_einj_ctl3_s {
6142 uint32_t einj3_cnt : 8;
6143 uint32_t einj3_symbol_type : 3;
6144 uint32_t reserved_11_31 : 21;
6145 } s;
6146 /* struct ody_pciercx_ras_einj_ctl3_s cn; */
6147 };
6148 typedef union ody_pciercx_ras_einj_ctl3 ody_pciercx_ras_einj_ctl3_t;
6149
6150 static inline uint64_t ODY_PCIERCX_RAS_EINJ_CTL3(uint64_t a) __attribute__ ((pure, always_inline));
ODY_PCIERCX_RAS_EINJ_CTL3(uint64_t a)6151 static inline uint64_t ODY_PCIERCX_RAS_EINJ_CTL3(uint64_t a)
6152 {
6153 if (a <= 15)
6154 return 0x2ac;
6155 __ody_csr_fatal("PCIERCX_RAS_EINJ_CTL3", 1, a, 0, 0, 0, 0, 0);
6156 }
6157
6158 #define typedef_ODY_PCIERCX_RAS_EINJ_CTL3(a) ody_pciercx_ras_einj_ctl3_t
6159 #define bustype_ODY_PCIERCX_RAS_EINJ_CTL3(a) CSR_TYPE_PCICONFIGRC
6160 #define basename_ODY_PCIERCX_RAS_EINJ_CTL3(a) "PCIERCX_RAS_EINJ_CTL3"
6161 #define busnum_ODY_PCIERCX_RAS_EINJ_CTL3(a) (a)
6162 #define arguments_ODY_PCIERCX_RAS_EINJ_CTL3(a) (a), -1, -1, -1
6163
6164 /**
6165 * Register (PCICONFIGRC) pcierc#_ras_einj_ctl4
6166 *
6167 * PCIe RC Vendor RAS DES Error Injection Control 4 (FC Credit) Register
6168 */
6169 union ody_pciercx_ras_einj_ctl4 {
6170 uint32_t u;
6171 struct ody_pciercx_ras_einj_ctl4_s {
6172 uint32_t einj4_cnt : 8;
6173 uint32_t einj4_vc_type : 3;
6174 uint32_t reserved_11 : 1;
6175 uint32_t einj4_vc_num : 3;
6176 uint32_t reserved_15 : 1;
6177 uint32_t einj4_bad_updfc_val : 13;
6178 uint32_t reserved_29_31 : 3;
6179 } s;
6180 /* struct ody_pciercx_ras_einj_ctl4_s cn; */
6181 };
6182 typedef union ody_pciercx_ras_einj_ctl4 ody_pciercx_ras_einj_ctl4_t;
6183
6184 static inline uint64_t ODY_PCIERCX_RAS_EINJ_CTL4(uint64_t a) __attribute__ ((pure, always_inline));
ODY_PCIERCX_RAS_EINJ_CTL4(uint64_t a)6185 static inline uint64_t ODY_PCIERCX_RAS_EINJ_CTL4(uint64_t a)
6186 {
6187 if (a <= 15)
6188 return 0x2b0;
6189 __ody_csr_fatal("PCIERCX_RAS_EINJ_CTL4", 1, a, 0, 0, 0, 0, 0);
6190 }
6191
6192 #define typedef_ODY_PCIERCX_RAS_EINJ_CTL4(a) ody_pciercx_ras_einj_ctl4_t
6193 #define bustype_ODY_PCIERCX_RAS_EINJ_CTL4(a) CSR_TYPE_PCICONFIGRC
6194 #define basename_ODY_PCIERCX_RAS_EINJ_CTL4(a) "PCIERCX_RAS_EINJ_CTL4"
6195 #define busnum_ODY_PCIERCX_RAS_EINJ_CTL4(a) (a)
6196 #define arguments_ODY_PCIERCX_RAS_EINJ_CTL4(a) (a), -1, -1, -1
6197
6198 /**
6199 * Register (PCICONFIGRC) pcierc#_ras_einj_ctl5
6200 *
6201 * PCIe RC Vendor RAS DES Error Injection Control 5 (Specific TLP) Register
6202 */
6203 union ody_pciercx_ras_einj_ctl5 {
6204 uint32_t u;
6205 struct ody_pciercx_ras_einj_ctl5_s {
6206 uint32_t einj5_cnt : 8;
6207 uint32_t einj5_sp_tlp : 1;
6208 uint32_t reserved_9_31 : 23;
6209 } s;
6210 /* struct ody_pciercx_ras_einj_ctl5_s cn; */
6211 };
6212 typedef union ody_pciercx_ras_einj_ctl5 ody_pciercx_ras_einj_ctl5_t;
6213
6214 static inline uint64_t ODY_PCIERCX_RAS_EINJ_CTL5(uint64_t a) __attribute__ ((pure, always_inline));
ODY_PCIERCX_RAS_EINJ_CTL5(uint64_t a)6215 static inline uint64_t ODY_PCIERCX_RAS_EINJ_CTL5(uint64_t a)
6216 {
6217 if (a <= 15)
6218 return 0x2b4;
6219 __ody_csr_fatal("PCIERCX_RAS_EINJ_CTL5", 1, a, 0, 0, 0, 0, 0);
6220 }
6221
6222 #define typedef_ODY_PCIERCX_RAS_EINJ_CTL5(a) ody_pciercx_ras_einj_ctl5_t
6223 #define bustype_ODY_PCIERCX_RAS_EINJ_CTL5(a) CSR_TYPE_PCICONFIGRC
6224 #define basename_ODY_PCIERCX_RAS_EINJ_CTL5(a) "PCIERCX_RAS_EINJ_CTL5"
6225 #define busnum_ODY_PCIERCX_RAS_EINJ_CTL5(a) (a)
6226 #define arguments_ODY_PCIERCX_RAS_EINJ_CTL5(a) (a), -1, -1, -1
6227
6228 /**
6229 * Register (PCICONFIGRC) pcierc#_ras_einj_ctl6chgp0
6230 *
6231 * PCIe RC Vendor RAS DES Error Injection Control 6 (Change Point H0) Register
6232 */
6233 union ody_pciercx_ras_einj_ctl6chgp0 {
6234 uint32_t u;
6235 struct ody_pciercx_ras_einj_ctl6chgp0_s {
6236 uint32_t einj6_chg_pt_h0 : 32;
6237 } s;
6238 /* struct ody_pciercx_ras_einj_ctl6chgp0_s cn; */
6239 };
6240 typedef union ody_pciercx_ras_einj_ctl6chgp0 ody_pciercx_ras_einj_ctl6chgp0_t;
6241
6242 static inline uint64_t ODY_PCIERCX_RAS_EINJ_CTL6CHGP0(uint64_t a) __attribute__ ((pure, always_inline));
ODY_PCIERCX_RAS_EINJ_CTL6CHGP0(uint64_t a)6243 static inline uint64_t ODY_PCIERCX_RAS_EINJ_CTL6CHGP0(uint64_t a)
6244 {
6245 if (a <= 15)
6246 return 0x2d8;
6247 __ody_csr_fatal("PCIERCX_RAS_EINJ_CTL6CHGP0", 1, a, 0, 0, 0, 0, 0);
6248 }
6249
6250 #define typedef_ODY_PCIERCX_RAS_EINJ_CTL6CHGP0(a) ody_pciercx_ras_einj_ctl6chgp0_t
6251 #define bustype_ODY_PCIERCX_RAS_EINJ_CTL6CHGP0(a) CSR_TYPE_PCICONFIGRC
6252 #define basename_ODY_PCIERCX_RAS_EINJ_CTL6CHGP0(a) "PCIERCX_RAS_EINJ_CTL6CHGP0"
6253 #define busnum_ODY_PCIERCX_RAS_EINJ_CTL6CHGP0(a) (a)
6254 #define arguments_ODY_PCIERCX_RAS_EINJ_CTL6CHGP0(a) (a), -1, -1, -1
6255
6256 /**
6257 * Register (PCICONFIGRC) pcierc#_ras_einj_ctl6chgp1
6258 *
6259 * PCIe RC Vendor RAS DES Error Injection Control 6 (Change Point H1) Register
6260 */
6261 union ody_pciercx_ras_einj_ctl6chgp1 {
6262 uint32_t u;
6263 struct ody_pciercx_ras_einj_ctl6chgp1_s {
6264 uint32_t einj6_chg_pt_h1 : 32;
6265 } s;
6266 /* struct ody_pciercx_ras_einj_ctl6chgp1_s cn; */
6267 };
6268 typedef union ody_pciercx_ras_einj_ctl6chgp1 ody_pciercx_ras_einj_ctl6chgp1_t;
6269
6270 static inline uint64_t ODY_PCIERCX_RAS_EINJ_CTL6CHGP1(uint64_t a) __attribute__ ((pure, always_inline));
ODY_PCIERCX_RAS_EINJ_CTL6CHGP1(uint64_t a)6271 static inline uint64_t ODY_PCIERCX_RAS_EINJ_CTL6CHGP1(uint64_t a)
6272 {
6273 if (a <= 15)
6274 return 0x2dc;
6275 __ody_csr_fatal("PCIERCX_RAS_EINJ_CTL6CHGP1", 1, a, 0, 0, 0, 0, 0);
6276 }
6277
6278 #define typedef_ODY_PCIERCX_RAS_EINJ_CTL6CHGP1(a) ody_pciercx_ras_einj_ctl6chgp1_t
6279 #define bustype_ODY_PCIERCX_RAS_EINJ_CTL6CHGP1(a) CSR_TYPE_PCICONFIGRC
6280 #define basename_ODY_PCIERCX_RAS_EINJ_CTL6CHGP1(a) "PCIERCX_RAS_EINJ_CTL6CHGP1"
6281 #define busnum_ODY_PCIERCX_RAS_EINJ_CTL6CHGP1(a) (a)
6282 #define arguments_ODY_PCIERCX_RAS_EINJ_CTL6CHGP1(a) (a), -1, -1, -1
6283
6284 /**
6285 * Register (PCICONFIGRC) pcierc#_ras_einj_ctl6chgp2
6286 *
6287 * PCIe RC Vendor RAS DES Error Injection Control 6 (Change Point H2) Register
6288 */
6289 union ody_pciercx_ras_einj_ctl6chgp2 {
6290 uint32_t u;
6291 struct ody_pciercx_ras_einj_ctl6chgp2_s {
6292 uint32_t einj6_chg_pt_h2 : 32;
6293 } s;
6294 /* struct ody_pciercx_ras_einj_ctl6chgp2_s cn; */
6295 };
6296 typedef union ody_pciercx_ras_einj_ctl6chgp2 ody_pciercx_ras_einj_ctl6chgp2_t;
6297
6298 static inline uint64_t ODY_PCIERCX_RAS_EINJ_CTL6CHGP2(uint64_t a) __attribute__ ((pure, always_inline));
ODY_PCIERCX_RAS_EINJ_CTL6CHGP2(uint64_t a)6299 static inline uint64_t ODY_PCIERCX_RAS_EINJ_CTL6CHGP2(uint64_t a)
6300 {
6301 if (a <= 15)
6302 return 0x2e0;
6303 __ody_csr_fatal("PCIERCX_RAS_EINJ_CTL6CHGP2", 1, a, 0, 0, 0, 0, 0);
6304 }
6305
6306 #define typedef_ODY_PCIERCX_RAS_EINJ_CTL6CHGP2(a) ody_pciercx_ras_einj_ctl6chgp2_t
6307 #define bustype_ODY_PCIERCX_RAS_EINJ_CTL6CHGP2(a) CSR_TYPE_PCICONFIGRC
6308 #define basename_ODY_PCIERCX_RAS_EINJ_CTL6CHGP2(a) "PCIERCX_RAS_EINJ_CTL6CHGP2"
6309 #define busnum_ODY_PCIERCX_RAS_EINJ_CTL6CHGP2(a) (a)
6310 #define arguments_ODY_PCIERCX_RAS_EINJ_CTL6CHGP2(a) (a), -1, -1, -1
6311
6312 /**
6313 * Register (PCICONFIGRC) pcierc#_ras_einj_ctl6chgp3
6314 *
6315 * PCIe RC Vendor RAS DES Error Injection Control 6 (Change Point H3) Register
6316 */
6317 union ody_pciercx_ras_einj_ctl6chgp3 {
6318 uint32_t u;
6319 struct ody_pciercx_ras_einj_ctl6chgp3_s {
6320 uint32_t einj6_chg_pt_h3 : 32;
6321 } s;
6322 /* struct ody_pciercx_ras_einj_ctl6chgp3_s cn; */
6323 };
6324 typedef union ody_pciercx_ras_einj_ctl6chgp3 ody_pciercx_ras_einj_ctl6chgp3_t;
6325
6326 static inline uint64_t ODY_PCIERCX_RAS_EINJ_CTL6CHGP3(uint64_t a) __attribute__ ((pure, always_inline));
ODY_PCIERCX_RAS_EINJ_CTL6CHGP3(uint64_t a)6327 static inline uint64_t ODY_PCIERCX_RAS_EINJ_CTL6CHGP3(uint64_t a)
6328 {
6329 if (a <= 15)
6330 return 0x2e4;
6331 __ody_csr_fatal("PCIERCX_RAS_EINJ_CTL6CHGP3", 1, a, 0, 0, 0, 0, 0);
6332 }
6333
6334 #define typedef_ODY_PCIERCX_RAS_EINJ_CTL6CHGP3(a) ody_pciercx_ras_einj_ctl6chgp3_t
6335 #define bustype_ODY_PCIERCX_RAS_EINJ_CTL6CHGP3(a) CSR_TYPE_PCICONFIGRC
6336 #define basename_ODY_PCIERCX_RAS_EINJ_CTL6CHGP3(a) "PCIERCX_RAS_EINJ_CTL6CHGP3"
6337 #define busnum_ODY_PCIERCX_RAS_EINJ_CTL6CHGP3(a) (a)
6338 #define arguments_ODY_PCIERCX_RAS_EINJ_CTL6CHGP3(a) (a), -1, -1, -1
6339
6340 /**
6341 * Register (PCICONFIGRC) pcierc#_ras_einj_ctl6chgv0
6342 *
6343 * PCIe RC Vendor RAS DES Error Injection Control 6 (Change Value H0) Register
6344 */
6345 union ody_pciercx_ras_einj_ctl6chgv0 {
6346 uint32_t u;
6347 struct ody_pciercx_ras_einj_ctl6chgv0_s {
6348 uint32_t einj6_chg_val_h0 : 32;
6349 } s;
6350 /* struct ody_pciercx_ras_einj_ctl6chgv0_s cn; */
6351 };
6352 typedef union ody_pciercx_ras_einj_ctl6chgv0 ody_pciercx_ras_einj_ctl6chgv0_t;
6353
6354 static inline uint64_t ODY_PCIERCX_RAS_EINJ_CTL6CHGV0(uint64_t a) __attribute__ ((pure, always_inline));
ODY_PCIERCX_RAS_EINJ_CTL6CHGV0(uint64_t a)6355 static inline uint64_t ODY_PCIERCX_RAS_EINJ_CTL6CHGV0(uint64_t a)
6356 {
6357 if (a <= 15)
6358 return 0x2e8;
6359 __ody_csr_fatal("PCIERCX_RAS_EINJ_CTL6CHGV0", 1, a, 0, 0, 0, 0, 0);
6360 }
6361
6362 #define typedef_ODY_PCIERCX_RAS_EINJ_CTL6CHGV0(a) ody_pciercx_ras_einj_ctl6chgv0_t
6363 #define bustype_ODY_PCIERCX_RAS_EINJ_CTL6CHGV0(a) CSR_TYPE_PCICONFIGRC
6364 #define basename_ODY_PCIERCX_RAS_EINJ_CTL6CHGV0(a) "PCIERCX_RAS_EINJ_CTL6CHGV0"
6365 #define busnum_ODY_PCIERCX_RAS_EINJ_CTL6CHGV0(a) (a)
6366 #define arguments_ODY_PCIERCX_RAS_EINJ_CTL6CHGV0(a) (a), -1, -1, -1
6367
6368 /**
6369 * Register (PCICONFIGRC) pcierc#_ras_einj_ctl6chgv1
6370 *
6371 * PCIe RC Vendor RAS DES Error Injection Control 6 (Change Value H1) Register
6372 */
6373 union ody_pciercx_ras_einj_ctl6chgv1 {
6374 uint32_t u;
6375 struct ody_pciercx_ras_einj_ctl6chgv1_s {
6376 uint32_t einj6_chg_val_h1 : 32;
6377 } s;
6378 /* struct ody_pciercx_ras_einj_ctl6chgv1_s cn; */
6379 };
6380 typedef union ody_pciercx_ras_einj_ctl6chgv1 ody_pciercx_ras_einj_ctl6chgv1_t;
6381
6382 static inline uint64_t ODY_PCIERCX_RAS_EINJ_CTL6CHGV1(uint64_t a) __attribute__ ((pure, always_inline));
ODY_PCIERCX_RAS_EINJ_CTL6CHGV1(uint64_t a)6383 static inline uint64_t ODY_PCIERCX_RAS_EINJ_CTL6CHGV1(uint64_t a)
6384 {
6385 if (a <= 15)
6386 return 0x2ec;
6387 __ody_csr_fatal("PCIERCX_RAS_EINJ_CTL6CHGV1", 1, a, 0, 0, 0, 0, 0);
6388 }
6389
6390 #define typedef_ODY_PCIERCX_RAS_EINJ_CTL6CHGV1(a) ody_pciercx_ras_einj_ctl6chgv1_t
6391 #define bustype_ODY_PCIERCX_RAS_EINJ_CTL6CHGV1(a) CSR_TYPE_PCICONFIGRC
6392 #define basename_ODY_PCIERCX_RAS_EINJ_CTL6CHGV1(a) "PCIERCX_RAS_EINJ_CTL6CHGV1"
6393 #define busnum_ODY_PCIERCX_RAS_EINJ_CTL6CHGV1(a) (a)
6394 #define arguments_ODY_PCIERCX_RAS_EINJ_CTL6CHGV1(a) (a), -1, -1, -1
6395
6396 /**
6397 * Register (PCICONFIGRC) pcierc#_ras_einj_ctl6chgv2
6398 *
6399 * PCIe RC Vendor RAS DES Error Injection Control 6 (Change Value H2) Register
6400 */
6401 union ody_pciercx_ras_einj_ctl6chgv2 {
6402 uint32_t u;
6403 struct ody_pciercx_ras_einj_ctl6chgv2_s {
6404 uint32_t einj6_chg_val_h2 : 32;
6405 } s;
6406 /* struct ody_pciercx_ras_einj_ctl6chgv2_s cn; */
6407 };
6408 typedef union ody_pciercx_ras_einj_ctl6chgv2 ody_pciercx_ras_einj_ctl6chgv2_t;
6409
6410 static inline uint64_t ODY_PCIERCX_RAS_EINJ_CTL6CHGV2(uint64_t a) __attribute__ ((pure, always_inline));
ODY_PCIERCX_RAS_EINJ_CTL6CHGV2(uint64_t a)6411 static inline uint64_t ODY_PCIERCX_RAS_EINJ_CTL6CHGV2(uint64_t a)
6412 {
6413 if (a <= 15)
6414 return 0x2f0;
6415 __ody_csr_fatal("PCIERCX_RAS_EINJ_CTL6CHGV2", 1, a, 0, 0, 0, 0, 0);
6416 }
6417
6418 #define typedef_ODY_PCIERCX_RAS_EINJ_CTL6CHGV2(a) ody_pciercx_ras_einj_ctl6chgv2_t
6419 #define bustype_ODY_PCIERCX_RAS_EINJ_CTL6CHGV2(a) CSR_TYPE_PCICONFIGRC
6420 #define basename_ODY_PCIERCX_RAS_EINJ_CTL6CHGV2(a) "PCIERCX_RAS_EINJ_CTL6CHGV2"
6421 #define busnum_ODY_PCIERCX_RAS_EINJ_CTL6CHGV2(a) (a)
6422 #define arguments_ODY_PCIERCX_RAS_EINJ_CTL6CHGV2(a) (a), -1, -1, -1
6423
6424 /**
6425 * Register (PCICONFIGRC) pcierc#_ras_einj_ctl6chgv3
6426 *
6427 * PCIe RC Vendor RAS DES Error Injection Control 6 (Change Value H3) Register
6428 */
6429 union ody_pciercx_ras_einj_ctl6chgv3 {
6430 uint32_t u;
6431 struct ody_pciercx_ras_einj_ctl6chgv3_s {
6432 uint32_t einj6_chg_val_h3 : 32;
6433 } s;
6434 /* struct ody_pciercx_ras_einj_ctl6chgv3_s cn; */
6435 };
6436 typedef union ody_pciercx_ras_einj_ctl6chgv3 ody_pciercx_ras_einj_ctl6chgv3_t;
6437
6438 static inline uint64_t ODY_PCIERCX_RAS_EINJ_CTL6CHGV3(uint64_t a) __attribute__ ((pure, always_inline));
ODY_PCIERCX_RAS_EINJ_CTL6CHGV3(uint64_t a)6439 static inline uint64_t ODY_PCIERCX_RAS_EINJ_CTL6CHGV3(uint64_t a)
6440 {
6441 if (a <= 15)
6442 return 0x2f4;
6443 __ody_csr_fatal("PCIERCX_RAS_EINJ_CTL6CHGV3", 1, a, 0, 0, 0, 0, 0);
6444 }
6445
6446 #define typedef_ODY_PCIERCX_RAS_EINJ_CTL6CHGV3(a) ody_pciercx_ras_einj_ctl6chgv3_t
6447 #define bustype_ODY_PCIERCX_RAS_EINJ_CTL6CHGV3(a) CSR_TYPE_PCICONFIGRC
6448 #define basename_ODY_PCIERCX_RAS_EINJ_CTL6CHGV3(a) "PCIERCX_RAS_EINJ_CTL6CHGV3"
6449 #define busnum_ODY_PCIERCX_RAS_EINJ_CTL6CHGV3(a) (a)
6450 #define arguments_ODY_PCIERCX_RAS_EINJ_CTL6CHGV3(a) (a), -1, -1, -1
6451
6452 /**
6453 * Register (PCICONFIGRC) pcierc#_ras_einj_ctl6cmpp0
6454 *
6455 * PCIe RC Vendor RAS DES Error Injection Control 6 (Compare Point H0) Register
6456 */
6457 union ody_pciercx_ras_einj_ctl6cmpp0 {
6458 uint32_t u;
6459 struct ody_pciercx_ras_einj_ctl6cmpp0_s {
6460 uint32_t einj6_com_pt_h0 : 32;
6461 } s;
6462 /* struct ody_pciercx_ras_einj_ctl6cmpp0_s cn; */
6463 };
6464 typedef union ody_pciercx_ras_einj_ctl6cmpp0 ody_pciercx_ras_einj_ctl6cmpp0_t;
6465
6466 static inline uint64_t ODY_PCIERCX_RAS_EINJ_CTL6CMPP0(uint64_t a) __attribute__ ((pure, always_inline));
ODY_PCIERCX_RAS_EINJ_CTL6CMPP0(uint64_t a)6467 static inline uint64_t ODY_PCIERCX_RAS_EINJ_CTL6CMPP0(uint64_t a)
6468 {
6469 if (a <= 15)
6470 return 0x2b8;
6471 __ody_csr_fatal("PCIERCX_RAS_EINJ_CTL6CMPP0", 1, a, 0, 0, 0, 0, 0);
6472 }
6473
6474 #define typedef_ODY_PCIERCX_RAS_EINJ_CTL6CMPP0(a) ody_pciercx_ras_einj_ctl6cmpp0_t
6475 #define bustype_ODY_PCIERCX_RAS_EINJ_CTL6CMPP0(a) CSR_TYPE_PCICONFIGRC
6476 #define basename_ODY_PCIERCX_RAS_EINJ_CTL6CMPP0(a) "PCIERCX_RAS_EINJ_CTL6CMPP0"
6477 #define busnum_ODY_PCIERCX_RAS_EINJ_CTL6CMPP0(a) (a)
6478 #define arguments_ODY_PCIERCX_RAS_EINJ_CTL6CMPP0(a) (a), -1, -1, -1
6479
6480 /**
6481 * Register (PCICONFIGRC) pcierc#_ras_einj_ctl6cmpp1
6482 *
6483 * PCIe RC Vendor RAS DES Error Injection Control 6 (Compare Point H1) Register
6484 */
6485 union ody_pciercx_ras_einj_ctl6cmpp1 {
6486 uint32_t u;
6487 struct ody_pciercx_ras_einj_ctl6cmpp1_s {
6488 uint32_t einj6_com_pt_h1 : 32;
6489 } s;
6490 /* struct ody_pciercx_ras_einj_ctl6cmpp1_s cn; */
6491 };
6492 typedef union ody_pciercx_ras_einj_ctl6cmpp1 ody_pciercx_ras_einj_ctl6cmpp1_t;
6493
6494 static inline uint64_t ODY_PCIERCX_RAS_EINJ_CTL6CMPP1(uint64_t a) __attribute__ ((pure, always_inline));
ODY_PCIERCX_RAS_EINJ_CTL6CMPP1(uint64_t a)6495 static inline uint64_t ODY_PCIERCX_RAS_EINJ_CTL6CMPP1(uint64_t a)
6496 {
6497 if (a <= 15)
6498 return 0x2bc;
6499 __ody_csr_fatal("PCIERCX_RAS_EINJ_CTL6CMPP1", 1, a, 0, 0, 0, 0, 0);
6500 }
6501
6502 #define typedef_ODY_PCIERCX_RAS_EINJ_CTL6CMPP1(a) ody_pciercx_ras_einj_ctl6cmpp1_t
6503 #define bustype_ODY_PCIERCX_RAS_EINJ_CTL6CMPP1(a) CSR_TYPE_PCICONFIGRC
6504 #define basename_ODY_PCIERCX_RAS_EINJ_CTL6CMPP1(a) "PCIERCX_RAS_EINJ_CTL6CMPP1"
6505 #define busnum_ODY_PCIERCX_RAS_EINJ_CTL6CMPP1(a) (a)
6506 #define arguments_ODY_PCIERCX_RAS_EINJ_CTL6CMPP1(a) (a), -1, -1, -1
6507
6508 /**
6509 * Register (PCICONFIGRC) pcierc#_ras_einj_ctl6cmpp2
6510 *
6511 * PCIe RC Vendor RAS DES Error Injection Control 6 (Compare Point H2) Register
6512 */
6513 union ody_pciercx_ras_einj_ctl6cmpp2 {
6514 uint32_t u;
6515 struct ody_pciercx_ras_einj_ctl6cmpp2_s {
6516 uint32_t einj6_com_pt_h2 : 32;
6517 } s;
6518 /* struct ody_pciercx_ras_einj_ctl6cmpp2_s cn; */
6519 };
6520 typedef union ody_pciercx_ras_einj_ctl6cmpp2 ody_pciercx_ras_einj_ctl6cmpp2_t;
6521
6522 static inline uint64_t ODY_PCIERCX_RAS_EINJ_CTL6CMPP2(uint64_t a) __attribute__ ((pure, always_inline));
ODY_PCIERCX_RAS_EINJ_CTL6CMPP2(uint64_t a)6523 static inline uint64_t ODY_PCIERCX_RAS_EINJ_CTL6CMPP2(uint64_t a)
6524 {
6525 if (a <= 15)
6526 return 0x2c0;
6527 __ody_csr_fatal("PCIERCX_RAS_EINJ_CTL6CMPP2", 1, a, 0, 0, 0, 0, 0);
6528 }
6529
6530 #define typedef_ODY_PCIERCX_RAS_EINJ_CTL6CMPP2(a) ody_pciercx_ras_einj_ctl6cmpp2_t
6531 #define bustype_ODY_PCIERCX_RAS_EINJ_CTL6CMPP2(a) CSR_TYPE_PCICONFIGRC
6532 #define basename_ODY_PCIERCX_RAS_EINJ_CTL6CMPP2(a) "PCIERCX_RAS_EINJ_CTL6CMPP2"
6533 #define busnum_ODY_PCIERCX_RAS_EINJ_CTL6CMPP2(a) (a)
6534 #define arguments_ODY_PCIERCX_RAS_EINJ_CTL6CMPP2(a) (a), -1, -1, -1
6535
6536 /**
6537 * Register (PCICONFIGRC) pcierc#_ras_einj_ctl6cmpp3
6538 *
6539 * PCIe RC Vendor RAS DES Error Injection Control 6 (Compare Point H3) Register
6540 */
6541 union ody_pciercx_ras_einj_ctl6cmpp3 {
6542 uint32_t u;
6543 struct ody_pciercx_ras_einj_ctl6cmpp3_s {
6544 uint32_t einj6_com_pt_h3 : 32;
6545 } s;
6546 /* struct ody_pciercx_ras_einj_ctl6cmpp3_s cn; */
6547 };
6548 typedef union ody_pciercx_ras_einj_ctl6cmpp3 ody_pciercx_ras_einj_ctl6cmpp3_t;
6549
6550 static inline uint64_t ODY_PCIERCX_RAS_EINJ_CTL6CMPP3(uint64_t a) __attribute__ ((pure, always_inline));
ODY_PCIERCX_RAS_EINJ_CTL6CMPP3(uint64_t a)6551 static inline uint64_t ODY_PCIERCX_RAS_EINJ_CTL6CMPP3(uint64_t a)
6552 {
6553 if (a <= 15)
6554 return 0x2c4;
6555 __ody_csr_fatal("PCIERCX_RAS_EINJ_CTL6CMPP3", 1, a, 0, 0, 0, 0, 0);
6556 }
6557
6558 #define typedef_ODY_PCIERCX_RAS_EINJ_CTL6CMPP3(a) ody_pciercx_ras_einj_ctl6cmpp3_t
6559 #define bustype_ODY_PCIERCX_RAS_EINJ_CTL6CMPP3(a) CSR_TYPE_PCICONFIGRC
6560 #define basename_ODY_PCIERCX_RAS_EINJ_CTL6CMPP3(a) "PCIERCX_RAS_EINJ_CTL6CMPP3"
6561 #define busnum_ODY_PCIERCX_RAS_EINJ_CTL6CMPP3(a) (a)
6562 #define arguments_ODY_PCIERCX_RAS_EINJ_CTL6CMPP3(a) (a), -1, -1, -1
6563
6564 /**
6565 * Register (PCICONFIGRC) pcierc#_ras_einj_ctl6cmpv0
6566 *
6567 * PCIe RC Vendor RAS DES Error Injection Control 6 (Compare Value H0) Register
6568 */
6569 union ody_pciercx_ras_einj_ctl6cmpv0 {
6570 uint32_t u;
6571 struct ody_pciercx_ras_einj_ctl6cmpv0_s {
6572 uint32_t einj6_com_val_h0 : 32;
6573 } s;
6574 /* struct ody_pciercx_ras_einj_ctl6cmpv0_s cn; */
6575 };
6576 typedef union ody_pciercx_ras_einj_ctl6cmpv0 ody_pciercx_ras_einj_ctl6cmpv0_t;
6577
6578 static inline uint64_t ODY_PCIERCX_RAS_EINJ_CTL6CMPV0(uint64_t a) __attribute__ ((pure, always_inline));
ODY_PCIERCX_RAS_EINJ_CTL6CMPV0(uint64_t a)6579 static inline uint64_t ODY_PCIERCX_RAS_EINJ_CTL6CMPV0(uint64_t a)
6580 {
6581 if (a <= 15)
6582 return 0x2c8;
6583 __ody_csr_fatal("PCIERCX_RAS_EINJ_CTL6CMPV0", 1, a, 0, 0, 0, 0, 0);
6584 }
6585
6586 #define typedef_ODY_PCIERCX_RAS_EINJ_CTL6CMPV0(a) ody_pciercx_ras_einj_ctl6cmpv0_t
6587 #define bustype_ODY_PCIERCX_RAS_EINJ_CTL6CMPV0(a) CSR_TYPE_PCICONFIGRC
6588 #define basename_ODY_PCIERCX_RAS_EINJ_CTL6CMPV0(a) "PCIERCX_RAS_EINJ_CTL6CMPV0"
6589 #define busnum_ODY_PCIERCX_RAS_EINJ_CTL6CMPV0(a) (a)
6590 #define arguments_ODY_PCIERCX_RAS_EINJ_CTL6CMPV0(a) (a), -1, -1, -1
6591
6592 /**
6593 * Register (PCICONFIGRC) pcierc#_ras_einj_ctl6cmpv1
6594 *
6595 * PCIe RC Vendor RAS DES Error Injection Control 6 (Compare Value H1) Register
6596 */
6597 union ody_pciercx_ras_einj_ctl6cmpv1 {
6598 uint32_t u;
6599 struct ody_pciercx_ras_einj_ctl6cmpv1_s {
6600 uint32_t einj6_com_val_h1 : 32;
6601 } s;
6602 /* struct ody_pciercx_ras_einj_ctl6cmpv1_s cn; */
6603 };
6604 typedef union ody_pciercx_ras_einj_ctl6cmpv1 ody_pciercx_ras_einj_ctl6cmpv1_t;
6605
6606 static inline uint64_t ODY_PCIERCX_RAS_EINJ_CTL6CMPV1(uint64_t a) __attribute__ ((pure, always_inline));
ODY_PCIERCX_RAS_EINJ_CTL6CMPV1(uint64_t a)6607 static inline uint64_t ODY_PCIERCX_RAS_EINJ_CTL6CMPV1(uint64_t a)
6608 {
6609 if (a <= 15)
6610 return 0x2cc;
6611 __ody_csr_fatal("PCIERCX_RAS_EINJ_CTL6CMPV1", 1, a, 0, 0, 0, 0, 0);
6612 }
6613
6614 #define typedef_ODY_PCIERCX_RAS_EINJ_CTL6CMPV1(a) ody_pciercx_ras_einj_ctl6cmpv1_t
6615 #define bustype_ODY_PCIERCX_RAS_EINJ_CTL6CMPV1(a) CSR_TYPE_PCICONFIGRC
6616 #define basename_ODY_PCIERCX_RAS_EINJ_CTL6CMPV1(a) "PCIERCX_RAS_EINJ_CTL6CMPV1"
6617 #define busnum_ODY_PCIERCX_RAS_EINJ_CTL6CMPV1(a) (a)
6618 #define arguments_ODY_PCIERCX_RAS_EINJ_CTL6CMPV1(a) (a), -1, -1, -1
6619
6620 /**
6621 * Register (PCICONFIGRC) pcierc#_ras_einj_ctl6cmpv2
6622 *
6623 * PCIe RC Vendor RAS DES Error Injection Control 6 (Compare Value H2) Register
6624 */
6625 union ody_pciercx_ras_einj_ctl6cmpv2 {
6626 uint32_t u;
6627 struct ody_pciercx_ras_einj_ctl6cmpv2_s {
6628 uint32_t einj6_com_val_h2 : 32;
6629 } s;
6630 /* struct ody_pciercx_ras_einj_ctl6cmpv2_s cn; */
6631 };
6632 typedef union ody_pciercx_ras_einj_ctl6cmpv2 ody_pciercx_ras_einj_ctl6cmpv2_t;
6633
6634 static inline uint64_t ODY_PCIERCX_RAS_EINJ_CTL6CMPV2(uint64_t a) __attribute__ ((pure, always_inline));
ODY_PCIERCX_RAS_EINJ_CTL6CMPV2(uint64_t a)6635 static inline uint64_t ODY_PCIERCX_RAS_EINJ_CTL6CMPV2(uint64_t a)
6636 {
6637 if (a <= 15)
6638 return 0x2d0;
6639 __ody_csr_fatal("PCIERCX_RAS_EINJ_CTL6CMPV2", 1, a, 0, 0, 0, 0, 0);
6640 }
6641
6642 #define typedef_ODY_PCIERCX_RAS_EINJ_CTL6CMPV2(a) ody_pciercx_ras_einj_ctl6cmpv2_t
6643 #define bustype_ODY_PCIERCX_RAS_EINJ_CTL6CMPV2(a) CSR_TYPE_PCICONFIGRC
6644 #define basename_ODY_PCIERCX_RAS_EINJ_CTL6CMPV2(a) "PCIERCX_RAS_EINJ_CTL6CMPV2"
6645 #define busnum_ODY_PCIERCX_RAS_EINJ_CTL6CMPV2(a) (a)
6646 #define arguments_ODY_PCIERCX_RAS_EINJ_CTL6CMPV2(a) (a), -1, -1, -1
6647
6648 /**
6649 * Register (PCICONFIGRC) pcierc#_ras_einj_ctl6cmpv3
6650 *
6651 * PCIe RC Vendor RAS DES Error Injection Control 6 (Compare Value H3) Register
6652 */
6653 union ody_pciercx_ras_einj_ctl6cmpv3 {
6654 uint32_t u;
6655 struct ody_pciercx_ras_einj_ctl6cmpv3_s {
6656 uint32_t einj6_com_val_h3 : 32;
6657 } s;
6658 /* struct ody_pciercx_ras_einj_ctl6cmpv3_s cn; */
6659 };
6660 typedef union ody_pciercx_ras_einj_ctl6cmpv3 ody_pciercx_ras_einj_ctl6cmpv3_t;
6661
6662 static inline uint64_t ODY_PCIERCX_RAS_EINJ_CTL6CMPV3(uint64_t a) __attribute__ ((pure, always_inline));
ODY_PCIERCX_RAS_EINJ_CTL6CMPV3(uint64_t a)6663 static inline uint64_t ODY_PCIERCX_RAS_EINJ_CTL6CMPV3(uint64_t a)
6664 {
6665 if (a <= 15)
6666 return 0x2d4;
6667 __ody_csr_fatal("PCIERCX_RAS_EINJ_CTL6CMPV3", 1, a, 0, 0, 0, 0, 0);
6668 }
6669
6670 #define typedef_ODY_PCIERCX_RAS_EINJ_CTL6CMPV3(a) ody_pciercx_ras_einj_ctl6cmpv3_t
6671 #define bustype_ODY_PCIERCX_RAS_EINJ_CTL6CMPV3(a) CSR_TYPE_PCICONFIGRC
6672 #define basename_ODY_PCIERCX_RAS_EINJ_CTL6CMPV3(a) "PCIERCX_RAS_EINJ_CTL6CMPV3"
6673 #define busnum_ODY_PCIERCX_RAS_EINJ_CTL6CMPV3(a) (a)
6674 #define arguments_ODY_PCIERCX_RAS_EINJ_CTL6CMPV3(a) (a), -1, -1, -1
6675
6676 /**
6677 * Register (PCICONFIGRC) pcierc#_ras_einj_ctl6pe
6678 *
6679 * PCIe RC Vendor RAS DES Error Injection Control 6 (Packet Error) Register
6680 */
6681 union ody_pciercx_ras_einj_ctl6pe {
6682 uint32_t u;
6683 struct ody_pciercx_ras_einj_ctl6pe_s {
6684 uint32_t einj6_cnt : 8;
6685 uint32_t einj6_inv_cntrl : 1;
6686 uint32_t einj6_pkt_typ : 3;
6687 uint32_t reserved_12_31 : 20;
6688 } s;
6689 /* struct ody_pciercx_ras_einj_ctl6pe_s cn; */
6690 };
6691 typedef union ody_pciercx_ras_einj_ctl6pe ody_pciercx_ras_einj_ctl6pe_t;
6692
6693 static inline uint64_t ODY_PCIERCX_RAS_EINJ_CTL6PE(uint64_t a) __attribute__ ((pure, always_inline));
ODY_PCIERCX_RAS_EINJ_CTL6PE(uint64_t a)6694 static inline uint64_t ODY_PCIERCX_RAS_EINJ_CTL6PE(uint64_t a)
6695 {
6696 if (a <= 15)
6697 return 0x2f8;
6698 __ody_csr_fatal("PCIERCX_RAS_EINJ_CTL6PE", 1, a, 0, 0, 0, 0, 0);
6699 }
6700
6701 #define typedef_ODY_PCIERCX_RAS_EINJ_CTL6PE(a) ody_pciercx_ras_einj_ctl6pe_t
6702 #define bustype_ODY_PCIERCX_RAS_EINJ_CTL6PE(a) CSR_TYPE_PCICONFIGRC
6703 #define basename_ODY_PCIERCX_RAS_EINJ_CTL6PE(a) "PCIERCX_RAS_EINJ_CTL6PE"
6704 #define busnum_ODY_PCIERCX_RAS_EINJ_CTL6PE(a) (a)
6705 #define arguments_ODY_PCIERCX_RAS_EINJ_CTL6PE(a) (a), -1, -1, -1
6706
6707 /**
6708 * Register (PCICONFIGRC) pcierc#_ras_einj_en
6709 *
6710 * PCIe RC Vendor RAS DES Error Injection Enable Register
6711 */
6712 union ody_pciercx_ras_einj_en {
6713 uint32_t u;
6714 struct ody_pciercx_ras_einj_en_s {
6715 uint32_t einj0_en : 1;
6716 uint32_t einj1_en : 1;
6717 uint32_t einj2_en : 1;
6718 uint32_t einj3_en : 1;
6719 uint32_t einj4_en : 1;
6720 uint32_t einj5_en : 1;
6721 uint32_t einj6_en : 1;
6722 uint32_t reserved_7_31 : 25;
6723 } s;
6724 /* struct ody_pciercx_ras_einj_en_s cn; */
6725 };
6726 typedef union ody_pciercx_ras_einj_en ody_pciercx_ras_einj_en_t;
6727
6728 static inline uint64_t ODY_PCIERCX_RAS_EINJ_EN(uint64_t a) __attribute__ ((pure, always_inline));
ODY_PCIERCX_RAS_EINJ_EN(uint64_t a)6729 static inline uint64_t ODY_PCIERCX_RAS_EINJ_EN(uint64_t a)
6730 {
6731 if (a <= 15)
6732 return 0x29c;
6733 __ody_csr_fatal("PCIERCX_RAS_EINJ_EN", 1, a, 0, 0, 0, 0, 0);
6734 }
6735
6736 #define typedef_ODY_PCIERCX_RAS_EINJ_EN(a) ody_pciercx_ras_einj_en_t
6737 #define bustype_ODY_PCIERCX_RAS_EINJ_EN(a) CSR_TYPE_PCICONFIGRC
6738 #define basename_ODY_PCIERCX_RAS_EINJ_EN(a) "PCIERCX_RAS_EINJ_EN"
6739 #define busnum_ODY_PCIERCX_RAS_EINJ_EN(a) (a)
6740 #define arguments_ODY_PCIERCX_RAS_EINJ_EN(a) (a), -1, -1, -1
6741
6742 /**
6743 * Register (PCICONFIGRC) pcierc#_ras_hdr
6744 *
6745 * PCIe RC Vendor RAS DES Header Register
6746 */
6747 union ody_pciercx_ras_hdr {
6748 uint32_t u;
6749 struct ody_pciercx_ras_hdr_s {
6750 uint32_t vsec_id : 16;
6751 uint32_t vsec_rev : 4;
6752 uint32_t vsec_length : 12;
6753 } s;
6754 /* struct ody_pciercx_ras_hdr_s cn; */
6755 };
6756 typedef union ody_pciercx_ras_hdr ody_pciercx_ras_hdr_t;
6757
6758 static inline uint64_t ODY_PCIERCX_RAS_HDR(uint64_t a) __attribute__ ((pure, always_inline));
ODY_PCIERCX_RAS_HDR(uint64_t a)6759 static inline uint64_t ODY_PCIERCX_RAS_HDR(uint64_t a)
6760 {
6761 if (a <= 15)
6762 return 0x270;
6763 __ody_csr_fatal("PCIERCX_RAS_HDR", 1, a, 0, 0, 0, 0, 0);
6764 }
6765
6766 #define typedef_ODY_PCIERCX_RAS_HDR(a) ody_pciercx_ras_hdr_t
6767 #define bustype_ODY_PCIERCX_RAS_HDR(a) CSR_TYPE_PCICONFIGRC
6768 #define basename_ODY_PCIERCX_RAS_HDR(a) "PCIERCX_RAS_HDR"
6769 #define busnum_ODY_PCIERCX_RAS_HDR(a) (a)
6770 #define arguments_ODY_PCIERCX_RAS_HDR(a) (a), -1, -1, -1
6771
6772 /**
6773 * Register (PCICONFIGRC) pcierc#_ras_sd_ctl1
6774 *
6775 * PCIe RC Vendor RAS DES Silicon Debug Control 1 Register
6776 */
6777 union ody_pciercx_ras_sd_ctl1 {
6778 uint32_t u;
6779 struct ody_pciercx_ras_sd_ctl1_s {
6780 uint32_t force_detect_lane : 16;
6781 uint32_t force_detect_lane_en : 1;
6782 uint32_t reserved_17_19 : 3;
6783 uint32_t tx_eios_num : 2;
6784 uint32_t lp_intv : 2;
6785 uint32_t reserved_24_31 : 8;
6786 } s;
6787 /* struct ody_pciercx_ras_sd_ctl1_s cn; */
6788 };
6789 typedef union ody_pciercx_ras_sd_ctl1 ody_pciercx_ras_sd_ctl1_t;
6790
6791 static inline uint64_t ODY_PCIERCX_RAS_SD_CTL1(uint64_t a) __attribute__ ((pure, always_inline));
ODY_PCIERCX_RAS_SD_CTL1(uint64_t a)6792 static inline uint64_t ODY_PCIERCX_RAS_SD_CTL1(uint64_t a)
6793 {
6794 if (a <= 15)
6795 return 0x30c;
6796 __ody_csr_fatal("PCIERCX_RAS_SD_CTL1", 1, a, 0, 0, 0, 0, 0);
6797 }
6798
6799 #define typedef_ODY_PCIERCX_RAS_SD_CTL1(a) ody_pciercx_ras_sd_ctl1_t
6800 #define bustype_ODY_PCIERCX_RAS_SD_CTL1(a) CSR_TYPE_PCICONFIGRC
6801 #define basename_ODY_PCIERCX_RAS_SD_CTL1(a) "PCIERCX_RAS_SD_CTL1"
6802 #define busnum_ODY_PCIERCX_RAS_SD_CTL1(a) (a)
6803 #define arguments_ODY_PCIERCX_RAS_SD_CTL1(a) (a), -1, -1, -1
6804
6805 /**
6806 * Register (PCICONFIGRC) pcierc#_ras_sd_ctl2
6807 *
6808 * PCIe RC Vendor RAS DES Silicon Debug Control 2 Register
6809 */
6810 union ody_pciercx_ras_sd_ctl2 {
6811 uint32_t u;
6812 struct ody_pciercx_ras_sd_ctl2_s {
6813 uint32_t hold_ltssm : 1;
6814 uint32_t rcry_req : 1;
6815 uint32_t noack_force_lnkdn : 1;
6816 uint32_t reserved_3_7 : 5;
6817 uint32_t dir_recidle_config : 1;
6818 uint32_t dir_polcmp_to_det : 1;
6819 uint32_t dir_lpbslv_to_exit : 1;
6820 uint32_t reserved_11_15 : 5;
6821 uint32_t fr_err_rcvy_dis : 1;
6822 uint32_t reserved_17_31 : 15;
6823 } s;
6824 /* struct ody_pciercx_ras_sd_ctl2_s cn; */
6825 };
6826 typedef union ody_pciercx_ras_sd_ctl2 ody_pciercx_ras_sd_ctl2_t;
6827
6828 static inline uint64_t ODY_PCIERCX_RAS_SD_CTL2(uint64_t a) __attribute__ ((pure, always_inline));
ODY_PCIERCX_RAS_SD_CTL2(uint64_t a)6829 static inline uint64_t ODY_PCIERCX_RAS_SD_CTL2(uint64_t a)
6830 {
6831 if (a <= 15)
6832 return 0x310;
6833 __ody_csr_fatal("PCIERCX_RAS_SD_CTL2", 1, a, 0, 0, 0, 0, 0);
6834 }
6835
6836 #define typedef_ODY_PCIERCX_RAS_SD_CTL2(a) ody_pciercx_ras_sd_ctl2_t
6837 #define bustype_ODY_PCIERCX_RAS_SD_CTL2(a) CSR_TYPE_PCICONFIGRC
6838 #define basename_ODY_PCIERCX_RAS_SD_CTL2(a) "PCIERCX_RAS_SD_CTL2"
6839 #define busnum_ODY_PCIERCX_RAS_SD_CTL2(a) (a)
6840 #define arguments_ODY_PCIERCX_RAS_SD_CTL2(a) (a), -1, -1, -1
6841
6842 /**
6843 * Register (PCICONFIGRC) pcierc#_ras_sd_eq_ctl1
6844 *
6845 * PCIe RC Vendor RAS DES Silicon Debug EQ Control 1 Register
6846 */
6847 union ody_pciercx_ras_sd_eq_ctl1 {
6848 uint32_t u;
6849 struct ody_pciercx_ras_sd_eq_ctl1_s {
6850 uint32_t eq_lane_sel : 4;
6851 uint32_t eq_rate_sel : 2;
6852 uint32_t reserved_6_7 : 2;
6853 uint32_t ext_eq_timeout : 2;
6854 uint32_t reserved_10_15 : 6;
6855 uint32_t eval_interval_time : 2;
6856 uint32_t reserved_18_22 : 5;
6857 uint32_t fom_target_en : 1;
6858 uint32_t fom_target : 8;
6859 } s;
6860 /* struct ody_pciercx_ras_sd_eq_ctl1_s cn; */
6861 };
6862 typedef union ody_pciercx_ras_sd_eq_ctl1 ody_pciercx_ras_sd_eq_ctl1_t;
6863
6864 static inline uint64_t ODY_PCIERCX_RAS_SD_EQ_CTL1(uint64_t a) __attribute__ ((pure, always_inline));
ODY_PCIERCX_RAS_SD_EQ_CTL1(uint64_t a)6865 static inline uint64_t ODY_PCIERCX_RAS_SD_EQ_CTL1(uint64_t a)
6866 {
6867 if (a <= 15)
6868 return 0x33c;
6869 __ody_csr_fatal("PCIERCX_RAS_SD_EQ_CTL1", 1, a, 0, 0, 0, 0, 0);
6870 }
6871
6872 #define typedef_ODY_PCIERCX_RAS_SD_EQ_CTL1(a) ody_pciercx_ras_sd_eq_ctl1_t
6873 #define bustype_ODY_PCIERCX_RAS_SD_EQ_CTL1(a) CSR_TYPE_PCICONFIGRC
6874 #define basename_ODY_PCIERCX_RAS_SD_EQ_CTL1(a) "PCIERCX_RAS_SD_EQ_CTL1"
6875 #define busnum_ODY_PCIERCX_RAS_SD_EQ_CTL1(a) (a)
6876 #define arguments_ODY_PCIERCX_RAS_SD_EQ_CTL1(a) (a), -1, -1, -1
6877
6878 /**
6879 * Register (PCICONFIGRC) pcierc#_ras_sd_eq_ctl2
6880 *
6881 * PCIe RC Vendor RAS DES Silicon Debug EQ Control 2 Register
6882 */
6883 union ody_pciercx_ras_sd_eq_ctl2 {
6884 uint32_t u;
6885 struct ody_pciercx_ras_sd_eq_ctl2_s {
6886 uint32_t force_loc_txpre_cur : 6;
6887 uint32_t force_loc_tx_cur : 6;
6888 uint32_t force_loc_txpost_cur : 6;
6889 uint32_t force_loc_rxhint : 3;
6890 uint32_t reserved_21_23 : 3;
6891 uint32_t force_loc_txpre : 4;
6892 uint32_t force_loc_txcoef_en : 1;
6893 uint32_t force_loc_rxhint_en : 1;
6894 uint32_t force_loc_txpre_en : 1;
6895 uint32_t reserved_31 : 1;
6896 } s;
6897 /* struct ody_pciercx_ras_sd_eq_ctl2_s cn; */
6898 };
6899 typedef union ody_pciercx_ras_sd_eq_ctl2 ody_pciercx_ras_sd_eq_ctl2_t;
6900
6901 static inline uint64_t ODY_PCIERCX_RAS_SD_EQ_CTL2(uint64_t a) __attribute__ ((pure, always_inline));
ODY_PCIERCX_RAS_SD_EQ_CTL2(uint64_t a)6902 static inline uint64_t ODY_PCIERCX_RAS_SD_EQ_CTL2(uint64_t a)
6903 {
6904 if (a <= 15)
6905 return 0x340;
6906 __ody_csr_fatal("PCIERCX_RAS_SD_EQ_CTL2", 1, a, 0, 0, 0, 0, 0);
6907 }
6908
6909 #define typedef_ODY_PCIERCX_RAS_SD_EQ_CTL2(a) ody_pciercx_ras_sd_eq_ctl2_t
6910 #define bustype_ODY_PCIERCX_RAS_SD_EQ_CTL2(a) CSR_TYPE_PCICONFIGRC
6911 #define basename_ODY_PCIERCX_RAS_SD_EQ_CTL2(a) "PCIERCX_RAS_SD_EQ_CTL2"
6912 #define busnum_ODY_PCIERCX_RAS_SD_EQ_CTL2(a) (a)
6913 #define arguments_ODY_PCIERCX_RAS_SD_EQ_CTL2(a) (a), -1, -1, -1
6914
6915 /**
6916 * Register (PCICONFIGRC) pcierc#_ras_sd_eq_ctl3
6917 *
6918 * PCIe RC Vendor RAS DES Silicon Debug EQ Control 3 Register
6919 */
6920 union ody_pciercx_ras_sd_eq_ctl3 {
6921 uint32_t u;
6922 struct ody_pciercx_ras_sd_eq_ctl3_s {
6923 uint32_t force_rem_txpre_cur : 6;
6924 uint32_t force_rem_tx_cur : 6;
6925 uint32_t force_rem_txpost_cur : 6;
6926 uint32_t reserved_18_27 : 10;
6927 uint32_t force_rem_txcoef_en : 1;
6928 uint32_t reserved_29_31 : 3;
6929 } s;
6930 /* struct ody_pciercx_ras_sd_eq_ctl3_s cn; */
6931 };
6932 typedef union ody_pciercx_ras_sd_eq_ctl3 ody_pciercx_ras_sd_eq_ctl3_t;
6933
6934 static inline uint64_t ODY_PCIERCX_RAS_SD_EQ_CTL3(uint64_t a) __attribute__ ((pure, always_inline));
ODY_PCIERCX_RAS_SD_EQ_CTL3(uint64_t a)6935 static inline uint64_t ODY_PCIERCX_RAS_SD_EQ_CTL3(uint64_t a)
6936 {
6937 if (a <= 15)
6938 return 0x344;
6939 __ody_csr_fatal("PCIERCX_RAS_SD_EQ_CTL3", 1, a, 0, 0, 0, 0, 0);
6940 }
6941
6942 #define typedef_ODY_PCIERCX_RAS_SD_EQ_CTL3(a) ody_pciercx_ras_sd_eq_ctl3_t
6943 #define bustype_ODY_PCIERCX_RAS_SD_EQ_CTL3(a) CSR_TYPE_PCICONFIGRC
6944 #define basename_ODY_PCIERCX_RAS_SD_EQ_CTL3(a) "PCIERCX_RAS_SD_EQ_CTL3"
6945 #define busnum_ODY_PCIERCX_RAS_SD_EQ_CTL3(a) (a)
6946 #define arguments_ODY_PCIERCX_RAS_SD_EQ_CTL3(a) (a), -1, -1, -1
6947
6948 /**
6949 * Register (PCICONFIGRC) pcierc#_ras_sd_eq_stat1
6950 *
6951 * PCIe RC Vendor RAS DES Silicon Debug EQ Status 1 Register
6952 */
6953 union ody_pciercx_ras_sd_eq_stat1 {
6954 uint32_t u;
6955 struct ody_pciercx_ras_sd_eq_stat1_s {
6956 uint32_t eq_sequence : 1;
6957 uint32_t eq_conv_info : 2;
6958 uint32_t reserved_3 : 1;
6959 uint32_t eq_rulea_viol : 1;
6960 uint32_t eq_ruleb_viol : 1;
6961 uint32_t eq_rulec_viol : 1;
6962 uint32_t eq_reject_event : 1;
6963 uint32_t reserved_8_31 : 24;
6964 } s;
6965 /* struct ody_pciercx_ras_sd_eq_stat1_s cn; */
6966 };
6967 typedef union ody_pciercx_ras_sd_eq_stat1 ody_pciercx_ras_sd_eq_stat1_t;
6968
6969 static inline uint64_t ODY_PCIERCX_RAS_SD_EQ_STAT1(uint64_t a) __attribute__ ((pure, always_inline));
ODY_PCIERCX_RAS_SD_EQ_STAT1(uint64_t a)6970 static inline uint64_t ODY_PCIERCX_RAS_SD_EQ_STAT1(uint64_t a)
6971 {
6972 if (a <= 15)
6973 return 0x34c;
6974 __ody_csr_fatal("PCIERCX_RAS_SD_EQ_STAT1", 1, a, 0, 0, 0, 0, 0);
6975 }
6976
6977 #define typedef_ODY_PCIERCX_RAS_SD_EQ_STAT1(a) ody_pciercx_ras_sd_eq_stat1_t
6978 #define bustype_ODY_PCIERCX_RAS_SD_EQ_STAT1(a) CSR_TYPE_PCICONFIGRC
6979 #define basename_ODY_PCIERCX_RAS_SD_EQ_STAT1(a) "PCIERCX_RAS_SD_EQ_STAT1"
6980 #define busnum_ODY_PCIERCX_RAS_SD_EQ_STAT1(a) (a)
6981 #define arguments_ODY_PCIERCX_RAS_SD_EQ_STAT1(a) (a), -1, -1, -1
6982
6983 /**
6984 * Register (PCICONFIGRC) pcierc#_ras_sd_eq_stat2
6985 *
6986 * PCIe RC Vendor RAS DES Silicon Debug EQ Status 2 Register
6987 */
6988 union ody_pciercx_ras_sd_eq_stat2 {
6989 uint32_t u;
6990 struct ody_pciercx_ras_sd_eq_stat2_s {
6991 uint32_t eq_loc_pre_cur : 6;
6992 uint32_t eq_loc_cur : 6;
6993 uint32_t eq_loc_post_cur : 6;
6994 uint32_t eq_loc_rxhint : 3;
6995 uint32_t reserved_21_23 : 3;
6996 uint32_t eq_loc_fom_val : 8;
6997 } s;
6998 /* struct ody_pciercx_ras_sd_eq_stat2_s cn; */
6999 };
7000 typedef union ody_pciercx_ras_sd_eq_stat2 ody_pciercx_ras_sd_eq_stat2_t;
7001
7002 static inline uint64_t ODY_PCIERCX_RAS_SD_EQ_STAT2(uint64_t a) __attribute__ ((pure, always_inline));
ODY_PCIERCX_RAS_SD_EQ_STAT2(uint64_t a)7003 static inline uint64_t ODY_PCIERCX_RAS_SD_EQ_STAT2(uint64_t a)
7004 {
7005 if (a <= 15)
7006 return 0x350;
7007 __ody_csr_fatal("PCIERCX_RAS_SD_EQ_STAT2", 1, a, 0, 0, 0, 0, 0);
7008 }
7009
7010 #define typedef_ODY_PCIERCX_RAS_SD_EQ_STAT2(a) ody_pciercx_ras_sd_eq_stat2_t
7011 #define bustype_ODY_PCIERCX_RAS_SD_EQ_STAT2(a) CSR_TYPE_PCICONFIGRC
7012 #define basename_ODY_PCIERCX_RAS_SD_EQ_STAT2(a) "PCIERCX_RAS_SD_EQ_STAT2"
7013 #define busnum_ODY_PCIERCX_RAS_SD_EQ_STAT2(a) (a)
7014 #define arguments_ODY_PCIERCX_RAS_SD_EQ_STAT2(a) (a), -1, -1, -1
7015
7016 /**
7017 * Register (PCICONFIGRC) pcierc#_ras_sd_eq_stat3
7018 *
7019 * PCIe RC Vendor RAS DES Silicon Debug EQ Status 3 Register
7020 */
7021 union ody_pciercx_ras_sd_eq_stat3 {
7022 uint32_t u;
7023 struct ody_pciercx_ras_sd_eq_stat3_s {
7024 uint32_t eq_rem_pre_cur : 6;
7025 uint32_t eq_rem_cur : 6;
7026 uint32_t eq_rem_post_cur : 6;
7027 uint32_t eq_rem_lf : 6;
7028 uint32_t eq_rem_fs : 6;
7029 uint32_t reserved_30_31 : 2;
7030 } s;
7031 /* struct ody_pciercx_ras_sd_eq_stat3_s cn; */
7032 };
7033 typedef union ody_pciercx_ras_sd_eq_stat3 ody_pciercx_ras_sd_eq_stat3_t;
7034
7035 static inline uint64_t ODY_PCIERCX_RAS_SD_EQ_STAT3(uint64_t a) __attribute__ ((pure, always_inline));
ODY_PCIERCX_RAS_SD_EQ_STAT3(uint64_t a)7036 static inline uint64_t ODY_PCIERCX_RAS_SD_EQ_STAT3(uint64_t a)
7037 {
7038 if (a <= 15)
7039 return 0x354;
7040 __ody_csr_fatal("PCIERCX_RAS_SD_EQ_STAT3", 1, a, 0, 0, 0, 0, 0);
7041 }
7042
7043 #define typedef_ODY_PCIERCX_RAS_SD_EQ_STAT3(a) ody_pciercx_ras_sd_eq_stat3_t
7044 #define bustype_ODY_PCIERCX_RAS_SD_EQ_STAT3(a) CSR_TYPE_PCICONFIGRC
7045 #define basename_ODY_PCIERCX_RAS_SD_EQ_STAT3(a) "PCIERCX_RAS_SD_EQ_STAT3"
7046 #define busnum_ODY_PCIERCX_RAS_SD_EQ_STAT3(a) (a)
7047 #define arguments_ODY_PCIERCX_RAS_SD_EQ_STAT3(a) (a), -1, -1, -1
7048
7049 /**
7050 * Register (PCICONFIGRC) pcierc#_ras_sd_l1lane
7051 *
7052 * PCIe RC Vendor RAS DES Silicon Debug Status L1Lane Register
7053 */
7054 union ody_pciercx_ras_sd_l1lane {
7055 uint32_t u;
7056 struct ody_pciercx_ras_sd_l1lane_s {
7057 uint32_t lane_select : 4;
7058 uint32_t reserved_4_15 : 12;
7059 uint32_t pipe_rxpol : 1;
7060 uint32_t pipe_det_lane : 1;
7061 uint32_t pipe_rxvalid : 1;
7062 uint32_t pipe_rxelecidle : 1;
7063 uint32_t pipe_txelecidle : 1;
7064 uint32_t reserved_21_23 : 3;
7065 uint32_t deskew_ptr : 8;
7066 } s;
7067 /* struct ody_pciercx_ras_sd_l1lane_s cn; */
7068 };
7069 typedef union ody_pciercx_ras_sd_l1lane ody_pciercx_ras_sd_l1lane_t;
7070
7071 static inline uint64_t ODY_PCIERCX_RAS_SD_L1LANE(uint64_t a) __attribute__ ((pure, always_inline));
ODY_PCIERCX_RAS_SD_L1LANE(uint64_t a)7072 static inline uint64_t ODY_PCIERCX_RAS_SD_L1LANE(uint64_t a)
7073 {
7074 if (a <= 15)
7075 return 0x31c;
7076 __ody_csr_fatal("PCIERCX_RAS_SD_L1LANE", 1, a, 0, 0, 0, 0, 0);
7077 }
7078
7079 #define typedef_ODY_PCIERCX_RAS_SD_L1LANE(a) ody_pciercx_ras_sd_l1lane_t
7080 #define bustype_ODY_PCIERCX_RAS_SD_L1LANE(a) CSR_TYPE_PCICONFIGRC
7081 #define basename_ODY_PCIERCX_RAS_SD_L1LANE(a) "PCIERCX_RAS_SD_L1LANE"
7082 #define busnum_ODY_PCIERCX_RAS_SD_L1LANE(a) (a)
7083 #define arguments_ODY_PCIERCX_RAS_SD_L1LANE(a) (a), -1, -1, -1
7084
7085 /**
7086 * Register (PCICONFIGRC) pcierc#_ras_sd_l1ltssm
7087 *
7088 * PCIe RC Vendor RAS DES Silicon Debug Status L1LTSSM Register
7089 */
7090 union ody_pciercx_ras_sd_l1ltssm {
7091 uint32_t u;
7092 struct ody_pciercx_ras_sd_l1ltssm_s {
7093 uint32_t framing_err_ptr : 7;
7094 uint32_t framing_err : 1;
7095 uint32_t pipe_pwr_dwn : 3;
7096 uint32_t reserved_11_14 : 4;
7097 uint32_t lane_rev : 1;
7098 uint32_t ltssm_var : 16;
7099 } s;
7100 /* struct ody_pciercx_ras_sd_l1ltssm_s cn; */
7101 };
7102 typedef union ody_pciercx_ras_sd_l1ltssm ody_pciercx_ras_sd_l1ltssm_t;
7103
7104 static inline uint64_t ODY_PCIERCX_RAS_SD_L1LTSSM(uint64_t a) __attribute__ ((pure, always_inline));
ODY_PCIERCX_RAS_SD_L1LTSSM(uint64_t a)7105 static inline uint64_t ODY_PCIERCX_RAS_SD_L1LTSSM(uint64_t a)
7106 {
7107 if (a <= 15)
7108 return 0x320;
7109 __ody_csr_fatal("PCIERCX_RAS_SD_L1LTSSM", 1, a, 0, 0, 0, 0, 0);
7110 }
7111
7112 #define typedef_ODY_PCIERCX_RAS_SD_L1LTSSM(a) ody_pciercx_ras_sd_l1ltssm_t
7113 #define bustype_ODY_PCIERCX_RAS_SD_L1LTSSM(a) CSR_TYPE_PCICONFIGRC
7114 #define basename_ODY_PCIERCX_RAS_SD_L1LTSSM(a) "PCIERCX_RAS_SD_L1LTSSM"
7115 #define busnum_ODY_PCIERCX_RAS_SD_L1LTSSM(a) (a)
7116 #define arguments_ODY_PCIERCX_RAS_SD_L1LTSSM(a) (a), -1, -1, -1
7117
7118 /**
7119 * Register (PCICONFIGRC) pcierc#_ras_sd_statusl2
7120 *
7121 * PCIe RC Vendor RAS DES Silicon Debug Status L2 Register
7122 */
7123 union ody_pciercx_ras_sd_statusl2 {
7124 uint32_t u;
7125 struct ody_pciercx_ras_sd_statusl2_s {
7126 uint32_t tx_ack_seq_no : 12;
7127 uint32_t rx_ack_seq_no : 12;
7128 uint32_t dlcmsm : 2;
7129 uint32_t fc_init1 : 1;
7130 uint32_t fc_init2 : 1;
7131 uint32_t reserved_28_31 : 4;
7132 } s;
7133 /* struct ody_pciercx_ras_sd_statusl2_s cn; */
7134 };
7135 typedef union ody_pciercx_ras_sd_statusl2 ody_pciercx_ras_sd_statusl2_t;
7136
7137 static inline uint64_t ODY_PCIERCX_RAS_SD_STATUSL2(uint64_t a) __attribute__ ((pure, always_inline));
ODY_PCIERCX_RAS_SD_STATUSL2(uint64_t a)7138 static inline uint64_t ODY_PCIERCX_RAS_SD_STATUSL2(uint64_t a)
7139 {
7140 if (a <= 15)
7141 return 0x328;
7142 __ody_csr_fatal("PCIERCX_RAS_SD_STATUSL2", 1, a, 0, 0, 0, 0, 0);
7143 }
7144
7145 #define typedef_ODY_PCIERCX_RAS_SD_STATUSL2(a) ody_pciercx_ras_sd_statusl2_t
7146 #define bustype_ODY_PCIERCX_RAS_SD_STATUSL2(a) CSR_TYPE_PCICONFIGRC
7147 #define basename_ODY_PCIERCX_RAS_SD_STATUSL2(a) "PCIERCX_RAS_SD_STATUSL2"
7148 #define busnum_ODY_PCIERCX_RAS_SD_STATUSL2(a) (a)
7149 #define arguments_ODY_PCIERCX_RAS_SD_STATUSL2(a) (a), -1, -1, -1
7150
7151 /**
7152 * Register (PCICONFIGRC) pcierc#_ras_sd_statusl3
7153 *
7154 * PCIe RC Vendor RAS DES Silicon Debug Status L3 Register
7155 */
7156 union ody_pciercx_ras_sd_statusl3 {
7157 uint32_t u;
7158 struct ody_pciercx_ras_sd_statusl3_s {
7159 uint32_t mftlp_ptr : 7;
7160 uint32_t mftlp_status : 1;
7161 uint32_t reserved_8_31 : 24;
7162 } s;
7163 /* struct ody_pciercx_ras_sd_statusl3_s cn; */
7164 };
7165 typedef union ody_pciercx_ras_sd_statusl3 ody_pciercx_ras_sd_statusl3_t;
7166
7167 static inline uint64_t ODY_PCIERCX_RAS_SD_STATUSL3(uint64_t a) __attribute__ ((pure, always_inline));
ODY_PCIERCX_RAS_SD_STATUSL3(uint64_t a)7168 static inline uint64_t ODY_PCIERCX_RAS_SD_STATUSL3(uint64_t a)
7169 {
7170 if (a <= 15)
7171 return 0x330;
7172 __ody_csr_fatal("PCIERCX_RAS_SD_STATUSL3", 1, a, 0, 0, 0, 0, 0);
7173 }
7174
7175 #define typedef_ODY_PCIERCX_RAS_SD_STATUSL3(a) ody_pciercx_ras_sd_statusl3_t
7176 #define bustype_ODY_PCIERCX_RAS_SD_STATUSL3(a) CSR_TYPE_PCICONFIGRC
7177 #define basename_ODY_PCIERCX_RAS_SD_STATUSL3(a) "PCIERCX_RAS_SD_STATUSL3"
7178 #define busnum_ODY_PCIERCX_RAS_SD_STATUSL3(a) (a)
7179 #define arguments_ODY_PCIERCX_RAS_SD_STATUSL3(a) (a), -1, -1, -1
7180
7181 /**
7182 * Register (PCICONFIGRC) pcierc#_ras_sd_statusl3fc
7183 *
7184 * PCIe RC Vendor RAS DES Silicon Debug Status L2 Register
7185 */
7186 union ody_pciercx_ras_sd_statusl3fc {
7187 uint32_t u;
7188 struct ody_pciercx_ras_sd_statusl3fc_s {
7189 uint32_t credit_sel_vc : 3;
7190 uint32_t credit_sel_credit_type : 1;
7191 uint32_t credit_sel_tlp_type : 2;
7192 uint32_t credit_sel_hd : 1;
7193 uint32_t reserved_7 : 1;
7194 uint32_t credit_data0 : 12;
7195 uint32_t credit_data1 : 12;
7196 } s;
7197 /* struct ody_pciercx_ras_sd_statusl3fc_s cn; */
7198 };
7199 typedef union ody_pciercx_ras_sd_statusl3fc ody_pciercx_ras_sd_statusl3fc_t;
7200
7201 static inline uint64_t ODY_PCIERCX_RAS_SD_STATUSL3FC(uint64_t a) __attribute__ ((pure, always_inline));
ODY_PCIERCX_RAS_SD_STATUSL3FC(uint64_t a)7202 static inline uint64_t ODY_PCIERCX_RAS_SD_STATUSL3FC(uint64_t a)
7203 {
7204 if (a <= 15)
7205 return 0x32c;
7206 __ody_csr_fatal("PCIERCX_RAS_SD_STATUSL3FC", 1, a, 0, 0, 0, 0, 0);
7207 }
7208
7209 #define typedef_ODY_PCIERCX_RAS_SD_STATUSL3FC(a) ody_pciercx_ras_sd_statusl3fc_t
7210 #define bustype_ODY_PCIERCX_RAS_SD_STATUSL3FC(a) CSR_TYPE_PCICONFIGRC
7211 #define basename_ODY_PCIERCX_RAS_SD_STATUSL3FC(a) "PCIERCX_RAS_SD_STATUSL3FC"
7212 #define busnum_ODY_PCIERCX_RAS_SD_STATUSL3FC(a) (a)
7213 #define arguments_ODY_PCIERCX_RAS_SD_STATUSL3FC(a) (a), -1, -1, -1
7214
7215 /**
7216 * Register (PCICONFIGRC) pcierc#_ras_sd_statuspm
7217 *
7218 * PCIe RC Vendor RAS DES Silicon Debug Status PM Register
7219 */
7220 union ody_pciercx_ras_sd_statuspm {
7221 uint32_t u;
7222 struct ody_pciercx_ras_sd_statuspm_s {
7223 uint32_t int_pm_mstate : 5;
7224 uint32_t reserved_5_7 : 3;
7225 uint32_t int_pm_sstate : 4;
7226 uint32_t pme_rsnd_flag : 1;
7227 uint32_t l1sub_state : 3;
7228 uint32_t latched_nfts : 8;
7229 uint32_t reserved_24_31 : 8;
7230 } s;
7231 /* struct ody_pciercx_ras_sd_statuspm_s cn; */
7232 };
7233 typedef union ody_pciercx_ras_sd_statuspm ody_pciercx_ras_sd_statuspm_t;
7234
7235 static inline uint64_t ODY_PCIERCX_RAS_SD_STATUSPM(uint64_t a) __attribute__ ((pure, always_inline));
ODY_PCIERCX_RAS_SD_STATUSPM(uint64_t a)7236 static inline uint64_t ODY_PCIERCX_RAS_SD_STATUSPM(uint64_t a)
7237 {
7238 if (a <= 15)
7239 return 0x324;
7240 __ody_csr_fatal("PCIERCX_RAS_SD_STATUSPM", 1, a, 0, 0, 0, 0, 0);
7241 }
7242
7243 #define typedef_ODY_PCIERCX_RAS_SD_STATUSPM(a) ody_pciercx_ras_sd_statuspm_t
7244 #define bustype_ODY_PCIERCX_RAS_SD_STATUSPM(a) CSR_TYPE_PCICONFIGRC
7245 #define basename_ODY_PCIERCX_RAS_SD_STATUSPM(a) "PCIERCX_RAS_SD_STATUSPM"
7246 #define busnum_ODY_PCIERCX_RAS_SD_STATUSPM(a) (a)
7247 #define arguments_ODY_PCIERCX_RAS_SD_STATUSPM(a) (a), -1, -1, -1
7248
7249 /**
7250 * Register (PCICONFIGRC) pcierc#_ras_tba_ctl
7251 *
7252 * PCIe RC Vendor RAS DES Time Based Analysis Control Register
7253 */
7254 union ody_pciercx_ras_tba_ctl {
7255 uint32_t u;
7256 struct ody_pciercx_ras_tba_ctl_s {
7257 uint32_t timer_start : 1;
7258 uint32_t reserved_1_7 : 7;
7259 uint32_t tbase_dur_sel : 8;
7260 uint32_t reserved_16_23 : 8;
7261 uint32_t tbase_rpt_sel : 8;
7262 } s;
7263 /* struct ody_pciercx_ras_tba_ctl_s cn; */
7264 };
7265 typedef union ody_pciercx_ras_tba_ctl ody_pciercx_ras_tba_ctl_t;
7266
7267 static inline uint64_t ODY_PCIERCX_RAS_TBA_CTL(uint64_t a) __attribute__ ((pure, always_inline));
ODY_PCIERCX_RAS_TBA_CTL(uint64_t a)7268 static inline uint64_t ODY_PCIERCX_RAS_TBA_CTL(uint64_t a)
7269 {
7270 if (a <= 15)
7271 return 0x27c;
7272 __ody_csr_fatal("PCIERCX_RAS_TBA_CTL", 1, a, 0, 0, 0, 0, 0);
7273 }
7274
7275 #define typedef_ODY_PCIERCX_RAS_TBA_CTL(a) ody_pciercx_ras_tba_ctl_t
7276 #define bustype_ODY_PCIERCX_RAS_TBA_CTL(a) CSR_TYPE_PCICONFIGRC
7277 #define basename_ODY_PCIERCX_RAS_TBA_CTL(a) "PCIERCX_RAS_TBA_CTL"
7278 #define busnum_ODY_PCIERCX_RAS_TBA_CTL(a) (a)
7279 #define arguments_ODY_PCIERCX_RAS_TBA_CTL(a) (a), -1, -1, -1
7280
7281 /**
7282 * Register (PCICONFIGRC) pcierc#_ras_tba_data
7283 *
7284 * PCIe RC Vendor RAS DES Time Based Analysis Data Register
7285 */
7286 union ody_pciercx_ras_tba_data {
7287 uint32_t u;
7288 struct ody_pciercx_ras_tba_data_s {
7289 uint32_t tbase_data : 32;
7290 } s;
7291 /* struct ody_pciercx_ras_tba_data_s cn; */
7292 };
7293 typedef union ody_pciercx_ras_tba_data ody_pciercx_ras_tba_data_t;
7294
7295 static inline uint64_t ODY_PCIERCX_RAS_TBA_DATA(uint64_t a) __attribute__ ((pure, always_inline));
ODY_PCIERCX_RAS_TBA_DATA(uint64_t a)7296 static inline uint64_t ODY_PCIERCX_RAS_TBA_DATA(uint64_t a)
7297 {
7298 if (a <= 15)
7299 return 0x280;
7300 __ody_csr_fatal("PCIERCX_RAS_TBA_DATA", 1, a, 0, 0, 0, 0, 0);
7301 }
7302
7303 #define typedef_ODY_PCIERCX_RAS_TBA_DATA(a) ody_pciercx_ras_tba_data_t
7304 #define bustype_ODY_PCIERCX_RAS_TBA_DATA(a) CSR_TYPE_PCICONFIGRC
7305 #define basename_ODY_PCIERCX_RAS_TBA_DATA(a) "PCIERCX_RAS_TBA_DATA"
7306 #define busnum_ODY_PCIERCX_RAS_TBA_DATA(a) (a)
7307 #define arguments_ODY_PCIERCX_RAS_TBA_DATA(a) (a), -1, -1, -1
7308
7309 /**
7310 * Register (PCICONFIGRC) pcierc#_rasdp_cap_hdr
7311 *
7312 * PCIe RC Vendor RAS Data Path Protection Header Register
7313 */
7314 union ody_pciercx_rasdp_cap_hdr {
7315 uint32_t u;
7316 struct ody_pciercx_rasdp_cap_hdr_s {
7317 uint32_t pcieec : 16;
7318 uint32_t cv : 4;
7319 uint32_t nco : 12;
7320 } s;
7321 /* struct ody_pciercx_rasdp_cap_hdr_s cn; */
7322 };
7323 typedef union ody_pciercx_rasdp_cap_hdr ody_pciercx_rasdp_cap_hdr_t;
7324
7325 static inline uint64_t ODY_PCIERCX_RASDP_CAP_HDR(uint64_t a) __attribute__ ((pure, always_inline));
ODY_PCIERCX_RASDP_CAP_HDR(uint64_t a)7326 static inline uint64_t ODY_PCIERCX_RASDP_CAP_HDR(uint64_t a)
7327 {
7328 if (a <= 15)
7329 return 0x36c;
7330 __ody_csr_fatal("PCIERCX_RASDP_CAP_HDR", 1, a, 0, 0, 0, 0, 0);
7331 }
7332
7333 #define typedef_ODY_PCIERCX_RASDP_CAP_HDR(a) ody_pciercx_rasdp_cap_hdr_t
7334 #define bustype_ODY_PCIERCX_RASDP_CAP_HDR(a) CSR_TYPE_PCICONFIGRC
7335 #define basename_ODY_PCIERCX_RASDP_CAP_HDR(a) "PCIERCX_RASDP_CAP_HDR"
7336 #define busnum_ODY_PCIERCX_RASDP_CAP_HDR(a) (a)
7337 #define arguments_ODY_PCIERCX_RASDP_CAP_HDR(a) (a), -1, -1, -1
7338
7339 /**
7340 * Register (PCICONFIGRC) pcierc#_rasdp_ce_ctl
7341 *
7342 * PCIe RC RAS Data Path Correctable Error Control Register
7343 */
7344 union ody_pciercx_rasdp_ce_ctl {
7345 uint32_t u;
7346 struct ody_pciercx_rasdp_ce_ctl_s {
7347 uint32_t ep_dis_l3_rx : 1;
7348 uint32_t reserved_1_3 : 3;
7349 uint32_t corr_en_cntrs : 1;
7350 uint32_t reserved_5_19 : 15;
7351 uint32_t corr_cnt_sel_reg : 4;
7352 uint32_t corr_cnt_sel : 8;
7353 } s;
7354 /* struct ody_pciercx_rasdp_ce_ctl_s cn; */
7355 };
7356 typedef union ody_pciercx_rasdp_ce_ctl ody_pciercx_rasdp_ce_ctl_t;
7357
7358 static inline uint64_t ODY_PCIERCX_RASDP_CE_CTL(uint64_t a) __attribute__ ((pure, always_inline));
ODY_PCIERCX_RASDP_CE_CTL(uint64_t a)7359 static inline uint64_t ODY_PCIERCX_RASDP_CE_CTL(uint64_t a)
7360 {
7361 if (a <= 15)
7362 return 0x378;
7363 __ody_csr_fatal("PCIERCX_RASDP_CE_CTL", 1, a, 0, 0, 0, 0, 0);
7364 }
7365
7366 #define typedef_ODY_PCIERCX_RASDP_CE_CTL(a) ody_pciercx_rasdp_ce_ctl_t
7367 #define bustype_ODY_PCIERCX_RASDP_CE_CTL(a) CSR_TYPE_PCICONFIGRC
7368 #define basename_ODY_PCIERCX_RASDP_CE_CTL(a) "PCIERCX_RASDP_CE_CTL"
7369 #define busnum_ODY_PCIERCX_RASDP_CE_CTL(a) (a)
7370 #define arguments_ODY_PCIERCX_RASDP_CE_CTL(a) (a), -1, -1, -1
7371
7372 /**
7373 * Register (PCICONFIGRC) pcierc#_rasdp_ce_ictl
7374 *
7375 * PCIe RC RAS Data Correctable Error Injection Control Register
7376 */
7377 union ody_pciercx_rasdp_ce_ictl {
7378 uint32_t u;
7379 struct ody_pciercx_rasdp_ce_ictl_s {
7380 uint32_t err_inj_en : 1;
7381 uint32_t reserved_1_3 : 3;
7382 uint32_t err_inj_type : 2;
7383 uint32_t reserved_6_7 : 2;
7384 uint32_t err_inj_cnt : 8;
7385 uint32_t err_inj_loc : 8;
7386 uint32_t reserved_24_31 : 8;
7387 } s;
7388 /* struct ody_pciercx_rasdp_ce_ictl_s cn; */
7389 };
7390 typedef union ody_pciercx_rasdp_ce_ictl ody_pciercx_rasdp_ce_ictl_t;
7391
7392 static inline uint64_t ODY_PCIERCX_RASDP_CE_ICTL(uint64_t a) __attribute__ ((pure, always_inline));
ODY_PCIERCX_RASDP_CE_ICTL(uint64_t a)7393 static inline uint64_t ODY_PCIERCX_RASDP_CE_ICTL(uint64_t a)
7394 {
7395 if (a <= 15)
7396 return 0x388;
7397 __ody_csr_fatal("PCIERCX_RASDP_CE_ICTL", 1, a, 0, 0, 0, 0, 0);
7398 }
7399
7400 #define typedef_ODY_PCIERCX_RASDP_CE_ICTL(a) ody_pciercx_rasdp_ce_ictl_t
7401 #define bustype_ODY_PCIERCX_RASDP_CE_ICTL(a) CSR_TYPE_PCICONFIGRC
7402 #define basename_ODY_PCIERCX_RASDP_CE_ICTL(a) "PCIERCX_RASDP_CE_ICTL"
7403 #define busnum_ODY_PCIERCX_RASDP_CE_ICTL(a) (a)
7404 #define arguments_ODY_PCIERCX_RASDP_CE_ICTL(a) (a), -1, -1, -1
7405
7406 /**
7407 * Register (PCICONFIGRC) pcierc#_rasdp_ce_loc
7408 *
7409 * PCIe RC RAS Data Correctable Error Location Register
7410 */
7411 union ody_pciercx_rasdp_ce_loc {
7412 uint32_t u;
7413 struct ody_pciercx_rasdp_ce_loc_s {
7414 uint32_t reserved_0_3 : 4;
7415 uint32_t reg_first_corr_err : 4;
7416 uint32_t loc_first_corr_err : 8;
7417 uint32_t reserved_16_19 : 4;
7418 uint32_t reg_last_corr_err : 4;
7419 uint32_t loc_last_corr_err : 8;
7420 } s;
7421 /* struct ody_pciercx_rasdp_ce_loc_s cn; */
7422 };
7423 typedef union ody_pciercx_rasdp_ce_loc ody_pciercx_rasdp_ce_loc_t;
7424
7425 static inline uint64_t ODY_PCIERCX_RASDP_CE_LOC(uint64_t a) __attribute__ ((pure, always_inline));
ODY_PCIERCX_RASDP_CE_LOC(uint64_t a)7426 static inline uint64_t ODY_PCIERCX_RASDP_CE_LOC(uint64_t a)
7427 {
7428 if (a <= 15)
7429 return 0x38c;
7430 __ody_csr_fatal("PCIERCX_RASDP_CE_LOC", 1, a, 0, 0, 0, 0, 0);
7431 }
7432
7433 #define typedef_ODY_PCIERCX_RASDP_CE_LOC(a) ody_pciercx_rasdp_ce_loc_t
7434 #define bustype_ODY_PCIERCX_RASDP_CE_LOC(a) CSR_TYPE_PCICONFIGRC
7435 #define basename_ODY_PCIERCX_RASDP_CE_LOC(a) "PCIERCX_RASDP_CE_LOC"
7436 #define busnum_ODY_PCIERCX_RASDP_CE_LOC(a) (a)
7437 #define arguments_ODY_PCIERCX_RASDP_CE_LOC(a) (a), -1, -1, -1
7438
7439 /**
7440 * Register (PCICONFIGRC) pcierc#_rasdp_ce_rp
7441 *
7442 * PCIe RC RAS Data Path Correctable Error Report Register
7443 */
7444 union ody_pciercx_rasdp_ce_rp {
7445 uint32_t u;
7446 struct ody_pciercx_rasdp_ce_rp_s {
7447 uint32_t corr_count : 8;
7448 uint32_t reserved_8_19 : 12;
7449 uint32_t corr_cnt_sel_reg : 4;
7450 uint32_t corr_cnt_sel : 8;
7451 } s;
7452 /* struct ody_pciercx_rasdp_ce_rp_s cn; */
7453 };
7454 typedef union ody_pciercx_rasdp_ce_rp ody_pciercx_rasdp_ce_rp_t;
7455
7456 static inline uint64_t ODY_PCIERCX_RASDP_CE_RP(uint64_t a) __attribute__ ((pure, always_inline));
ODY_PCIERCX_RASDP_CE_RP(uint64_t a)7457 static inline uint64_t ODY_PCIERCX_RASDP_CE_RP(uint64_t a)
7458 {
7459 if (a <= 15)
7460 return 0x37c;
7461 __ody_csr_fatal("PCIERCX_RASDP_CE_RP", 1, a, 0, 0, 0, 0, 0);
7462 }
7463
7464 #define typedef_ODY_PCIERCX_RASDP_CE_RP(a) ody_pciercx_rasdp_ce_rp_t
7465 #define bustype_ODY_PCIERCX_RASDP_CE_RP(a) CSR_TYPE_PCICONFIGRC
7466 #define basename_ODY_PCIERCX_RASDP_CE_RP(a) "PCIERCX_RASDP_CE_RP"
7467 #define busnum_ODY_PCIERCX_RASDP_CE_RP(a) (a)
7468 #define arguments_ODY_PCIERCX_RASDP_CE_RP(a) (a), -1, -1, -1
7469
7470 /**
7471 * Register (PCICONFIGRC) pcierc#_rasdp_de_mc
7472 *
7473 * PCIe RC RAS Data Error Mode Clear Register
7474 */
7475 union ody_pciercx_rasdp_de_mc {
7476 uint32_t u;
7477 struct ody_pciercx_rasdp_de_mc_s {
7478 uint32_t err_mode_clr : 1;
7479 uint32_t reserved_1_31 : 31;
7480 } s;
7481 /* struct ody_pciercx_rasdp_de_mc_s cn; */
7482 };
7483 typedef union ody_pciercx_rasdp_de_mc ody_pciercx_rasdp_de_mc_t;
7484
7485 static inline uint64_t ODY_PCIERCX_RASDP_DE_MC(uint64_t a) __attribute__ ((pure, always_inline));
ODY_PCIERCX_RASDP_DE_MC(uint64_t a)7486 static inline uint64_t ODY_PCIERCX_RASDP_DE_MC(uint64_t a)
7487 {
7488 if (a <= 15)
7489 return 0x398;
7490 __ody_csr_fatal("PCIERCX_RASDP_DE_MC", 1, a, 0, 0, 0, 0, 0);
7491 }
7492
7493 #define typedef_ODY_PCIERCX_RASDP_DE_MC(a) ody_pciercx_rasdp_de_mc_t
7494 #define bustype_ODY_PCIERCX_RASDP_DE_MC(a) CSR_TYPE_PCICONFIGRC
7495 #define basename_ODY_PCIERCX_RASDP_DE_MC(a) "PCIERCX_RASDP_DE_MC"
7496 #define busnum_ODY_PCIERCX_RASDP_DE_MC(a) (a)
7497 #define arguments_ODY_PCIERCX_RASDP_DE_MC(a) (a), -1, -1, -1
7498
7499 /**
7500 * Register (PCICONFIGRC) pcierc#_rasdp_de_me
7501 *
7502 * PCIe RC RAS Data Error Mode Enable Register
7503 */
7504 union ody_pciercx_rasdp_de_me {
7505 uint32_t u;
7506 struct ody_pciercx_rasdp_de_me_s {
7507 uint32_t err_mode_en : 1;
7508 uint32_t auto_lnk_dn_en : 1;
7509 uint32_t reserved_2_31 : 30;
7510 } s;
7511 /* struct ody_pciercx_rasdp_de_me_s cn; */
7512 };
7513 typedef union ody_pciercx_rasdp_de_me ody_pciercx_rasdp_de_me_t;
7514
7515 static inline uint64_t ODY_PCIERCX_RASDP_DE_ME(uint64_t a) __attribute__ ((pure, always_inline));
ODY_PCIERCX_RASDP_DE_ME(uint64_t a)7516 static inline uint64_t ODY_PCIERCX_RASDP_DE_ME(uint64_t a)
7517 {
7518 if (a <= 15)
7519 return 0x394;
7520 __ody_csr_fatal("PCIERCX_RASDP_DE_ME", 1, a, 0, 0, 0, 0, 0);
7521 }
7522
7523 #define typedef_ODY_PCIERCX_RASDP_DE_ME(a) ody_pciercx_rasdp_de_me_t
7524 #define bustype_ODY_PCIERCX_RASDP_DE_ME(a) CSR_TYPE_PCICONFIGRC
7525 #define basename_ODY_PCIERCX_RASDP_DE_ME(a) "PCIERCX_RASDP_DE_ME"
7526 #define busnum_ODY_PCIERCX_RASDP_DE_ME(a) (a)
7527 #define arguments_ODY_PCIERCX_RASDP_DE_ME(a) (a), -1, -1, -1
7528
7529 /**
7530 * Register (PCICONFIGRC) pcierc#_rasdp_ep_ctl
7531 *
7532 * PCIe RC RAS Data Path Error Protection Control Register
7533 */
7534 union ody_pciercx_rasdp_ep_ctl {
7535 uint32_t u;
7536 struct ody_pciercx_rasdp_ep_ctl_s {
7537 uint32_t ep_dis_tx : 1;
7538 uint32_t ep_dis_axib_masc : 1;
7539 uint32_t ep_dis_axib_outb : 1;
7540 uint32_t ep_dis_dma_wr : 1;
7541 uint32_t ep_dis_l2_tx : 1;
7542 uint32_t ep_dis_l3_tx : 1;
7543 uint32_t ep_dis_adm_tx : 1;
7544 uint32_t ep_dis_cxs_tx : 1;
7545 uint32_t ep_dis_dtim_tx : 1;
7546 uint32_t ep_dis_cxl_tx : 1;
7547 uint32_t reserved_10_15 : 6;
7548 uint32_t ep_dis_rx : 1;
7549 uint32_t ep_dis_axib_inbc : 1;
7550 uint32_t ep_dis_axib_inbr : 1;
7551 uint32_t ep_dis_dma_rd : 1;
7552 uint32_t ep_dis_l2_rx : 1;
7553 uint32_t ep_dis_l3_rx : 1;
7554 uint32_t ep_dis_adm_rx : 1;
7555 uint32_t ep_dis_cxs_rx : 1;
7556 uint32_t ep_dis_ltim : 1;
7557 uint32_t reserved_25_31 : 7;
7558 } s;
7559 /* struct ody_pciercx_rasdp_ep_ctl_s cn; */
7560 };
7561 typedef union ody_pciercx_rasdp_ep_ctl ody_pciercx_rasdp_ep_ctl_t;
7562
7563 static inline uint64_t ODY_PCIERCX_RASDP_EP_CTL(uint64_t a) __attribute__ ((pure, always_inline));
ODY_PCIERCX_RASDP_EP_CTL(uint64_t a)7564 static inline uint64_t ODY_PCIERCX_RASDP_EP_CTL(uint64_t a)
7565 {
7566 if (a <= 15)
7567 return 0x374;
7568 __ody_csr_fatal("PCIERCX_RASDP_EP_CTL", 1, a, 0, 0, 0, 0, 0);
7569 }
7570
7571 #define typedef_ODY_PCIERCX_RASDP_EP_CTL(a) ody_pciercx_rasdp_ep_ctl_t
7572 #define bustype_ODY_PCIERCX_RASDP_EP_CTL(a) CSR_TYPE_PCICONFIGRC
7573 #define basename_ODY_PCIERCX_RASDP_EP_CTL(a) "PCIERCX_RASDP_EP_CTL"
7574 #define busnum_ODY_PCIERCX_RASDP_EP_CTL(a) (a)
7575 #define arguments_ODY_PCIERCX_RASDP_EP_CTL(a) (a), -1, -1, -1
7576
7577 /**
7578 * Register (PCICONFIGRC) pcierc#_rasdp_hdr
7579 *
7580 * PCIe RC RAS Data Path Extended Capability Register
7581 */
7582 union ody_pciercx_rasdp_hdr {
7583 uint32_t u;
7584 struct ody_pciercx_rasdp_hdr_s {
7585 uint32_t vsec_id : 16;
7586 uint32_t vsec_rev : 4;
7587 uint32_t vsec_length : 12;
7588 } s;
7589 /* struct ody_pciercx_rasdp_hdr_s cn; */
7590 };
7591 typedef union ody_pciercx_rasdp_hdr ody_pciercx_rasdp_hdr_t;
7592
7593 static inline uint64_t ODY_PCIERCX_RASDP_HDR(uint64_t a) __attribute__ ((pure, always_inline));
ODY_PCIERCX_RASDP_HDR(uint64_t a)7594 static inline uint64_t ODY_PCIERCX_RASDP_HDR(uint64_t a)
7595 {
7596 if (a <= 15)
7597 return 0x370;
7598 __ody_csr_fatal("PCIERCX_RASDP_HDR", 1, a, 0, 0, 0, 0, 0);
7599 }
7600
7601 #define typedef_ODY_PCIERCX_RASDP_HDR(a) ody_pciercx_rasdp_hdr_t
7602 #define bustype_ODY_PCIERCX_RASDP_HDR(a) CSR_TYPE_PCICONFIGRC
7603 #define basename_ODY_PCIERCX_RASDP_HDR(a) "PCIERCX_RASDP_HDR"
7604 #define busnum_ODY_PCIERCX_RASDP_HDR(a) (a)
7605 #define arguments_ODY_PCIERCX_RASDP_HDR(a) (a), -1, -1, -1
7606
7607 /**
7608 * Register (PCICONFIGRC) pcierc#_rasdp_radr_ce
7609 *
7610 * PCIe RC RAS RAM Address Corrected Error Register
7611 */
7612 union ody_pciercx_rasdp_radr_ce {
7613 uint32_t u;
7614 struct ody_pciercx_rasdp_radr_ce_s {
7615 uint32_t ram_addr_corr_err : 27;
7616 uint32_t reserved_27 : 1;
7617 uint32_t ram_idx_corr_err : 4;
7618 } s;
7619 /* struct ody_pciercx_rasdp_radr_ce_s cn; */
7620 };
7621 typedef union ody_pciercx_rasdp_radr_ce ody_pciercx_rasdp_radr_ce_t;
7622
7623 static inline uint64_t ODY_PCIERCX_RASDP_RADR_CE(uint64_t a) __attribute__ ((pure, always_inline));
ODY_PCIERCX_RASDP_RADR_CE(uint64_t a)7624 static inline uint64_t ODY_PCIERCX_RASDP_RADR_CE(uint64_t a)
7625 {
7626 if (a <= 15)
7627 return 0x39c;
7628 __ody_csr_fatal("PCIERCX_RASDP_RADR_CE", 1, a, 0, 0, 0, 0, 0);
7629 }
7630
7631 #define typedef_ODY_PCIERCX_RASDP_RADR_CE(a) ody_pciercx_rasdp_radr_ce_t
7632 #define bustype_ODY_PCIERCX_RASDP_RADR_CE(a) CSR_TYPE_PCICONFIGRC
7633 #define basename_ODY_PCIERCX_RASDP_RADR_CE(a) "PCIERCX_RASDP_RADR_CE"
7634 #define busnum_ODY_PCIERCX_RASDP_RADR_CE(a) (a)
7635 #define arguments_ODY_PCIERCX_RASDP_RADR_CE(a) (a), -1, -1, -1
7636
7637 /**
7638 * Register (PCICONFIGRC) pcierc#_rasdp_radr_uce
7639 *
7640 * PCIe RC RAS RAM Address Uncorrected Error Register
7641 */
7642 union ody_pciercx_rasdp_radr_uce {
7643 uint32_t u;
7644 struct ody_pciercx_rasdp_radr_uce_s {
7645 uint32_t ram_addr_ucorr_err : 27;
7646 uint32_t reserved_27 : 1;
7647 uint32_t ram_idx_ucorr_err : 4;
7648 } s;
7649 /* struct ody_pciercx_rasdp_radr_uce_s cn; */
7650 };
7651 typedef union ody_pciercx_rasdp_radr_uce ody_pciercx_rasdp_radr_uce_t;
7652
7653 static inline uint64_t ODY_PCIERCX_RASDP_RADR_UCE(uint64_t a) __attribute__ ((pure, always_inline));
ODY_PCIERCX_RASDP_RADR_UCE(uint64_t a)7654 static inline uint64_t ODY_PCIERCX_RASDP_RADR_UCE(uint64_t a)
7655 {
7656 if (a <= 15)
7657 return 0x3a0;
7658 __ody_csr_fatal("PCIERCX_RASDP_RADR_UCE", 1, a, 0, 0, 0, 0, 0);
7659 }
7660
7661 #define typedef_ODY_PCIERCX_RASDP_RADR_UCE(a) ody_pciercx_rasdp_radr_uce_t
7662 #define bustype_ODY_PCIERCX_RASDP_RADR_UCE(a) CSR_TYPE_PCICONFIGRC
7663 #define basename_ODY_PCIERCX_RASDP_RADR_UCE(a) "PCIERCX_RASDP_RADR_UCE"
7664 #define busnum_ODY_PCIERCX_RASDP_RADR_UCE(a) (a)
7665 #define arguments_ODY_PCIERCX_RASDP_RADR_UCE(a) (a), -1, -1, -1
7666
7667 /**
7668 * Register (PCICONFIGRC) pcierc#_rasdp_uce_ctl
7669 *
7670 * PCIe RC RAS Data Path Uncorrectable Error Control Register
7671 */
7672 union ody_pciercx_rasdp_uce_ctl {
7673 uint32_t u;
7674 struct ody_pciercx_rasdp_uce_ctl_s {
7675 uint32_t ep_dis_l3_rx : 1;
7676 uint32_t reserved_1_3 : 3;
7677 uint32_t ucorr_en_cntrs : 1;
7678 uint32_t reserved_5_19 : 15;
7679 uint32_t ucorr_cnt_sel_reg : 4;
7680 uint32_t ucorr_cnt_sel : 8;
7681 } s;
7682 /* struct ody_pciercx_rasdp_uce_ctl_s cn; */
7683 };
7684 typedef union ody_pciercx_rasdp_uce_ctl ody_pciercx_rasdp_uce_ctl_t;
7685
7686 static inline uint64_t ODY_PCIERCX_RASDP_UCE_CTL(uint64_t a) __attribute__ ((pure, always_inline));
ODY_PCIERCX_RASDP_UCE_CTL(uint64_t a)7687 static inline uint64_t ODY_PCIERCX_RASDP_UCE_CTL(uint64_t a)
7688 {
7689 if (a <= 15)
7690 return 0x380;
7691 __ody_csr_fatal("PCIERCX_RASDP_UCE_CTL", 1, a, 0, 0, 0, 0, 0);
7692 }
7693
7694 #define typedef_ODY_PCIERCX_RASDP_UCE_CTL(a) ody_pciercx_rasdp_uce_ctl_t
7695 #define bustype_ODY_PCIERCX_RASDP_UCE_CTL(a) CSR_TYPE_PCICONFIGRC
7696 #define basename_ODY_PCIERCX_RASDP_UCE_CTL(a) "PCIERCX_RASDP_UCE_CTL"
7697 #define busnum_ODY_PCIERCX_RASDP_UCE_CTL(a) (a)
7698 #define arguments_ODY_PCIERCX_RASDP_UCE_CTL(a) (a), -1, -1, -1
7699
7700 /**
7701 * Register (PCICONFIGRC) pcierc#_rasdp_uce_loc
7702 *
7703 * PCIe RC RAS Data Uncorrectable Error Location Register
7704 */
7705 union ody_pciercx_rasdp_uce_loc {
7706 uint32_t u;
7707 struct ody_pciercx_rasdp_uce_loc_s {
7708 uint32_t reserved_0_3 : 4;
7709 uint32_t reg_first_ucorr_err : 4;
7710 uint32_t loc_first_ucorr_err : 8;
7711 uint32_t reserved_16_19 : 4;
7712 uint32_t reg_last_ucorr_err : 4;
7713 uint32_t loc_last_ucorr_err : 8;
7714 } s;
7715 /* struct ody_pciercx_rasdp_uce_loc_s cn; */
7716 };
7717 typedef union ody_pciercx_rasdp_uce_loc ody_pciercx_rasdp_uce_loc_t;
7718
7719 static inline uint64_t ODY_PCIERCX_RASDP_UCE_LOC(uint64_t a) __attribute__ ((pure, always_inline));
ODY_PCIERCX_RASDP_UCE_LOC(uint64_t a)7720 static inline uint64_t ODY_PCIERCX_RASDP_UCE_LOC(uint64_t a)
7721 {
7722 if (a <= 15)
7723 return 0x390;
7724 __ody_csr_fatal("PCIERCX_RASDP_UCE_LOC", 1, a, 0, 0, 0, 0, 0);
7725 }
7726
7727 #define typedef_ODY_PCIERCX_RASDP_UCE_LOC(a) ody_pciercx_rasdp_uce_loc_t
7728 #define bustype_ODY_PCIERCX_RASDP_UCE_LOC(a) CSR_TYPE_PCICONFIGRC
7729 #define basename_ODY_PCIERCX_RASDP_UCE_LOC(a) "PCIERCX_RASDP_UCE_LOC"
7730 #define busnum_ODY_PCIERCX_RASDP_UCE_LOC(a) (a)
7731 #define arguments_ODY_PCIERCX_RASDP_UCE_LOC(a) (a), -1, -1, -1
7732
7733 /**
7734 * Register (PCICONFIGRC) pcierc#_rasdp_uce_rp
7735 *
7736 * PCIe RC RAS Data Path Uncorrectable Error Report Register
7737 */
7738 union ody_pciercx_rasdp_uce_rp {
7739 uint32_t u;
7740 struct ody_pciercx_rasdp_uce_rp_s {
7741 uint32_t ucorr_count : 8;
7742 uint32_t reserved_8_19 : 12;
7743 uint32_t ucorr_cnt_sel_reg : 4;
7744 uint32_t ucorr_cnt_sel : 8;
7745 } s;
7746 /* struct ody_pciercx_rasdp_uce_rp_s cn; */
7747 };
7748 typedef union ody_pciercx_rasdp_uce_rp ody_pciercx_rasdp_uce_rp_t;
7749
7750 static inline uint64_t ODY_PCIERCX_RASDP_UCE_RP(uint64_t a) __attribute__ ((pure, always_inline));
ODY_PCIERCX_RASDP_UCE_RP(uint64_t a)7751 static inline uint64_t ODY_PCIERCX_RASDP_UCE_RP(uint64_t a)
7752 {
7753 if (a <= 15)
7754 return 0x384;
7755 __ody_csr_fatal("PCIERCX_RASDP_UCE_RP", 1, a, 0, 0, 0, 0, 0);
7756 }
7757
7758 #define typedef_ODY_PCIERCX_RASDP_UCE_RP(a) ody_pciercx_rasdp_uce_rp_t
7759 #define bustype_ODY_PCIERCX_RASDP_UCE_RP(a) CSR_TYPE_PCICONFIGRC
7760 #define basename_ODY_PCIERCX_RASDP_UCE_RP(a) "PCIERCX_RASDP_UCE_RP"
7761 #define busnum_ODY_PCIERCX_RASDP_UCE_RP(a) (a)
7762 #define arguments_ODY_PCIERCX_RASDP_UCE_RP(a) (a), -1, -1, -1
7763
7764 /**
7765 * Register (PCICONFIGRC) pcierc#_rev
7766 *
7767 * PCIe RC Class Code/Revision ID Register
7768 */
7769 union ody_pciercx_rev {
7770 uint32_t u;
7771 struct ody_pciercx_rev_s {
7772 uint32_t rid : 8;
7773 uint32_t pi : 8;
7774 uint32_t sc : 8;
7775 uint32_t bcc : 8;
7776 } s;
7777 /* struct ody_pciercx_rev_s cn; */
7778 };
7779 typedef union ody_pciercx_rev ody_pciercx_rev_t;
7780
7781 static inline uint64_t ODY_PCIERCX_REV(uint64_t a) __attribute__ ((pure, always_inline));
ODY_PCIERCX_REV(uint64_t a)7782 static inline uint64_t ODY_PCIERCX_REV(uint64_t a)
7783 {
7784 if (a <= 15)
7785 return 8;
7786 __ody_csr_fatal("PCIERCX_REV", 1, a, 0, 0, 0, 0, 0);
7787 }
7788
7789 #define typedef_ODY_PCIERCX_REV(a) ody_pciercx_rev_t
7790 #define bustype_ODY_PCIERCX_REV(a) CSR_TYPE_PCICONFIGRC
7791 #define basename_ODY_PCIERCX_REV(a) "PCIERCX_REV"
7792 #define busnum_ODY_PCIERCX_REV(a) (a)
7793 #define arguments_ODY_PCIERCX_REV(a) (a), -1, -1, -1
7794
7795 /**
7796 * Register (PCICONFIGRC) pcierc#_root_ctl_cap
7797 *
7798 * PCIe RC Root Control/Root Capabilities Register
7799 */
7800 union ody_pciercx_root_ctl_cap {
7801 uint32_t u;
7802 struct ody_pciercx_root_ctl_cap_s {
7803 uint32_t secee : 1;
7804 uint32_t senfee : 1;
7805 uint32_t sefee : 1;
7806 uint32_t pmeie : 1;
7807 uint32_t crssve : 1;
7808 uint32_t reserved_5_15 : 11;
7809 uint32_t crssv : 1;
7810 uint32_t reserved_17_31 : 15;
7811 } s;
7812 /* struct ody_pciercx_root_ctl_cap_s cn; */
7813 };
7814 typedef union ody_pciercx_root_ctl_cap ody_pciercx_root_ctl_cap_t;
7815
7816 static inline uint64_t ODY_PCIERCX_ROOT_CTL_CAP(uint64_t a) __attribute__ ((pure, always_inline));
ODY_PCIERCX_ROOT_CTL_CAP(uint64_t a)7817 static inline uint64_t ODY_PCIERCX_ROOT_CTL_CAP(uint64_t a)
7818 {
7819 if (a <= 15)
7820 return 0x8c;
7821 __ody_csr_fatal("PCIERCX_ROOT_CTL_CAP", 1, a, 0, 0, 0, 0, 0);
7822 }
7823
7824 #define typedef_ODY_PCIERCX_ROOT_CTL_CAP(a) ody_pciercx_root_ctl_cap_t
7825 #define bustype_ODY_PCIERCX_ROOT_CTL_CAP(a) CSR_TYPE_PCICONFIGRC
7826 #define basename_ODY_PCIERCX_ROOT_CTL_CAP(a) "PCIERCX_ROOT_CTL_CAP"
7827 #define busnum_ODY_PCIERCX_ROOT_CTL_CAP(a) (a)
7828 #define arguments_ODY_PCIERCX_ROOT_CTL_CAP(a) (a), -1, -1, -1
7829
7830 /**
7831 * Register (PCICONFIGRC) pcierc#_root_err_cmd
7832 *
7833 * PCIe RC Root Error Command Register
7834 */
7835 union ody_pciercx_root_err_cmd {
7836 uint32_t u;
7837 struct ody_pciercx_root_err_cmd_s {
7838 uint32_t cere : 1;
7839 uint32_t nfere : 1;
7840 uint32_t fere : 1;
7841 uint32_t reserved_3_31 : 29;
7842 } s;
7843 /* struct ody_pciercx_root_err_cmd_s cn; */
7844 };
7845 typedef union ody_pciercx_root_err_cmd ody_pciercx_root_err_cmd_t;
7846
7847 static inline uint64_t ODY_PCIERCX_ROOT_ERR_CMD(uint64_t a) __attribute__ ((pure, always_inline));
ODY_PCIERCX_ROOT_ERR_CMD(uint64_t a)7848 static inline uint64_t ODY_PCIERCX_ROOT_ERR_CMD(uint64_t a)
7849 {
7850 if (a <= 15)
7851 return 0x12c;
7852 __ody_csr_fatal("PCIERCX_ROOT_ERR_CMD", 1, a, 0, 0, 0, 0, 0);
7853 }
7854
7855 #define typedef_ODY_PCIERCX_ROOT_ERR_CMD(a) ody_pciercx_root_err_cmd_t
7856 #define bustype_ODY_PCIERCX_ROOT_ERR_CMD(a) CSR_TYPE_PCICONFIGRC
7857 #define basename_ODY_PCIERCX_ROOT_ERR_CMD(a) "PCIERCX_ROOT_ERR_CMD"
7858 #define busnum_ODY_PCIERCX_ROOT_ERR_CMD(a) (a)
7859 #define arguments_ODY_PCIERCX_ROOT_ERR_CMD(a) (a), -1, -1, -1
7860
7861 /**
7862 * Register (PCICONFIGRC) pcierc#_root_err_stat
7863 *
7864 * PCIe RC Root Error Status Register
7865 */
7866 union ody_pciercx_root_err_stat {
7867 uint32_t u;
7868 struct ody_pciercx_root_err_stat_s {
7869 uint32_t ecr : 1;
7870 uint32_t multi_ecr : 1;
7871 uint32_t efnfr : 1;
7872 uint32_t multi_efnfr : 1;
7873 uint32_t fuf : 1;
7874 uint32_t nfemr : 1;
7875 uint32_t femr : 1;
7876 uint32_t reserved_7_26 : 20;
7877 uint32_t aeimn : 5;
7878 } s;
7879 /* struct ody_pciercx_root_err_stat_s cn; */
7880 };
7881 typedef union ody_pciercx_root_err_stat ody_pciercx_root_err_stat_t;
7882
7883 static inline uint64_t ODY_PCIERCX_ROOT_ERR_STAT(uint64_t a) __attribute__ ((pure, always_inline));
ODY_PCIERCX_ROOT_ERR_STAT(uint64_t a)7884 static inline uint64_t ODY_PCIERCX_ROOT_ERR_STAT(uint64_t a)
7885 {
7886 if (a <= 15)
7887 return 0x130;
7888 __ody_csr_fatal("PCIERCX_ROOT_ERR_STAT", 1, a, 0, 0, 0, 0, 0);
7889 }
7890
7891 #define typedef_ODY_PCIERCX_ROOT_ERR_STAT(a) ody_pciercx_root_err_stat_t
7892 #define bustype_ODY_PCIERCX_ROOT_ERR_STAT(a) CSR_TYPE_PCICONFIGRC
7893 #define basename_ODY_PCIERCX_ROOT_ERR_STAT(a) "PCIERCX_ROOT_ERR_STAT"
7894 #define busnum_ODY_PCIERCX_ROOT_ERR_STAT(a) (a)
7895 #define arguments_ODY_PCIERCX_ROOT_ERR_STAT(a) (a), -1, -1, -1
7896
7897 /**
7898 * Register (PCICONFIGRC) pcierc#_root_stat
7899 *
7900 * PCIe RC Root Status Register
7901 */
7902 union ody_pciercx_root_stat {
7903 uint32_t u;
7904 struct ody_pciercx_root_stat_s {
7905 uint32_t pme_rid : 16;
7906 uint32_t pme_stat : 1;
7907 uint32_t pme_pend : 1;
7908 uint32_t reserved_18_31 : 14;
7909 } s;
7910 /* struct ody_pciercx_root_stat_s cn; */
7911 };
7912 typedef union ody_pciercx_root_stat ody_pciercx_root_stat_t;
7913
7914 static inline uint64_t ODY_PCIERCX_ROOT_STAT(uint64_t a) __attribute__ ((pure, always_inline));
ODY_PCIERCX_ROOT_STAT(uint64_t a)7915 static inline uint64_t ODY_PCIERCX_ROOT_STAT(uint64_t a)
7916 {
7917 if (a <= 15)
7918 return 0x90;
7919 __ody_csr_fatal("PCIERCX_ROOT_STAT", 1, a, 0, 0, 0, 0, 0);
7920 }
7921
7922 #define typedef_ODY_PCIERCX_ROOT_STAT(a) ody_pciercx_root_stat_t
7923 #define bustype_ODY_PCIERCX_ROOT_STAT(a) CSR_TYPE_PCICONFIGRC
7924 #define basename_ODY_PCIERCX_ROOT_STAT(a) "PCIERCX_ROOT_STAT"
7925 #define busnum_ODY_PCIERCX_ROOT_STAT(a) (a)
7926 #define arguments_ODY_PCIERCX_ROOT_STAT(a) (a), -1, -1, -1
7927
7928 /**
7929 * Register (PCICONFIGRC) pcierc#_scap_hdr
7930 *
7931 * PCIe RC PCI Express Secondary Capability (Gen3) Header Register
7932 */
7933 union ody_pciercx_scap_hdr {
7934 uint32_t u;
7935 struct ody_pciercx_scap_hdr_s {
7936 uint32_t pcieec : 16;
7937 uint32_t cv : 4;
7938 uint32_t nco : 12;
7939 } s;
7940 /* struct ody_pciercx_scap_hdr_s cn; */
7941 };
7942 typedef union ody_pciercx_scap_hdr ody_pciercx_scap_hdr_t;
7943
7944 static inline uint64_t ODY_PCIERCX_SCAP_HDR(uint64_t a) __attribute__ ((pure, always_inline));
ODY_PCIERCX_SCAP_HDR(uint64_t a)7945 static inline uint64_t ODY_PCIERCX_SCAP_HDR(uint64_t a)
7946 {
7947 if (a <= 15)
7948 return 0x168;
7949 __ody_csr_fatal("PCIERCX_SCAP_HDR", 1, a, 0, 0, 0, 0, 0);
7950 }
7951
7952 #define typedef_ODY_PCIERCX_SCAP_HDR(a) ody_pciercx_scap_hdr_t
7953 #define bustype_ODY_PCIERCX_SCAP_HDR(a) CSR_TYPE_PCICONFIGRC
7954 #define basename_ODY_PCIERCX_SCAP_HDR(a) "PCIERCX_SCAP_HDR"
7955 #define busnum_ODY_PCIERCX_SCAP_HDR(a) (a)
7956 #define arguments_ODY_PCIERCX_SCAP_HDR(a) (a), -1, -1, -1
7957
7958 /**
7959 * Register (PCICONFIGRC) pcierc#_ser_num_1
7960 *
7961 * PCIe RC Serial Number 1 Register
7962 */
7963 union ody_pciercx_ser_num_1 {
7964 uint32_t u;
7965 struct ody_pciercx_ser_num_1_s {
7966 uint32_t dword1 : 32;
7967 } s;
7968 /* struct ody_pciercx_ser_num_1_s cn; */
7969 };
7970 typedef union ody_pciercx_ser_num_1 ody_pciercx_ser_num_1_t;
7971
7972 static inline uint64_t ODY_PCIERCX_SER_NUM_1(uint64_t a) __attribute__ ((pure, always_inline));
ODY_PCIERCX_SER_NUM_1(uint64_t a)7973 static inline uint64_t ODY_PCIERCX_SER_NUM_1(uint64_t a)
7974 {
7975 if (a <= 15)
7976 return 0x14c;
7977 __ody_csr_fatal("PCIERCX_SER_NUM_1", 1, a, 0, 0, 0, 0, 0);
7978 }
7979
7980 #define typedef_ODY_PCIERCX_SER_NUM_1(a) ody_pciercx_ser_num_1_t
7981 #define bustype_ODY_PCIERCX_SER_NUM_1(a) CSR_TYPE_PCICONFIGRC
7982 #define basename_ODY_PCIERCX_SER_NUM_1(a) "PCIERCX_SER_NUM_1"
7983 #define busnum_ODY_PCIERCX_SER_NUM_1(a) (a)
7984 #define arguments_ODY_PCIERCX_SER_NUM_1(a) (a), -1, -1, -1
7985
7986 /**
7987 * Register (PCICONFIGRC) pcierc#_ser_num_2
7988 *
7989 * PCIe RC Serial Number 2 Register
7990 */
7991 union ody_pciercx_ser_num_2 {
7992 uint32_t u;
7993 struct ody_pciercx_ser_num_2_s {
7994 uint32_t dword2 : 32;
7995 } s;
7996 /* struct ody_pciercx_ser_num_2_s cn; */
7997 };
7998 typedef union ody_pciercx_ser_num_2 ody_pciercx_ser_num_2_t;
7999
8000 static inline uint64_t ODY_PCIERCX_SER_NUM_2(uint64_t a) __attribute__ ((pure, always_inline));
ODY_PCIERCX_SER_NUM_2(uint64_t a)8001 static inline uint64_t ODY_PCIERCX_SER_NUM_2(uint64_t a)
8002 {
8003 if (a <= 15)
8004 return 0x150;
8005 __ody_csr_fatal("PCIERCX_SER_NUM_2", 1, a, 0, 0, 0, 0, 0);
8006 }
8007
8008 #define typedef_ODY_PCIERCX_SER_NUM_2(a) ody_pciercx_ser_num_2_t
8009 #define bustype_ODY_PCIERCX_SER_NUM_2(a) CSR_TYPE_PCICONFIGRC
8010 #define basename_ODY_PCIERCX_SER_NUM_2(a) "PCIERCX_SER_NUM_2"
8011 #define busnum_ODY_PCIERCX_SER_NUM_2(a) (a)
8012 #define arguments_ODY_PCIERCX_SER_NUM_2(a) (a), -1, -1, -1
8013
8014 /**
8015 * Register (PCICONFIGRC) pcierc#_slot_cap
8016 *
8017 * PCIe RC Slot Capabilities Register
8018 */
8019 union ody_pciercx_slot_cap {
8020 uint32_t u;
8021 struct ody_pciercx_slot_cap_s {
8022 uint32_t abp : 1;
8023 uint32_t pcp : 1;
8024 uint32_t mrlsp : 1;
8025 uint32_t aip : 1;
8026 uint32_t pip : 1;
8027 uint32_t hp_s : 1;
8028 uint32_t hp_c : 1;
8029 uint32_t sp_lv : 8;
8030 uint32_t sp_ls : 2;
8031 uint32_t emip : 1;
8032 uint32_t nccs : 1;
8033 uint32_t ps_num : 13;
8034 } s;
8035 /* struct ody_pciercx_slot_cap_s cn; */
8036 };
8037 typedef union ody_pciercx_slot_cap ody_pciercx_slot_cap_t;
8038
8039 static inline uint64_t ODY_PCIERCX_SLOT_CAP(uint64_t a) __attribute__ ((pure, always_inline));
ODY_PCIERCX_SLOT_CAP(uint64_t a)8040 static inline uint64_t ODY_PCIERCX_SLOT_CAP(uint64_t a)
8041 {
8042 if (a <= 15)
8043 return 0x84;
8044 __ody_csr_fatal("PCIERCX_SLOT_CAP", 1, a, 0, 0, 0, 0, 0);
8045 }
8046
8047 #define typedef_ODY_PCIERCX_SLOT_CAP(a) ody_pciercx_slot_cap_t
8048 #define bustype_ODY_PCIERCX_SLOT_CAP(a) CSR_TYPE_PCICONFIGRC
8049 #define basename_ODY_PCIERCX_SLOT_CAP(a) "PCIERCX_SLOT_CAP"
8050 #define busnum_ODY_PCIERCX_SLOT_CAP(a) (a)
8051 #define arguments_ODY_PCIERCX_SLOT_CAP(a) (a), -1, -1, -1
8052
8053 /**
8054 * Register (PCICONFIGRC) pcierc#_slot_cap2
8055 *
8056 * PCIe RC Slot Capabilities 2 Register
8057 */
8058 union ody_pciercx_slot_cap2 {
8059 uint32_t u;
8060 struct ody_pciercx_slot_cap2_s {
8061 uint32_t reserved_0_31 : 32;
8062 } s;
8063 /* struct ody_pciercx_slot_cap2_s cn; */
8064 };
8065 typedef union ody_pciercx_slot_cap2 ody_pciercx_slot_cap2_t;
8066
8067 static inline uint64_t ODY_PCIERCX_SLOT_CAP2(uint64_t a) __attribute__ ((pure, always_inline));
ODY_PCIERCX_SLOT_CAP2(uint64_t a)8068 static inline uint64_t ODY_PCIERCX_SLOT_CAP2(uint64_t a)
8069 {
8070 if (a <= 15)
8071 return 0xa4;
8072 __ody_csr_fatal("PCIERCX_SLOT_CAP2", 1, a, 0, 0, 0, 0, 0);
8073 }
8074
8075 #define typedef_ODY_PCIERCX_SLOT_CAP2(a) ody_pciercx_slot_cap2_t
8076 #define bustype_ODY_PCIERCX_SLOT_CAP2(a) CSR_TYPE_PCICONFIGRC
8077 #define basename_ODY_PCIERCX_SLOT_CAP2(a) "PCIERCX_SLOT_CAP2"
8078 #define busnum_ODY_PCIERCX_SLOT_CAP2(a) (a)
8079 #define arguments_ODY_PCIERCX_SLOT_CAP2(a) (a), -1, -1, -1
8080
8081 /**
8082 * Register (PCICONFIGRC) pcierc#_slot_ctl
8083 *
8084 * PCIe RC Slot Control/Slot Status Register
8085 */
8086 union ody_pciercx_slot_ctl {
8087 uint32_t u;
8088 struct ody_pciercx_slot_ctl_s {
8089 uint32_t abp_en : 1;
8090 uint32_t pf_en : 1;
8091 uint32_t mrls_en : 1;
8092 uint32_t pd_en : 1;
8093 uint32_t ccint_en : 1;
8094 uint32_t hpint_en : 1;
8095 uint32_t aic : 2;
8096 uint32_t pic : 2;
8097 uint32_t pcc : 1;
8098 uint32_t emic : 1;
8099 uint32_t dlls_en : 1;
8100 uint32_t reserved_13_15 : 3;
8101 uint32_t abp_d : 1;
8102 uint32_t pf_d : 1;
8103 uint32_t mrls_c : 1;
8104 uint32_t pd_c : 1;
8105 uint32_t ccint_d : 1;
8106 uint32_t mrlss : 1;
8107 uint32_t pds : 1;
8108 uint32_t emis : 1;
8109 uint32_t dlls_c : 1;
8110 uint32_t reserved_25_31 : 7;
8111 } s;
8112 /* struct ody_pciercx_slot_ctl_s cn; */
8113 };
8114 typedef union ody_pciercx_slot_ctl ody_pciercx_slot_ctl_t;
8115
8116 static inline uint64_t ODY_PCIERCX_SLOT_CTL(uint64_t a) __attribute__ ((pure, always_inline));
ODY_PCIERCX_SLOT_CTL(uint64_t a)8117 static inline uint64_t ODY_PCIERCX_SLOT_CTL(uint64_t a)
8118 {
8119 if (a <= 15)
8120 return 0x88;
8121 __ody_csr_fatal("PCIERCX_SLOT_CTL", 1, a, 0, 0, 0, 0, 0);
8122 }
8123
8124 #define typedef_ODY_PCIERCX_SLOT_CTL(a) ody_pciercx_slot_ctl_t
8125 #define bustype_ODY_PCIERCX_SLOT_CTL(a) CSR_TYPE_PCICONFIGRC
8126 #define basename_ODY_PCIERCX_SLOT_CTL(a) "PCIERCX_SLOT_CTL"
8127 #define busnum_ODY_PCIERCX_SLOT_CTL(a) (a)
8128 #define arguments_ODY_PCIERCX_SLOT_CTL(a) (a), -1, -1, -1
8129
8130 /**
8131 * Register (PCICONFIGRC) pcierc#_slot_ctl_stat2
8132 *
8133 * PCIe RC Slot Control 2 Register/Slot Status 2 Register
8134 */
8135 union ody_pciercx_slot_ctl_stat2 {
8136 uint32_t u;
8137 struct ody_pciercx_slot_ctl_stat2_s {
8138 uint32_t reserved_0_31 : 32;
8139 } s;
8140 /* struct ody_pciercx_slot_ctl_stat2_s cn; */
8141 };
8142 typedef union ody_pciercx_slot_ctl_stat2 ody_pciercx_slot_ctl_stat2_t;
8143
8144 static inline uint64_t ODY_PCIERCX_SLOT_CTL_STAT2(uint64_t a) __attribute__ ((pure, always_inline));
ODY_PCIERCX_SLOT_CTL_STAT2(uint64_t a)8145 static inline uint64_t ODY_PCIERCX_SLOT_CTL_STAT2(uint64_t a)
8146 {
8147 if (a <= 15)
8148 return 0xa8;
8149 __ody_csr_fatal("PCIERCX_SLOT_CTL_STAT2", 1, a, 0, 0, 0, 0, 0);
8150 }
8151
8152 #define typedef_ODY_PCIERCX_SLOT_CTL_STAT2(a) ody_pciercx_slot_ctl_stat2_t
8153 #define bustype_ODY_PCIERCX_SLOT_CTL_STAT2(a) CSR_TYPE_PCICONFIGRC
8154 #define basename_ODY_PCIERCX_SLOT_CTL_STAT2(a) "PCIERCX_SLOT_CTL_STAT2"
8155 #define busnum_ODY_PCIERCX_SLOT_CTL_STAT2(a) (a)
8156 #define arguments_ODY_PCIERCX_SLOT_CTL_STAT2(a) (a), -1, -1, -1
8157
8158 /**
8159 * Register (PCICONFIGRC) pcierc#_sn_base
8160 *
8161 * Device Serial Number Extended Capability Header Register
8162 */
8163 union ody_pciercx_sn_base {
8164 uint32_t u;
8165 struct ody_pciercx_sn_base_s {
8166 uint32_t pcieec : 16;
8167 uint32_t cv : 4;
8168 uint32_t nco : 12;
8169 } s;
8170 /* struct ody_pciercx_sn_base_s cn; */
8171 };
8172 typedef union ody_pciercx_sn_base ody_pciercx_sn_base_t;
8173
8174 static inline uint64_t ODY_PCIERCX_SN_BASE(uint64_t a) __attribute__ ((pure, always_inline));
ODY_PCIERCX_SN_BASE(uint64_t a)8175 static inline uint64_t ODY_PCIERCX_SN_BASE(uint64_t a)
8176 {
8177 if (a <= 15)
8178 return 0x148;
8179 __ody_csr_fatal("PCIERCX_SN_BASE", 1, a, 0, 0, 0, 0, 0);
8180 }
8181
8182 #define typedef_ODY_PCIERCX_SN_BASE(a) ody_pciercx_sn_base_t
8183 #define bustype_ODY_PCIERCX_SN_BASE(a) CSR_TYPE_PCICONFIGRC
8184 #define basename_ODY_PCIERCX_SN_BASE(a) "PCIERCX_SN_BASE"
8185 #define busnum_ODY_PCIERCX_SN_BASE(a) (a)
8186 #define arguments_ODY_PCIERCX_SN_BASE(a) (a), -1, -1, -1
8187
8188 /**
8189 * Register (PCICONFIGRC) pcierc#_symb_timer
8190 *
8191 * PCIe RC Symbol Timer/Filter Mask Register 1
8192 */
8193 union ody_pciercx_symb_timer {
8194 uint32_t u;
8195 struct ody_pciercx_symb_timer_s {
8196 uint32_t skpiv : 11;
8197 uint32_t reserved_11_14 : 4;
8198 uint32_t dfcwt : 1;
8199 uint32_t m_fun : 1;
8200 uint32_t m_pois_filt : 1;
8201 uint32_t m_bar_match : 1;
8202 uint32_t m_cfg1_filt : 1;
8203 uint32_t m_lk_filt : 1;
8204 uint32_t m_cpl_tag_err : 1;
8205 uint32_t m_cpl_rid_err : 1;
8206 uint32_t m_cpl_fun_err : 1;
8207 uint32_t m_cpl_tc_err : 1;
8208 uint32_t m_cpl_attr_err : 1;
8209 uint32_t m_cpl_len_err : 1;
8210 uint32_t m_ecrc_filt : 1;
8211 uint32_t m_cpl_ecrc_filt : 1;
8212 uint32_t msg_ctrl : 1;
8213 uint32_t m_io_filt : 1;
8214 uint32_t m_cfg0_filt : 1;
8215 } s;
8216 /* struct ody_pciercx_symb_timer_s cn; */
8217 };
8218 typedef union ody_pciercx_symb_timer ody_pciercx_symb_timer_t;
8219
8220 static inline uint64_t ODY_PCIERCX_SYMB_TIMER(uint64_t a) __attribute__ ((pure, always_inline));
ODY_PCIERCX_SYMB_TIMER(uint64_t a)8221 static inline uint64_t ODY_PCIERCX_SYMB_TIMER(uint64_t a)
8222 {
8223 if (a <= 15)
8224 return 0x71c;
8225 __ody_csr_fatal("PCIERCX_SYMB_TIMER", 1, a, 0, 0, 0, 0, 0);
8226 }
8227
8228 #define typedef_ODY_PCIERCX_SYMB_TIMER(a) ody_pciercx_symb_timer_t
8229 #define bustype_ODY_PCIERCX_SYMB_TIMER(a) CSR_TYPE_PCICONFIGRC
8230 #define basename_ODY_PCIERCX_SYMB_TIMER(a) "PCIERCX_SYMB_TIMER"
8231 #define busnum_ODY_PCIERCX_SYMB_TIMER(a) (a)
8232 #define arguments_ODY_PCIERCX_SYMB_TIMER(a) (a), -1, -1, -1
8233
8234 /**
8235 * Register (PCICONFIGRC) pcierc#_timer_ctl
8236 *
8237 * PCIe RC PF Timer Control and Max Function Number Register
8238 */
8239 union ody_pciercx_timer_ctl {
8240 uint32_t u;
8241 struct ody_pciercx_timer_ctl_s {
8242 uint32_t mfuncn : 8;
8243 uint32_t reserved_8_13 : 6;
8244 uint32_t tmrt : 5;
8245 uint32_t tmanlt : 5;
8246 uint32_t updft : 5;
8247 uint32_t flmsf : 2;
8248 uint32_t reserved_31 : 1;
8249 } s;
8250 /* struct ody_pciercx_timer_ctl_s cn; */
8251 };
8252 typedef union ody_pciercx_timer_ctl ody_pciercx_timer_ctl_t;
8253
8254 static inline uint64_t ODY_PCIERCX_TIMER_CTL(uint64_t a) __attribute__ ((pure, always_inline));
ODY_PCIERCX_TIMER_CTL(uint64_t a)8255 static inline uint64_t ODY_PCIERCX_TIMER_CTL(uint64_t a)
8256 {
8257 if (a <= 15)
8258 return 0x718;
8259 __ody_csr_fatal("PCIERCX_TIMER_CTL", 1, a, 0, 0, 0, 0, 0);
8260 }
8261
8262 #define typedef_ODY_PCIERCX_TIMER_CTL(a) ody_pciercx_timer_ctl_t
8263 #define bustype_ODY_PCIERCX_TIMER_CTL(a) CSR_TYPE_PCICONFIGRC
8264 #define basename_ODY_PCIERCX_TIMER_CTL(a) "PCIERCX_TIMER_CTL"
8265 #define busnum_ODY_PCIERCX_TIMER_CTL(a) (a)
8266 #define arguments_ODY_PCIERCX_TIMER_CTL(a) (a), -1, -1, -1
8267
8268 /**
8269 * Register (PCICONFIGRC) pcierc#_tlp_plog1
8270 *
8271 * PCIe RC TLP Prefix Log Register 1
8272 */
8273 union ody_pciercx_tlp_plog1 {
8274 uint32_t u;
8275 struct ody_pciercx_tlp_plog1_s {
8276 uint32_t dword1 : 32;
8277 } s;
8278 /* struct ody_pciercx_tlp_plog1_s cn; */
8279 };
8280 typedef union ody_pciercx_tlp_plog1 ody_pciercx_tlp_plog1_t;
8281
8282 static inline uint64_t ODY_PCIERCX_TLP_PLOG1(uint64_t a) __attribute__ ((pure, always_inline));
ODY_PCIERCX_TLP_PLOG1(uint64_t a)8283 static inline uint64_t ODY_PCIERCX_TLP_PLOG1(uint64_t a)
8284 {
8285 if (a <= 15)
8286 return 0x138;
8287 __ody_csr_fatal("PCIERCX_TLP_PLOG1", 1, a, 0, 0, 0, 0, 0);
8288 }
8289
8290 #define typedef_ODY_PCIERCX_TLP_PLOG1(a) ody_pciercx_tlp_plog1_t
8291 #define bustype_ODY_PCIERCX_TLP_PLOG1(a) CSR_TYPE_PCICONFIGRC
8292 #define basename_ODY_PCIERCX_TLP_PLOG1(a) "PCIERCX_TLP_PLOG1"
8293 #define busnum_ODY_PCIERCX_TLP_PLOG1(a) (a)
8294 #define arguments_ODY_PCIERCX_TLP_PLOG1(a) (a), -1, -1, -1
8295
8296 /**
8297 * Register (PCICONFIGRC) pcierc#_tlp_plog2
8298 *
8299 * PCIe RC TLP Prefix Log Register 2
8300 */
8301 union ody_pciercx_tlp_plog2 {
8302 uint32_t u;
8303 struct ody_pciercx_tlp_plog2_s {
8304 uint32_t dword2 : 32;
8305 } s;
8306 /* struct ody_pciercx_tlp_plog2_s cn; */
8307 };
8308 typedef union ody_pciercx_tlp_plog2 ody_pciercx_tlp_plog2_t;
8309
8310 static inline uint64_t ODY_PCIERCX_TLP_PLOG2(uint64_t a) __attribute__ ((pure, always_inline));
ODY_PCIERCX_TLP_PLOG2(uint64_t a)8311 static inline uint64_t ODY_PCIERCX_TLP_PLOG2(uint64_t a)
8312 {
8313 if (a <= 15)
8314 return 0x13c;
8315 __ody_csr_fatal("PCIERCX_TLP_PLOG2", 1, a, 0, 0, 0, 0, 0);
8316 }
8317
8318 #define typedef_ODY_PCIERCX_TLP_PLOG2(a) ody_pciercx_tlp_plog2_t
8319 #define bustype_ODY_PCIERCX_TLP_PLOG2(a) CSR_TYPE_PCICONFIGRC
8320 #define basename_ODY_PCIERCX_TLP_PLOG2(a) "PCIERCX_TLP_PLOG2"
8321 #define busnum_ODY_PCIERCX_TLP_PLOG2(a) (a)
8322 #define arguments_ODY_PCIERCX_TLP_PLOG2(a) (a), -1, -1, -1
8323
8324 /**
8325 * Register (PCICONFIGRC) pcierc#_tlp_plog3
8326 *
8327 * PCIe RC TLP Prefix Log Register 3
8328 */
8329 union ody_pciercx_tlp_plog3 {
8330 uint32_t u;
8331 struct ody_pciercx_tlp_plog3_s {
8332 uint32_t dword3 : 32;
8333 } s;
8334 /* struct ody_pciercx_tlp_plog3_s cn; */
8335 };
8336 typedef union ody_pciercx_tlp_plog3 ody_pciercx_tlp_plog3_t;
8337
8338 static inline uint64_t ODY_PCIERCX_TLP_PLOG3(uint64_t a) __attribute__ ((pure, always_inline));
ODY_PCIERCX_TLP_PLOG3(uint64_t a)8339 static inline uint64_t ODY_PCIERCX_TLP_PLOG3(uint64_t a)
8340 {
8341 if (a <= 15)
8342 return 0x140;
8343 __ody_csr_fatal("PCIERCX_TLP_PLOG3", 1, a, 0, 0, 0, 0, 0);
8344 }
8345
8346 #define typedef_ODY_PCIERCX_TLP_PLOG3(a) ody_pciercx_tlp_plog3_t
8347 #define bustype_ODY_PCIERCX_TLP_PLOG3(a) CSR_TYPE_PCICONFIGRC
8348 #define basename_ODY_PCIERCX_TLP_PLOG3(a) "PCIERCX_TLP_PLOG3"
8349 #define busnum_ODY_PCIERCX_TLP_PLOG3(a) (a)
8350 #define arguments_ODY_PCIERCX_TLP_PLOG3(a) (a), -1, -1, -1
8351
8352 /**
8353 * Register (PCICONFIGRC) pcierc#_tlp_plog4
8354 *
8355 * PCIe RC TLP Prefix Log Register 4
8356 */
8357 union ody_pciercx_tlp_plog4 {
8358 uint32_t u;
8359 struct ody_pciercx_tlp_plog4_s {
8360 uint32_t dword4 : 32;
8361 } s;
8362 /* struct ody_pciercx_tlp_plog4_s cn; */
8363 };
8364 typedef union ody_pciercx_tlp_plog4 ody_pciercx_tlp_plog4_t;
8365
8366 static inline uint64_t ODY_PCIERCX_TLP_PLOG4(uint64_t a) __attribute__ ((pure, always_inline));
ODY_PCIERCX_TLP_PLOG4(uint64_t a)8367 static inline uint64_t ODY_PCIERCX_TLP_PLOG4(uint64_t a)
8368 {
8369 if (a <= 15)
8370 return 0x144;
8371 __ody_csr_fatal("PCIERCX_TLP_PLOG4", 1, a, 0, 0, 0, 0, 0);
8372 }
8373
8374 #define typedef_ODY_PCIERCX_TLP_PLOG4(a) ody_pciercx_tlp_plog4_t
8375 #define bustype_ODY_PCIERCX_TLP_PLOG4(a) CSR_TYPE_PCICONFIGRC
8376 #define basename_ODY_PCIERCX_TLP_PLOG4(a) "PCIERCX_TLP_PLOG4"
8377 #define busnum_ODY_PCIERCX_TLP_PLOG4(a) (a)
8378 #define arguments_ODY_PCIERCX_TLP_PLOG4(a) (a), -1, -1, -1
8379
8380 /**
8381 * Register (PCICONFIGRC) pcierc#_trgt_cpl_lut_del_ent
8382 *
8383 * PCIe RC TRGT_CPL_LUT Delete Entry Control Register
8384 */
8385 union ody_pciercx_trgt_cpl_lut_del_ent {
8386 uint32_t u;
8387 struct ody_pciercx_trgt_cpl_lut_del_ent_s {
8388 uint32_t lkup_id : 31;
8389 uint32_t del_en : 1;
8390 } s;
8391 /* struct ody_pciercx_trgt_cpl_lut_del_ent_s cn; */
8392 };
8393 typedef union ody_pciercx_trgt_cpl_lut_del_ent ody_pciercx_trgt_cpl_lut_del_ent_t;
8394
8395 static inline uint64_t ODY_PCIERCX_TRGT_CPL_LUT_DEL_ENT(uint64_t a) __attribute__ ((pure, always_inline));
ODY_PCIERCX_TRGT_CPL_LUT_DEL_ENT(uint64_t a)8396 static inline uint64_t ODY_PCIERCX_TRGT_CPL_LUT_DEL_ENT(uint64_t a)
8397 {
8398 if (a <= 15)
8399 return 0x8c8;
8400 __ody_csr_fatal("PCIERCX_TRGT_CPL_LUT_DEL_ENT", 1, a, 0, 0, 0, 0, 0);
8401 }
8402
8403 #define typedef_ODY_PCIERCX_TRGT_CPL_LUT_DEL_ENT(a) ody_pciercx_trgt_cpl_lut_del_ent_t
8404 #define bustype_ODY_PCIERCX_TRGT_CPL_LUT_DEL_ENT(a) CSR_TYPE_PCICONFIGRC
8405 #define basename_ODY_PCIERCX_TRGT_CPL_LUT_DEL_ENT(a) "PCIERCX_TRGT_CPL_LUT_DEL_ENT"
8406 #define busnum_ODY_PCIERCX_TRGT_CPL_LUT_DEL_ENT(a) (a)
8407 #define arguments_ODY_PCIERCX_TRGT_CPL_LUT_DEL_ENT(a) (a), -1, -1, -1
8408
8409 /**
8410 * Register (PCICONFIGRC) pcierc#_trgt_map_ctl
8411 *
8412 * PCIe RC Programmable Target Map Control Register
8413 */
8414 union ody_pciercx_trgt_map_ctl {
8415 uint32_t u;
8416 struct ody_pciercx_trgt_map_ctl_s {
8417 uint32_t map_pf : 6;
8418 uint32_t map_rom : 1;
8419 uint32_t map_vf : 6;
8420 uint32_t reserved_13_15 : 3;
8421 uint32_t map_idx : 5;
8422 uint32_t reserved_21_31 : 11;
8423 } s;
8424 /* struct ody_pciercx_trgt_map_ctl_s cn; */
8425 };
8426 typedef union ody_pciercx_trgt_map_ctl ody_pciercx_trgt_map_ctl_t;
8427
8428 static inline uint64_t ODY_PCIERCX_TRGT_MAP_CTL(uint64_t a) __attribute__ ((pure, always_inline));
ODY_PCIERCX_TRGT_MAP_CTL(uint64_t a)8429 static inline uint64_t ODY_PCIERCX_TRGT_MAP_CTL(uint64_t a)
8430 {
8431 if (a <= 15)
8432 return 0x81c;
8433 __ody_csr_fatal("PCIERCX_TRGT_MAP_CTL", 1, a, 0, 0, 0, 0, 0);
8434 }
8435
8436 #define typedef_ODY_PCIERCX_TRGT_MAP_CTL(a) ody_pciercx_trgt_map_ctl_t
8437 #define bustype_ODY_PCIERCX_TRGT_MAP_CTL(a) CSR_TYPE_PCICONFIGRC
8438 #define basename_ODY_PCIERCX_TRGT_MAP_CTL(a) "PCIERCX_TRGT_MAP_CTL"
8439 #define busnum_ODY_PCIERCX_TRGT_MAP_CTL(a) (a)
8440 #define arguments_ODY_PCIERCX_TRGT_MAP_CTL(a) (a), -1, -1, -1
8441
8442 /**
8443 * Register (PCICONFIGRC) pcierc#_ucor_err_msk
8444 *
8445 * PCIe RC Uncorrectable Error Mask Register
8446 */
8447 union ody_pciercx_ucor_err_msk {
8448 uint32_t u;
8449 struct ody_pciercx_ucor_err_msk_s {
8450 uint32_t reserved_0_3 : 4;
8451 uint32_t dlpem : 1;
8452 uint32_t sdem : 1;
8453 uint32_t reserved_6_11 : 6;
8454 uint32_t ptlpm : 1;
8455 uint32_t fcpem : 1;
8456 uint32_t ctm : 1;
8457 uint32_t cam : 1;
8458 uint32_t ucm : 1;
8459 uint32_t rom : 1;
8460 uint32_t mtlpm : 1;
8461 uint32_t ecrcem : 1;
8462 uint32_t urem : 1;
8463 uint32_t avm : 1;
8464 uint32_t uciem : 1;
8465 uint32_t reserved_23 : 1;
8466 uint32_t uatombm : 1;
8467 uint32_t tpbem : 1;
8468 uint32_t tebem : 1;
8469 uint32_t debem : 1;
8470 uint32_t icfm : 1;
8471 uint32_t mitm : 1;
8472 uint32_t pcfm : 1;
8473 uint32_t reserved_31 : 1;
8474 } s;
8475 struct ody_pciercx_ucor_err_msk_cn {
8476 uint32_t reserved_0 : 1;
8477 uint32_t reserved_1_3 : 3;
8478 uint32_t dlpem : 1;
8479 uint32_t sdem : 1;
8480 uint32_t reserved_6_11 : 6;
8481 uint32_t ptlpm : 1;
8482 uint32_t fcpem : 1;
8483 uint32_t ctm : 1;
8484 uint32_t cam : 1;
8485 uint32_t ucm : 1;
8486 uint32_t rom : 1;
8487 uint32_t mtlpm : 1;
8488 uint32_t ecrcem : 1;
8489 uint32_t urem : 1;
8490 uint32_t avm : 1;
8491 uint32_t uciem : 1;
8492 uint32_t reserved_23 : 1;
8493 uint32_t uatombm : 1;
8494 uint32_t tpbem : 1;
8495 uint32_t tebem : 1;
8496 uint32_t debem : 1;
8497 uint32_t icfm : 1;
8498 uint32_t mitm : 1;
8499 uint32_t pcfm : 1;
8500 uint32_t reserved_31 : 1;
8501 } cn;
8502 };
8503 typedef union ody_pciercx_ucor_err_msk ody_pciercx_ucor_err_msk_t;
8504
8505 static inline uint64_t ODY_PCIERCX_UCOR_ERR_MSK(uint64_t a) __attribute__ ((pure, always_inline));
ODY_PCIERCX_UCOR_ERR_MSK(uint64_t a)8506 static inline uint64_t ODY_PCIERCX_UCOR_ERR_MSK(uint64_t a)
8507 {
8508 if (a <= 15)
8509 return 0x108;
8510 __ody_csr_fatal("PCIERCX_UCOR_ERR_MSK", 1, a, 0, 0, 0, 0, 0);
8511 }
8512
8513 #define typedef_ODY_PCIERCX_UCOR_ERR_MSK(a) ody_pciercx_ucor_err_msk_t
8514 #define bustype_ODY_PCIERCX_UCOR_ERR_MSK(a) CSR_TYPE_PCICONFIGRC
8515 #define basename_ODY_PCIERCX_UCOR_ERR_MSK(a) "PCIERCX_UCOR_ERR_MSK"
8516 #define busnum_ODY_PCIERCX_UCOR_ERR_MSK(a) (a)
8517 #define arguments_ODY_PCIERCX_UCOR_ERR_MSK(a) (a), -1, -1, -1
8518
8519 /**
8520 * Register (PCICONFIGRC) pcierc#_ucor_err_sev
8521 *
8522 * PCIe RC Uncorrectable Error Severity Register
8523 */
8524 union ody_pciercx_ucor_err_sev {
8525 uint32_t u;
8526 struct ody_pciercx_ucor_err_sev_s {
8527 uint32_t reserved_0_3 : 4;
8528 uint32_t dlpes : 1;
8529 uint32_t sdes : 1;
8530 uint32_t reserved_6_11 : 6;
8531 uint32_t ptlps : 1;
8532 uint32_t fcpes : 1;
8533 uint32_t cts : 1;
8534 uint32_t cas : 1;
8535 uint32_t ucs : 1;
8536 uint32_t ros : 1;
8537 uint32_t mtlps : 1;
8538 uint32_t ecrces : 1;
8539 uint32_t ures : 1;
8540 uint32_t avs : 1;
8541 uint32_t ies : 1;
8542 uint32_t reserved_23 : 1;
8543 uint32_t uatombs : 1;
8544 uint32_t tpbes : 1;
8545 uint32_t ptebes : 1;
8546 uint32_t debes : 1;
8547 uint32_t icfs : 1;
8548 uint32_t mits : 1;
8549 uint32_t pcfs : 1;
8550 uint32_t reserved_31 : 1;
8551 } s;
8552 struct ody_pciercx_ucor_err_sev_cn {
8553 uint32_t reserved_0 : 1;
8554 uint32_t reserved_1_3 : 3;
8555 uint32_t dlpes : 1;
8556 uint32_t sdes : 1;
8557 uint32_t reserved_6_11 : 6;
8558 uint32_t ptlps : 1;
8559 uint32_t fcpes : 1;
8560 uint32_t cts : 1;
8561 uint32_t cas : 1;
8562 uint32_t ucs : 1;
8563 uint32_t ros : 1;
8564 uint32_t mtlps : 1;
8565 uint32_t ecrces : 1;
8566 uint32_t ures : 1;
8567 uint32_t avs : 1;
8568 uint32_t ies : 1;
8569 uint32_t reserved_23 : 1;
8570 uint32_t uatombs : 1;
8571 uint32_t tpbes : 1;
8572 uint32_t ptebes : 1;
8573 uint32_t debes : 1;
8574 uint32_t icfs : 1;
8575 uint32_t mits : 1;
8576 uint32_t pcfs : 1;
8577 uint32_t reserved_31 : 1;
8578 } cn;
8579 };
8580 typedef union ody_pciercx_ucor_err_sev ody_pciercx_ucor_err_sev_t;
8581
8582 static inline uint64_t ODY_PCIERCX_UCOR_ERR_SEV(uint64_t a) __attribute__ ((pure, always_inline));
ODY_PCIERCX_UCOR_ERR_SEV(uint64_t a)8583 static inline uint64_t ODY_PCIERCX_UCOR_ERR_SEV(uint64_t a)
8584 {
8585 if (a <= 15)
8586 return 0x10c;
8587 __ody_csr_fatal("PCIERCX_UCOR_ERR_SEV", 1, a, 0, 0, 0, 0, 0);
8588 }
8589
8590 #define typedef_ODY_PCIERCX_UCOR_ERR_SEV(a) ody_pciercx_ucor_err_sev_t
8591 #define bustype_ODY_PCIERCX_UCOR_ERR_SEV(a) CSR_TYPE_PCICONFIGRC
8592 #define basename_ODY_PCIERCX_UCOR_ERR_SEV(a) "PCIERCX_UCOR_ERR_SEV"
8593 #define busnum_ODY_PCIERCX_UCOR_ERR_SEV(a) (a)
8594 #define arguments_ODY_PCIERCX_UCOR_ERR_SEV(a) (a), -1, -1, -1
8595
8596 /**
8597 * Register (PCICONFIGRC) pcierc#_ucor_err_stat
8598 *
8599 * PCIe RC Uncorrectable Error Status Register
8600 */
8601 union ody_pciercx_ucor_err_stat {
8602 uint32_t u;
8603 struct ody_pciercx_ucor_err_stat_s {
8604 uint32_t reserved_0_3 : 4;
8605 uint32_t dlpes : 1;
8606 uint32_t sdes : 1;
8607 uint32_t reserved_6_11 : 6;
8608 uint32_t ptlps : 1;
8609 uint32_t fcpes : 1;
8610 uint32_t cts : 1;
8611 uint32_t cas : 1;
8612 uint32_t ucs : 1;
8613 uint32_t ros : 1;
8614 uint32_t mtlps : 1;
8615 uint32_t ecrces : 1;
8616 uint32_t ures : 1;
8617 uint32_t avs : 1;
8618 uint32_t ucies : 1;
8619 uint32_t reserved_23 : 1;
8620 uint32_t uatombs : 1;
8621 uint32_t tpbes : 1;
8622 uint32_t ptebes : 1;
8623 uint32_t debes : 1;
8624 uint32_t icfst : 1;
8625 uint32_t mitst : 1;
8626 uint32_t pcfst : 1;
8627 uint32_t reserved_31 : 1;
8628 } s;
8629 struct ody_pciercx_ucor_err_stat_cn {
8630 uint32_t reserved_0 : 1;
8631 uint32_t reserved_1_3 : 3;
8632 uint32_t dlpes : 1;
8633 uint32_t sdes : 1;
8634 uint32_t reserved_6_11 : 6;
8635 uint32_t ptlps : 1;
8636 uint32_t fcpes : 1;
8637 uint32_t cts : 1;
8638 uint32_t cas : 1;
8639 uint32_t ucs : 1;
8640 uint32_t ros : 1;
8641 uint32_t mtlps : 1;
8642 uint32_t ecrces : 1;
8643 uint32_t ures : 1;
8644 uint32_t avs : 1;
8645 uint32_t ucies : 1;
8646 uint32_t reserved_23 : 1;
8647 uint32_t uatombs : 1;
8648 uint32_t tpbes : 1;
8649 uint32_t ptebes : 1;
8650 uint32_t debes : 1;
8651 uint32_t icfst : 1;
8652 uint32_t mitst : 1;
8653 uint32_t pcfst : 1;
8654 uint32_t reserved_31 : 1;
8655 } cn;
8656 };
8657 typedef union ody_pciercx_ucor_err_stat ody_pciercx_ucor_err_stat_t;
8658
8659 static inline uint64_t ODY_PCIERCX_UCOR_ERR_STAT(uint64_t a) __attribute__ ((pure, always_inline));
ODY_PCIERCX_UCOR_ERR_STAT(uint64_t a)8660 static inline uint64_t ODY_PCIERCX_UCOR_ERR_STAT(uint64_t a)
8661 {
8662 if (a <= 15)
8663 return 0x104;
8664 __ody_csr_fatal("PCIERCX_UCOR_ERR_STAT", 1, a, 0, 0, 0, 0, 0);
8665 }
8666
8667 #define typedef_ODY_PCIERCX_UCOR_ERR_STAT(a) ody_pciercx_ucor_err_stat_t
8668 #define bustype_ODY_PCIERCX_UCOR_ERR_STAT(a) CSR_TYPE_PCICONFIGRC
8669 #define basename_ODY_PCIERCX_UCOR_ERR_STAT(a) "PCIERCX_UCOR_ERR_STAT"
8670 #define busnum_ODY_PCIERCX_UCOR_ERR_STAT(a) (a)
8671 #define arguments_ODY_PCIERCX_UCOR_ERR_STAT(a) (a), -1, -1, -1
8672
8673 /**
8674 * Register (PCICONFIGRC) pcierc#_unused_cap0
8675 *
8676 * PCIe RC Unused Capability Registers
8677 */
8678 union ody_pciercx_unused_cap0 {
8679 uint32_t u;
8680 struct ody_pciercx_unused_cap0_s {
8681 uint32_t sw_hdr : 32;
8682 } s;
8683 /* struct ody_pciercx_unused_cap0_s cn; */
8684 };
8685 typedef union ody_pciercx_unused_cap0 ody_pciercx_unused_cap0_t;
8686
8687 static inline uint64_t ODY_PCIERCX_UNUSED_CAP0(uint64_t a) __attribute__ ((pure, always_inline));
ODY_PCIERCX_UNUSED_CAP0(uint64_t a)8688 static inline uint64_t ODY_PCIERCX_UNUSED_CAP0(uint64_t a)
8689 {
8690 if (a <= 15)
8691 return 0xbc;
8692 __ody_csr_fatal("PCIERCX_UNUSED_CAP0", 1, a, 0, 0, 0, 0, 0);
8693 }
8694
8695 #define typedef_ODY_PCIERCX_UNUSED_CAP0(a) ody_pciercx_unused_cap0_t
8696 #define bustype_ODY_PCIERCX_UNUSED_CAP0(a) CSR_TYPE_PCICONFIGRC
8697 #define basename_ODY_PCIERCX_UNUSED_CAP0(a) "PCIERCX_UNUSED_CAP0"
8698 #define busnum_ODY_PCIERCX_UNUSED_CAP0(a) (a)
8699 #define arguments_ODY_PCIERCX_UNUSED_CAP0(a) (a), -1, -1, -1
8700
8701 /**
8702 * Register (PCICONFIGRC) pcierc#_unused_cap1
8703 *
8704 * PCIe RC Unused Capability Registers
8705 */
8706 union ody_pciercx_unused_cap1 {
8707 uint32_t u;
8708 struct ody_pciercx_unused_cap1_s {
8709 uint32_t sw_hdr : 32;
8710 } s;
8711 /* struct ody_pciercx_unused_cap1_s cn; */
8712 };
8713 typedef union ody_pciercx_unused_cap1 ody_pciercx_unused_cap1_t;
8714
8715 static inline uint64_t ODY_PCIERCX_UNUSED_CAP1(uint64_t a) __attribute__ ((pure, always_inline));
ODY_PCIERCX_UNUSED_CAP1(uint64_t a)8716 static inline uint64_t ODY_PCIERCX_UNUSED_CAP1(uint64_t a)
8717 {
8718 if (a <= 15)
8719 return 0xc0;
8720 __ody_csr_fatal("PCIERCX_UNUSED_CAP1", 1, a, 0, 0, 0, 0, 0);
8721 }
8722
8723 #define typedef_ODY_PCIERCX_UNUSED_CAP1(a) ody_pciercx_unused_cap1_t
8724 #define bustype_ODY_PCIERCX_UNUSED_CAP1(a) CSR_TYPE_PCICONFIGRC
8725 #define basename_ODY_PCIERCX_UNUSED_CAP1(a) "PCIERCX_UNUSED_CAP1"
8726 #define busnum_ODY_PCIERCX_UNUSED_CAP1(a) (a)
8727 #define arguments_ODY_PCIERCX_UNUSED_CAP1(a) (a), -1, -1, -1
8728
8729 /**
8730 * Register (PCICONFIGRC) pcierc#_unused_cap10
8731 *
8732 * PCIe RC Unused Capability Registers
8733 */
8734 union ody_pciercx_unused_cap10 {
8735 uint32_t u;
8736 struct ody_pciercx_unused_cap10_s {
8737 uint32_t sw_hdr : 32;
8738 } s;
8739 /* struct ody_pciercx_unused_cap10_s cn; */
8740 };
8741 typedef union ody_pciercx_unused_cap10 ody_pciercx_unused_cap10_t;
8742
8743 static inline uint64_t ODY_PCIERCX_UNUSED_CAP10(uint64_t a) __attribute__ ((pure, always_inline));
ODY_PCIERCX_UNUSED_CAP10(uint64_t a)8744 static inline uint64_t ODY_PCIERCX_UNUSED_CAP10(uint64_t a)
8745 {
8746 if (a <= 15)
8747 return 0xe4;
8748 __ody_csr_fatal("PCIERCX_UNUSED_CAP10", 1, a, 0, 0, 0, 0, 0);
8749 }
8750
8751 #define typedef_ODY_PCIERCX_UNUSED_CAP10(a) ody_pciercx_unused_cap10_t
8752 #define bustype_ODY_PCIERCX_UNUSED_CAP10(a) CSR_TYPE_PCICONFIGRC
8753 #define basename_ODY_PCIERCX_UNUSED_CAP10(a) "PCIERCX_UNUSED_CAP10"
8754 #define busnum_ODY_PCIERCX_UNUSED_CAP10(a) (a)
8755 #define arguments_ODY_PCIERCX_UNUSED_CAP10(a) (a), -1, -1, -1
8756
8757 /**
8758 * Register (PCICONFIGRC) pcierc#_unused_cap11
8759 *
8760 * PCIe RC Unused Capability Registers
8761 */
8762 union ody_pciercx_unused_cap11 {
8763 uint32_t u;
8764 struct ody_pciercx_unused_cap11_s {
8765 uint32_t sw_hdr : 32;
8766 } s;
8767 /* struct ody_pciercx_unused_cap11_s cn; */
8768 };
8769 typedef union ody_pciercx_unused_cap11 ody_pciercx_unused_cap11_t;
8770
8771 static inline uint64_t ODY_PCIERCX_UNUSED_CAP11(uint64_t a) __attribute__ ((pure, always_inline));
ODY_PCIERCX_UNUSED_CAP11(uint64_t a)8772 static inline uint64_t ODY_PCIERCX_UNUSED_CAP11(uint64_t a)
8773 {
8774 if (a <= 15)
8775 return 0xe8;
8776 __ody_csr_fatal("PCIERCX_UNUSED_CAP11", 1, a, 0, 0, 0, 0, 0);
8777 }
8778
8779 #define typedef_ODY_PCIERCX_UNUSED_CAP11(a) ody_pciercx_unused_cap11_t
8780 #define bustype_ODY_PCIERCX_UNUSED_CAP11(a) CSR_TYPE_PCICONFIGRC
8781 #define basename_ODY_PCIERCX_UNUSED_CAP11(a) "PCIERCX_UNUSED_CAP11"
8782 #define busnum_ODY_PCIERCX_UNUSED_CAP11(a) (a)
8783 #define arguments_ODY_PCIERCX_UNUSED_CAP11(a) (a), -1, -1, -1
8784
8785 /**
8786 * Register (PCICONFIGRC) pcierc#_unused_cap12
8787 *
8788 * PCIe RC Unused Capability Registers
8789 */
8790 union ody_pciercx_unused_cap12 {
8791 uint32_t u;
8792 struct ody_pciercx_unused_cap12_s {
8793 uint32_t sw_hdr : 32;
8794 } s;
8795 /* struct ody_pciercx_unused_cap12_s cn; */
8796 };
8797 typedef union ody_pciercx_unused_cap12 ody_pciercx_unused_cap12_t;
8798
8799 static inline uint64_t ODY_PCIERCX_UNUSED_CAP12(uint64_t a) __attribute__ ((pure, always_inline));
ODY_PCIERCX_UNUSED_CAP12(uint64_t a)8800 static inline uint64_t ODY_PCIERCX_UNUSED_CAP12(uint64_t a)
8801 {
8802 if (a <= 15)
8803 return 0xec;
8804 __ody_csr_fatal("PCIERCX_UNUSED_CAP12", 1, a, 0, 0, 0, 0, 0);
8805 }
8806
8807 #define typedef_ODY_PCIERCX_UNUSED_CAP12(a) ody_pciercx_unused_cap12_t
8808 #define bustype_ODY_PCIERCX_UNUSED_CAP12(a) CSR_TYPE_PCICONFIGRC
8809 #define basename_ODY_PCIERCX_UNUSED_CAP12(a) "PCIERCX_UNUSED_CAP12"
8810 #define busnum_ODY_PCIERCX_UNUSED_CAP12(a) (a)
8811 #define arguments_ODY_PCIERCX_UNUSED_CAP12(a) (a), -1, -1, -1
8812
8813 /**
8814 * Register (PCICONFIGRC) pcierc#_unused_cap13
8815 *
8816 * PCIe RC Unused Capability Registers
8817 */
8818 union ody_pciercx_unused_cap13 {
8819 uint32_t u;
8820 struct ody_pciercx_unused_cap13_s {
8821 uint32_t sw_hdr : 32;
8822 } s;
8823 /* struct ody_pciercx_unused_cap13_s cn; */
8824 };
8825 typedef union ody_pciercx_unused_cap13 ody_pciercx_unused_cap13_t;
8826
8827 static inline uint64_t ODY_PCIERCX_UNUSED_CAP13(uint64_t a) __attribute__ ((pure, always_inline));
ODY_PCIERCX_UNUSED_CAP13(uint64_t a)8828 static inline uint64_t ODY_PCIERCX_UNUSED_CAP13(uint64_t a)
8829 {
8830 if (a <= 15)
8831 return 0xf0;
8832 __ody_csr_fatal("PCIERCX_UNUSED_CAP13", 1, a, 0, 0, 0, 0, 0);
8833 }
8834
8835 #define typedef_ODY_PCIERCX_UNUSED_CAP13(a) ody_pciercx_unused_cap13_t
8836 #define bustype_ODY_PCIERCX_UNUSED_CAP13(a) CSR_TYPE_PCICONFIGRC
8837 #define basename_ODY_PCIERCX_UNUSED_CAP13(a) "PCIERCX_UNUSED_CAP13"
8838 #define busnum_ODY_PCIERCX_UNUSED_CAP13(a) (a)
8839 #define arguments_ODY_PCIERCX_UNUSED_CAP13(a) (a), -1, -1, -1
8840
8841 /**
8842 * Register (PCICONFIGRC) pcierc#_unused_cap14
8843 *
8844 * PCIe RC Unused Capability Registers
8845 */
8846 union ody_pciercx_unused_cap14 {
8847 uint32_t u;
8848 struct ody_pciercx_unused_cap14_s {
8849 uint32_t sw_hdr : 32;
8850 } s;
8851 /* struct ody_pciercx_unused_cap14_s cn; */
8852 };
8853 typedef union ody_pciercx_unused_cap14 ody_pciercx_unused_cap14_t;
8854
8855 static inline uint64_t ODY_PCIERCX_UNUSED_CAP14(uint64_t a) __attribute__ ((pure, always_inline));
ODY_PCIERCX_UNUSED_CAP14(uint64_t a)8856 static inline uint64_t ODY_PCIERCX_UNUSED_CAP14(uint64_t a)
8857 {
8858 if (a <= 15)
8859 return 0xf4;
8860 __ody_csr_fatal("PCIERCX_UNUSED_CAP14", 1, a, 0, 0, 0, 0, 0);
8861 }
8862
8863 #define typedef_ODY_PCIERCX_UNUSED_CAP14(a) ody_pciercx_unused_cap14_t
8864 #define bustype_ODY_PCIERCX_UNUSED_CAP14(a) CSR_TYPE_PCICONFIGRC
8865 #define basename_ODY_PCIERCX_UNUSED_CAP14(a) "PCIERCX_UNUSED_CAP14"
8866 #define busnum_ODY_PCIERCX_UNUSED_CAP14(a) (a)
8867 #define arguments_ODY_PCIERCX_UNUSED_CAP14(a) (a), -1, -1, -1
8868
8869 /**
8870 * Register (PCICONFIGRC) pcierc#_unused_cap15
8871 *
8872 * PCIe RC Unused Capability Registers
8873 */
8874 union ody_pciercx_unused_cap15 {
8875 uint32_t u;
8876 struct ody_pciercx_unused_cap15_s {
8877 uint32_t sw_hdr : 32;
8878 } s;
8879 /* struct ody_pciercx_unused_cap15_s cn; */
8880 };
8881 typedef union ody_pciercx_unused_cap15 ody_pciercx_unused_cap15_t;
8882
8883 static inline uint64_t ODY_PCIERCX_UNUSED_CAP15(uint64_t a) __attribute__ ((pure, always_inline));
ODY_PCIERCX_UNUSED_CAP15(uint64_t a)8884 static inline uint64_t ODY_PCIERCX_UNUSED_CAP15(uint64_t a)
8885 {
8886 if (a <= 15)
8887 return 0xf8;
8888 __ody_csr_fatal("PCIERCX_UNUSED_CAP15", 1, a, 0, 0, 0, 0, 0);
8889 }
8890
8891 #define typedef_ODY_PCIERCX_UNUSED_CAP15(a) ody_pciercx_unused_cap15_t
8892 #define bustype_ODY_PCIERCX_UNUSED_CAP15(a) CSR_TYPE_PCICONFIGRC
8893 #define basename_ODY_PCIERCX_UNUSED_CAP15(a) "PCIERCX_UNUSED_CAP15"
8894 #define busnum_ODY_PCIERCX_UNUSED_CAP15(a) (a)
8895 #define arguments_ODY_PCIERCX_UNUSED_CAP15(a) (a), -1, -1, -1
8896
8897 /**
8898 * Register (PCICONFIGRC) pcierc#_unused_cap16
8899 *
8900 * PCIe RC Unused Capability Registers
8901 */
8902 union ody_pciercx_unused_cap16 {
8903 uint32_t u;
8904 struct ody_pciercx_unused_cap16_s {
8905 uint32_t sw_hdr : 32;
8906 } s;
8907 /* struct ody_pciercx_unused_cap16_s cn; */
8908 };
8909 typedef union ody_pciercx_unused_cap16 ody_pciercx_unused_cap16_t;
8910
8911 static inline uint64_t ODY_PCIERCX_UNUSED_CAP16(uint64_t a) __attribute__ ((pure, always_inline));
ODY_PCIERCX_UNUSED_CAP16(uint64_t a)8912 static inline uint64_t ODY_PCIERCX_UNUSED_CAP16(uint64_t a)
8913 {
8914 if (a <= 15)
8915 return 0xfc;
8916 __ody_csr_fatal("PCIERCX_UNUSED_CAP16", 1, a, 0, 0, 0, 0, 0);
8917 }
8918
8919 #define typedef_ODY_PCIERCX_UNUSED_CAP16(a) ody_pciercx_unused_cap16_t
8920 #define bustype_ODY_PCIERCX_UNUSED_CAP16(a) CSR_TYPE_PCICONFIGRC
8921 #define basename_ODY_PCIERCX_UNUSED_CAP16(a) "PCIERCX_UNUSED_CAP16"
8922 #define busnum_ODY_PCIERCX_UNUSED_CAP16(a) (a)
8923 #define arguments_ODY_PCIERCX_UNUSED_CAP16(a) (a), -1, -1, -1
8924
8925 /**
8926 * Register (PCICONFIGRC) pcierc#_unused_cap2
8927 *
8928 * PCIe RC Unused Capability Registers
8929 */
8930 union ody_pciercx_unused_cap2 {
8931 uint32_t u;
8932 struct ody_pciercx_unused_cap2_s {
8933 uint32_t sw_hdr : 32;
8934 } s;
8935 /* struct ody_pciercx_unused_cap2_s cn; */
8936 };
8937 typedef union ody_pciercx_unused_cap2 ody_pciercx_unused_cap2_t;
8938
8939 static inline uint64_t ODY_PCIERCX_UNUSED_CAP2(uint64_t a) __attribute__ ((pure, always_inline));
ODY_PCIERCX_UNUSED_CAP2(uint64_t a)8940 static inline uint64_t ODY_PCIERCX_UNUSED_CAP2(uint64_t a)
8941 {
8942 if (a <= 15)
8943 return 0xc4;
8944 __ody_csr_fatal("PCIERCX_UNUSED_CAP2", 1, a, 0, 0, 0, 0, 0);
8945 }
8946
8947 #define typedef_ODY_PCIERCX_UNUSED_CAP2(a) ody_pciercx_unused_cap2_t
8948 #define bustype_ODY_PCIERCX_UNUSED_CAP2(a) CSR_TYPE_PCICONFIGRC
8949 #define basename_ODY_PCIERCX_UNUSED_CAP2(a) "PCIERCX_UNUSED_CAP2"
8950 #define busnum_ODY_PCIERCX_UNUSED_CAP2(a) (a)
8951 #define arguments_ODY_PCIERCX_UNUSED_CAP2(a) (a), -1, -1, -1
8952
8953 /**
8954 * Register (PCICONFIGRC) pcierc#_unused_cap3
8955 *
8956 * PCIe RC Unused Capability Registers
8957 */
8958 union ody_pciercx_unused_cap3 {
8959 uint32_t u;
8960 struct ody_pciercx_unused_cap3_s {
8961 uint32_t sw_hdr : 32;
8962 } s;
8963 /* struct ody_pciercx_unused_cap3_s cn; */
8964 };
8965 typedef union ody_pciercx_unused_cap3 ody_pciercx_unused_cap3_t;
8966
8967 static inline uint64_t ODY_PCIERCX_UNUSED_CAP3(uint64_t a) __attribute__ ((pure, always_inline));
ODY_PCIERCX_UNUSED_CAP3(uint64_t a)8968 static inline uint64_t ODY_PCIERCX_UNUSED_CAP3(uint64_t a)
8969 {
8970 if (a <= 15)
8971 return 0xc8;
8972 __ody_csr_fatal("PCIERCX_UNUSED_CAP3", 1, a, 0, 0, 0, 0, 0);
8973 }
8974
8975 #define typedef_ODY_PCIERCX_UNUSED_CAP3(a) ody_pciercx_unused_cap3_t
8976 #define bustype_ODY_PCIERCX_UNUSED_CAP3(a) CSR_TYPE_PCICONFIGRC
8977 #define basename_ODY_PCIERCX_UNUSED_CAP3(a) "PCIERCX_UNUSED_CAP3"
8978 #define busnum_ODY_PCIERCX_UNUSED_CAP3(a) (a)
8979 #define arguments_ODY_PCIERCX_UNUSED_CAP3(a) (a), -1, -1, -1
8980
8981 /**
8982 * Register (PCICONFIGRC) pcierc#_unused_cap4
8983 *
8984 * PCIe RC Unused Capability Registers
8985 */
8986 union ody_pciercx_unused_cap4 {
8987 uint32_t u;
8988 struct ody_pciercx_unused_cap4_s {
8989 uint32_t sw_hdr : 32;
8990 } s;
8991 /* struct ody_pciercx_unused_cap4_s cn; */
8992 };
8993 typedef union ody_pciercx_unused_cap4 ody_pciercx_unused_cap4_t;
8994
8995 static inline uint64_t ODY_PCIERCX_UNUSED_CAP4(uint64_t a) __attribute__ ((pure, always_inline));
ODY_PCIERCX_UNUSED_CAP4(uint64_t a)8996 static inline uint64_t ODY_PCIERCX_UNUSED_CAP4(uint64_t a)
8997 {
8998 if (a <= 15)
8999 return 0xcc;
9000 __ody_csr_fatal("PCIERCX_UNUSED_CAP4", 1, a, 0, 0, 0, 0, 0);
9001 }
9002
9003 #define typedef_ODY_PCIERCX_UNUSED_CAP4(a) ody_pciercx_unused_cap4_t
9004 #define bustype_ODY_PCIERCX_UNUSED_CAP4(a) CSR_TYPE_PCICONFIGRC
9005 #define basename_ODY_PCIERCX_UNUSED_CAP4(a) "PCIERCX_UNUSED_CAP4"
9006 #define busnum_ODY_PCIERCX_UNUSED_CAP4(a) (a)
9007 #define arguments_ODY_PCIERCX_UNUSED_CAP4(a) (a), -1, -1, -1
9008
9009 /**
9010 * Register (PCICONFIGRC) pcierc#_unused_cap5
9011 *
9012 * PCIe RC Unused Capability Registers
9013 */
9014 union ody_pciercx_unused_cap5 {
9015 uint32_t u;
9016 struct ody_pciercx_unused_cap5_s {
9017 uint32_t sw_hdr : 32;
9018 } s;
9019 /* struct ody_pciercx_unused_cap5_s cn; */
9020 };
9021 typedef union ody_pciercx_unused_cap5 ody_pciercx_unused_cap5_t;
9022
9023 static inline uint64_t ODY_PCIERCX_UNUSED_CAP5(uint64_t a) __attribute__ ((pure, always_inline));
ODY_PCIERCX_UNUSED_CAP5(uint64_t a)9024 static inline uint64_t ODY_PCIERCX_UNUSED_CAP5(uint64_t a)
9025 {
9026 if (a <= 15)
9027 return 0xd0;
9028 __ody_csr_fatal("PCIERCX_UNUSED_CAP5", 1, a, 0, 0, 0, 0, 0);
9029 }
9030
9031 #define typedef_ODY_PCIERCX_UNUSED_CAP5(a) ody_pciercx_unused_cap5_t
9032 #define bustype_ODY_PCIERCX_UNUSED_CAP5(a) CSR_TYPE_PCICONFIGRC
9033 #define basename_ODY_PCIERCX_UNUSED_CAP5(a) "PCIERCX_UNUSED_CAP5"
9034 #define busnum_ODY_PCIERCX_UNUSED_CAP5(a) (a)
9035 #define arguments_ODY_PCIERCX_UNUSED_CAP5(a) (a), -1, -1, -1
9036
9037 /**
9038 * Register (PCICONFIGRC) pcierc#_unused_cap6
9039 *
9040 * PCIe RC Unused Capability Registers
9041 */
9042 union ody_pciercx_unused_cap6 {
9043 uint32_t u;
9044 struct ody_pciercx_unused_cap6_s {
9045 uint32_t sw_hdr : 32;
9046 } s;
9047 /* struct ody_pciercx_unused_cap6_s cn; */
9048 };
9049 typedef union ody_pciercx_unused_cap6 ody_pciercx_unused_cap6_t;
9050
9051 static inline uint64_t ODY_PCIERCX_UNUSED_CAP6(uint64_t a) __attribute__ ((pure, always_inline));
ODY_PCIERCX_UNUSED_CAP6(uint64_t a)9052 static inline uint64_t ODY_PCIERCX_UNUSED_CAP6(uint64_t a)
9053 {
9054 if (a <= 15)
9055 return 0xd4;
9056 __ody_csr_fatal("PCIERCX_UNUSED_CAP6", 1, a, 0, 0, 0, 0, 0);
9057 }
9058
9059 #define typedef_ODY_PCIERCX_UNUSED_CAP6(a) ody_pciercx_unused_cap6_t
9060 #define bustype_ODY_PCIERCX_UNUSED_CAP6(a) CSR_TYPE_PCICONFIGRC
9061 #define basename_ODY_PCIERCX_UNUSED_CAP6(a) "PCIERCX_UNUSED_CAP6"
9062 #define busnum_ODY_PCIERCX_UNUSED_CAP6(a) (a)
9063 #define arguments_ODY_PCIERCX_UNUSED_CAP6(a) (a), -1, -1, -1
9064
9065 /**
9066 * Register (PCICONFIGRC) pcierc#_unused_cap7
9067 *
9068 * PCIe RC Unused Capability Registers
9069 */
9070 union ody_pciercx_unused_cap7 {
9071 uint32_t u;
9072 struct ody_pciercx_unused_cap7_s {
9073 uint32_t sw_hdr : 32;
9074 } s;
9075 /* struct ody_pciercx_unused_cap7_s cn; */
9076 };
9077 typedef union ody_pciercx_unused_cap7 ody_pciercx_unused_cap7_t;
9078
9079 static inline uint64_t ODY_PCIERCX_UNUSED_CAP7(uint64_t a) __attribute__ ((pure, always_inline));
ODY_PCIERCX_UNUSED_CAP7(uint64_t a)9080 static inline uint64_t ODY_PCIERCX_UNUSED_CAP7(uint64_t a)
9081 {
9082 if (a <= 15)
9083 return 0xd8;
9084 __ody_csr_fatal("PCIERCX_UNUSED_CAP7", 1, a, 0, 0, 0, 0, 0);
9085 }
9086
9087 #define typedef_ODY_PCIERCX_UNUSED_CAP7(a) ody_pciercx_unused_cap7_t
9088 #define bustype_ODY_PCIERCX_UNUSED_CAP7(a) CSR_TYPE_PCICONFIGRC
9089 #define basename_ODY_PCIERCX_UNUSED_CAP7(a) "PCIERCX_UNUSED_CAP7"
9090 #define busnum_ODY_PCIERCX_UNUSED_CAP7(a) (a)
9091 #define arguments_ODY_PCIERCX_UNUSED_CAP7(a) (a), -1, -1, -1
9092
9093 /**
9094 * Register (PCICONFIGRC) pcierc#_unused_cap8
9095 *
9096 * PCIe RC Unused Capability Registers
9097 */
9098 union ody_pciercx_unused_cap8 {
9099 uint32_t u;
9100 struct ody_pciercx_unused_cap8_s {
9101 uint32_t sw_hdr : 32;
9102 } s;
9103 /* struct ody_pciercx_unused_cap8_s cn; */
9104 };
9105 typedef union ody_pciercx_unused_cap8 ody_pciercx_unused_cap8_t;
9106
9107 static inline uint64_t ODY_PCIERCX_UNUSED_CAP8(uint64_t a) __attribute__ ((pure, always_inline));
ODY_PCIERCX_UNUSED_CAP8(uint64_t a)9108 static inline uint64_t ODY_PCIERCX_UNUSED_CAP8(uint64_t a)
9109 {
9110 if (a <= 15)
9111 return 0xdc;
9112 __ody_csr_fatal("PCIERCX_UNUSED_CAP8", 1, a, 0, 0, 0, 0, 0);
9113 }
9114
9115 #define typedef_ODY_PCIERCX_UNUSED_CAP8(a) ody_pciercx_unused_cap8_t
9116 #define bustype_ODY_PCIERCX_UNUSED_CAP8(a) CSR_TYPE_PCICONFIGRC
9117 #define basename_ODY_PCIERCX_UNUSED_CAP8(a) "PCIERCX_UNUSED_CAP8"
9118 #define busnum_ODY_PCIERCX_UNUSED_CAP8(a) (a)
9119 #define arguments_ODY_PCIERCX_UNUSED_CAP8(a) (a), -1, -1, -1
9120
9121 /**
9122 * Register (PCICONFIGRC) pcierc#_unused_cap9
9123 *
9124 * PCIe RC Unused Capability Registers
9125 */
9126 union ody_pciercx_unused_cap9 {
9127 uint32_t u;
9128 struct ody_pciercx_unused_cap9_s {
9129 uint32_t sw_hdr : 32;
9130 } s;
9131 /* struct ody_pciercx_unused_cap9_s cn; */
9132 };
9133 typedef union ody_pciercx_unused_cap9 ody_pciercx_unused_cap9_t;
9134
9135 static inline uint64_t ODY_PCIERCX_UNUSED_CAP9(uint64_t a) __attribute__ ((pure, always_inline));
ODY_PCIERCX_UNUSED_CAP9(uint64_t a)9136 static inline uint64_t ODY_PCIERCX_UNUSED_CAP9(uint64_t a)
9137 {
9138 if (a <= 15)
9139 return 0xe0;
9140 __ody_csr_fatal("PCIERCX_UNUSED_CAP9", 1, a, 0, 0, 0, 0, 0);
9141 }
9142
9143 #define typedef_ODY_PCIERCX_UNUSED_CAP9(a) ody_pciercx_unused_cap9_t
9144 #define bustype_ODY_PCIERCX_UNUSED_CAP9(a) CSR_TYPE_PCICONFIGRC
9145 #define basename_ODY_PCIERCX_UNUSED_CAP9(a) "PCIERCX_UNUSED_CAP9"
9146 #define busnum_ODY_PCIERCX_UNUSED_CAP9(a) (a)
9147 #define arguments_ODY_PCIERCX_UNUSED_CAP9(a) (a), -1, -1, -1
9148
9149 /**
9150 * Register (PCICONFIGRC) pcierc#_upconfig
9151 *
9152 * PCIe RC UpConfigure Multi-lane Control Register
9153 */
9154 union ody_pciercx_upconfig {
9155 uint32_t u;
9156 struct ody_pciercx_upconfig_s {
9157 uint32_t trgt_lnk_wdth : 6;
9158 uint32_t dir_lnk_wdth_chg : 1;
9159 uint32_t upc_supp : 1;
9160 uint32_t rel_lnk_wdth_chg : 1;
9161 uint32_t reserved_9_31 : 23;
9162 } s;
9163 /* struct ody_pciercx_upconfig_s cn; */
9164 };
9165 typedef union ody_pciercx_upconfig ody_pciercx_upconfig_t;
9166
9167 static inline uint64_t ODY_PCIERCX_UPCONFIG(uint64_t a) __attribute__ ((pure, always_inline));
ODY_PCIERCX_UPCONFIG(uint64_t a)9168 static inline uint64_t ODY_PCIERCX_UPCONFIG(uint64_t a)
9169 {
9170 if (a <= 15)
9171 return 0x8c0;
9172 __ody_csr_fatal("PCIERCX_UPCONFIG", 1, a, 0, 0, 0, 0, 0);
9173 }
9174
9175 #define typedef_ODY_PCIERCX_UPCONFIG(a) ody_pciercx_upconfig_t
9176 #define bustype_ODY_PCIERCX_UPCONFIG(a) CSR_TYPE_PCICONFIGRC
9177 #define basename_ODY_PCIERCX_UPCONFIG(a) "PCIERCX_UPCONFIG"
9178 #define busnum_ODY_PCIERCX_UPCONFIG(a) (a)
9179 #define arguments_ODY_PCIERCX_UPCONFIG(a) (a), -1, -1, -1
9180
9181 /**
9182 * Register (PCICONFIGRC) pcierc#_ver_num
9183 *
9184 * PCIe RC Controller IIP Release Version Number Register
9185 */
9186 union ody_pciercx_ver_num {
9187 uint32_t u;
9188 struct ody_pciercx_ver_num_s {
9189 uint32_t vn : 32;
9190 } s;
9191 /* struct ody_pciercx_ver_num_s cn; */
9192 };
9193 typedef union ody_pciercx_ver_num ody_pciercx_ver_num_t;
9194
9195 static inline uint64_t ODY_PCIERCX_VER_NUM(uint64_t a) __attribute__ ((pure, always_inline));
ODY_PCIERCX_VER_NUM(uint64_t a)9196 static inline uint64_t ODY_PCIERCX_VER_NUM(uint64_t a)
9197 {
9198 if (a <= 15)
9199 return 0x8f8;
9200 __ody_csr_fatal("PCIERCX_VER_NUM", 1, a, 0, 0, 0, 0, 0);
9201 }
9202
9203 #define typedef_ODY_PCIERCX_VER_NUM(a) ody_pciercx_ver_num_t
9204 #define bustype_ODY_PCIERCX_VER_NUM(a) CSR_TYPE_PCICONFIGRC
9205 #define basename_ODY_PCIERCX_VER_NUM(a) "PCIERCX_VER_NUM"
9206 #define busnum_ODY_PCIERCX_VER_NUM(a) (a)
9207 #define arguments_ODY_PCIERCX_VER_NUM(a) (a), -1, -1, -1
9208
9209 /**
9210 * Register (PCICONFIGRC) pcierc#_ver_type
9211 *
9212 * PCIe RC Controller IIP Release Version Type Register
9213 */
9214 union ody_pciercx_ver_type {
9215 uint32_t u;
9216 struct ody_pciercx_ver_type_s {
9217 uint32_t vt : 32;
9218 } s;
9219 /* struct ody_pciercx_ver_type_s cn; */
9220 };
9221 typedef union ody_pciercx_ver_type ody_pciercx_ver_type_t;
9222
9223 static inline uint64_t ODY_PCIERCX_VER_TYPE(uint64_t a) __attribute__ ((pure, always_inline));
ODY_PCIERCX_VER_TYPE(uint64_t a)9224 static inline uint64_t ODY_PCIERCX_VER_TYPE(uint64_t a)
9225 {
9226 if (a <= 15)
9227 return 0x8fc;
9228 __ody_csr_fatal("PCIERCX_VER_TYPE", 1, a, 0, 0, 0, 0, 0);
9229 }
9230
9231 #define typedef_ODY_PCIERCX_VER_TYPE(a) ody_pciercx_ver_type_t
9232 #define bustype_ODY_PCIERCX_VER_TYPE(a) CSR_TYPE_PCICONFIGRC
9233 #define basename_ODY_PCIERCX_VER_TYPE(a) "PCIERCX_VER_TYPE"
9234 #define busnum_ODY_PCIERCX_VER_TYPE(a) (a)
9235 #define arguments_ODY_PCIERCX_VER_TYPE(a) (a), -1, -1, -1
9236
9237 /**
9238 * Register (PCICONFIGRC) pcierc#_xmit_arb1
9239 *
9240 * PCIe RC VC Transmit Arbitration Register 1
9241 */
9242 union ody_pciercx_xmit_arb1 {
9243 uint32_t u;
9244 struct ody_pciercx_xmit_arb1_s {
9245 uint32_t wrr_vc0 : 8;
9246 uint32_t wrr_vc1 : 8;
9247 uint32_t wrr_vc2 : 8;
9248 uint32_t wrr_vc3 : 8;
9249 } s;
9250 /* struct ody_pciercx_xmit_arb1_s cn; */
9251 };
9252 typedef union ody_pciercx_xmit_arb1 ody_pciercx_xmit_arb1_t;
9253
9254 static inline uint64_t ODY_PCIERCX_XMIT_ARB1(uint64_t a) __attribute__ ((pure, always_inline));
ODY_PCIERCX_XMIT_ARB1(uint64_t a)9255 static inline uint64_t ODY_PCIERCX_XMIT_ARB1(uint64_t a)
9256 {
9257 if (a <= 15)
9258 return 0x740;
9259 __ody_csr_fatal("PCIERCX_XMIT_ARB1", 1, a, 0, 0, 0, 0, 0);
9260 }
9261
9262 #define typedef_ODY_PCIERCX_XMIT_ARB1(a) ody_pciercx_xmit_arb1_t
9263 #define bustype_ODY_PCIERCX_XMIT_ARB1(a) CSR_TYPE_PCICONFIGRC
9264 #define basename_ODY_PCIERCX_XMIT_ARB1(a) "PCIERCX_XMIT_ARB1"
9265 #define busnum_ODY_PCIERCX_XMIT_ARB1(a) (a)
9266 #define arguments_ODY_PCIERCX_XMIT_ARB1(a) (a), -1, -1, -1
9267
9268 /**
9269 * Register (PCICONFIGRC) pcierc#_xmit_arb2
9270 *
9271 * PCIe RC VC Transmit Arbitration Register 2
9272 */
9273 union ody_pciercx_xmit_arb2 {
9274 uint32_t u;
9275 struct ody_pciercx_xmit_arb2_s {
9276 uint32_t wrr_vc4 : 8;
9277 uint32_t wrr_vc5 : 8;
9278 uint32_t wrr_vc6 : 8;
9279 uint32_t wrr_vc7 : 8;
9280 } s;
9281 /* struct ody_pciercx_xmit_arb2_s cn; */
9282 };
9283 typedef union ody_pciercx_xmit_arb2 ody_pciercx_xmit_arb2_t;
9284
9285 static inline uint64_t ODY_PCIERCX_XMIT_ARB2(uint64_t a) __attribute__ ((pure, always_inline));
ODY_PCIERCX_XMIT_ARB2(uint64_t a)9286 static inline uint64_t ODY_PCIERCX_XMIT_ARB2(uint64_t a)
9287 {
9288 if (a <= 15)
9289 return 0x744;
9290 __ody_csr_fatal("PCIERCX_XMIT_ARB2", 1, a, 0, 0, 0, 0, 0);
9291 }
9292
9293 #define typedef_ODY_PCIERCX_XMIT_ARB2(a) ody_pciercx_xmit_arb2_t
9294 #define bustype_ODY_PCIERCX_XMIT_ARB2(a) CSR_TYPE_PCICONFIGRC
9295 #define basename_ODY_PCIERCX_XMIT_ARB2(a) "PCIERCX_XMIT_ARB2"
9296 #define busnum_ODY_PCIERCX_XMIT_ARB2(a) (a)
9297 #define arguments_ODY_PCIERCX_XMIT_ARB2(a) (a), -1, -1, -1
9298
9299 #endif /* __ODY_CSRS_PCIERC_H__ */
9300