1 #ifndef __ODY_CSRS_SPI_H__
2 #define __ODY_CSRS_SPI_H__
3 /* This file is auto-generated. Do not edit */
4
5 /***********************license start***********************************
6 * Copyright (C) 2021-2026 Marvell.
7 * SPDX-License-Identifier: BSD-3-Clause
8 * https://spdx.org/licenses
9 ***********************license end**************************************/
10
11
12 /**
13 * @file
14 *
15 * Configuration and status register (CSR) address and type definitions for
16 * SPI.
17 *
18 * This file is auto generated. Do not edit.
19 *
20 */
21
22 /**
23 * Enumeration spi_bar_e
24 *
25 * SPI Base Address Register Enumeration
26 * Enumerates the base address registers.
27 */
28 #define ODY_SPI_BAR_E_SPIX_PF_BAR0(a) (0x804000000000ll + 0x1000000000ll * (a))
29 #define ODY_SPI_BAR_E_SPIX_PF_BAR0_SIZE 0x40000000ull
30 #define ODY_SPI_BAR_E_SPIX_PF_BAR4(a) (0x804100000000ll + 0x1000000000ll * (a))
31 #define ODY_SPI_BAR_E_SPIX_PF_BAR4_SIZE 0x100000ull
32
33 /**
34 * Enumeration spi_int_vec_e
35 *
36 * SPI MSI-X Vector Enumeration
37 * Enumerates the MSI-X interrupt vectors.
38 */
39 #define ODY_SPI_INT_VEC_E_SPI_INTR (0)
40
41 /**
42 * Register (NCB) spi#_clk_ctrl
43 *
44 * SPI Clock Control Register
45 */
46 union ody_spix_clk_ctrl {
47 uint64_t u;
48 struct ody_spix_clk_ctrl_s {
49 uint64_t spi_clk_en : 1;
50 uint64_t spi_io_clk_div : 4;
51 uint64_t spi_sclk_force : 1;
52 uint64_t spi_imsc_shadow : 1;
53 uint64_t xspi_supports_xfer : 1;
54 uint64_t reserved_8_63 : 56;
55 } s;
56 /* struct ody_spix_clk_ctrl_s cn; */
57 };
58 typedef union ody_spix_clk_ctrl ody_spix_clk_ctrl_t;
59
60 static inline uint64_t ODY_SPIX_CLK_CTRL(uint64_t a) __attribute__ ((pure, always_inline));
ODY_SPIX_CLK_CTRL(uint64_t a)61 static inline uint64_t ODY_SPIX_CLK_CTRL(uint64_t a)
62 {
63 if (a <= 1)
64 return 0x804000004020ll + 0x1000000000ll * ((a) & 0x1);
65 __ody_csr_fatal("SPIX_CLK_CTRL", 1, a, 0, 0, 0, 0, 0);
66 }
67
68 #define typedef_ODY_SPIX_CLK_CTRL(a) ody_spix_clk_ctrl_t
69 #define bustype_ODY_SPIX_CLK_CTRL(a) CSR_TYPE_NCB
70 #define basename_ODY_SPIX_CLK_CTRL(a) "SPIX_CLK_CTRL"
71 #define device_bar_ODY_SPIX_CLK_CTRL(a) 0x0 /* PF_BAR0 */
72 #define busnum_ODY_SPIX_CLK_CTRL(a) (a)
73 #define arguments_ODY_SPIX_CLK_CTRL(a) (a), -1, -1, -1
74
75 /**
76 * Register (NCB32b) spi#_cmn_seq_regs_direct_access_cfg
77 *
78 * SPI Cmn Seq Regs Direct Access Cfg Register
79 * to hold configuration required only by DIRECT work mode.
80 */
81 union ody_spix_cmn_seq_regs_direct_access_cfg {
82 uint32_t u;
83 struct ody_spix_cmn_seq_regs_direct_access_cfg_s {
84 uint32_t dac_bank_num : 3;
85 uint32_t reserved_3_7 : 5;
86 uint32_t mode_bit_xip_en : 1;
87 uint32_t mode_bit_xip_dis : 1;
88 uint32_t reserved_10_11 : 2;
89 uint32_t rmp_addr_en : 1;
90 uint32_t reserved_13_15 : 3;
91 uint32_t dac_addr_mask : 13;
92 uint32_t reserved_29_31 : 3;
93 } s;
94 /* struct ody_spix_cmn_seq_regs_direct_access_cfg_s cn; */
95 };
96 typedef union ody_spix_cmn_seq_regs_direct_access_cfg ody_spix_cmn_seq_regs_direct_access_cfg_t;
97
98 static inline uint64_t ODY_SPIX_CMN_SEQ_REGS_DIRECT_ACCESS_CFG(uint64_t a) __attribute__ ((pure, always_inline));
ODY_SPIX_CMN_SEQ_REGS_DIRECT_ACCESS_CFG(uint64_t a)99 static inline uint64_t ODY_SPIX_CMN_SEQ_REGS_DIRECT_ACCESS_CFG(uint64_t a)
100 {
101 if (a <= 1)
102 return 0x804000000398ll + 0x1000000000ll * ((a) & 0x1);
103 __ody_csr_fatal("SPIX_CMN_SEQ_REGS_DIRECT_ACCESS_CFG", 1, a, 0, 0, 0, 0, 0);
104 }
105
106 #define typedef_ODY_SPIX_CMN_SEQ_REGS_DIRECT_ACCESS_CFG(a) ody_spix_cmn_seq_regs_direct_access_cfg_t
107 #define bustype_ODY_SPIX_CMN_SEQ_REGS_DIRECT_ACCESS_CFG(a) CSR_TYPE_NCB32b
108 #define basename_ODY_SPIX_CMN_SEQ_REGS_DIRECT_ACCESS_CFG(a) "SPIX_CMN_SEQ_REGS_DIRECT_ACCESS_CFG"
109 #define device_bar_ODY_SPIX_CMN_SEQ_REGS_DIRECT_ACCESS_CFG(a) 0x0 /* PF_BAR0 */
110 #define busnum_ODY_SPIX_CMN_SEQ_REGS_DIRECT_ACCESS_CFG(a) (a)
111 #define arguments_ODY_SPIX_CMN_SEQ_REGS_DIRECT_ACCESS_CFG(a) (a), -1, -1, -1
112
113 /**
114 * Register (NCB32b) spi#_cmn_seq_regs_direct_access_rmp
115 *
116 * SPI Cmn Seq Regs Direct Access Rmp Register
117 * This register allows to the user to define the address offset for DIRECT work mode
118 * for lower part of
119 * input address on slave data interface.
120 */
121 union ody_spix_cmn_seq_regs_direct_access_rmp {
122 uint32_t u;
123 struct ody_spix_cmn_seq_regs_direct_access_rmp_s {
124 uint32_t rmp_addr_val : 32;
125 } s;
126 /* struct ody_spix_cmn_seq_regs_direct_access_rmp_s cn; */
127 };
128 typedef union ody_spix_cmn_seq_regs_direct_access_rmp ody_spix_cmn_seq_regs_direct_access_rmp_t;
129
130 static inline uint64_t ODY_SPIX_CMN_SEQ_REGS_DIRECT_ACCESS_RMP(uint64_t a) __attribute__ ((pure, always_inline));
ODY_SPIX_CMN_SEQ_REGS_DIRECT_ACCESS_RMP(uint64_t a)131 static inline uint64_t ODY_SPIX_CMN_SEQ_REGS_DIRECT_ACCESS_RMP(uint64_t a)
132 {
133 if (a <= 1)
134 return 0x80400000039cll + 0x1000000000ll * ((a) & 0x1);
135 __ody_csr_fatal("SPIX_CMN_SEQ_REGS_DIRECT_ACCESS_RMP", 1, a, 0, 0, 0, 0, 0);
136 }
137
138 #define typedef_ODY_SPIX_CMN_SEQ_REGS_DIRECT_ACCESS_RMP(a) ody_spix_cmn_seq_regs_direct_access_rmp_t
139 #define bustype_ODY_SPIX_CMN_SEQ_REGS_DIRECT_ACCESS_RMP(a) CSR_TYPE_NCB32b
140 #define basename_ODY_SPIX_CMN_SEQ_REGS_DIRECT_ACCESS_RMP(a) "SPIX_CMN_SEQ_REGS_DIRECT_ACCESS_RMP"
141 #define device_bar_ODY_SPIX_CMN_SEQ_REGS_DIRECT_ACCESS_RMP(a) 0x0 /* PF_BAR0 */
142 #define busnum_ODY_SPIX_CMN_SEQ_REGS_DIRECT_ACCESS_RMP(a) (a)
143 #define arguments_ODY_SPIX_CMN_SEQ_REGS_DIRECT_ACCESS_RMP(a) (a), -1, -1, -1
144
145 /**
146 * Register (NCB32b) spi#_cmn_seq_regs_direct_access_rmp_1
147 *
148 * SPI Cmn Seq Regs Direct Access Rmp 1 Register
149 * This register allows to the user to define the address offset for DIRECT work mode
150 * for upper part of
151 * input address on Slave Data Interface.
152 */
153 union ody_spix_cmn_seq_regs_direct_access_rmp_1 {
154 uint32_t u;
155 struct ody_spix_cmn_seq_regs_direct_access_rmp_1_s {
156 uint32_t rmp_addr_val_1 : 32;
157 } s;
158 /* struct ody_spix_cmn_seq_regs_direct_access_rmp_1_s cn; */
159 };
160 typedef union ody_spix_cmn_seq_regs_direct_access_rmp_1 ody_spix_cmn_seq_regs_direct_access_rmp_1_t;
161
162 static inline uint64_t ODY_SPIX_CMN_SEQ_REGS_DIRECT_ACCESS_RMP_1(uint64_t a) __attribute__ ((pure, always_inline));
ODY_SPIX_CMN_SEQ_REGS_DIRECT_ACCESS_RMP_1(uint64_t a)163 static inline uint64_t ODY_SPIX_CMN_SEQ_REGS_DIRECT_ACCESS_RMP_1(uint64_t a)
164 {
165 if (a <= 1)
166 return 0x8040000003a0ll + 0x1000000000ll * ((a) & 0x1);
167 __ody_csr_fatal("SPIX_CMN_SEQ_REGS_DIRECT_ACCESS_RMP_1", 1, a, 0, 0, 0, 0, 0);
168 }
169
170 #define typedef_ODY_SPIX_CMN_SEQ_REGS_DIRECT_ACCESS_RMP_1(a) ody_spix_cmn_seq_regs_direct_access_rmp_1_t
171 #define bustype_ODY_SPIX_CMN_SEQ_REGS_DIRECT_ACCESS_RMP_1(a) CSR_TYPE_NCB32b
172 #define basename_ODY_SPIX_CMN_SEQ_REGS_DIRECT_ACCESS_RMP_1(a) "SPIX_CMN_SEQ_REGS_DIRECT_ACCESS_RMP_1"
173 #define device_bar_ODY_SPIX_CMN_SEQ_REGS_DIRECT_ACCESS_RMP_1(a) 0x0 /* PF_BAR0 */
174 #define busnum_ODY_SPIX_CMN_SEQ_REGS_DIRECT_ACCESS_RMP_1(a) (a)
175 #define arguments_ODY_SPIX_CMN_SEQ_REGS_DIRECT_ACCESS_RMP_1(a) (a), -1, -1, -1
176
177 /**
178 * Register (NCB32b) spi#_cmn_seq_regs_global_seq_cfg
179 *
180 * SPI Cmn Seq Regs Global Seq Cfg Register
181 * to configure common values for sequences in CDMA, PIO and DIRECT work mode.
182 */
183 union ody_spix_cmn_seq_regs_global_seq_cfg {
184 uint32_t u;
185 struct ody_spix_cmn_seq_regs_global_seq_cfg_s {
186 uint32_t seq_page_size_rd : 4;
187 uint32_t seq_page_size_pgm : 4;
188 uint32_t seq_crc_en : 1;
189 uint32_t seq_crc_variant : 1;
190 uint32_t seq_crc_oe : 1;
191 uint32_t reserved_11 : 1;
192 uint32_t seq_crc_chunk_size : 3;
193 uint32_t reserved_15 : 1;
194 uint32_t seq_crc_ual_chunk_en : 1;
195 uint32_t seq_crc_ual_chunk_chk : 1;
196 uint32_t seq_tcms_en : 1;
197 uint32_t reserved_19 : 1;
198 uint32_t seq_data_swap : 1;
199 uint32_t seq_data_per_addr : 1;
200 uint32_t reserved_22 : 1;
201 uint32_t seq_type : 2;
202 uint32_t reserved_25_31 : 7;
203 } s;
204 /* struct ody_spix_cmn_seq_regs_global_seq_cfg_s cn; */
205 };
206 typedef union ody_spix_cmn_seq_regs_global_seq_cfg ody_spix_cmn_seq_regs_global_seq_cfg_t;
207
208 static inline uint64_t ODY_SPIX_CMN_SEQ_REGS_GLOBAL_SEQ_CFG(uint64_t a) __attribute__ ((pure, always_inline));
ODY_SPIX_CMN_SEQ_REGS_GLOBAL_SEQ_CFG(uint64_t a)209 static inline uint64_t ODY_SPIX_CMN_SEQ_REGS_GLOBAL_SEQ_CFG(uint64_t a)
210 {
211 if (a <= 1)
212 return 0x804000000390ll + 0x1000000000ll * ((a) & 0x1);
213 __ody_csr_fatal("SPIX_CMN_SEQ_REGS_GLOBAL_SEQ_CFG", 1, a, 0, 0, 0, 0, 0);
214 }
215
216 #define typedef_ODY_SPIX_CMN_SEQ_REGS_GLOBAL_SEQ_CFG(a) ody_spix_cmn_seq_regs_global_seq_cfg_t
217 #define bustype_ODY_SPIX_CMN_SEQ_REGS_GLOBAL_SEQ_CFG(a) CSR_TYPE_NCB32b
218 #define basename_ODY_SPIX_CMN_SEQ_REGS_GLOBAL_SEQ_CFG(a) "SPIX_CMN_SEQ_REGS_GLOBAL_SEQ_CFG"
219 #define device_bar_ODY_SPIX_CMN_SEQ_REGS_GLOBAL_SEQ_CFG(a) 0x0 /* PF_BAR0 */
220 #define busnum_ODY_SPIX_CMN_SEQ_REGS_GLOBAL_SEQ_CFG(a) (a)
221 #define arguments_ODY_SPIX_CMN_SEQ_REGS_GLOBAL_SEQ_CFG(a) (a), -1, -1, -1
222
223 /**
224 * Register (NCB32b) spi#_cmn_seq_regs_global_seq_cfg_1
225 *
226 * SPI Cmn Seq Regs Global Seq Cfg 1 Register
227 * to configure common values for sequences in CDMA, PIO and DIRECT work mode.
228 */
229 union ody_spix_cmn_seq_regs_global_seq_cfg_1 {
230 uint32_t u;
231 struct ody_spix_cmn_seq_regs_global_seq_cfg_1_s {
232 uint32_t seq_page_size_ext : 9;
233 uint32_t reserved_9_15 : 7;
234 uint32_t seq_page_ca_size : 1;
235 uint32_t reserved_17_23 : 7;
236 uint32_t seq_page_per_block : 3;
237 uint32_t reserved_27 : 1;
238 uint32_t seq_plane_cnt : 2;
239 uint32_t reserved_30_31 : 2;
240 } s;
241 /* struct ody_spix_cmn_seq_regs_global_seq_cfg_1_s cn; */
242 };
243 typedef union ody_spix_cmn_seq_regs_global_seq_cfg_1 ody_spix_cmn_seq_regs_global_seq_cfg_1_t;
244
245 static inline uint64_t ODY_SPIX_CMN_SEQ_REGS_GLOBAL_SEQ_CFG_1(uint64_t a) __attribute__ ((pure, always_inline));
ODY_SPIX_CMN_SEQ_REGS_GLOBAL_SEQ_CFG_1(uint64_t a)246 static inline uint64_t ODY_SPIX_CMN_SEQ_REGS_GLOBAL_SEQ_CFG_1(uint64_t a)
247 {
248 if (a <= 1)
249 return 0x804000000394ll + 0x1000000000ll * ((a) & 0x1);
250 __ody_csr_fatal("SPIX_CMN_SEQ_REGS_GLOBAL_SEQ_CFG_1", 1, a, 0, 0, 0, 0, 0);
251 }
252
253 #define typedef_ODY_SPIX_CMN_SEQ_REGS_GLOBAL_SEQ_CFG_1(a) ody_spix_cmn_seq_regs_global_seq_cfg_1_t
254 #define bustype_ODY_SPIX_CMN_SEQ_REGS_GLOBAL_SEQ_CFG_1(a) CSR_TYPE_NCB32b
255 #define basename_ODY_SPIX_CMN_SEQ_REGS_GLOBAL_SEQ_CFG_1(a) "SPIX_CMN_SEQ_REGS_GLOBAL_SEQ_CFG_1"
256 #define device_bar_ODY_SPIX_CMN_SEQ_REGS_GLOBAL_SEQ_CFG_1(a) 0x0 /* PF_BAR0 */
257 #define busnum_ODY_SPIX_CMN_SEQ_REGS_GLOBAL_SEQ_CFG_1(a) (a)
258 #define arguments_ODY_SPIX_CMN_SEQ_REGS_GLOBAL_SEQ_CFG_1(a) (a), -1, -1, -1
259
260 /**
261 * Register (NCB32b) spi#_cmn_seq_regs_xip_mode_cfg
262 *
263 * SPI Cmn Seq Regs XIP Mode Cfg Register
264 * designated to configure controller in XIP work mode in CDMA, PIO and DIRECT work mode.
265 */
266 union ody_spix_cmn_seq_regs_xip_mode_cfg {
267 uint32_t u;
268 struct ody_spix_cmn_seq_regs_xip_mode_cfg_s {
269 uint32_t xip_en : 8;
270 uint32_t xip_en_mb_val : 8;
271 uint32_t xip_dis_mb_val : 8;
272 uint32_t reserved_24_31 : 8;
273 } s;
274 /* struct ody_spix_cmn_seq_regs_xip_mode_cfg_s cn; */
275 };
276 typedef union ody_spix_cmn_seq_regs_xip_mode_cfg ody_spix_cmn_seq_regs_xip_mode_cfg_t;
277
278 static inline uint64_t ODY_SPIX_CMN_SEQ_REGS_XIP_MODE_CFG(uint64_t a) __attribute__ ((pure, always_inline));
ODY_SPIX_CMN_SEQ_REGS_XIP_MODE_CFG(uint64_t a)279 static inline uint64_t ODY_SPIX_CMN_SEQ_REGS_XIP_MODE_CFG(uint64_t a)
280 {
281 if (a <= 1)
282 return 0x804000000388ll + 0x1000000000ll * ((a) & 0x1);
283 __ody_csr_fatal("SPIX_CMN_SEQ_REGS_XIP_MODE_CFG", 1, a, 0, 0, 0, 0, 0);
284 }
285
286 #define typedef_ODY_SPIX_CMN_SEQ_REGS_XIP_MODE_CFG(a) ody_spix_cmn_seq_regs_xip_mode_cfg_t
287 #define bustype_ODY_SPIX_CMN_SEQ_REGS_XIP_MODE_CFG(a) CSR_TYPE_NCB32b
288 #define basename_ODY_SPIX_CMN_SEQ_REGS_XIP_MODE_CFG(a) "SPIX_CMN_SEQ_REGS_XIP_MODE_CFG"
289 #define device_bar_ODY_SPIX_CMN_SEQ_REGS_XIP_MODE_CFG(a) 0x0 /* PF_BAR0 */
290 #define busnum_ODY_SPIX_CMN_SEQ_REGS_XIP_MODE_CFG(a) (a)
291 #define arguments_ODY_SPIX_CMN_SEQ_REGS_XIP_MODE_CFG(a) (a), -1, -1, -1
292
293 /**
294 * Register (NCB) spi#_const
295 *
296 * SPI Constants Register
297 */
298 union ody_spix_const {
299 uint64_t u;
300 struct ody_spix_const_s {
301 uint64_t reserved_0_63 : 64;
302 } s;
303 /* struct ody_spix_const_s cn; */
304 };
305 typedef union ody_spix_const ody_spix_const_t;
306
307 static inline uint64_t ODY_SPIX_CONST(uint64_t a) __attribute__ ((pure, always_inline));
ODY_SPIX_CONST(uint64_t a)308 static inline uint64_t ODY_SPIX_CONST(uint64_t a)
309 {
310 if (a <= 1)
311 return 0x804000001058ll + 0x1000000000ll * ((a) & 0x1);
312 __ody_csr_fatal("SPIX_CONST", 1, a, 0, 0, 0, 0, 0);
313 }
314
315 #define typedef_ODY_SPIX_CONST(a) ody_spix_const_t
316 #define bustype_ODY_SPIX_CONST(a) CSR_TYPE_NCB
317 #define basename_ODY_SPIX_CONST(a) "SPIX_CONST"
318 #define device_bar_ODY_SPIX_CONST(a) 0x0 /* PF_BAR0 */
319 #define busnum_ODY_SPIX_CONST(a) (a)
320 #define arguments_ODY_SPIX_CONST(a) (a), -1, -1, -1
321
322 /**
323 * Register (NCB32b) spi#_ctrl_cfg_common_ctrl_config
324 *
325 * SPI Control Cfg Common Control Config Register
326 * Device control register.
327 */
328 union ody_spix_ctrl_cfg_common_ctrl_config {
329 uint32_t u;
330 struct ody_spix_ctrl_cfg_common_ctrl_config_s {
331 uint32_t reserved_0_2 : 3;
332 uint32_t cont_on_err : 1;
333 uint32_t reserved_4 : 1;
334 uint32_t work_mode : 2;
335 uint32_t reserved_7_31 : 25;
336 } s;
337 /* struct ody_spix_ctrl_cfg_common_ctrl_config_s cn; */
338 };
339 typedef union ody_spix_ctrl_cfg_common_ctrl_config ody_spix_ctrl_cfg_common_ctrl_config_t;
340
341 static inline uint64_t ODY_SPIX_CTRL_CFG_COMMON_CTRL_CONFIG(uint64_t a) __attribute__ ((pure, always_inline));
ODY_SPIX_CTRL_CFG_COMMON_CTRL_CONFIG(uint64_t a)342 static inline uint64_t ODY_SPIX_CTRL_CFG_COMMON_CTRL_CONFIG(uint64_t a)
343 {
344 if (a <= 1)
345 return 0x804000000230ll + 0x1000000000ll * ((a) & 0x1);
346 __ody_csr_fatal("SPIX_CTRL_CFG_COMMON_CTRL_CONFIG", 1, a, 0, 0, 0, 0, 0);
347 }
348
349 #define typedef_ODY_SPIX_CTRL_CFG_COMMON_CTRL_CONFIG(a) ody_spix_ctrl_cfg_common_ctrl_config_t
350 #define bustype_ODY_SPIX_CTRL_CFG_COMMON_CTRL_CONFIG(a) CSR_TYPE_NCB32b
351 #define basename_ODY_SPIX_CTRL_CFG_COMMON_CTRL_CONFIG(a) "SPIX_CTRL_CFG_COMMON_CTRL_CONFIG"
352 #define device_bar_ODY_SPIX_CTRL_CFG_COMMON_CTRL_CONFIG(a) 0x0 /* PF_BAR0 */
353 #define busnum_ODY_SPIX_CTRL_CFG_COMMON_CTRL_CONFIG(a) (a)
354 #define arguments_ODY_SPIX_CTRL_CFG_COMMON_CTRL_CONFIG(a) (a), -1, -1, -1
355
356 /**
357 * Register (NCB32b) spi#_ctrl_cfg_common_discovery_control
358 *
359 * SPI Control Cfg Common Discovery Control Register
360 * Device discovery control register.
361 */
362 union ody_spix_ctrl_cfg_common_discovery_control {
363 uint32_t u;
364 struct ody_spix_ctrl_cfg_common_discovery_control_s {
365 uint32_t discovery_req : 1;
366 uint32_t discovery_req_type : 1;
367 uint32_t discovery_comp : 1;
368 uint32_t discovery_fail : 2;
369 uint32_t discovery_inhibit : 1;
370 uint32_t discovery_extop_val : 1;
371 uint32_t discovery_extop_en : 1;
372 uint32_t discovery_cmd_type : 2;
373 uint32_t discovery_dummy_cnt : 1;
374 uint32_t discovery_abnum : 1;
375 uint32_t discovery_num_lines : 4;
376 uint32_t discovery_bank : 3;
377 uint32_t reserved_19_31 : 13;
378 } s;
379 /* struct ody_spix_ctrl_cfg_common_discovery_control_s cn; */
380 };
381 typedef union ody_spix_ctrl_cfg_common_discovery_control ody_spix_ctrl_cfg_common_discovery_control_t;
382
383 static inline uint64_t ODY_SPIX_CTRL_CFG_COMMON_DISCOVERY_CONTROL(uint64_t a) __attribute__ ((pure, always_inline));
ODY_SPIX_CTRL_CFG_COMMON_DISCOVERY_CONTROL(uint64_t a)384 static inline uint64_t ODY_SPIX_CTRL_CFG_COMMON_DISCOVERY_CONTROL(uint64_t a)
385 {
386 if (a <= 1)
387 return 0x804000000260ll + 0x1000000000ll * ((a) & 0x1);
388 __ody_csr_fatal("SPIX_CTRL_CFG_COMMON_DISCOVERY_CONTROL", 1, a, 0, 0, 0, 0, 0);
389 }
390
391 #define typedef_ODY_SPIX_CTRL_CFG_COMMON_DISCOVERY_CONTROL(a) ody_spix_ctrl_cfg_common_discovery_control_t
392 #define bustype_ODY_SPIX_CTRL_CFG_COMMON_DISCOVERY_CONTROL(a) CSR_TYPE_NCB32b
393 #define basename_ODY_SPIX_CTRL_CFG_COMMON_DISCOVERY_CONTROL(a) "SPIX_CTRL_CFG_COMMON_DISCOVERY_CONTROL"
394 #define device_bar_ODY_SPIX_CTRL_CFG_COMMON_DISCOVERY_CONTROL(a) 0x0 /* PF_BAR0 */
395 #define busnum_ODY_SPIX_CTRL_CFG_COMMON_DISCOVERY_CONTROL(a) (a)
396 #define arguments_ODY_SPIX_CTRL_CFG_COMMON_DISCOVERY_CONTROL(a) (a), -1, -1, -1
397
398 /**
399 * Register (NCB32b) spi#_ctrl_cfg_common_dma_settings
400 *
401 * SPI Control Cfg Common DMA Settings Register
402 * DMA settings register. It is common register for both master and slave interface.
403 */
404 union ody_spix_ctrl_cfg_common_dma_settings {
405 uint32_t u;
406 struct ody_spix_ctrl_cfg_common_dma_settings_s {
407 uint32_t burst_sel : 8;
408 uint32_t reserved_8_15 : 8;
409 uint32_t ote : 1;
410 uint32_t sdma_err_rsp : 1;
411 uint32_t word_size : 2;
412 uint32_t reserved_20_31 : 12;
413 } s;
414 /* struct ody_spix_ctrl_cfg_common_dma_settings_s cn; */
415 };
416 typedef union ody_spix_ctrl_cfg_common_dma_settings ody_spix_ctrl_cfg_common_dma_settings_t;
417
418 static inline uint64_t ODY_SPIX_CTRL_CFG_COMMON_DMA_SETTINGS(uint64_t a) __attribute__ ((pure, always_inline));
ODY_SPIX_CTRL_CFG_COMMON_DMA_SETTINGS(uint64_t a)419 static inline uint64_t ODY_SPIX_CTRL_CFG_COMMON_DMA_SETTINGS(uint64_t a)
420 {
421 if (a <= 1)
422 return 0x80400000023cll + 0x1000000000ll * ((a) & 0x1);
423 __ody_csr_fatal("SPIX_CTRL_CFG_COMMON_DMA_SETTINGS", 1, a, 0, 0, 0, 0, 0);
424 }
425
426 #define typedef_ODY_SPIX_CTRL_CFG_COMMON_DMA_SETTINGS(a) ody_spix_ctrl_cfg_common_dma_settings_t
427 #define bustype_ODY_SPIX_CTRL_CFG_COMMON_DMA_SETTINGS(a) CSR_TYPE_NCB32b
428 #define basename_ODY_SPIX_CTRL_CFG_COMMON_DMA_SETTINGS(a) "SPIX_CTRL_CFG_COMMON_DMA_SETTINGS"
429 #define device_bar_ODY_SPIX_CTRL_CFG_COMMON_DMA_SETTINGS(a) 0x0 /* PF_BAR0 */
430 #define busnum_ODY_SPIX_CTRL_CFG_COMMON_DMA_SETTINGS(a) (a)
431 #define arguments_ODY_SPIX_CTRL_CFG_COMMON_DMA_SETTINGS(a) (a), -1, -1, -1
432
433 /**
434 * Register (NCB32b) spi#_ctrl_cfg_common_long_polling
435 *
436 * SPI Control Cfg Common Long Polling Register
437 * Wait count value for long polling.
438 */
439 union ody_spix_ctrl_cfg_common_long_polling {
440 uint32_t u;
441 struct ody_spix_ctrl_cfg_common_long_polling_s {
442 uint32_t long_polling : 16;
443 uint32_t reserved_16_31 : 16;
444 } s;
445 /* struct ody_spix_ctrl_cfg_common_long_polling_s cn; */
446 };
447 typedef union ody_spix_ctrl_cfg_common_long_polling ody_spix_ctrl_cfg_common_long_polling_t;
448
449 static inline uint64_t ODY_SPIX_CTRL_CFG_COMMON_LONG_POLLING(uint64_t a) __attribute__ ((pure, always_inline));
ODY_SPIX_CTRL_CFG_COMMON_LONG_POLLING(uint64_t a)450 static inline uint64_t ODY_SPIX_CTRL_CFG_COMMON_LONG_POLLING(uint64_t a)
451 {
452 if (a <= 1)
453 return 0x804000000208ll + 0x1000000000ll * ((a) & 0x1);
454 __ody_csr_fatal("SPIX_CTRL_CFG_COMMON_LONG_POLLING", 1, a, 0, 0, 0, 0, 0);
455 }
456
457 #define typedef_ODY_SPIX_CTRL_CFG_COMMON_LONG_POLLING(a) ody_spix_ctrl_cfg_common_long_polling_t
458 #define bustype_ODY_SPIX_CTRL_CFG_COMMON_LONG_POLLING(a) CSR_TYPE_NCB32b
459 #define basename_ODY_SPIX_CTRL_CFG_COMMON_LONG_POLLING(a) "SPIX_CTRL_CFG_COMMON_LONG_POLLING"
460 #define device_bar_ODY_SPIX_CTRL_CFG_COMMON_LONG_POLLING(a) 0x0 /* PF_BAR0 */
461 #define busnum_ODY_SPIX_CTRL_CFG_COMMON_LONG_POLLING(a) (a)
462 #define arguments_ODY_SPIX_CTRL_CFG_COMMON_LONG_POLLING(a) (a), -1, -1, -1
463
464 /**
465 * Register (NCB32b) spi#_ctrl_cfg_common_sdma_addr0
466 *
467 * SPI Control Cfg Common SDMA Addr0 Register
468 * This register stores the buffer address in the host memory that will be used as a
469 * sink/source for the
470 * SDMA transfer. The SDMA address is based on the Memory Pointer field that was
471 * programed by the host as
472 * part of the CDMA/PIO command. A single CDMA/PIO command can trigger multiple transfers on the slave
473 * interface, so the SDMA address value will be automatically incremented and updated before each SDMA
474 * transfer.
475 */
476 union ody_spix_ctrl_cfg_common_sdma_addr0 {
477 uint32_t u;
478 struct ody_spix_ctrl_cfg_common_sdma_addr0_s {
479 uint32_t sdma_addr_l : 32;
480 } s;
481 /* struct ody_spix_ctrl_cfg_common_sdma_addr0_s cn; */
482 };
483 typedef union ody_spix_ctrl_cfg_common_sdma_addr0 ody_spix_ctrl_cfg_common_sdma_addr0_t;
484
485 static inline uint64_t ODY_SPIX_CTRL_CFG_COMMON_SDMA_ADDR0(uint64_t a) __attribute__ ((pure, always_inline));
ODY_SPIX_CTRL_CFG_COMMON_SDMA_ADDR0(uint64_t a)486 static inline uint64_t ODY_SPIX_CTRL_CFG_COMMON_SDMA_ADDR0(uint64_t a)
487 {
488 if (a <= 1)
489 return 0x80400000024cll + 0x1000000000ll * ((a) & 0x1);
490 __ody_csr_fatal("SPIX_CTRL_CFG_COMMON_SDMA_ADDR0", 1, a, 0, 0, 0, 0, 0);
491 }
492
493 #define typedef_ODY_SPIX_CTRL_CFG_COMMON_SDMA_ADDR0(a) ody_spix_ctrl_cfg_common_sdma_addr0_t
494 #define bustype_ODY_SPIX_CTRL_CFG_COMMON_SDMA_ADDR0(a) CSR_TYPE_NCB32b
495 #define basename_ODY_SPIX_CTRL_CFG_COMMON_SDMA_ADDR0(a) "SPIX_CTRL_CFG_COMMON_SDMA_ADDR0"
496 #define device_bar_ODY_SPIX_CTRL_CFG_COMMON_SDMA_ADDR0(a) 0x0 /* PF_BAR0 */
497 #define busnum_ODY_SPIX_CTRL_CFG_COMMON_SDMA_ADDR0(a) (a)
498 #define arguments_ODY_SPIX_CTRL_CFG_COMMON_SDMA_ADDR0(a) (a), -1, -1, -1
499
500 /**
501 * Register (NCB32b) spi#_ctrl_cfg_common_sdma_addr1
502 *
503 * SPI Control Cfg Common SDMA Addr1 Register
504 * This register stores the buffer address in the host memory that will be used as a
505 * sink/source for the
506 * SDMA transfer. The SDMA address is based on the Memory Pointer field that was
507 * programed by the host as
508 * part of the CDMA/PIO command. A single CDMA/PIO command can trigger multiple transfers on the slave
509 * interface, so the SDMA address value will be automatically incremented and updated before each SDMA
510 * transfer.
511 */
512 union ody_spix_ctrl_cfg_common_sdma_addr1 {
513 uint32_t u;
514 struct ody_spix_ctrl_cfg_common_sdma_addr1_s {
515 uint32_t sdma_addr_h : 32;
516 } s;
517 /* struct ody_spix_ctrl_cfg_common_sdma_addr1_s cn; */
518 };
519 typedef union ody_spix_ctrl_cfg_common_sdma_addr1 ody_spix_ctrl_cfg_common_sdma_addr1_t;
520
521 static inline uint64_t ODY_SPIX_CTRL_CFG_COMMON_SDMA_ADDR1(uint64_t a) __attribute__ ((pure, always_inline));
ODY_SPIX_CTRL_CFG_COMMON_SDMA_ADDR1(uint64_t a)522 static inline uint64_t ODY_SPIX_CTRL_CFG_COMMON_SDMA_ADDR1(uint64_t a)
523 {
524 if (a <= 1)
525 return 0x804000000250ll + 0x1000000000ll * ((a) & 0x1);
526 __ody_csr_fatal("SPIX_CTRL_CFG_COMMON_SDMA_ADDR1", 1, a, 0, 0, 0, 0, 0);
527 }
528
529 #define typedef_ODY_SPIX_CTRL_CFG_COMMON_SDMA_ADDR1(a) ody_spix_ctrl_cfg_common_sdma_addr1_t
530 #define bustype_ODY_SPIX_CTRL_CFG_COMMON_SDMA_ADDR1(a) CSR_TYPE_NCB32b
531 #define basename_ODY_SPIX_CTRL_CFG_COMMON_SDMA_ADDR1(a) "SPIX_CTRL_CFG_COMMON_SDMA_ADDR1"
532 #define device_bar_ODY_SPIX_CTRL_CFG_COMMON_SDMA_ADDR1(a) 0x0 /* PF_BAR0 */
533 #define busnum_ODY_SPIX_CTRL_CFG_COMMON_SDMA_ADDR1(a) (a)
534 #define arguments_ODY_SPIX_CTRL_CFG_COMMON_SDMA_ADDR1(a) (a), -1, -1, -1
535
536 /**
537 * Register (NCB32b) spi#_ctrl_cfg_common_sdma_size
538 *
539 * SPI Control Cfg Common SDMA Size Register
540 * Transferred data block size for the slave DMA module.
541 */
542 union ody_spix_ctrl_cfg_common_sdma_size {
543 uint32_t u;
544 struct ody_spix_ctrl_cfg_common_sdma_size_s {
545 uint32_t sdma_size : 32;
546 } s;
547 /* struct ody_spix_ctrl_cfg_common_sdma_size_s cn; */
548 };
549 typedef union ody_spix_ctrl_cfg_common_sdma_size ody_spix_ctrl_cfg_common_sdma_size_t;
550
551 static inline uint64_t ODY_SPIX_CTRL_CFG_COMMON_SDMA_SIZE(uint64_t a) __attribute__ ((pure, always_inline));
ODY_SPIX_CTRL_CFG_COMMON_SDMA_SIZE(uint64_t a)552 static inline uint64_t ODY_SPIX_CTRL_CFG_COMMON_SDMA_SIZE(uint64_t a)
553 {
554 if (a <= 1)
555 return 0x804000000240ll + 0x1000000000ll * ((a) & 0x1);
556 __ody_csr_fatal("SPIX_CTRL_CFG_COMMON_SDMA_SIZE", 1, a, 0, 0, 0, 0, 0);
557 }
558
559 #define typedef_ODY_SPIX_CTRL_CFG_COMMON_SDMA_SIZE(a) ody_spix_ctrl_cfg_common_sdma_size_t
560 #define bustype_ODY_SPIX_CTRL_CFG_COMMON_SDMA_SIZE(a) CSR_TYPE_NCB32b
561 #define basename_ODY_SPIX_CTRL_CFG_COMMON_SDMA_SIZE(a) "SPIX_CTRL_CFG_COMMON_SDMA_SIZE"
562 #define device_bar_ODY_SPIX_CTRL_CFG_COMMON_SDMA_SIZE(a) 0x0 /* PF_BAR0 */
563 #define busnum_ODY_SPIX_CTRL_CFG_COMMON_SDMA_SIZE(a) (a)
564 #define arguments_ODY_SPIX_CTRL_CFG_COMMON_SDMA_SIZE(a) (a), -1, -1, -1
565
566 /**
567 * Register (NCB32b) spi#_ctrl_cfg_common_sdma_trd_info
568 *
569 * SPI Control Cfg Common SDMA Thread Info Register
570 * Information for current slave DMA transaction related with execution thread.
571 */
572 union ody_spix_ctrl_cfg_common_sdma_trd_info {
573 uint32_t u;
574 struct ody_spix_ctrl_cfg_common_sdma_trd_info_s {
575 uint32_t sdma_trd : 3;
576 uint32_t reserved_3_7 : 5;
577 uint32_t sdma_dir : 1;
578 uint32_t reserved_9_31 : 23;
579 } s;
580 /* struct ody_spix_ctrl_cfg_common_sdma_trd_info_s cn; */
581 };
582 typedef union ody_spix_ctrl_cfg_common_sdma_trd_info ody_spix_ctrl_cfg_common_sdma_trd_info_t;
583
584 static inline uint64_t ODY_SPIX_CTRL_CFG_COMMON_SDMA_TRD_INFO(uint64_t a) __attribute__ ((pure, always_inline));
ODY_SPIX_CTRL_CFG_COMMON_SDMA_TRD_INFO(uint64_t a)585 static inline uint64_t ODY_SPIX_CTRL_CFG_COMMON_SDMA_TRD_INFO(uint64_t a)
586 {
587 if (a <= 1)
588 return 0x804000000244ll + 0x1000000000ll * ((a) & 0x1);
589 __ody_csr_fatal("SPIX_CTRL_CFG_COMMON_SDMA_TRD_INFO", 1, a, 0, 0, 0, 0, 0);
590 }
591
592 #define typedef_ODY_SPIX_CTRL_CFG_COMMON_SDMA_TRD_INFO(a) ody_spix_ctrl_cfg_common_sdma_trd_info_t
593 #define bustype_ODY_SPIX_CTRL_CFG_COMMON_SDMA_TRD_INFO(a) CSR_TYPE_NCB32b
594 #define basename_ODY_SPIX_CTRL_CFG_COMMON_SDMA_TRD_INFO(a) "SPIX_CTRL_CFG_COMMON_SDMA_TRD_INFO"
595 #define device_bar_ODY_SPIX_CTRL_CFG_COMMON_SDMA_TRD_INFO(a) 0x0 /* PF_BAR0 */
596 #define busnum_ODY_SPIX_CTRL_CFG_COMMON_SDMA_TRD_INFO(a) (a)
597 #define arguments_ODY_SPIX_CTRL_CFG_COMMON_SDMA_TRD_INFO(a) (a), -1, -1, -1
598
599 /**
600 * Register (NCB32b) spi#_ctrl_cfg_common_short_polling
601 *
602 * SPI Control Cfg Common Short Polling Register
603 * Status monitor cycle count value.
604 */
605 union ody_spix_ctrl_cfg_common_short_polling {
606 uint32_t u;
607 struct ody_spix_ctrl_cfg_common_short_polling_s {
608 uint32_t short_polling : 16;
609 uint32_t reserved_16_31 : 16;
610 } s;
611 /* struct ody_spix_ctrl_cfg_common_short_polling_s cn; */
612 };
613 typedef union ody_spix_ctrl_cfg_common_short_polling ody_spix_ctrl_cfg_common_short_polling_t;
614
615 static inline uint64_t ODY_SPIX_CTRL_CFG_COMMON_SHORT_POLLING(uint64_t a) __attribute__ ((pure, always_inline));
ODY_SPIX_CTRL_CFG_COMMON_SHORT_POLLING(uint64_t a)616 static inline uint64_t ODY_SPIX_CTRL_CFG_COMMON_SHORT_POLLING(uint64_t a)
617 {
618 if (a <= 1)
619 return 0x80400000020cll + 0x1000000000ll * ((a) & 0x1);
620 __ody_csr_fatal("SPIX_CTRL_CFG_COMMON_SHORT_POLLING", 1, a, 0, 0, 0, 0, 0);
621 }
622
623 #define typedef_ODY_SPIX_CTRL_CFG_COMMON_SHORT_POLLING(a) ody_spix_ctrl_cfg_common_short_polling_t
624 #define bustype_ODY_SPIX_CTRL_CFG_COMMON_SHORT_POLLING(a) CSR_TYPE_NCB32b
625 #define basename_ODY_SPIX_CTRL_CFG_COMMON_SHORT_POLLING(a) "SPIX_CTRL_CFG_COMMON_SHORT_POLLING"
626 #define device_bar_ODY_SPIX_CTRL_CFG_COMMON_SHORT_POLLING(a) 0x0 /* PF_BAR0 */
627 #define busnum_ODY_SPIX_CTRL_CFG_COMMON_SHORT_POLLING(a) (a)
628 #define arguments_ODY_SPIX_CTRL_CFG_COMMON_SHORT_POLLING(a) (a), -1, -1, -1
629
630 /**
631 * Register (NCB32b) spi#_ctrl_cmd_stat_boot_status
632 *
633 * SPI Control Command Stat Boot Status Register
634 * This register provides status of the latest boot operation.
635 */
636 union ody_spix_ctrl_cmd_stat_boot_status {
637 uint32_t u;
638 struct ody_spix_ctrl_cmd_stat_boot_status_s {
639 uint32_t boot_dqs_err : 1;
640 uint32_t boot_crc_err : 1;
641 uint32_t boot_bus_err : 1;
642 uint32_t reserved_3_31 : 29;
643 } s;
644 /* struct ody_spix_ctrl_cmd_stat_boot_status_s cn; */
645 };
646 typedef union ody_spix_ctrl_cmd_stat_boot_status ody_spix_ctrl_cmd_stat_boot_status_t;
647
648 static inline uint64_t ODY_SPIX_CTRL_CMD_STAT_BOOT_STATUS(uint64_t a) __attribute__ ((pure, always_inline));
ODY_SPIX_CTRL_CMD_STAT_BOOT_STATUS(uint64_t a)649 static inline uint64_t ODY_SPIX_CTRL_CMD_STAT_BOOT_STATUS(uint64_t a)
650 {
651 if (a <= 1)
652 return 0x804000000158ll + 0x1000000000ll * ((a) & 0x1);
653 __ody_csr_fatal("SPIX_CTRL_CMD_STAT_BOOT_STATUS", 1, a, 0, 0, 0, 0, 0);
654 }
655
656 #define typedef_ODY_SPIX_CTRL_CMD_STAT_BOOT_STATUS(a) ody_spix_ctrl_cmd_stat_boot_status_t
657 #define bustype_ODY_SPIX_CTRL_CMD_STAT_BOOT_STATUS(a) CSR_TYPE_NCB32b
658 #define basename_ODY_SPIX_CTRL_CMD_STAT_BOOT_STATUS(a) "SPIX_CTRL_CMD_STAT_BOOT_STATUS"
659 #define device_bar_ODY_SPIX_CTRL_CMD_STAT_BOOT_STATUS(a) 0x0 /* PF_BAR0 */
660 #define busnum_ODY_SPIX_CTRL_CMD_STAT_BOOT_STATUS(a) (a)
661 #define arguments_ODY_SPIX_CTRL_CMD_STAT_BOOT_STATUS(a) (a), -1, -1, -1
662
663 /**
664 * Register (NCB32b) spi#_ctrl_cmd_stat_cmd_reg0
665 *
666 * SPI Control Command Stat Command Register 0
667 * Command register 0. Writing data to this register will initiate a new transaction of the xSPI Flash
668 * Controller in CDMA/PIO and STIG work mode. Fields encoding of those registers
669 * depends on selected work
670 * mode.
671 */
672 union ody_spix_ctrl_cmd_stat_cmd_reg0 {
673 uint32_t u;
674 struct ody_spix_ctrl_cmd_stat_cmd_reg0_s {
675 uint32_t cmd0 : 32;
676 } s;
677 /* struct ody_spix_ctrl_cmd_stat_cmd_reg0_s cn; */
678 };
679 typedef union ody_spix_ctrl_cmd_stat_cmd_reg0 ody_spix_ctrl_cmd_stat_cmd_reg0_t;
680
681 static inline uint64_t ODY_SPIX_CTRL_CMD_STAT_CMD_REG0(uint64_t a) __attribute__ ((pure, always_inline));
ODY_SPIX_CTRL_CMD_STAT_CMD_REG0(uint64_t a)682 static inline uint64_t ODY_SPIX_CTRL_CMD_STAT_CMD_REG0(uint64_t a)
683 {
684 if (a <= 1)
685 return 0x804000000000ll + 0x1000000000ll * ((a) & 0x1);
686 __ody_csr_fatal("SPIX_CTRL_CMD_STAT_CMD_REG0", 1, a, 0, 0, 0, 0, 0);
687 }
688
689 #define typedef_ODY_SPIX_CTRL_CMD_STAT_CMD_REG0(a) ody_spix_ctrl_cmd_stat_cmd_reg0_t
690 #define bustype_ODY_SPIX_CTRL_CMD_STAT_CMD_REG0(a) CSR_TYPE_NCB32b
691 #define basename_ODY_SPIX_CTRL_CMD_STAT_CMD_REG0(a) "SPIX_CTRL_CMD_STAT_CMD_REG0"
692 #define device_bar_ODY_SPIX_CTRL_CMD_STAT_CMD_REG0(a) 0x0 /* PF_BAR0 */
693 #define busnum_ODY_SPIX_CTRL_CMD_STAT_CMD_REG0(a) (a)
694 #define arguments_ODY_SPIX_CTRL_CMD_STAT_CMD_REG0(a) (a), -1, -1, -1
695
696 /**
697 * Register (NCB32b) spi#_ctrl_cmd_stat_cmd_reg1
698 *
699 * SPI Control Command Stat Command Register 1
700 * Command register 1.
701 */
702 union ody_spix_ctrl_cmd_stat_cmd_reg1 {
703 uint32_t u;
704 struct ody_spix_ctrl_cmd_stat_cmd_reg1_s {
705 uint32_t cmd1 : 32;
706 } s;
707 /* struct ody_spix_ctrl_cmd_stat_cmd_reg1_s cn; */
708 };
709 typedef union ody_spix_ctrl_cmd_stat_cmd_reg1 ody_spix_ctrl_cmd_stat_cmd_reg1_t;
710
711 static inline uint64_t ODY_SPIX_CTRL_CMD_STAT_CMD_REG1(uint64_t a) __attribute__ ((pure, always_inline));
ODY_SPIX_CTRL_CMD_STAT_CMD_REG1(uint64_t a)712 static inline uint64_t ODY_SPIX_CTRL_CMD_STAT_CMD_REG1(uint64_t a)
713 {
714 if (a <= 1)
715 return 0x804000000004ll + 0x1000000000ll * ((a) & 0x1);
716 __ody_csr_fatal("SPIX_CTRL_CMD_STAT_CMD_REG1", 1, a, 0, 0, 0, 0, 0);
717 }
718
719 #define typedef_ODY_SPIX_CTRL_CMD_STAT_CMD_REG1(a) ody_spix_ctrl_cmd_stat_cmd_reg1_t
720 #define bustype_ODY_SPIX_CTRL_CMD_STAT_CMD_REG1(a) CSR_TYPE_NCB32b
721 #define basename_ODY_SPIX_CTRL_CMD_STAT_CMD_REG1(a) "SPIX_CTRL_CMD_STAT_CMD_REG1"
722 #define device_bar_ODY_SPIX_CTRL_CMD_STAT_CMD_REG1(a) 0x0 /* PF_BAR0 */
723 #define busnum_ODY_SPIX_CTRL_CMD_STAT_CMD_REG1(a) (a)
724 #define arguments_ODY_SPIX_CTRL_CMD_STAT_CMD_REG1(a) (a), -1, -1, -1
725
726 /**
727 * Register (NCB32b) spi#_ctrl_cmd_stat_cmd_reg2
728 *
729 * SPI Control Command Stat Command Register 2
730 * Command register 2.
731 */
732 union ody_spix_ctrl_cmd_stat_cmd_reg2 {
733 uint32_t u;
734 struct ody_spix_ctrl_cmd_stat_cmd_reg2_s {
735 uint32_t cmd2 : 32;
736 } s;
737 /* struct ody_spix_ctrl_cmd_stat_cmd_reg2_s cn; */
738 };
739 typedef union ody_spix_ctrl_cmd_stat_cmd_reg2 ody_spix_ctrl_cmd_stat_cmd_reg2_t;
740
741 static inline uint64_t ODY_SPIX_CTRL_CMD_STAT_CMD_REG2(uint64_t a) __attribute__ ((pure, always_inline));
ODY_SPIX_CTRL_CMD_STAT_CMD_REG2(uint64_t a)742 static inline uint64_t ODY_SPIX_CTRL_CMD_STAT_CMD_REG2(uint64_t a)
743 {
744 if (a <= 1)
745 return 0x804000000008ll + 0x1000000000ll * ((a) & 0x1);
746 __ody_csr_fatal("SPIX_CTRL_CMD_STAT_CMD_REG2", 1, a, 0, 0, 0, 0, 0);
747 }
748
749 #define typedef_ODY_SPIX_CTRL_CMD_STAT_CMD_REG2(a) ody_spix_ctrl_cmd_stat_cmd_reg2_t
750 #define bustype_ODY_SPIX_CTRL_CMD_STAT_CMD_REG2(a) CSR_TYPE_NCB32b
751 #define basename_ODY_SPIX_CTRL_CMD_STAT_CMD_REG2(a) "SPIX_CTRL_CMD_STAT_CMD_REG2"
752 #define device_bar_ODY_SPIX_CTRL_CMD_STAT_CMD_REG2(a) 0x0 /* PF_BAR0 */
753 #define busnum_ODY_SPIX_CTRL_CMD_STAT_CMD_REG2(a) (a)
754 #define arguments_ODY_SPIX_CTRL_CMD_STAT_CMD_REG2(a) (a), -1, -1, -1
755
756 /**
757 * Register (NCB32b) spi#_ctrl_cmd_stat_cmd_reg3
758 *
759 * SPI Control Command Stat Command Register 3
760 * Command register 3.
761 */
762 union ody_spix_ctrl_cmd_stat_cmd_reg3 {
763 uint32_t u;
764 struct ody_spix_ctrl_cmd_stat_cmd_reg3_s {
765 uint32_t cmd3 : 32;
766 } s;
767 /* struct ody_spix_ctrl_cmd_stat_cmd_reg3_s cn; */
768 };
769 typedef union ody_spix_ctrl_cmd_stat_cmd_reg3 ody_spix_ctrl_cmd_stat_cmd_reg3_t;
770
771 static inline uint64_t ODY_SPIX_CTRL_CMD_STAT_CMD_REG3(uint64_t a) __attribute__ ((pure, always_inline));
ODY_SPIX_CTRL_CMD_STAT_CMD_REG3(uint64_t a)772 static inline uint64_t ODY_SPIX_CTRL_CMD_STAT_CMD_REG3(uint64_t a)
773 {
774 if (a <= 1)
775 return 0x80400000000cll + 0x1000000000ll * ((a) & 0x1);
776 __ody_csr_fatal("SPIX_CTRL_CMD_STAT_CMD_REG3", 1, a, 0, 0, 0, 0, 0);
777 }
778
779 #define typedef_ODY_SPIX_CTRL_CMD_STAT_CMD_REG3(a) ody_spix_ctrl_cmd_stat_cmd_reg3_t
780 #define bustype_ODY_SPIX_CTRL_CMD_STAT_CMD_REG3(a) CSR_TYPE_NCB32b
781 #define basename_ODY_SPIX_CTRL_CMD_STAT_CMD_REG3(a) "SPIX_CTRL_CMD_STAT_CMD_REG3"
782 #define device_bar_ODY_SPIX_CTRL_CMD_STAT_CMD_REG3(a) 0x0 /* PF_BAR0 */
783 #define busnum_ODY_SPIX_CTRL_CMD_STAT_CMD_REG3(a) (a)
784 #define arguments_ODY_SPIX_CTRL_CMD_STAT_CMD_REG3(a) (a), -1, -1, -1
785
786 /**
787 * Register (NCB32b) spi#_ctrl_cmd_stat_cmd_reg4
788 *
789 * SPI Control Command Stat Command Register 4
790 * Command register 4.
791 */
792 union ody_spix_ctrl_cmd_stat_cmd_reg4 {
793 uint32_t u;
794 struct ody_spix_ctrl_cmd_stat_cmd_reg4_s {
795 uint32_t cmd4 : 32;
796 } s;
797 /* struct ody_spix_ctrl_cmd_stat_cmd_reg4_s cn; */
798 };
799 typedef union ody_spix_ctrl_cmd_stat_cmd_reg4 ody_spix_ctrl_cmd_stat_cmd_reg4_t;
800
801 static inline uint64_t ODY_SPIX_CTRL_CMD_STAT_CMD_REG4(uint64_t a) __attribute__ ((pure, always_inline));
ODY_SPIX_CTRL_CMD_STAT_CMD_REG4(uint64_t a)802 static inline uint64_t ODY_SPIX_CTRL_CMD_STAT_CMD_REG4(uint64_t a)
803 {
804 if (a <= 1)
805 return 0x804000000010ll + 0x1000000000ll * ((a) & 0x1);
806 __ody_csr_fatal("SPIX_CTRL_CMD_STAT_CMD_REG4", 1, a, 0, 0, 0, 0, 0);
807 }
808
809 #define typedef_ODY_SPIX_CTRL_CMD_STAT_CMD_REG4(a) ody_spix_ctrl_cmd_stat_cmd_reg4_t
810 #define bustype_ODY_SPIX_CTRL_CMD_STAT_CMD_REG4(a) CSR_TYPE_NCB32b
811 #define basename_ODY_SPIX_CTRL_CMD_STAT_CMD_REG4(a) "SPIX_CTRL_CMD_STAT_CMD_REG4"
812 #define device_bar_ODY_SPIX_CTRL_CMD_STAT_CMD_REG4(a) 0x0 /* PF_BAR0 */
813 #define busnum_ODY_SPIX_CTRL_CMD_STAT_CMD_REG4(a) (a)
814 #define arguments_ODY_SPIX_CTRL_CMD_STAT_CMD_REG4(a) (a), -1, -1, -1
815
816 /**
817 * Register (NCB32b) spi#_ctrl_cmd_stat_cmd_reg5
818 *
819 * SPI Control Command Stat Command Register 5
820 * Command register 5.
821 */
822 union ody_spix_ctrl_cmd_stat_cmd_reg5 {
823 uint32_t u;
824 struct ody_spix_ctrl_cmd_stat_cmd_reg5_s {
825 uint32_t cmd5 : 32;
826 } s;
827 /* struct ody_spix_ctrl_cmd_stat_cmd_reg5_s cn; */
828 };
829 typedef union ody_spix_ctrl_cmd_stat_cmd_reg5 ody_spix_ctrl_cmd_stat_cmd_reg5_t;
830
831 static inline uint64_t ODY_SPIX_CTRL_CMD_STAT_CMD_REG5(uint64_t a) __attribute__ ((pure, always_inline));
ODY_SPIX_CTRL_CMD_STAT_CMD_REG5(uint64_t a)832 static inline uint64_t ODY_SPIX_CTRL_CMD_STAT_CMD_REG5(uint64_t a)
833 {
834 if (a <= 1)
835 return 0x804000000014ll + 0x1000000000ll * ((a) & 0x1);
836 __ody_csr_fatal("SPIX_CTRL_CMD_STAT_CMD_REG5", 1, a, 0, 0, 0, 0, 0);
837 }
838
839 #define typedef_ODY_SPIX_CTRL_CMD_STAT_CMD_REG5(a) ody_spix_ctrl_cmd_stat_cmd_reg5_t
840 #define bustype_ODY_SPIX_CTRL_CMD_STAT_CMD_REG5(a) CSR_TYPE_NCB32b
841 #define basename_ODY_SPIX_CTRL_CMD_STAT_CMD_REG5(a) "SPIX_CTRL_CMD_STAT_CMD_REG5"
842 #define device_bar_ODY_SPIX_CTRL_CMD_STAT_CMD_REG5(a) 0x0 /* PF_BAR0 */
843 #define busnum_ODY_SPIX_CTRL_CMD_STAT_CMD_REG5(a) (a)
844 #define arguments_ODY_SPIX_CTRL_CMD_STAT_CMD_REG5(a) (a), -1, -1, -1
845
846 /**
847 * Register (NCB32b) spi#_ctrl_cmd_stat_cmd_status
848 *
849 * SPI Control Command Stat Command Status Register
850 * Command status register for selected thread in ACMD work mode and for STIG work mode
851 * when xSPI flash
852 * transaction is completed.
853 */
854 union ody_spix_ctrl_cmd_stat_cmd_status {
855 uint32_t u;
856 struct ody_spix_ctrl_cmd_stat_cmd_status_s {
857 uint32_t cmd_status : 32;
858 } s;
859 /* struct ody_spix_ctrl_cmd_stat_cmd_status_s cn; */
860 };
861 typedef union ody_spix_ctrl_cmd_stat_cmd_status ody_spix_ctrl_cmd_stat_cmd_status_t;
862
863 static inline uint64_t ODY_SPIX_CTRL_CMD_STAT_CMD_STATUS(uint64_t a) __attribute__ ((pure, always_inline));
ODY_SPIX_CTRL_CMD_STAT_CMD_STATUS(uint64_t a)864 static inline uint64_t ODY_SPIX_CTRL_CMD_STAT_CMD_STATUS(uint64_t a)
865 {
866 if (a <= 1)
867 return 0x804000000044ll + 0x1000000000ll * ((a) & 0x1);
868 __ody_csr_fatal("SPIX_CTRL_CMD_STAT_CMD_STATUS", 1, a, 0, 0, 0, 0, 0);
869 }
870
871 #define typedef_ODY_SPIX_CTRL_CMD_STAT_CMD_STATUS(a) ody_spix_ctrl_cmd_stat_cmd_status_t
872 #define bustype_ODY_SPIX_CTRL_CMD_STAT_CMD_STATUS(a) CSR_TYPE_NCB32b
873 #define basename_ODY_SPIX_CTRL_CMD_STAT_CMD_STATUS(a) "SPIX_CTRL_CMD_STAT_CMD_STATUS"
874 #define device_bar_ODY_SPIX_CTRL_CMD_STAT_CMD_STATUS(a) 0x0 /* PF_BAR0 */
875 #define busnum_ODY_SPIX_CTRL_CMD_STAT_CMD_STATUS(a) (a)
876 #define arguments_ODY_SPIX_CTRL_CMD_STAT_CMD_STATUS(a) (a), -1, -1, -1
877
878 /**
879 * Register (NCB32b) spi#_ctrl_cmd_stat_cmd_status_ptr
880 *
881 * SPI Control Command Stat Command Status Ptr Register
882 * Pointer register to select which thread status will be selected for ACMD work mode
883 * (not applicable for
884 * STIG and DIRECT work modes).
885 */
886 union ody_spix_ctrl_cmd_stat_cmd_status_ptr {
887 uint32_t u;
888 struct ody_spix_ctrl_cmd_stat_cmd_status_ptr_s {
889 uint32_t thrd_status_sel : 3;
890 uint32_t reserved_3_31 : 29;
891 } s;
892 /* struct ody_spix_ctrl_cmd_stat_cmd_status_ptr_s cn; */
893 };
894 typedef union ody_spix_ctrl_cmd_stat_cmd_status_ptr ody_spix_ctrl_cmd_stat_cmd_status_ptr_t;
895
896 static inline uint64_t ODY_SPIX_CTRL_CMD_STAT_CMD_STATUS_PTR(uint64_t a) __attribute__ ((pure, always_inline));
ODY_SPIX_CTRL_CMD_STAT_CMD_STATUS_PTR(uint64_t a)897 static inline uint64_t ODY_SPIX_CTRL_CMD_STAT_CMD_STATUS_PTR(uint64_t a)
898 {
899 if (a <= 1)
900 return 0x804000000040ll + 0x1000000000ll * ((a) & 0x1);
901 __ody_csr_fatal("SPIX_CTRL_CMD_STAT_CMD_STATUS_PTR", 1, a, 0, 0, 0, 0, 0);
902 }
903
904 #define typedef_ODY_SPIX_CTRL_CMD_STAT_CMD_STATUS_PTR(a) ody_spix_ctrl_cmd_stat_cmd_status_ptr_t
905 #define bustype_ODY_SPIX_CTRL_CMD_STAT_CMD_STATUS_PTR(a) CSR_TYPE_NCB32b
906 #define basename_ODY_SPIX_CTRL_CMD_STAT_CMD_STATUS_PTR(a) "SPIX_CTRL_CMD_STAT_CMD_STATUS_PTR"
907 #define device_bar_ODY_SPIX_CTRL_CMD_STAT_CMD_STATUS_PTR(a) 0x0 /* PF_BAR0 */
908 #define busnum_ODY_SPIX_CTRL_CMD_STAT_CMD_STATUS_PTR(a) (a)
909 #define arguments_ODY_SPIX_CTRL_CMD_STAT_CMD_STATUS_PTR(a) (a), -1, -1, -1
910
911 /**
912 * Register (NCB32b) spi#_ctrl_cmd_stat_ctrl_status
913 *
914 * SPI Control Command Stat Control Status Register
915 * Controller internal state.
916 */
917 union ody_spix_ctrl_cmd_stat_ctrl_status {
918 uint32_t u;
919 struct ody_spix_ctrl_cmd_stat_ctrl_status_s {
920 uint32_t sdma_busy : 1;
921 uint32_t mdma_busy : 1;
922 uint32_t acmd_eng_busy : 1;
923 uint32_t gcmd_eng_busy : 1;
924 uint32_t gcmd_eng_mc_busy : 1;
925 uint32_t reserved_5 : 1;
926 uint32_t discovery_busy : 1;
927 uint32_t ctrl_busy : 1;
928 uint32_t init_fail : 2;
929 uint32_t reserved_10_15 : 6;
930 uint32_t init_comp : 1;
931 uint32_t reserved_17_31 : 15;
932 } s;
933 /* struct ody_spix_ctrl_cmd_stat_ctrl_status_s cn; */
934 };
935 typedef union ody_spix_ctrl_cmd_stat_ctrl_status ody_spix_ctrl_cmd_stat_ctrl_status_t;
936
937 static inline uint64_t ODY_SPIX_CTRL_CMD_STAT_CTRL_STATUS(uint64_t a) __attribute__ ((pure, always_inline));
ODY_SPIX_CTRL_CMD_STAT_CTRL_STATUS(uint64_t a)938 static inline uint64_t ODY_SPIX_CTRL_CMD_STAT_CTRL_STATUS(uint64_t a)
939 {
940 if (a <= 1)
941 return 0x804000000100ll + 0x1000000000ll * ((a) & 0x1);
942 __ody_csr_fatal("SPIX_CTRL_CMD_STAT_CTRL_STATUS", 1, a, 0, 0, 0, 0, 0);
943 }
944
945 #define typedef_ODY_SPIX_CTRL_CMD_STAT_CTRL_STATUS(a) ody_spix_ctrl_cmd_stat_ctrl_status_t
946 #define bustype_ODY_SPIX_CTRL_CMD_STAT_CTRL_STATUS(a) CSR_TYPE_NCB32b
947 #define basename_ODY_SPIX_CTRL_CMD_STAT_CTRL_STATUS(a) "SPIX_CTRL_CMD_STAT_CTRL_STATUS"
948 #define device_bar_ODY_SPIX_CTRL_CMD_STAT_CTRL_STATUS(a) 0x0 /* PF_BAR0 */
949 #define busnum_ODY_SPIX_CTRL_CMD_STAT_CTRL_STATUS(a) (a)
950 #define arguments_ODY_SPIX_CTRL_CMD_STAT_CTRL_STATUS(a) (a), -1, -1, -1
951
952 /**
953 * Register (NCB32b) spi#_ctrl_cmd_stat_dma_target_error_h
954 *
955 * SPI Control Command Stat DMA Target Error H Register
956 * Master data interface error address [63:32]. This register store address of request on the system
957 * master data interface that caused setting [CDMA_TERR] or [DDMA_TERR] in
958 * SPI()_CTRL_CMD_STAT_INTR_STATUS.
959 * Address can be overwritten if error response is detected for the following command sequences.
960 */
961 union ody_spix_ctrl_cmd_stat_dma_target_error_h {
962 uint32_t u;
963 struct ody_spix_ctrl_cmd_stat_dma_target_error_h_s {
964 uint32_t target_err_h : 32;
965 } s;
966 /* struct ody_spix_ctrl_cmd_stat_dma_target_error_h_s cn; */
967 };
968 typedef union ody_spix_ctrl_cmd_stat_dma_target_error_h ody_spix_ctrl_cmd_stat_dma_target_error_h_t;
969
970 static inline uint64_t ODY_SPIX_CTRL_CMD_STAT_DMA_TARGET_ERROR_H(uint64_t a) __attribute__ ((pure, always_inline));
ODY_SPIX_CTRL_CMD_STAT_DMA_TARGET_ERROR_H(uint64_t a)971 static inline uint64_t ODY_SPIX_CTRL_CMD_STAT_DMA_TARGET_ERROR_H(uint64_t a)
972 {
973 if (a <= 1)
974 return 0x804000000154ll + 0x1000000000ll * ((a) & 0x1);
975 __ody_csr_fatal("SPIX_CTRL_CMD_STAT_DMA_TARGET_ERROR_H", 1, a, 0, 0, 0, 0, 0);
976 }
977
978 #define typedef_ODY_SPIX_CTRL_CMD_STAT_DMA_TARGET_ERROR_H(a) ody_spix_ctrl_cmd_stat_dma_target_error_h_t
979 #define bustype_ODY_SPIX_CTRL_CMD_STAT_DMA_TARGET_ERROR_H(a) CSR_TYPE_NCB32b
980 #define basename_ODY_SPIX_CTRL_CMD_STAT_DMA_TARGET_ERROR_H(a) "SPIX_CTRL_CMD_STAT_DMA_TARGET_ERROR_H"
981 #define device_bar_ODY_SPIX_CTRL_CMD_STAT_DMA_TARGET_ERROR_H(a) 0x0 /* PF_BAR0 */
982 #define busnum_ODY_SPIX_CTRL_CMD_STAT_DMA_TARGET_ERROR_H(a) (a)
983 #define arguments_ODY_SPIX_CTRL_CMD_STAT_DMA_TARGET_ERROR_H(a) (a), -1, -1, -1
984
985 /**
986 * Register (NCB32b) spi#_ctrl_cmd_stat_dma_target_error_l
987 *
988 * SPI Control Command Stat DMA Target Error L Register
989 * Master data interface error address [31:0]. This register store address of request on the system
990 * master data interface that caused setting [CDMA_TERR] or [DDMA_TERR] in
991 * SPI()_CTRL_CMD_STAT_INTR_STATUS.
992 * Address can be overwritten if an error response is detected for the following command sequences.
993 */
994 union ody_spix_ctrl_cmd_stat_dma_target_error_l {
995 uint32_t u;
996 struct ody_spix_ctrl_cmd_stat_dma_target_error_l_s {
997 uint32_t target_err_l : 32;
998 } s;
999 /* struct ody_spix_ctrl_cmd_stat_dma_target_error_l_s cn; */
1000 };
1001 typedef union ody_spix_ctrl_cmd_stat_dma_target_error_l ody_spix_ctrl_cmd_stat_dma_target_error_l_t;
1002
1003 static inline uint64_t ODY_SPIX_CTRL_CMD_STAT_DMA_TARGET_ERROR_L(uint64_t a) __attribute__ ((pure, always_inline));
ODY_SPIX_CTRL_CMD_STAT_DMA_TARGET_ERROR_L(uint64_t a)1004 static inline uint64_t ODY_SPIX_CTRL_CMD_STAT_DMA_TARGET_ERROR_L(uint64_t a)
1005 {
1006 if (a <= 1)
1007 return 0x804000000150ll + 0x1000000000ll * ((a) & 0x1);
1008 __ody_csr_fatal("SPIX_CTRL_CMD_STAT_DMA_TARGET_ERROR_L", 1, a, 0, 0, 0, 0, 0);
1009 }
1010
1011 #define typedef_ODY_SPIX_CTRL_CMD_STAT_DMA_TARGET_ERROR_L(a) ody_spix_ctrl_cmd_stat_dma_target_error_l_t
1012 #define bustype_ODY_SPIX_CTRL_CMD_STAT_DMA_TARGET_ERROR_L(a) CSR_TYPE_NCB32b
1013 #define basename_ODY_SPIX_CTRL_CMD_STAT_DMA_TARGET_ERROR_L(a) "SPIX_CTRL_CMD_STAT_DMA_TARGET_ERROR_L"
1014 #define device_bar_ODY_SPIX_CTRL_CMD_STAT_DMA_TARGET_ERROR_L(a) 0x0 /* PF_BAR0 */
1015 #define busnum_ODY_SPIX_CTRL_CMD_STAT_DMA_TARGET_ERROR_L(a) (a)
1016 #define arguments_ODY_SPIX_CTRL_CMD_STAT_DMA_TARGET_ERROR_L(a) (a), -1, -1, -1
1017
1018 /**
1019 * Register (NCB32b) spi#_ctrl_cmd_stat_intr_enable
1020 *
1021 * SPI Control Command Stat Interrupt Enable Register
1022 * Interrupt enable register. If selected bit of this register is set, rising edge of
1023 * the corresponding
1024 * bit in SPI(()_CTRL_CMD_STAT_INTR_STATUS will generate setting of external interrupt line.
1025 */
1026 union ody_spix_ctrl_cmd_stat_intr_enable {
1027 uint32_t u;
1028 struct ody_spix_ctrl_cmd_stat_intr_enable_s {
1029 uint32_t reserved_0_11 : 12;
1030 uint32_t gp_open_drain_0_en : 1;
1031 uint32_t gp_open_drain_1_en : 1;
1032 uint32_t gp_open_drain_2_en : 1;
1033 uint32_t gp_open_drain_3_en : 1;
1034 uint32_t ctrl_idle_en : 1;
1035 uint32_t cdma_terr_en : 1;
1036 uint32_t ddma_terr_en : 1;
1037 uint32_t reserved_19 : 1;
1038 uint32_t cmd_ignored_en : 1;
1039 uint32_t sdma_trigg_en : 1;
1040 uint32_t sdma_err_en : 1;
1041 uint32_t stig_done_en : 1;
1042 uint32_t dir_crc_err_en : 1;
1043 uint32_t dir_dqs_err_en : 1;
1044 uint32_t dir_cmd_err_en : 1;
1045 uint32_t dir_ecc_corr_err_en : 1;
1046 uint32_t dir_dev_err_en : 1;
1047 uint32_t reserved_29_30 : 2;
1048 uint32_t intr_en : 1;
1049 } s;
1050 /* struct ody_spix_ctrl_cmd_stat_intr_enable_s cn; */
1051 };
1052 typedef union ody_spix_ctrl_cmd_stat_intr_enable ody_spix_ctrl_cmd_stat_intr_enable_t;
1053
1054 static inline uint64_t ODY_SPIX_CTRL_CMD_STAT_INTR_ENABLE(uint64_t a) __attribute__ ((pure, always_inline));
ODY_SPIX_CTRL_CMD_STAT_INTR_ENABLE(uint64_t a)1055 static inline uint64_t ODY_SPIX_CTRL_CMD_STAT_INTR_ENABLE(uint64_t a)
1056 {
1057 if (a <= 1)
1058 return 0x804000000114ll + 0x1000000000ll * ((a) & 0x1);
1059 __ody_csr_fatal("SPIX_CTRL_CMD_STAT_INTR_ENABLE", 1, a, 0, 0, 0, 0, 0);
1060 }
1061
1062 #define typedef_ODY_SPIX_CTRL_CMD_STAT_INTR_ENABLE(a) ody_spix_ctrl_cmd_stat_intr_enable_t
1063 #define bustype_ODY_SPIX_CTRL_CMD_STAT_INTR_ENABLE(a) CSR_TYPE_NCB32b
1064 #define basename_ODY_SPIX_CTRL_CMD_STAT_INTR_ENABLE(a) "SPIX_CTRL_CMD_STAT_INTR_ENABLE"
1065 #define device_bar_ODY_SPIX_CTRL_CMD_STAT_INTR_ENABLE(a) 0x0 /* PF_BAR0 */
1066 #define busnum_ODY_SPIX_CTRL_CMD_STAT_INTR_ENABLE(a) (a)
1067 #define arguments_ODY_SPIX_CTRL_CMD_STAT_INTR_ENABLE(a) (a), -1, -1, -1
1068
1069 /**
1070 * Register (NCB32b) spi#_ctrl_cmd_stat_intr_status
1071 *
1072 * SPI Control Command Stat Interrupt Status Register
1073 * Controller status register.
1074 */
1075 union ody_spix_ctrl_cmd_stat_intr_status {
1076 uint32_t u;
1077 struct ody_spix_ctrl_cmd_stat_intr_status_s {
1078 uint32_t reserved_0_11 : 12;
1079 uint32_t gp_open_drain_0 : 1;
1080 uint32_t gp_open_drain_1 : 1;
1081 uint32_t gp_open_drain_2 : 1;
1082 uint32_t gp_open_drain_3 : 1;
1083 uint32_t ctrl_idle : 1;
1084 uint32_t cdma_terr : 1;
1085 uint32_t ddma_terr : 1;
1086 uint32_t reserved_19 : 1;
1087 uint32_t cmd_ignored : 1;
1088 uint32_t sdma_trigg : 1;
1089 uint32_t sdma_err : 1;
1090 uint32_t stig_done : 1;
1091 uint32_t dir_crc_err : 1;
1092 uint32_t dir_dqs_err : 1;
1093 uint32_t dir_cmd_err : 1;
1094 uint32_t dir_ecc_corr_err : 1;
1095 uint32_t dir_dev_err : 1;
1096 uint32_t reserved_29_31 : 3;
1097 } s;
1098 /* struct ody_spix_ctrl_cmd_stat_intr_status_s cn; */
1099 };
1100 typedef union ody_spix_ctrl_cmd_stat_intr_status ody_spix_ctrl_cmd_stat_intr_status_t;
1101
1102 static inline uint64_t ODY_SPIX_CTRL_CMD_STAT_INTR_STATUS(uint64_t a) __attribute__ ((pure, always_inline));
ODY_SPIX_CTRL_CMD_STAT_INTR_STATUS(uint64_t a)1103 static inline uint64_t ODY_SPIX_CTRL_CMD_STAT_INTR_STATUS(uint64_t a)
1104 {
1105 if (a <= 1)
1106 return 0x804000000110ll + 0x1000000000ll * ((a) & 0x1);
1107 __ody_csr_fatal("SPIX_CTRL_CMD_STAT_INTR_STATUS", 1, a, 0, 0, 0, 0, 0);
1108 }
1109
1110 #define typedef_ODY_SPIX_CTRL_CMD_STAT_INTR_STATUS(a) ody_spix_ctrl_cmd_stat_intr_status_t
1111 #define bustype_ODY_SPIX_CTRL_CMD_STAT_INTR_STATUS(a) CSR_TYPE_NCB32b
1112 #define basename_ODY_SPIX_CTRL_CMD_STAT_INTR_STATUS(a) "SPIX_CTRL_CMD_STAT_INTR_STATUS"
1113 #define device_bar_ODY_SPIX_CTRL_CMD_STAT_INTR_STATUS(a) 0x0 /* PF_BAR0 */
1114 #define busnum_ODY_SPIX_CTRL_CMD_STAT_INTR_STATUS(a) (a)
1115 #define arguments_ODY_SPIX_CTRL_CMD_STAT_INTR_STATUS(a) (a), -1, -1, -1
1116
1117 /**
1118 * Register (NCB32b) spi#_ctrl_cmd_stat_trd_comp_intr_status
1119 *
1120 * SPI Control Command Stat Thread Comp Interrupt Status Register
1121 * Each bit of this field correspond to the auto command engine thread. Each bit
1122 * informs about descriptor
1123 * status for selected thread. It is set only when INT bit of the descriptor is set.
1124 */
1125 union ody_spix_ctrl_cmd_stat_trd_comp_intr_status {
1126 uint32_t u;
1127 struct ody_spix_ctrl_cmd_stat_trd_comp_intr_status_s {
1128 uint32_t trd0_comp : 1;
1129 uint32_t trd1_comp : 1;
1130 uint32_t trd2_comp : 1;
1131 uint32_t trd3_comp : 1;
1132 uint32_t trd4_comp : 1;
1133 uint32_t trd5_comp : 1;
1134 uint32_t trd6_comp : 1;
1135 uint32_t trd7_comp : 1;
1136 uint32_t reserved_8_31 : 24;
1137 } s;
1138 /* struct ody_spix_ctrl_cmd_stat_trd_comp_intr_status_s cn; */
1139 };
1140 typedef union ody_spix_ctrl_cmd_stat_trd_comp_intr_status ody_spix_ctrl_cmd_stat_trd_comp_intr_status_t;
1141
1142 static inline uint64_t ODY_SPIX_CTRL_CMD_STAT_TRD_COMP_INTR_STATUS(uint64_t a) __attribute__ ((pure, always_inline));
ODY_SPIX_CTRL_CMD_STAT_TRD_COMP_INTR_STATUS(uint64_t a)1143 static inline uint64_t ODY_SPIX_CTRL_CMD_STAT_TRD_COMP_INTR_STATUS(uint64_t a)
1144 {
1145 if (a <= 1)
1146 return 0x804000000120ll + 0x1000000000ll * ((a) & 0x1);
1147 __ody_csr_fatal("SPIX_CTRL_CMD_STAT_TRD_COMP_INTR_STATUS", 1, a, 0, 0, 0, 0, 0);
1148 }
1149
1150 #define typedef_ODY_SPIX_CTRL_CMD_STAT_TRD_COMP_INTR_STATUS(a) ody_spix_ctrl_cmd_stat_trd_comp_intr_status_t
1151 #define bustype_ODY_SPIX_CTRL_CMD_STAT_TRD_COMP_INTR_STATUS(a) CSR_TYPE_NCB32b
1152 #define basename_ODY_SPIX_CTRL_CMD_STAT_TRD_COMP_INTR_STATUS(a) "SPIX_CTRL_CMD_STAT_TRD_COMP_INTR_STATUS"
1153 #define device_bar_ODY_SPIX_CTRL_CMD_STAT_TRD_COMP_INTR_STATUS(a) 0x0 /* PF_BAR0 */
1154 #define busnum_ODY_SPIX_CTRL_CMD_STAT_TRD_COMP_INTR_STATUS(a) (a)
1155 #define arguments_ODY_SPIX_CTRL_CMD_STAT_TRD_COMP_INTR_STATUS(a) (a), -1, -1, -1
1156
1157 /**
1158 * Register (NCB32b) spi#_ctrl_cmd_stat_trd_error_intr_en
1159 *
1160 * SPI Control Command Stat Thread Error Interrupt En Register
1161 * Interrupt enable register. If the selected bit of this register is set, the rising edge of
1162 * corresponding bit
1163 * in SPI()_CTRL_CMD_STAT_TRD_ERROR_INTR_STATUS will cause setting of the external interrupt line.
1164 */
1165 union ody_spix_ctrl_cmd_stat_trd_error_intr_en {
1166 uint32_t u;
1167 struct ody_spix_ctrl_cmd_stat_trd_error_intr_en_s {
1168 uint32_t trd_error_intr_en : 8;
1169 uint32_t reserved_8_31 : 24;
1170 } s;
1171 /* struct ody_spix_ctrl_cmd_stat_trd_error_intr_en_s cn; */
1172 };
1173 typedef union ody_spix_ctrl_cmd_stat_trd_error_intr_en ody_spix_ctrl_cmd_stat_trd_error_intr_en_t;
1174
1175 static inline uint64_t ODY_SPIX_CTRL_CMD_STAT_TRD_ERROR_INTR_EN(uint64_t a) __attribute__ ((pure, always_inline));
ODY_SPIX_CTRL_CMD_STAT_TRD_ERROR_INTR_EN(uint64_t a)1176 static inline uint64_t ODY_SPIX_CTRL_CMD_STAT_TRD_ERROR_INTR_EN(uint64_t a)
1177 {
1178 if (a <= 1)
1179 return 0x804000000134ll + 0x1000000000ll * ((a) & 0x1);
1180 __ody_csr_fatal("SPIX_CTRL_CMD_STAT_TRD_ERROR_INTR_EN", 1, a, 0, 0, 0, 0, 0);
1181 }
1182
1183 #define typedef_ODY_SPIX_CTRL_CMD_STAT_TRD_ERROR_INTR_EN(a) ody_spix_ctrl_cmd_stat_trd_error_intr_en_t
1184 #define bustype_ODY_SPIX_CTRL_CMD_STAT_TRD_ERROR_INTR_EN(a) CSR_TYPE_NCB32b
1185 #define basename_ODY_SPIX_CTRL_CMD_STAT_TRD_ERROR_INTR_EN(a) "SPIX_CTRL_CMD_STAT_TRD_ERROR_INTR_EN"
1186 #define device_bar_ODY_SPIX_CTRL_CMD_STAT_TRD_ERROR_INTR_EN(a) 0x0 /* PF_BAR0 */
1187 #define busnum_ODY_SPIX_CTRL_CMD_STAT_TRD_ERROR_INTR_EN(a) (a)
1188 #define arguments_ODY_SPIX_CTRL_CMD_STAT_TRD_ERROR_INTR_EN(a) (a), -1, -1, -1
1189
1190 /**
1191 * Register (NCB32b) spi#_ctrl_cmd_stat_trd_error_intr_status
1192 *
1193 * SPI Control Command Stat Thread Error Interrupt Status Register
1194 * Thread error indicates that the auto command engine thread detected an error condition. To get more
1195 * information on the error, software must read the status field of the descriptor or
1196 * appropriate status
1197 * register depending on the current work mode.
1198 */
1199 union ody_spix_ctrl_cmd_stat_trd_error_intr_status {
1200 uint32_t u;
1201 struct ody_spix_ctrl_cmd_stat_trd_error_intr_status_s {
1202 uint32_t trd0_error_stat : 1;
1203 uint32_t trd1_error_stat : 1;
1204 uint32_t trd2_error_stat : 1;
1205 uint32_t trd3_error_stat : 1;
1206 uint32_t trd4_error_stat : 1;
1207 uint32_t trd5_error_stat : 1;
1208 uint32_t trd6_error_stat : 1;
1209 uint32_t trd7_error_stat : 1;
1210 uint32_t reserved_8_31 : 24;
1211 } s;
1212 /* struct ody_spix_ctrl_cmd_stat_trd_error_intr_status_s cn; */
1213 };
1214 typedef union ody_spix_ctrl_cmd_stat_trd_error_intr_status ody_spix_ctrl_cmd_stat_trd_error_intr_status_t;
1215
1216 static inline uint64_t ODY_SPIX_CTRL_CMD_STAT_TRD_ERROR_INTR_STATUS(uint64_t a) __attribute__ ((pure, always_inline));
ODY_SPIX_CTRL_CMD_STAT_TRD_ERROR_INTR_STATUS(uint64_t a)1217 static inline uint64_t ODY_SPIX_CTRL_CMD_STAT_TRD_ERROR_INTR_STATUS(uint64_t a)
1218 {
1219 if (a <= 1)
1220 return 0x804000000130ll + 0x1000000000ll * ((a) & 0x1);
1221 __ody_csr_fatal("SPIX_CTRL_CMD_STAT_TRD_ERROR_INTR_STATUS", 1, a, 0, 0, 0, 0, 0);
1222 }
1223
1224 #define typedef_ODY_SPIX_CTRL_CMD_STAT_TRD_ERROR_INTR_STATUS(a) ody_spix_ctrl_cmd_stat_trd_error_intr_status_t
1225 #define bustype_ODY_SPIX_CTRL_CMD_STAT_TRD_ERROR_INTR_STATUS(a) CSR_TYPE_NCB32b
1226 #define basename_ODY_SPIX_CTRL_CMD_STAT_TRD_ERROR_INTR_STATUS(a) "SPIX_CTRL_CMD_STAT_TRD_ERROR_INTR_STATUS"
1227 #define device_bar_ODY_SPIX_CTRL_CMD_STAT_TRD_ERROR_INTR_STATUS(a) 0x0 /* PF_BAR0 */
1228 #define busnum_ODY_SPIX_CTRL_CMD_STAT_TRD_ERROR_INTR_STATUS(a) (a)
1229 #define arguments_ODY_SPIX_CTRL_CMD_STAT_TRD_ERROR_INTR_STATUS(a) (a), -1, -1, -1
1230
1231 /**
1232 * Register (NCB32b) spi#_ctrl_cmd_stat_trd_status
1233 *
1234 * SPI Control Command Stat Thread Status Register
1235 * Auto command engine threads state.
1236 */
1237 union ody_spix_ctrl_cmd_stat_trd_status {
1238 uint32_t u;
1239 struct ody_spix_ctrl_cmd_stat_trd_status_s {
1240 uint32_t trd_busy : 8;
1241 uint32_t reserved_8_31 : 24;
1242 } s;
1243 /* struct ody_spix_ctrl_cmd_stat_trd_status_s cn; */
1244 };
1245 typedef union ody_spix_ctrl_cmd_stat_trd_status ody_spix_ctrl_cmd_stat_trd_status_t;
1246
1247 static inline uint64_t ODY_SPIX_CTRL_CMD_STAT_TRD_STATUS(uint64_t a) __attribute__ ((pure, always_inline));
ODY_SPIX_CTRL_CMD_STAT_TRD_STATUS(uint64_t a)1248 static inline uint64_t ODY_SPIX_CTRL_CMD_STAT_TRD_STATUS(uint64_t a)
1249 {
1250 if (a <= 1)
1251 return 0x804000000104ll + 0x1000000000ll * ((a) & 0x1);
1252 __ody_csr_fatal("SPIX_CTRL_CMD_STAT_TRD_STATUS", 1, a, 0, 0, 0, 0, 0);
1253 }
1254
1255 #define typedef_ODY_SPIX_CTRL_CMD_STAT_TRD_STATUS(a) ody_spix_ctrl_cmd_stat_trd_status_t
1256 #define bustype_ODY_SPIX_CTRL_CMD_STAT_TRD_STATUS(a) CSR_TYPE_NCB32b
1257 #define basename_ODY_SPIX_CTRL_CMD_STAT_TRD_STATUS(a) "SPIX_CTRL_CMD_STAT_TRD_STATUS"
1258 #define device_bar_ODY_SPIX_CTRL_CMD_STAT_TRD_STATUS(a) 0x0 /* PF_BAR0 */
1259 #define busnum_ODY_SPIX_CTRL_CMD_STAT_TRD_STATUS(a) (a)
1260 #define arguments_ODY_SPIX_CTRL_CMD_STAT_TRD_STATUS(a) (a), -1, -1, -1
1261
1262 /**
1263 * Register (NCB32b) spi#_ctrl_consts_ctrl_features_reg
1264 *
1265 * SPI Control Consts Control Features Register
1266 * Shows available hardware features of the controller.
1267 */
1268 union ody_spix_ctrl_consts_ctrl_features_reg {
1269 uint32_t u;
1270 struct ody_spix_ctrl_consts_ctrl_features_reg_s {
1271 uint32_t n_threads : 4;
1272 uint32_t reserved_4_11 : 8;
1273 uint32_t asf_available : 1;
1274 uint32_t reserved_13_15 : 3;
1275 uint32_t boot_available : 1;
1276 uint32_t reserved_17 : 1;
1277 uint32_t dma_intf : 2;
1278 uint32_t dma_addr_width : 1;
1279 uint32_t dma_data_width : 1;
1280 uint32_t sfr_intf : 2;
1281 uint32_t n_banks : 2;
1282 uint32_t reserved_26_31 : 6;
1283 } s;
1284 /* struct ody_spix_ctrl_consts_ctrl_features_reg_s cn; */
1285 };
1286 typedef union ody_spix_ctrl_consts_ctrl_features_reg ody_spix_ctrl_consts_ctrl_features_reg_t;
1287
1288 static inline uint64_t ODY_SPIX_CTRL_CONSTS_CTRL_FEATURES_REG(uint64_t a) __attribute__ ((pure, always_inline));
ODY_SPIX_CTRL_CONSTS_CTRL_FEATURES_REG(uint64_t a)1289 static inline uint64_t ODY_SPIX_CTRL_CONSTS_CTRL_FEATURES_REG(uint64_t a)
1290 {
1291 if (a <= 1)
1292 return 0x804000000f04ll + 0x1000000000ll * ((a) & 0x1);
1293 __ody_csr_fatal("SPIX_CTRL_CONSTS_CTRL_FEATURES_REG", 1, a, 0, 0, 0, 0, 0);
1294 }
1295
1296 #define typedef_ODY_SPIX_CTRL_CONSTS_CTRL_FEATURES_REG(a) ody_spix_ctrl_consts_ctrl_features_reg_t
1297 #define bustype_ODY_SPIX_CTRL_CONSTS_CTRL_FEATURES_REG(a) CSR_TYPE_NCB32b
1298 #define basename_ODY_SPIX_CTRL_CONSTS_CTRL_FEATURES_REG(a) "SPIX_CTRL_CONSTS_CTRL_FEATURES_REG"
1299 #define device_bar_ODY_SPIX_CTRL_CONSTS_CTRL_FEATURES_REG(a) 0x0 /* PF_BAR0 */
1300 #define busnum_ODY_SPIX_CTRL_CONSTS_CTRL_FEATURES_REG(a) (a)
1301 #define arguments_ODY_SPIX_CTRL_CONSTS_CTRL_FEATURES_REG(a) (a), -1, -1, -1
1302
1303 /**
1304 * Register (NCB32b) spi#_ctrl_consts_spi_ctrl_version
1305 *
1306 * SPI Control Consts xSPI Control Version Register
1307 * contains release identification number.
1308 */
1309 union ody_spix_ctrl_consts_spi_ctrl_version {
1310 uint32_t u;
1311 struct ody_spix_ctrl_consts_spi_ctrl_version_s {
1312 uint32_t spi_ctrl_rev : 8;
1313 uint32_t spi_ctrl_fix : 8;
1314 uint32_t spi_ctrl_magic_number : 16;
1315 } s;
1316 /* struct ody_spix_ctrl_consts_spi_ctrl_version_s cn; */
1317 };
1318 typedef union ody_spix_ctrl_consts_spi_ctrl_version ody_spix_ctrl_consts_spi_ctrl_version_t;
1319
1320 static inline uint64_t ODY_SPIX_CTRL_CONSTS_SPI_CTRL_VERSION(uint64_t a) __attribute__ ((pure, always_inline));
ODY_SPIX_CTRL_CONSTS_SPI_CTRL_VERSION(uint64_t a)1321 static inline uint64_t ODY_SPIX_CTRL_CONSTS_SPI_CTRL_VERSION(uint64_t a)
1322 {
1323 if (a <= 1)
1324 return 0x804000000f00ll + 0x1000000000ll * ((a) & 0x1);
1325 __ody_csr_fatal("SPIX_CTRL_CONSTS_SPI_CTRL_VERSION", 1, a, 0, 0, 0, 0, 0);
1326 }
1327
1328 #define typedef_ODY_SPIX_CTRL_CONSTS_SPI_CTRL_VERSION(a) ody_spix_ctrl_consts_spi_ctrl_version_t
1329 #define bustype_ODY_SPIX_CTRL_CONSTS_SPI_CTRL_VERSION(a) CSR_TYPE_NCB32b
1330 #define basename_ODY_SPIX_CTRL_CONSTS_SPI_CTRL_VERSION(a) "SPIX_CTRL_CONSTS_SPI_CTRL_VERSION"
1331 #define device_bar_ODY_SPIX_CTRL_CONSTS_SPI_CTRL_VERSION(a) 0x0 /* PF_BAR0 */
1332 #define busnum_ODY_SPIX_CTRL_CONSTS_SPI_CTRL_VERSION(a) (a)
1333 #define arguments_ODY_SPIX_CTRL_CONSTS_SPI_CTRL_VERSION(a) (a), -1, -1, -1
1334
1335 /**
1336 * Register (NCB32b) spi#_dev_seq_regs_ers_seq_cfg_0
1337 *
1338 * SPI Dev Seq Regs Ers Seq Cfg 0 Register
1339 * to configure ERASE_SECTOR sequence for PROFILE 1 and SPI NAND in ACMD work mode.
1340 */
1341 union ody_spix_dev_seq_regs_ers_seq_cfg_0 {
1342 uint32_t u;
1343 struct ody_spix_dev_seq_regs_ers_seq_cfg_0_s {
1344 uint32_t erss_seq_p1_cmd_val : 8;
1345 uint32_t erss_seq_p1_cmd_ios : 2;
1346 uint32_t reserved_10 : 1;
1347 uint32_t erss_seq_p1_cmd_edge : 1;
1348 uint32_t erss_seq_p1_addr_cnt : 3;
1349 uint32_t erss_seq_p1_cmd_ext_en : 1;
1350 uint32_t erss_seq_p1_cmd_ext_val : 8;
1351 uint32_t erss_seq_p1_addr_ios : 2;
1352 uint32_t reserved_26_27 : 2;
1353 uint32_t erss_seq_p1_addr_edge : 1;
1354 uint32_t reserved_29_31 : 3;
1355 } s;
1356 /* struct ody_spix_dev_seq_regs_ers_seq_cfg_0_s cn; */
1357 };
1358 typedef union ody_spix_dev_seq_regs_ers_seq_cfg_0 ody_spix_dev_seq_regs_ers_seq_cfg_0_t;
1359
1360 static inline uint64_t ODY_SPIX_DEV_SEQ_REGS_ERS_SEQ_CFG_0(uint64_t a) __attribute__ ((pure, always_inline));
ODY_SPIX_DEV_SEQ_REGS_ERS_SEQ_CFG_0(uint64_t a)1361 static inline uint64_t ODY_SPIX_DEV_SEQ_REGS_ERS_SEQ_CFG_0(uint64_t a)
1362 {
1363 if (a <= 1)
1364 return 0x804000000410ll + 0x1000000000ll * ((a) & 0x1);
1365 __ody_csr_fatal("SPIX_DEV_SEQ_REGS_ERS_SEQ_CFG_0", 1, a, 0, 0, 0, 0, 0);
1366 }
1367
1368 #define typedef_ODY_SPIX_DEV_SEQ_REGS_ERS_SEQ_CFG_0(a) ody_spix_dev_seq_regs_ers_seq_cfg_0_t
1369 #define bustype_ODY_SPIX_DEV_SEQ_REGS_ERS_SEQ_CFG_0(a) CSR_TYPE_NCB32b
1370 #define basename_ODY_SPIX_DEV_SEQ_REGS_ERS_SEQ_CFG_0(a) "SPIX_DEV_SEQ_REGS_ERS_SEQ_CFG_0"
1371 #define device_bar_ODY_SPIX_DEV_SEQ_REGS_ERS_SEQ_CFG_0(a) 0x0 /* PF_BAR0 */
1372 #define busnum_ODY_SPIX_DEV_SEQ_REGS_ERS_SEQ_CFG_0(a) (a)
1373 #define arguments_ODY_SPIX_DEV_SEQ_REGS_ERS_SEQ_CFG_0(a) (a), -1, -1, -1
1374
1375 /**
1376 * Register (NCB32b) spi#_dev_seq_regs_ers_seq_cfg_1
1377 *
1378 * SPI Dev Seq Regs Ers Seq Cfg 1 Register
1379 * to configure ERASE_SECTOR sequence for PROFILE 1 and SPI NAND in ACMD work mode.
1380 */
1381 union ody_spix_dev_seq_regs_ers_seq_cfg_1 {
1382 uint32_t u;
1383 struct ody_spix_dev_seq_regs_ers_seq_cfg_1_s {
1384 uint32_t erss_seq_p1_sect_size : 5;
1385 uint32_t reserved_5_31 : 27;
1386 } s;
1387 /* struct ody_spix_dev_seq_regs_ers_seq_cfg_1_s cn; */
1388 };
1389 typedef union ody_spix_dev_seq_regs_ers_seq_cfg_1 ody_spix_dev_seq_regs_ers_seq_cfg_1_t;
1390
1391 static inline uint64_t ODY_SPIX_DEV_SEQ_REGS_ERS_SEQ_CFG_1(uint64_t a) __attribute__ ((pure, always_inline));
ODY_SPIX_DEV_SEQ_REGS_ERS_SEQ_CFG_1(uint64_t a)1392 static inline uint64_t ODY_SPIX_DEV_SEQ_REGS_ERS_SEQ_CFG_1(uint64_t a)
1393 {
1394 if (a <= 1)
1395 return 0x804000000414ll + 0x1000000000ll * ((a) & 0x1);
1396 __ody_csr_fatal("SPIX_DEV_SEQ_REGS_ERS_SEQ_CFG_1", 1, a, 0, 0, 0, 0, 0);
1397 }
1398
1399 #define typedef_ODY_SPIX_DEV_SEQ_REGS_ERS_SEQ_CFG_1(a) ody_spix_dev_seq_regs_ers_seq_cfg_1_t
1400 #define bustype_ODY_SPIX_DEV_SEQ_REGS_ERS_SEQ_CFG_1(a) CSR_TYPE_NCB32b
1401 #define basename_ODY_SPIX_DEV_SEQ_REGS_ERS_SEQ_CFG_1(a) "SPIX_DEV_SEQ_REGS_ERS_SEQ_CFG_1"
1402 #define device_bar_ODY_SPIX_DEV_SEQ_REGS_ERS_SEQ_CFG_1(a) 0x0 /* PF_BAR0 */
1403 #define busnum_ODY_SPIX_DEV_SEQ_REGS_ERS_SEQ_CFG_1(a) (a)
1404 #define arguments_ODY_SPIX_DEV_SEQ_REGS_ERS_SEQ_CFG_1(a) (a), -1, -1, -1
1405
1406 /**
1407 * Register (NCB32b) spi#_dev_seq_regs_ers_seq_cfg_2
1408 *
1409 * SPI Dev Seq Regs Ers Seq Cfg 2 Register
1410 * to configure ERASE_ALL sequence for PROFILE 1 in ACMD work mode.
1411 */
1412 union ody_spix_dev_seq_regs_ers_seq_cfg_2 {
1413 uint32_t u;
1414 struct ody_spix_dev_seq_regs_ers_seq_cfg_2_s {
1415 uint32_t ersa_seq_p1_cmd_val : 8;
1416 uint32_t ersa_seq_p1_cmd_ios : 2;
1417 uint32_t reserved_10 : 1;
1418 uint32_t ersa_seq_p1_cmd_edge : 1;
1419 uint32_t reserved_12_14 : 3;
1420 uint32_t ersa_seq_p1_cmd_ext_en : 1;
1421 uint32_t ersa_seq_p1_cmd_ext_val : 8;
1422 uint32_t reserved_24_31 : 8;
1423 } s;
1424 /* struct ody_spix_dev_seq_regs_ers_seq_cfg_2_s cn; */
1425 };
1426 typedef union ody_spix_dev_seq_regs_ers_seq_cfg_2 ody_spix_dev_seq_regs_ers_seq_cfg_2_t;
1427
1428 static inline uint64_t ODY_SPIX_DEV_SEQ_REGS_ERS_SEQ_CFG_2(uint64_t a) __attribute__ ((pure, always_inline));
ODY_SPIX_DEV_SEQ_REGS_ERS_SEQ_CFG_2(uint64_t a)1429 static inline uint64_t ODY_SPIX_DEV_SEQ_REGS_ERS_SEQ_CFG_2(uint64_t a)
1430 {
1431 if (a <= 1)
1432 return 0x804000000418ll + 0x1000000000ll * ((a) & 0x1);
1433 __ody_csr_fatal("SPIX_DEV_SEQ_REGS_ERS_SEQ_CFG_2", 1, a, 0, 0, 0, 0, 0);
1434 }
1435
1436 #define typedef_ODY_SPIX_DEV_SEQ_REGS_ERS_SEQ_CFG_2(a) ody_spix_dev_seq_regs_ers_seq_cfg_2_t
1437 #define bustype_ODY_SPIX_DEV_SEQ_REGS_ERS_SEQ_CFG_2(a) CSR_TYPE_NCB32b
1438 #define basename_ODY_SPIX_DEV_SEQ_REGS_ERS_SEQ_CFG_2(a) "SPIX_DEV_SEQ_REGS_ERS_SEQ_CFG_2"
1439 #define device_bar_ODY_SPIX_DEV_SEQ_REGS_ERS_SEQ_CFG_2(a) 0x0 /* PF_BAR0 */
1440 #define busnum_ODY_SPIX_DEV_SEQ_REGS_ERS_SEQ_CFG_2(a) (a)
1441 #define arguments_ODY_SPIX_DEV_SEQ_REGS_ERS_SEQ_CFG_2(a) (a), -1, -1, -1
1442
1443 /**
1444 * Register (NCB32b) spi#_dev_seq_regs_prog_seq_cfg_0
1445 *
1446 * SPI Dev Seq Regs Prog Seq Cfg 0 Register
1447 * to configure PROGRAM sequence for PROFILE 1 and SPI NAND in ACMD and DIRECT work modes.
1448 */
1449 union ody_spix_dev_seq_regs_prog_seq_cfg_0 {
1450 uint32_t u;
1451 struct ody_spix_dev_seq_regs_prog_seq_cfg_0_s {
1452 uint32_t prog_seq_p1_cmd_val : 8;
1453 uint32_t prog_seq_p1_cmd_ios : 2;
1454 uint32_t reserved_10 : 1;
1455 uint32_t prog_seq_p1_cmd_edge : 1;
1456 uint32_t prog_seq_p1_addr_cnt : 3;
1457 uint32_t reserved_15 : 1;
1458 uint32_t prog_seq_p1_addr_ios : 2;
1459 uint32_t reserved_18 : 1;
1460 uint32_t prog_seq_p1_addr_edge : 1;
1461 uint32_t prog_seq_p1_data_ios : 2;
1462 uint32_t reserved_22 : 1;
1463 uint32_t prog_seq_p1_data_edge : 1;
1464 uint32_t prog_seq_p1_dummy_cnt : 6;
1465 uint32_t reserved_30_31 : 2;
1466 } s;
1467 /* struct ody_spix_dev_seq_regs_prog_seq_cfg_0_s cn; */
1468 };
1469 typedef union ody_spix_dev_seq_regs_prog_seq_cfg_0 ody_spix_dev_seq_regs_prog_seq_cfg_0_t;
1470
1471 static inline uint64_t ODY_SPIX_DEV_SEQ_REGS_PROG_SEQ_CFG_0(uint64_t a) __attribute__ ((pure, always_inline));
ODY_SPIX_DEV_SEQ_REGS_PROG_SEQ_CFG_0(uint64_t a)1472 static inline uint64_t ODY_SPIX_DEV_SEQ_REGS_PROG_SEQ_CFG_0(uint64_t a)
1473 {
1474 if (a <= 1)
1475 return 0x804000000420ll + 0x1000000000ll * ((a) & 0x1);
1476 __ody_csr_fatal("SPIX_DEV_SEQ_REGS_PROG_SEQ_CFG_0", 1, a, 0, 0, 0, 0, 0);
1477 }
1478
1479 #define typedef_ODY_SPIX_DEV_SEQ_REGS_PROG_SEQ_CFG_0(a) ody_spix_dev_seq_regs_prog_seq_cfg_0_t
1480 #define bustype_ODY_SPIX_DEV_SEQ_REGS_PROG_SEQ_CFG_0(a) CSR_TYPE_NCB32b
1481 #define basename_ODY_SPIX_DEV_SEQ_REGS_PROG_SEQ_CFG_0(a) "SPIX_DEV_SEQ_REGS_PROG_SEQ_CFG_0"
1482 #define device_bar_ODY_SPIX_DEV_SEQ_REGS_PROG_SEQ_CFG_0(a) 0x0 /* PF_BAR0 */
1483 #define busnum_ODY_SPIX_DEV_SEQ_REGS_PROG_SEQ_CFG_0(a) (a)
1484 #define arguments_ODY_SPIX_DEV_SEQ_REGS_PROG_SEQ_CFG_0(a) (a), -1, -1, -1
1485
1486 /**
1487 * Register (NCB32b) spi#_dev_seq_regs_prog_seq_cfg_1
1488 *
1489 * SPI Dev Seq Regs Prog Seq Cfg 1 Register
1490 * to configure PROGRAM sequence for PROFILE 1 and SPI NAND in ACMD and DIRECT work modes.
1491 */
1492 union ody_spix_dev_seq_regs_prog_seq_cfg_1 {
1493 uint32_t u;
1494 struct ody_spix_dev_seq_regs_prog_seq_cfg_1_s {
1495 uint32_t prog_seq_p1_cmd_ext_en : 1;
1496 uint32_t reserved_1_7 : 7;
1497 uint32_t prog_seq_p1_cmd_ext_val : 8;
1498 uint32_t reserved_16_31 : 16;
1499 } s;
1500 /* struct ody_spix_dev_seq_regs_prog_seq_cfg_1_s cn; */
1501 };
1502 typedef union ody_spix_dev_seq_regs_prog_seq_cfg_1 ody_spix_dev_seq_regs_prog_seq_cfg_1_t;
1503
1504 static inline uint64_t ODY_SPIX_DEV_SEQ_REGS_PROG_SEQ_CFG_1(uint64_t a) __attribute__ ((pure, always_inline));
ODY_SPIX_DEV_SEQ_REGS_PROG_SEQ_CFG_1(uint64_t a)1505 static inline uint64_t ODY_SPIX_DEV_SEQ_REGS_PROG_SEQ_CFG_1(uint64_t a)
1506 {
1507 if (a <= 1)
1508 return 0x804000000424ll + 0x1000000000ll * ((a) & 0x1);
1509 __ody_csr_fatal("SPIX_DEV_SEQ_REGS_PROG_SEQ_CFG_1", 1, a, 0, 0, 0, 0, 0);
1510 }
1511
1512 #define typedef_ODY_SPIX_DEV_SEQ_REGS_PROG_SEQ_CFG_1(a) ody_spix_dev_seq_regs_prog_seq_cfg_1_t
1513 #define bustype_ODY_SPIX_DEV_SEQ_REGS_PROG_SEQ_CFG_1(a) CSR_TYPE_NCB32b
1514 #define basename_ODY_SPIX_DEV_SEQ_REGS_PROG_SEQ_CFG_1(a) "SPIX_DEV_SEQ_REGS_PROG_SEQ_CFG_1"
1515 #define device_bar_ODY_SPIX_DEV_SEQ_REGS_PROG_SEQ_CFG_1(a) 0x0 /* PF_BAR0 */
1516 #define busnum_ODY_SPIX_DEV_SEQ_REGS_PROG_SEQ_CFG_1(a) (a)
1517 #define arguments_ODY_SPIX_DEV_SEQ_REGS_PROG_SEQ_CFG_1(a) (a), -1, -1, -1
1518
1519 /**
1520 * Register (NCB32b) spi#_dev_seq_regs_prog_seq_cfg_2
1521 *
1522 * SPI Dev Seq Regs Prog Seq Cfg 2 Register
1523 * to configure PROGRAM sequence for PROFILE 2 in ACMD and DIRECT work modes.
1524 */
1525 union ody_spix_dev_seq_regs_prog_seq_cfg_2 {
1526 uint32_t u;
1527 struct ody_spix_dev_seq_regs_prog_seq_cfg_2_s {
1528 uint32_t prog_seq_p2_target : 1;
1529 uint32_t prog_seq_p2_burst_type : 1;
1530 uint32_t prog_seq_p2_mask_cmd_mod : 1;
1531 uint32_t reserved_3_7 : 5;
1532 uint32_t prog_seq_p2_latency_cnt : 6;
1533 uint32_t reserved_14_31 : 18;
1534 } s;
1535 /* struct ody_spix_dev_seq_regs_prog_seq_cfg_2_s cn; */
1536 };
1537 typedef union ody_spix_dev_seq_regs_prog_seq_cfg_2 ody_spix_dev_seq_regs_prog_seq_cfg_2_t;
1538
1539 static inline uint64_t ODY_SPIX_DEV_SEQ_REGS_PROG_SEQ_CFG_2(uint64_t a) __attribute__ ((pure, always_inline));
ODY_SPIX_DEV_SEQ_REGS_PROG_SEQ_CFG_2(uint64_t a)1540 static inline uint64_t ODY_SPIX_DEV_SEQ_REGS_PROG_SEQ_CFG_2(uint64_t a)
1541 {
1542 if (a <= 1)
1543 return 0x804000000428ll + 0x1000000000ll * ((a) & 0x1);
1544 __ody_csr_fatal("SPIX_DEV_SEQ_REGS_PROG_SEQ_CFG_2", 1, a, 0, 0, 0, 0, 0);
1545 }
1546
1547 #define typedef_ODY_SPIX_DEV_SEQ_REGS_PROG_SEQ_CFG_2(a) ody_spix_dev_seq_regs_prog_seq_cfg_2_t
1548 #define bustype_ODY_SPIX_DEV_SEQ_REGS_PROG_SEQ_CFG_2(a) CSR_TYPE_NCB32b
1549 #define basename_ODY_SPIX_DEV_SEQ_REGS_PROG_SEQ_CFG_2(a) "SPIX_DEV_SEQ_REGS_PROG_SEQ_CFG_2"
1550 #define device_bar_ODY_SPIX_DEV_SEQ_REGS_PROG_SEQ_CFG_2(a) 0x0 /* PF_BAR0 */
1551 #define busnum_ODY_SPIX_DEV_SEQ_REGS_PROG_SEQ_CFG_2(a) (a)
1552 #define arguments_ODY_SPIX_DEV_SEQ_REGS_PROG_SEQ_CFG_2(a) (a), -1, -1, -1
1553
1554 /**
1555 * Register (NCB32b) spi#_dev_seq_regs_read_seq_cfg_0
1556 *
1557 * SPI Dev Seq Regs Read Seq Cfg 0 Register
1558 * to configure READ sequence for PROFILE 1 and SPI NAND in ACMD and DIRECT work modes.
1559 */
1560 union ody_spix_dev_seq_regs_read_seq_cfg_0 {
1561 uint32_t u;
1562 struct ody_spix_dev_seq_regs_read_seq_cfg_0_s {
1563 uint32_t read_seq_p1_cmd_val : 8;
1564 uint32_t read_seq_p1_cmd_ios : 2;
1565 uint32_t reserved_10 : 1;
1566 uint32_t read_seq_p1_cmd_edge : 1;
1567 uint32_t read_seq_p1_addr_cnt : 3;
1568 uint32_t reserved_15 : 1;
1569 uint32_t read_seq_p1_addr_ios : 2;
1570 uint32_t reserved_18 : 1;
1571 uint32_t read_seq_p1_addr_edge : 1;
1572 uint32_t read_seq_p1_data_ios : 2;
1573 uint32_t reserved_22 : 1;
1574 uint32_t read_seq_p1_data_edge : 1;
1575 uint32_t read_seq_p1_dummy_cnt : 6;
1576 uint32_t reserved_30_31 : 2;
1577 } s;
1578 /* struct ody_spix_dev_seq_regs_read_seq_cfg_0_s cn; */
1579 };
1580 typedef union ody_spix_dev_seq_regs_read_seq_cfg_0 ody_spix_dev_seq_regs_read_seq_cfg_0_t;
1581
1582 static inline uint64_t ODY_SPIX_DEV_SEQ_REGS_READ_SEQ_CFG_0(uint64_t a) __attribute__ ((pure, always_inline));
ODY_SPIX_DEV_SEQ_REGS_READ_SEQ_CFG_0(uint64_t a)1583 static inline uint64_t ODY_SPIX_DEV_SEQ_REGS_READ_SEQ_CFG_0(uint64_t a)
1584 {
1585 if (a <= 1)
1586 return 0x804000000430ll + 0x1000000000ll * ((a) & 0x1);
1587 __ody_csr_fatal("SPIX_DEV_SEQ_REGS_READ_SEQ_CFG_0", 1, a, 0, 0, 0, 0, 0);
1588 }
1589
1590 #define typedef_ODY_SPIX_DEV_SEQ_REGS_READ_SEQ_CFG_0(a) ody_spix_dev_seq_regs_read_seq_cfg_0_t
1591 #define bustype_ODY_SPIX_DEV_SEQ_REGS_READ_SEQ_CFG_0(a) CSR_TYPE_NCB32b
1592 #define basename_ODY_SPIX_DEV_SEQ_REGS_READ_SEQ_CFG_0(a) "SPIX_DEV_SEQ_REGS_READ_SEQ_CFG_0"
1593 #define device_bar_ODY_SPIX_DEV_SEQ_REGS_READ_SEQ_CFG_0(a) 0x0 /* PF_BAR0 */
1594 #define busnum_ODY_SPIX_DEV_SEQ_REGS_READ_SEQ_CFG_0(a) (a)
1595 #define arguments_ODY_SPIX_DEV_SEQ_REGS_READ_SEQ_CFG_0(a) (a), -1, -1, -1
1596
1597 /**
1598 * Register (NCB32b) spi#_dev_seq_regs_read_seq_cfg_1
1599 *
1600 * SPI Dev Seq Regs Read Seq Cfg 1 Register
1601 * to configure READ sequence for PROFILE 1 and SPI NAND in ACMD and DIRECT work modes.
1602 */
1603 union ody_spix_dev_seq_regs_read_seq_cfg_1 {
1604 uint32_t u;
1605 struct ody_spix_dev_seq_regs_read_seq_cfg_1_s {
1606 uint32_t read_seq_p1_cmd_ext_en : 1;
1607 uint32_t reserved_1_3 : 3;
1608 uint32_t read_seq_p1_cache_random_read_en : 1;
1609 uint32_t reserved_5_7 : 3;
1610 uint32_t read_seq_p1_cmd_ext_val : 8;
1611 uint32_t reserved_16_23 : 8;
1612 uint32_t read_seq_p1_mb_dummy_cnt : 6;
1613 uint32_t reserved_30 : 1;
1614 uint32_t read_seq_p1_mb_en : 1;
1615 } s;
1616 /* struct ody_spix_dev_seq_regs_read_seq_cfg_1_s cn; */
1617 };
1618 typedef union ody_spix_dev_seq_regs_read_seq_cfg_1 ody_spix_dev_seq_regs_read_seq_cfg_1_t;
1619
1620 static inline uint64_t ODY_SPIX_DEV_SEQ_REGS_READ_SEQ_CFG_1(uint64_t a) __attribute__ ((pure, always_inline));
ODY_SPIX_DEV_SEQ_REGS_READ_SEQ_CFG_1(uint64_t a)1621 static inline uint64_t ODY_SPIX_DEV_SEQ_REGS_READ_SEQ_CFG_1(uint64_t a)
1622 {
1623 if (a <= 1)
1624 return 0x804000000434ll + 0x1000000000ll * ((a) & 0x1);
1625 __ody_csr_fatal("SPIX_DEV_SEQ_REGS_READ_SEQ_CFG_1", 1, a, 0, 0, 0, 0, 0);
1626 }
1627
1628 #define typedef_ODY_SPIX_DEV_SEQ_REGS_READ_SEQ_CFG_1(a) ody_spix_dev_seq_regs_read_seq_cfg_1_t
1629 #define bustype_ODY_SPIX_DEV_SEQ_REGS_READ_SEQ_CFG_1(a) CSR_TYPE_NCB32b
1630 #define basename_ODY_SPIX_DEV_SEQ_REGS_READ_SEQ_CFG_1(a) "SPIX_DEV_SEQ_REGS_READ_SEQ_CFG_1"
1631 #define device_bar_ODY_SPIX_DEV_SEQ_REGS_READ_SEQ_CFG_1(a) 0x0 /* PF_BAR0 */
1632 #define busnum_ODY_SPIX_DEV_SEQ_REGS_READ_SEQ_CFG_1(a) (a)
1633 #define arguments_ODY_SPIX_DEV_SEQ_REGS_READ_SEQ_CFG_1(a) (a), -1, -1, -1
1634
1635 /**
1636 * Register (NCB32b) spi#_dev_seq_regs_read_seq_cfg_2
1637 *
1638 * SPI Dev Seq Regs Read Seq Cfg 2 Register
1639 * to configure READ sequence for PROFILE 2 in ACMD and DIRECT work modes.
1640 */
1641 union ody_spix_dev_seq_regs_read_seq_cfg_2 {
1642 uint32_t u;
1643 struct ody_spix_dev_seq_regs_read_seq_cfg_2_s {
1644 uint32_t read_seq_p2_target : 1;
1645 uint32_t read_seq_p2_burst_type : 1;
1646 uint32_t read_seq_p2_mask_cmd_mod : 1;
1647 uint32_t read_seq_p2_hf_bound_en : 1;
1648 uint32_t reserved_4_7 : 4;
1649 uint32_t read_seq_p2_latency_cnt : 6;
1650 uint32_t reserved_14_31 : 18;
1651 } s;
1652 /* struct ody_spix_dev_seq_regs_read_seq_cfg_2_s cn; */
1653 };
1654 typedef union ody_spix_dev_seq_regs_read_seq_cfg_2 ody_spix_dev_seq_regs_read_seq_cfg_2_t;
1655
1656 static inline uint64_t ODY_SPIX_DEV_SEQ_REGS_READ_SEQ_CFG_2(uint64_t a) __attribute__ ((pure, always_inline));
ODY_SPIX_DEV_SEQ_REGS_READ_SEQ_CFG_2(uint64_t a)1657 static inline uint64_t ODY_SPIX_DEV_SEQ_REGS_READ_SEQ_CFG_2(uint64_t a)
1658 {
1659 if (a <= 1)
1660 return 0x804000000438ll + 0x1000000000ll * ((a) & 0x1);
1661 __ody_csr_fatal("SPIX_DEV_SEQ_REGS_READ_SEQ_CFG_2", 1, a, 0, 0, 0, 0, 0);
1662 }
1663
1664 #define typedef_ODY_SPIX_DEV_SEQ_REGS_READ_SEQ_CFG_2(a) ody_spix_dev_seq_regs_read_seq_cfg_2_t
1665 #define bustype_ODY_SPIX_DEV_SEQ_REGS_READ_SEQ_CFG_2(a) CSR_TYPE_NCB32b
1666 #define basename_ODY_SPIX_DEV_SEQ_REGS_READ_SEQ_CFG_2(a) "SPIX_DEV_SEQ_REGS_READ_SEQ_CFG_2"
1667 #define device_bar_ODY_SPIX_DEV_SEQ_REGS_READ_SEQ_CFG_2(a) 0x0 /* PF_BAR0 */
1668 #define busnum_ODY_SPIX_DEV_SEQ_REGS_READ_SEQ_CFG_2(a) (a)
1669 #define arguments_ODY_SPIX_DEV_SEQ_REGS_READ_SEQ_CFG_2(a) (a), -1, -1, -1
1670
1671 /**
1672 * Register (NCB32b) spi#_dev_seq_regs_rst_seq_cfg_0
1673 *
1674 * SPI Dev Seq Regs Rst Seq Cfg 0 Register
1675 * to configure RESET sequence for PROFILE 1 and SPI NAND in ACMD work mode.
1676 */
1677 union ody_spix_dev_seq_regs_rst_seq_cfg_0 {
1678 uint32_t u;
1679 struct ody_spix_dev_seq_regs_rst_seq_cfg_0_s {
1680 uint32_t rst_seq_p1_cmd0_val : 8;
1681 uint32_t rst_seq_p1_cmd1_val : 8;
1682 uint32_t rst_seq_p1_cmd0_en : 1;
1683 uint32_t reserved_17 : 1;
1684 uint32_t rst_seq_p1_data_ios : 2;
1685 uint32_t reserved_20 : 1;
1686 uint32_t rst_seq_p1_data_edge : 1;
1687 uint32_t rst_seq_p1_data_en : 1;
1688 uint32_t reserved_23 : 1;
1689 uint32_t rst_seq_p1_cmd_ios : 2;
1690 uint32_t reserved_26_27 : 2;
1691 uint32_t rst_seq_p1_cmd_edge : 1;
1692 uint32_t reserved_29_31 : 3;
1693 } s;
1694 /* struct ody_spix_dev_seq_regs_rst_seq_cfg_0_s cn; */
1695 };
1696 typedef union ody_spix_dev_seq_regs_rst_seq_cfg_0 ody_spix_dev_seq_regs_rst_seq_cfg_0_t;
1697
1698 static inline uint64_t ODY_SPIX_DEV_SEQ_REGS_RST_SEQ_CFG_0(uint64_t a) __attribute__ ((pure, always_inline));
ODY_SPIX_DEV_SEQ_REGS_RST_SEQ_CFG_0(uint64_t a)1699 static inline uint64_t ODY_SPIX_DEV_SEQ_REGS_RST_SEQ_CFG_0(uint64_t a)
1700 {
1701 if (a <= 1)
1702 return 0x804000000400ll + 0x1000000000ll * ((a) & 0x1);
1703 __ody_csr_fatal("SPIX_DEV_SEQ_REGS_RST_SEQ_CFG_0", 1, a, 0, 0, 0, 0, 0);
1704 }
1705
1706 #define typedef_ODY_SPIX_DEV_SEQ_REGS_RST_SEQ_CFG_0(a) ody_spix_dev_seq_regs_rst_seq_cfg_0_t
1707 #define bustype_ODY_SPIX_DEV_SEQ_REGS_RST_SEQ_CFG_0(a) CSR_TYPE_NCB32b
1708 #define basename_ODY_SPIX_DEV_SEQ_REGS_RST_SEQ_CFG_0(a) "SPIX_DEV_SEQ_REGS_RST_SEQ_CFG_0"
1709 #define device_bar_ODY_SPIX_DEV_SEQ_REGS_RST_SEQ_CFG_0(a) 0x0 /* PF_BAR0 */
1710 #define busnum_ODY_SPIX_DEV_SEQ_REGS_RST_SEQ_CFG_0(a) (a)
1711 #define arguments_ODY_SPIX_DEV_SEQ_REGS_RST_SEQ_CFG_0(a) (a), -1, -1, -1
1712
1713 /**
1714 * Register (NCB32b) spi#_dev_seq_regs_rst_seq_cfg_1
1715 *
1716 * SPI Dev Seq Regs Rst Seq Cfg 1 Register
1717 * to configure RESET sequence for PROFILE 1 and SPI NAND in ACMD work mode.
1718 */
1719 union ody_spix_dev_seq_regs_rst_seq_cfg_1 {
1720 uint32_t u;
1721 struct ody_spix_dev_seq_regs_rst_seq_cfg_1_s {
1722 uint32_t rst_seq_p1_cmd0_ext_en : 1;
1723 uint32_t rst_seq_p1_cmd1_ext_en : 1;
1724 uint32_t reserved_2_7 : 6;
1725 uint32_t rst_seq_p1_cmd0_ext_val : 8;
1726 uint32_t rst_seq_p1_cmd1_ext_val : 8;
1727 uint32_t rst_seq_p1_data_val : 8;
1728 } s;
1729 /* struct ody_spix_dev_seq_regs_rst_seq_cfg_1_s cn; */
1730 };
1731 typedef union ody_spix_dev_seq_regs_rst_seq_cfg_1 ody_spix_dev_seq_regs_rst_seq_cfg_1_t;
1732
1733 static inline uint64_t ODY_SPIX_DEV_SEQ_REGS_RST_SEQ_CFG_1(uint64_t a) __attribute__ ((pure, always_inline));
ODY_SPIX_DEV_SEQ_REGS_RST_SEQ_CFG_1(uint64_t a)1734 static inline uint64_t ODY_SPIX_DEV_SEQ_REGS_RST_SEQ_CFG_1(uint64_t a)
1735 {
1736 if (a <= 1)
1737 return 0x804000000404ll + 0x1000000000ll * ((a) & 0x1);
1738 __ody_csr_fatal("SPIX_DEV_SEQ_REGS_RST_SEQ_CFG_1", 1, a, 0, 0, 0, 0, 0);
1739 }
1740
1741 #define typedef_ODY_SPIX_DEV_SEQ_REGS_RST_SEQ_CFG_1(a) ody_spix_dev_seq_regs_rst_seq_cfg_1_t
1742 #define bustype_ODY_SPIX_DEV_SEQ_REGS_RST_SEQ_CFG_1(a) CSR_TYPE_NCB32b
1743 #define basename_ODY_SPIX_DEV_SEQ_REGS_RST_SEQ_CFG_1(a) "SPIX_DEV_SEQ_REGS_RST_SEQ_CFG_1"
1744 #define device_bar_ODY_SPIX_DEV_SEQ_REGS_RST_SEQ_CFG_1(a) 0x0 /* PF_BAR0 */
1745 #define busnum_ODY_SPIX_DEV_SEQ_REGS_RST_SEQ_CFG_1(a) (a)
1746 #define arguments_ODY_SPIX_DEV_SEQ_REGS_RST_SEQ_CFG_1(a) (a), -1, -1, -1
1747
1748 /**
1749 * Register (NCB32b) spi#_dev_seq_regs_stat_seq_cfg_0
1750 *
1751 * SPI Dev Seq Regs Stat Seq Cfg 0 Register
1752 * to configure status checking sequence for PROFILE 1 and SPI NAND in ACMD and DIRECT work
1753 * modes.
1754 */
1755 union ody_spix_dev_seq_regs_stat_seq_cfg_0 {
1756 uint32_t u;
1757 struct ody_spix_dev_seq_regs_stat_seq_cfg_0_s {
1758 uint32_t stat_seq_p1_cmd_ios : 2;
1759 uint32_t reserved_2_3 : 2;
1760 uint32_t stat_seq_p1_cmd_edge : 1;
1761 uint32_t stat_seq_p1_cmd_ext_en : 1;
1762 uint32_t reserved_6_7 : 2;
1763 uint32_t stat_seq_p1_addr_cnt : 2;
1764 uint32_t stat_seq_p1_addr_ios : 2;
1765 uint32_t stat_seq_p1_addr_edge : 1;
1766 uint32_t reserved_13_19 : 7;
1767 uint32_t stat_seq_p1_data_ios : 2;
1768 uint32_t stat_seq_p1_data_edge : 1;
1769 uint32_t reserved_23_31 : 9;
1770 } s;
1771 /* struct ody_spix_dev_seq_regs_stat_seq_cfg_0_s cn; */
1772 };
1773 typedef union ody_spix_dev_seq_regs_stat_seq_cfg_0 ody_spix_dev_seq_regs_stat_seq_cfg_0_t;
1774
1775 static inline uint64_t ODY_SPIX_DEV_SEQ_REGS_STAT_SEQ_CFG_0(uint64_t a) __attribute__ ((pure, always_inline));
ODY_SPIX_DEV_SEQ_REGS_STAT_SEQ_CFG_0(uint64_t a)1776 static inline uint64_t ODY_SPIX_DEV_SEQ_REGS_STAT_SEQ_CFG_0(uint64_t a)
1777 {
1778 if (a <= 1)
1779 return 0x804000000450ll + 0x1000000000ll * ((a) & 0x1);
1780 __ody_csr_fatal("SPIX_DEV_SEQ_REGS_STAT_SEQ_CFG_0", 1, a, 0, 0, 0, 0, 0);
1781 }
1782
1783 #define typedef_ODY_SPIX_DEV_SEQ_REGS_STAT_SEQ_CFG_0(a) ody_spix_dev_seq_regs_stat_seq_cfg_0_t
1784 #define bustype_ODY_SPIX_DEV_SEQ_REGS_STAT_SEQ_CFG_0(a) CSR_TYPE_NCB32b
1785 #define basename_ODY_SPIX_DEV_SEQ_REGS_STAT_SEQ_CFG_0(a) "SPIX_DEV_SEQ_REGS_STAT_SEQ_CFG_0"
1786 #define device_bar_ODY_SPIX_DEV_SEQ_REGS_STAT_SEQ_CFG_0(a) 0x0 /* PF_BAR0 */
1787 #define busnum_ODY_SPIX_DEV_SEQ_REGS_STAT_SEQ_CFG_0(a) (a)
1788 #define arguments_ODY_SPIX_DEV_SEQ_REGS_STAT_SEQ_CFG_0(a) (a), -1, -1, -1
1789
1790 /**
1791 * Register (NCB32b) spi#_dev_seq_regs_stat_seq_cfg_1
1792 *
1793 * SPI Dev Seq Regs Stat Seq Cfg 1 Register
1794 * to configure status checking sequence for PROFILE 1 and SPI NAND ACMD and
1795 * DIRECT work modes.
1796 */
1797 union ody_spix_dev_seq_regs_stat_seq_cfg_1 {
1798 uint32_t u;
1799 struct ody_spix_dev_seq_regs_stat_seq_cfg_1_s {
1800 uint32_t stat_seq_p1_dev_rdy_dummy_cnt : 6;
1801 uint32_t stat_seq_p1_dev_rdy_addr_en : 1;
1802 uint32_t reserved_7_15 : 9;
1803 uint32_t stat_seq_p1_prog_fail_dummy_cnt : 6;
1804 uint32_t stat_seq_p1_prog_fail_addr_en : 1;
1805 uint32_t reserved_23 : 1;
1806 uint32_t stat_seq_p1_ers_fail_dummy_cnt : 6;
1807 uint32_t stat_seq_p1_ers_fail_addr_en : 1;
1808 uint32_t reserved_31 : 1;
1809 } s;
1810 /* struct ody_spix_dev_seq_regs_stat_seq_cfg_1_s cn; */
1811 };
1812 typedef union ody_spix_dev_seq_regs_stat_seq_cfg_1 ody_spix_dev_seq_regs_stat_seq_cfg_1_t;
1813
1814 static inline uint64_t ODY_SPIX_DEV_SEQ_REGS_STAT_SEQ_CFG_1(uint64_t a) __attribute__ ((pure, always_inline));
ODY_SPIX_DEV_SEQ_REGS_STAT_SEQ_CFG_1(uint64_t a)1815 static inline uint64_t ODY_SPIX_DEV_SEQ_REGS_STAT_SEQ_CFG_1(uint64_t a)
1816 {
1817 if (a <= 1)
1818 return 0x804000000454ll + 0x1000000000ll * ((a) & 0x1);
1819 __ody_csr_fatal("SPIX_DEV_SEQ_REGS_STAT_SEQ_CFG_1", 1, a, 0, 0, 0, 0, 0);
1820 }
1821
1822 #define typedef_ODY_SPIX_DEV_SEQ_REGS_STAT_SEQ_CFG_1(a) ody_spix_dev_seq_regs_stat_seq_cfg_1_t
1823 #define bustype_ODY_SPIX_DEV_SEQ_REGS_STAT_SEQ_CFG_1(a) CSR_TYPE_NCB32b
1824 #define basename_ODY_SPIX_DEV_SEQ_REGS_STAT_SEQ_CFG_1(a) "SPIX_DEV_SEQ_REGS_STAT_SEQ_CFG_1"
1825 #define device_bar_ODY_SPIX_DEV_SEQ_REGS_STAT_SEQ_CFG_1(a) 0x0 /* PF_BAR0 */
1826 #define busnum_ODY_SPIX_DEV_SEQ_REGS_STAT_SEQ_CFG_1(a) (a)
1827 #define arguments_ODY_SPIX_DEV_SEQ_REGS_STAT_SEQ_CFG_1(a) (a), -1, -1, -1
1828
1829 /**
1830 * Register (NCB32b) spi#_dev_seq_regs_stat_seq_cfg_10
1831 *
1832 * SPI Dev Seq Regs Stat Seq Cfg 10 Register
1833 * to configure status checking sequence for SPI NAND devices in ACMD and DIRECT work modes.
1834 */
1835 union ody_spix_dev_seq_regs_stat_seq_cfg_10 {
1836 uint32_t u;
1837 struct ody_spix_dev_seq_regs_stat_seq_cfg_10_s {
1838 uint32_t stat_seq_ecc_fail_mask : 8;
1839 uint32_t stat_seq_ecc_fail_val : 8;
1840 uint32_t stat_seq_ecc_corr_val : 8;
1841 uint32_t stat_seq_crdy_idx : 3;
1842 uint32_t stat_seq_crdy_val : 1;
1843 uint32_t reserved_28_30 : 3;
1844 uint32_t stat_seq_ecc_fail_en : 1;
1845 } s;
1846 /* struct ody_spix_dev_seq_regs_stat_seq_cfg_10_s cn; */
1847 };
1848 typedef union ody_spix_dev_seq_regs_stat_seq_cfg_10 ody_spix_dev_seq_regs_stat_seq_cfg_10_t;
1849
1850 static inline uint64_t ODY_SPIX_DEV_SEQ_REGS_STAT_SEQ_CFG_10(uint64_t a) __attribute__ ((pure, always_inline));
ODY_SPIX_DEV_SEQ_REGS_STAT_SEQ_CFG_10(uint64_t a)1851 static inline uint64_t ODY_SPIX_DEV_SEQ_REGS_STAT_SEQ_CFG_10(uint64_t a)
1852 {
1853 if (a <= 1)
1854 return 0x804000000478ll + 0x1000000000ll * ((a) & 0x1);
1855 __ody_csr_fatal("SPIX_DEV_SEQ_REGS_STAT_SEQ_CFG_10", 1, a, 0, 0, 0, 0, 0);
1856 }
1857
1858 #define typedef_ODY_SPIX_DEV_SEQ_REGS_STAT_SEQ_CFG_10(a) ody_spix_dev_seq_regs_stat_seq_cfg_10_t
1859 #define bustype_ODY_SPIX_DEV_SEQ_REGS_STAT_SEQ_CFG_10(a) CSR_TYPE_NCB32b
1860 #define basename_ODY_SPIX_DEV_SEQ_REGS_STAT_SEQ_CFG_10(a) "SPIX_DEV_SEQ_REGS_STAT_SEQ_CFG_10"
1861 #define device_bar_ODY_SPIX_DEV_SEQ_REGS_STAT_SEQ_CFG_10(a) 0x0 /* PF_BAR0 */
1862 #define busnum_ODY_SPIX_DEV_SEQ_REGS_STAT_SEQ_CFG_10(a) (a)
1863 #define arguments_ODY_SPIX_DEV_SEQ_REGS_STAT_SEQ_CFG_10(a) (a), -1, -1, -1
1864
1865 /**
1866 * Register (NCB32b) spi#_dev_seq_regs_stat_seq_cfg_2
1867 *
1868 * SPI Dev Seq Regs Stat Seq Cfg 2 Register
1869 * to configure status checking sequence for PROFILE 1 and SPI NAND in ACMD and DIRECT work
1870 * modes.
1871 */
1872 union ody_spix_dev_seq_regs_stat_seq_cfg_2 {
1873 uint32_t u;
1874 struct ody_spix_dev_seq_regs_stat_seq_cfg_2_s {
1875 uint32_t stat_seq_p1_dev_rdy_cmd_val : 8;
1876 uint32_t stat_seq_p1_ers_fail_cmd_val : 8;
1877 uint32_t reserved_16_23 : 8;
1878 uint32_t stat_seq_p1_prog_fail_cmd_val : 8;
1879 } s;
1880 /* struct ody_spix_dev_seq_regs_stat_seq_cfg_2_s cn; */
1881 };
1882 typedef union ody_spix_dev_seq_regs_stat_seq_cfg_2 ody_spix_dev_seq_regs_stat_seq_cfg_2_t;
1883
1884 static inline uint64_t ODY_SPIX_DEV_SEQ_REGS_STAT_SEQ_CFG_2(uint64_t a) __attribute__ ((pure, always_inline));
ODY_SPIX_DEV_SEQ_REGS_STAT_SEQ_CFG_2(uint64_t a)1885 static inline uint64_t ODY_SPIX_DEV_SEQ_REGS_STAT_SEQ_CFG_2(uint64_t a)
1886 {
1887 if (a <= 1)
1888 return 0x804000000458ll + 0x1000000000ll * ((a) & 0x1);
1889 __ody_csr_fatal("SPIX_DEV_SEQ_REGS_STAT_SEQ_CFG_2", 1, a, 0, 0, 0, 0, 0);
1890 }
1891
1892 #define typedef_ODY_SPIX_DEV_SEQ_REGS_STAT_SEQ_CFG_2(a) ody_spix_dev_seq_regs_stat_seq_cfg_2_t
1893 #define bustype_ODY_SPIX_DEV_SEQ_REGS_STAT_SEQ_CFG_2(a) CSR_TYPE_NCB32b
1894 #define basename_ODY_SPIX_DEV_SEQ_REGS_STAT_SEQ_CFG_2(a) "SPIX_DEV_SEQ_REGS_STAT_SEQ_CFG_2"
1895 #define device_bar_ODY_SPIX_DEV_SEQ_REGS_STAT_SEQ_CFG_2(a) 0x0 /* PF_BAR0 */
1896 #define busnum_ODY_SPIX_DEV_SEQ_REGS_STAT_SEQ_CFG_2(a) (a)
1897 #define arguments_ODY_SPIX_DEV_SEQ_REGS_STAT_SEQ_CFG_2(a) (a), -1, -1, -1
1898
1899 /**
1900 * Register (NCB32b) spi#_dev_seq_regs_stat_seq_cfg_3
1901 *
1902 * SPI Dev Seq Regs Stat Seq Cfg 3 Register
1903 * to configure status checking sequence for PROFILE 1 and SPI NAND in ACMD and DIRECT work
1904 * modes.
1905 */
1906 union ody_spix_dev_seq_regs_stat_seq_cfg_3 {
1907 uint32_t u;
1908 struct ody_spix_dev_seq_regs_stat_seq_cfg_3_s {
1909 uint32_t stat_seq_p1_dev_rdy_cmd_ext_val : 8;
1910 uint32_t stat_seq_p1_ers_fail_cmd_ext_val : 8;
1911 uint32_t reserved_16_23 : 8;
1912 uint32_t stat_seq_p1_prog_fail_cmd_ext_val : 8;
1913 } s;
1914 /* struct ody_spix_dev_seq_regs_stat_seq_cfg_3_s cn; */
1915 };
1916 typedef union ody_spix_dev_seq_regs_stat_seq_cfg_3 ody_spix_dev_seq_regs_stat_seq_cfg_3_t;
1917
1918 static inline uint64_t ODY_SPIX_DEV_SEQ_REGS_STAT_SEQ_CFG_3(uint64_t a) __attribute__ ((pure, always_inline));
ODY_SPIX_DEV_SEQ_REGS_STAT_SEQ_CFG_3(uint64_t a)1919 static inline uint64_t ODY_SPIX_DEV_SEQ_REGS_STAT_SEQ_CFG_3(uint64_t a)
1920 {
1921 if (a <= 1)
1922 return 0x80400000045cll + 0x1000000000ll * ((a) & 0x1);
1923 __ody_csr_fatal("SPIX_DEV_SEQ_REGS_STAT_SEQ_CFG_3", 1, a, 0, 0, 0, 0, 0);
1924 }
1925
1926 #define typedef_ODY_SPIX_DEV_SEQ_REGS_STAT_SEQ_CFG_3(a) ody_spix_dev_seq_regs_stat_seq_cfg_3_t
1927 #define bustype_ODY_SPIX_DEV_SEQ_REGS_STAT_SEQ_CFG_3(a) CSR_TYPE_NCB32b
1928 #define basename_ODY_SPIX_DEV_SEQ_REGS_STAT_SEQ_CFG_3(a) "SPIX_DEV_SEQ_REGS_STAT_SEQ_CFG_3"
1929 #define device_bar_ODY_SPIX_DEV_SEQ_REGS_STAT_SEQ_CFG_3(a) 0x0 /* PF_BAR0 */
1930 #define busnum_ODY_SPIX_DEV_SEQ_REGS_STAT_SEQ_CFG_3(a) (a)
1931 #define arguments_ODY_SPIX_DEV_SEQ_REGS_STAT_SEQ_CFG_3(a) (a), -1, -1, -1
1932
1933 /**
1934 * Register (NCB32b) spi#_dev_seq_regs_stat_seq_cfg_4
1935 *
1936 * SPI Dev Seq Regs Stat Seq Cfg 4 Register
1937 * to configure status checking sequence for PROFILE 2 - HF in ACMD and DIRECT work modes.
1938 */
1939 union ody_spix_dev_seq_regs_stat_seq_cfg_4 {
1940 uint32_t u;
1941 struct ody_spix_dev_seq_regs_stat_seq_cfg_4_s {
1942 uint32_t reserved_0_1 : 2;
1943 uint32_t stat_seq_p2_mask_cmd_mod : 1;
1944 uint32_t reserved_3_7 : 5;
1945 uint32_t stat_seq_p2_latency_cnt : 6;
1946 uint32_t reserved_14_31 : 18;
1947 } s;
1948 /* struct ody_spix_dev_seq_regs_stat_seq_cfg_4_s cn; */
1949 };
1950 typedef union ody_spix_dev_seq_regs_stat_seq_cfg_4 ody_spix_dev_seq_regs_stat_seq_cfg_4_t;
1951
1952 static inline uint64_t ODY_SPIX_DEV_SEQ_REGS_STAT_SEQ_CFG_4(uint64_t a) __attribute__ ((pure, always_inline));
ODY_SPIX_DEV_SEQ_REGS_STAT_SEQ_CFG_4(uint64_t a)1953 static inline uint64_t ODY_SPIX_DEV_SEQ_REGS_STAT_SEQ_CFG_4(uint64_t a)
1954 {
1955 if (a <= 1)
1956 return 0x804000000460ll + 0x1000000000ll * ((a) & 0x1);
1957 __ody_csr_fatal("SPIX_DEV_SEQ_REGS_STAT_SEQ_CFG_4", 1, a, 0, 0, 0, 0, 0);
1958 }
1959
1960 #define typedef_ODY_SPIX_DEV_SEQ_REGS_STAT_SEQ_CFG_4(a) ody_spix_dev_seq_regs_stat_seq_cfg_4_t
1961 #define bustype_ODY_SPIX_DEV_SEQ_REGS_STAT_SEQ_CFG_4(a) CSR_TYPE_NCB32b
1962 #define basename_ODY_SPIX_DEV_SEQ_REGS_STAT_SEQ_CFG_4(a) "SPIX_DEV_SEQ_REGS_STAT_SEQ_CFG_4"
1963 #define device_bar_ODY_SPIX_DEV_SEQ_REGS_STAT_SEQ_CFG_4(a) 0x0 /* PF_BAR0 */
1964 #define busnum_ODY_SPIX_DEV_SEQ_REGS_STAT_SEQ_CFG_4(a) (a)
1965 #define arguments_ODY_SPIX_DEV_SEQ_REGS_STAT_SEQ_CFG_4(a) (a), -1, -1, -1
1966
1967 /**
1968 * Register (NCB32b) spi#_dev_seq_regs_stat_seq_cfg_5
1969 *
1970 * SPI Dev Seq Regs Stat Seq Cfg 5 Register
1971 * to configure status checking sequence for PROFILE 1, SPI NAND and PROFILE 2
1972 * - HF in ACMD and
1973 * DIRECT work modes.
1974 */
1975 union ody_spix_dev_seq_regs_stat_seq_cfg_5 {
1976 uint32_t u;
1977 struct ody_spix_dev_seq_regs_stat_seq_cfg_5_s {
1978 uint32_t stat_seq_dev_rdy_idx : 4;
1979 uint32_t stat_seq_dev_rdy_val : 1;
1980 uint32_t stat_seq_dev_rdy_size : 1;
1981 uint32_t stat_seq_dev_rdy_en : 1;
1982 uint32_t reserved_7 : 1;
1983 uint32_t stat_seq_ers_fail_idx : 4;
1984 uint32_t stat_seq_ers_fail_val : 1;
1985 uint32_t stat_seq_ers_fail_size : 1;
1986 uint32_t stat_seq_ers_fail_en : 1;
1987 uint32_t reserved_15_23 : 9;
1988 uint32_t stat_seq_prog_fail_idx : 4;
1989 uint32_t stat_seq_prog_fail_val : 1;
1990 uint32_t stat_seq_prog_fail_size : 1;
1991 uint32_t stat_seq_prog_fail_en : 1;
1992 uint32_t reserved_31 : 1;
1993 } s;
1994 /* struct ody_spix_dev_seq_regs_stat_seq_cfg_5_s cn; */
1995 };
1996 typedef union ody_spix_dev_seq_regs_stat_seq_cfg_5 ody_spix_dev_seq_regs_stat_seq_cfg_5_t;
1997
1998 static inline uint64_t ODY_SPIX_DEV_SEQ_REGS_STAT_SEQ_CFG_5(uint64_t a) __attribute__ ((pure, always_inline));
ODY_SPIX_DEV_SEQ_REGS_STAT_SEQ_CFG_5(uint64_t a)1999 static inline uint64_t ODY_SPIX_DEV_SEQ_REGS_STAT_SEQ_CFG_5(uint64_t a)
2000 {
2001 if (a <= 1)
2002 return 0x804000000464ll + 0x1000000000ll * ((a) & 0x1);
2003 __ody_csr_fatal("SPIX_DEV_SEQ_REGS_STAT_SEQ_CFG_5", 1, a, 0, 0, 0, 0, 0);
2004 }
2005
2006 #define typedef_ODY_SPIX_DEV_SEQ_REGS_STAT_SEQ_CFG_5(a) ody_spix_dev_seq_regs_stat_seq_cfg_5_t
2007 #define bustype_ODY_SPIX_DEV_SEQ_REGS_STAT_SEQ_CFG_5(a) CSR_TYPE_NCB32b
2008 #define basename_ODY_SPIX_DEV_SEQ_REGS_STAT_SEQ_CFG_5(a) "SPIX_DEV_SEQ_REGS_STAT_SEQ_CFG_5"
2009 #define device_bar_ODY_SPIX_DEV_SEQ_REGS_STAT_SEQ_CFG_5(a) 0x0 /* PF_BAR0 */
2010 #define busnum_ODY_SPIX_DEV_SEQ_REGS_STAT_SEQ_CFG_5(a) (a)
2011 #define arguments_ODY_SPIX_DEV_SEQ_REGS_STAT_SEQ_CFG_5(a) (a), -1, -1, -1
2012
2013 /**
2014 * Register (NCB32b) spi#_dev_seq_regs_stat_seq_cfg_7
2015 *
2016 * SPI Dev Seq Regs Stat Seq Cfg 7 Register
2017 * to configure status checking sequence for PROFILE 1, SPI NAND and PROFILE 2
2018 * - HF in ACMD and
2019 * DIRECT work modes.
2020 */
2021 union ody_spix_dev_seq_regs_stat_seq_cfg_7 {
2022 uint32_t u;
2023 struct ody_spix_dev_seq_regs_stat_seq_cfg_7_s {
2024 uint32_t stat_seq_dev_rdy_addr : 32;
2025 } s;
2026 /* struct ody_spix_dev_seq_regs_stat_seq_cfg_7_s cn; */
2027 };
2028 typedef union ody_spix_dev_seq_regs_stat_seq_cfg_7 ody_spix_dev_seq_regs_stat_seq_cfg_7_t;
2029
2030 static inline uint64_t ODY_SPIX_DEV_SEQ_REGS_STAT_SEQ_CFG_7(uint64_t a) __attribute__ ((pure, always_inline));
ODY_SPIX_DEV_SEQ_REGS_STAT_SEQ_CFG_7(uint64_t a)2031 static inline uint64_t ODY_SPIX_DEV_SEQ_REGS_STAT_SEQ_CFG_7(uint64_t a)
2032 {
2033 if (a <= 1)
2034 return 0x80400000046cll + 0x1000000000ll * ((a) & 0x1);
2035 __ody_csr_fatal("SPIX_DEV_SEQ_REGS_STAT_SEQ_CFG_7", 1, a, 0, 0, 0, 0, 0);
2036 }
2037
2038 #define typedef_ODY_SPIX_DEV_SEQ_REGS_STAT_SEQ_CFG_7(a) ody_spix_dev_seq_regs_stat_seq_cfg_7_t
2039 #define bustype_ODY_SPIX_DEV_SEQ_REGS_STAT_SEQ_CFG_7(a) CSR_TYPE_NCB32b
2040 #define basename_ODY_SPIX_DEV_SEQ_REGS_STAT_SEQ_CFG_7(a) "SPIX_DEV_SEQ_REGS_STAT_SEQ_CFG_7"
2041 #define device_bar_ODY_SPIX_DEV_SEQ_REGS_STAT_SEQ_CFG_7(a) 0x0 /* PF_BAR0 */
2042 #define busnum_ODY_SPIX_DEV_SEQ_REGS_STAT_SEQ_CFG_7(a) (a)
2043 #define arguments_ODY_SPIX_DEV_SEQ_REGS_STAT_SEQ_CFG_7(a) (a), -1, -1, -1
2044
2045 /**
2046 * Register (NCB32b) spi#_dev_seq_regs_stat_seq_cfg_8
2047 *
2048 * SPI Dev Seq Regs Stat Seq Cfg 8 Register
2049 * to configure status checking sequence for PROFILE 1, SPI NAND and PROFILE 2
2050 * -HF in ACMD and
2051 * DIRECT work modes.
2052 */
2053 union ody_spix_dev_seq_regs_stat_seq_cfg_8 {
2054 uint32_t u;
2055 struct ody_spix_dev_seq_regs_stat_seq_cfg_8_s {
2056 uint32_t stat_seq_prog_fail_addr : 32;
2057 } s;
2058 /* struct ody_spix_dev_seq_regs_stat_seq_cfg_8_s cn; */
2059 };
2060 typedef union ody_spix_dev_seq_regs_stat_seq_cfg_8 ody_spix_dev_seq_regs_stat_seq_cfg_8_t;
2061
2062 static inline uint64_t ODY_SPIX_DEV_SEQ_REGS_STAT_SEQ_CFG_8(uint64_t a) __attribute__ ((pure, always_inline));
ODY_SPIX_DEV_SEQ_REGS_STAT_SEQ_CFG_8(uint64_t a)2063 static inline uint64_t ODY_SPIX_DEV_SEQ_REGS_STAT_SEQ_CFG_8(uint64_t a)
2064 {
2065 if (a <= 1)
2066 return 0x804000000470ll + 0x1000000000ll * ((a) & 0x1);
2067 __ody_csr_fatal("SPIX_DEV_SEQ_REGS_STAT_SEQ_CFG_8", 1, a, 0, 0, 0, 0, 0);
2068 }
2069
2070 #define typedef_ODY_SPIX_DEV_SEQ_REGS_STAT_SEQ_CFG_8(a) ody_spix_dev_seq_regs_stat_seq_cfg_8_t
2071 #define bustype_ODY_SPIX_DEV_SEQ_REGS_STAT_SEQ_CFG_8(a) CSR_TYPE_NCB32b
2072 #define basename_ODY_SPIX_DEV_SEQ_REGS_STAT_SEQ_CFG_8(a) "SPIX_DEV_SEQ_REGS_STAT_SEQ_CFG_8"
2073 #define device_bar_ODY_SPIX_DEV_SEQ_REGS_STAT_SEQ_CFG_8(a) 0x0 /* PF_BAR0 */
2074 #define busnum_ODY_SPIX_DEV_SEQ_REGS_STAT_SEQ_CFG_8(a) (a)
2075 #define arguments_ODY_SPIX_DEV_SEQ_REGS_STAT_SEQ_CFG_8(a) (a), -1, -1, -1
2076
2077 /**
2078 * Register (NCB32b) spi#_dev_seq_regs_stat_seq_cfg_9
2079 *
2080 * SPI Dev Seq Regs Stat Seq Cfg 9 Register
2081 * to configure status checking sequence for PROFILE 1, SPI NAND and PROFILE 2
2082 * - HF in ACMD work
2083 * mode.
2084 */
2085 union ody_spix_dev_seq_regs_stat_seq_cfg_9 {
2086 uint32_t u;
2087 struct ody_spix_dev_seq_regs_stat_seq_cfg_9_s {
2088 uint32_t stat_seq_ers_fail_addr : 32;
2089 } s;
2090 /* struct ody_spix_dev_seq_regs_stat_seq_cfg_9_s cn; */
2091 };
2092 typedef union ody_spix_dev_seq_regs_stat_seq_cfg_9 ody_spix_dev_seq_regs_stat_seq_cfg_9_t;
2093
2094 static inline uint64_t ODY_SPIX_DEV_SEQ_REGS_STAT_SEQ_CFG_9(uint64_t a) __attribute__ ((pure, always_inline));
ODY_SPIX_DEV_SEQ_REGS_STAT_SEQ_CFG_9(uint64_t a)2095 static inline uint64_t ODY_SPIX_DEV_SEQ_REGS_STAT_SEQ_CFG_9(uint64_t a)
2096 {
2097 if (a <= 1)
2098 return 0x804000000474ll + 0x1000000000ll * ((a) & 0x1);
2099 __ody_csr_fatal("SPIX_DEV_SEQ_REGS_STAT_SEQ_CFG_9", 1, a, 0, 0, 0, 0, 0);
2100 }
2101
2102 #define typedef_ODY_SPIX_DEV_SEQ_REGS_STAT_SEQ_CFG_9(a) ody_spix_dev_seq_regs_stat_seq_cfg_9_t
2103 #define bustype_ODY_SPIX_DEV_SEQ_REGS_STAT_SEQ_CFG_9(a) CSR_TYPE_NCB32b
2104 #define basename_ODY_SPIX_DEV_SEQ_REGS_STAT_SEQ_CFG_9(a) "SPIX_DEV_SEQ_REGS_STAT_SEQ_CFG_9"
2105 #define device_bar_ODY_SPIX_DEV_SEQ_REGS_STAT_SEQ_CFG_9(a) 0x0 /* PF_BAR0 */
2106 #define busnum_ODY_SPIX_DEV_SEQ_REGS_STAT_SEQ_CFG_9(a) (a)
2107 #define arguments_ODY_SPIX_DEV_SEQ_REGS_STAT_SEQ_CFG_9(a) (a), -1, -1, -1
2108
2109 /**
2110 * Register (NCB32b) spi#_dev_seq_regs_we_seq_cfg_0
2111 *
2112 * SPI Dev Seq Regs We Seq Cfg 0 Register
2113 * to configure Write Enable Latch (WEL) sequence for PROFILE 1 and SPI NAND
2114 * in ACMD and DIRECT
2115 * work modes.
2116 */
2117 union ody_spix_dev_seq_regs_we_seq_cfg_0 {
2118 uint32_t u;
2119 struct ody_spix_dev_seq_regs_we_seq_cfg_0_s {
2120 uint32_t we_seq_p1_cmd_val : 8;
2121 uint32_t we_seq_p1_cmd_ios : 2;
2122 uint32_t reserved_10 : 1;
2123 uint32_t we_seq_p1_cmd_edge : 1;
2124 uint32_t reserved_12_14 : 3;
2125 uint32_t we_seq_p1_cmd_ext_en : 1;
2126 uint32_t we_seq_p1_cmd_ext_val : 8;
2127 uint32_t we_seq_p1_en : 1;
2128 uint32_t reserved_25_31 : 7;
2129 } s;
2130 /* struct ody_spix_dev_seq_regs_we_seq_cfg_0_s cn; */
2131 };
2132 typedef union ody_spix_dev_seq_regs_we_seq_cfg_0 ody_spix_dev_seq_regs_we_seq_cfg_0_t;
2133
2134 static inline uint64_t ODY_SPIX_DEV_SEQ_REGS_WE_SEQ_CFG_0(uint64_t a) __attribute__ ((pure, always_inline));
ODY_SPIX_DEV_SEQ_REGS_WE_SEQ_CFG_0(uint64_t a)2135 static inline uint64_t ODY_SPIX_DEV_SEQ_REGS_WE_SEQ_CFG_0(uint64_t a)
2136 {
2137 if (a <= 1)
2138 return 0x804000000440ll + 0x1000000000ll * ((a) & 0x1);
2139 __ody_csr_fatal("SPIX_DEV_SEQ_REGS_WE_SEQ_CFG_0", 1, a, 0, 0, 0, 0, 0);
2140 }
2141
2142 #define typedef_ODY_SPIX_DEV_SEQ_REGS_WE_SEQ_CFG_0(a) ody_spix_dev_seq_regs_we_seq_cfg_0_t
2143 #define bustype_ODY_SPIX_DEV_SEQ_REGS_WE_SEQ_CFG_0(a) CSR_TYPE_NCB32b
2144 #define basename_ODY_SPIX_DEV_SEQ_REGS_WE_SEQ_CFG_0(a) "SPIX_DEV_SEQ_REGS_WE_SEQ_CFG_0"
2145 #define device_bar_ODY_SPIX_DEV_SEQ_REGS_WE_SEQ_CFG_0(a) 0x0 /* PF_BAR0 */
2146 #define busnum_ODY_SPIX_DEV_SEQ_REGS_WE_SEQ_CFG_0(a) (a)
2147 #define arguments_ODY_SPIX_DEV_SEQ_REGS_WE_SEQ_CFG_0(a) (a), -1, -1, -1
2148
2149 /**
2150 * Register (NCB) spi#_direct_access#
2151 *
2152 * SPI Flash Direct map Registers
2153 * This register is for memory mapping the external Flash Device to access it in direct mode.
2154 * A read transaction to this register would initiate a SPI Read transfer.
2155 */
2156 union ody_spix_direct_accessx {
2157 uint64_t u;
2158 struct ody_spix_direct_accessx_s {
2159 uint64_t data : 64;
2160 } s;
2161 /* struct ody_spix_direct_accessx_s cn; */
2162 };
2163 typedef union ody_spix_direct_accessx ody_spix_direct_accessx_t;
2164
2165 static inline uint64_t ODY_SPIX_DIRECT_ACCESSX(uint64_t a, uint64_t b) __attribute__ ((pure, always_inline));
ODY_SPIX_DIRECT_ACCESSX(uint64_t a,uint64_t b)2166 static inline uint64_t ODY_SPIX_DIRECT_ACCESSX(uint64_t a, uint64_t b)
2167 {
2168 if ((a <= 1) && (b <= 65535))
2169 return 0x804010000000ll + 0x1000000000ll * ((a) & 0x1) + 8ll * ((b) & 0xffff);
2170 __ody_csr_fatal("SPIX_DIRECT_ACCESSX", 2, a, b, 0, 0, 0, 0);
2171 }
2172
2173 #define typedef_ODY_SPIX_DIRECT_ACCESSX(a, b) ody_spix_direct_accessx_t
2174 #define bustype_ODY_SPIX_DIRECT_ACCESSX(a, b) CSR_TYPE_NCB
2175 #define basename_ODY_SPIX_DIRECT_ACCESSX(a, b) "SPIX_DIRECT_ACCESSX"
2176 #define device_bar_ODY_SPIX_DIRECT_ACCESSX(a, b) 0x0 /* PF_BAR0 */
2177 #define busnum_ODY_SPIX_DIRECT_ACCESSX(a, b) (a)
2178 #define arguments_ODY_SPIX_DIRECT_ACCESSX(a, b) (a), (b), -1, -1
2179
2180 /**
2181 * Register (NCB) spi#_msix_pba#
2182 *
2183 * SPI MSI-X Pending Bit Array Registers
2184 * This register is the MSI-X PBA table, the bit number is indexed by the SPI_INT_VEC_E enumeration.
2185 */
2186 union ody_spix_msix_pbax {
2187 uint64_t u;
2188 struct ody_spix_msix_pbax_s {
2189 uint64_t pend : 64;
2190 } s;
2191 /* struct ody_spix_msix_pbax_s cn; */
2192 };
2193 typedef union ody_spix_msix_pbax ody_spix_msix_pbax_t;
2194
2195 static inline uint64_t ODY_SPIX_MSIX_PBAX(uint64_t a, uint64_t b) __attribute__ ((pure, always_inline));
ODY_SPIX_MSIX_PBAX(uint64_t a,uint64_t b)2196 static inline uint64_t ODY_SPIX_MSIX_PBAX(uint64_t a, uint64_t b)
2197 {
2198 if ((a <= 1) && (b == 0))
2199 return 0x8041000f0000ll + 0x1000000000ll * ((a) & 0x1);
2200 __ody_csr_fatal("SPIX_MSIX_PBAX", 2, a, b, 0, 0, 0, 0);
2201 }
2202
2203 #define typedef_ODY_SPIX_MSIX_PBAX(a, b) ody_spix_msix_pbax_t
2204 #define bustype_ODY_SPIX_MSIX_PBAX(a, b) CSR_TYPE_NCB
2205 #define basename_ODY_SPIX_MSIX_PBAX(a, b) "SPIX_MSIX_PBAX"
2206 #define device_bar_ODY_SPIX_MSIX_PBAX(a, b) 0x4 /* PF_BAR4 */
2207 #define busnum_ODY_SPIX_MSIX_PBAX(a, b) (a)
2208 #define arguments_ODY_SPIX_MSIX_PBAX(a, b) (a), (b), -1, -1
2209
2210 /**
2211 * Register (NCB) spi#_msix_vec#_addr
2212 *
2213 * SPI MSI-X Vector Table Address Registers
2214 * This register is the MSI-X vector table, indexed by the SPI_INT_VEC_E enumeration.
2215 */
2216 union ody_spix_msix_vecx_addr {
2217 uint64_t u;
2218 struct ody_spix_msix_vecx_addr_s {
2219 uint64_t secvec : 1;
2220 uint64_t reserved_1 : 1;
2221 uint64_t addr : 51;
2222 uint64_t reserved_53_63 : 11;
2223 } s;
2224 /* struct ody_spix_msix_vecx_addr_s cn; */
2225 };
2226 typedef union ody_spix_msix_vecx_addr ody_spix_msix_vecx_addr_t;
2227
2228 static inline uint64_t ODY_SPIX_MSIX_VECX_ADDR(uint64_t a, uint64_t b) __attribute__ ((pure, always_inline));
ODY_SPIX_MSIX_VECX_ADDR(uint64_t a,uint64_t b)2229 static inline uint64_t ODY_SPIX_MSIX_VECX_ADDR(uint64_t a, uint64_t b)
2230 {
2231 if ((a <= 1) && (b == 0))
2232 return 0x804100000000ll + 0x1000000000ll * ((a) & 0x1);
2233 __ody_csr_fatal("SPIX_MSIX_VECX_ADDR", 2, a, b, 0, 0, 0, 0);
2234 }
2235
2236 #define typedef_ODY_SPIX_MSIX_VECX_ADDR(a, b) ody_spix_msix_vecx_addr_t
2237 #define bustype_ODY_SPIX_MSIX_VECX_ADDR(a, b) CSR_TYPE_NCB
2238 #define basename_ODY_SPIX_MSIX_VECX_ADDR(a, b) "SPIX_MSIX_VECX_ADDR"
2239 #define device_bar_ODY_SPIX_MSIX_VECX_ADDR(a, b) 0x4 /* PF_BAR4 */
2240 #define busnum_ODY_SPIX_MSIX_VECX_ADDR(a, b) (a)
2241 #define arguments_ODY_SPIX_MSIX_VECX_ADDR(a, b) (a), (b), -1, -1
2242
2243 /**
2244 * Register (NCB) spi#_msix_vec#_ctl
2245 *
2246 * SPI MSI-X Vector Table Control and Data Registers
2247 * This register is the MSI-X vector table, indexed by the SPI_INT_VEC_E enumeration.
2248 */
2249 union ody_spix_msix_vecx_ctl {
2250 uint64_t u;
2251 struct ody_spix_msix_vecx_ctl_s {
2252 uint64_t data : 32;
2253 uint64_t mask : 1;
2254 uint64_t reserved_33_63 : 31;
2255 } s;
2256 /* struct ody_spix_msix_vecx_ctl_s cn; */
2257 };
2258 typedef union ody_spix_msix_vecx_ctl ody_spix_msix_vecx_ctl_t;
2259
2260 static inline uint64_t ODY_SPIX_MSIX_VECX_CTL(uint64_t a, uint64_t b) __attribute__ ((pure, always_inline));
ODY_SPIX_MSIX_VECX_CTL(uint64_t a,uint64_t b)2261 static inline uint64_t ODY_SPIX_MSIX_VECX_CTL(uint64_t a, uint64_t b)
2262 {
2263 if ((a <= 1) && (b == 0))
2264 return 0x804100000008ll + 0x1000000000ll * ((a) & 0x1);
2265 __ody_csr_fatal("SPIX_MSIX_VECX_CTL", 2, a, b, 0, 0, 0, 0);
2266 }
2267
2268 #define typedef_ODY_SPIX_MSIX_VECX_CTL(a, b) ody_spix_msix_vecx_ctl_t
2269 #define bustype_ODY_SPIX_MSIX_VECX_CTL(a, b) CSR_TYPE_NCB
2270 #define basename_ODY_SPIX_MSIX_VECX_CTL(a, b) "SPIX_MSIX_VECX_CTL"
2271 #define device_bar_ODY_SPIX_MSIX_VECX_CTL(a, b) 0x4 /* PF_BAR4 */
2272 #define busnum_ODY_SPIX_MSIX_VECX_CTL(a, b) (a)
2273 #define arguments_ODY_SPIX_MSIX_VECX_CTL(a, b) (a), (b), -1, -1
2274
2275 /**
2276 * Register (NCB32b) spi#_phy_ctb_rfile_phy_ctrl
2277 *
2278 * SPI PHY Ctb Rfile PHY Control Register
2279 * This register handles the global control settings for the PHY.
2280 */
2281 union ody_spix_phy_ctb_rfile_phy_ctrl {
2282 uint32_t u;
2283 struct ody_spix_phy_ctb_rfile_phy_ctrl_s {
2284 uint32_t ctrl_clkperiod_delay : 1;
2285 uint32_t reserved_1_3 : 3;
2286 uint32_t phony_dqs_timing : 6;
2287 uint32_t reserved_10_13 : 4;
2288 uint32_t sdr_dqs_value : 1;
2289 uint32_t reserved_15_19 : 5;
2290 uint32_t low_freq_sel : 1;
2291 uint32_t pu_pd_polarity : 1;
2292 uint32_t reserved_22_31 : 10;
2293 } s;
2294 /* struct ody_spix_phy_ctb_rfile_phy_ctrl_s cn; */
2295 };
2296 typedef union ody_spix_phy_ctb_rfile_phy_ctrl ody_spix_phy_ctb_rfile_phy_ctrl_t;
2297
2298 static inline uint64_t ODY_SPIX_PHY_CTB_RFILE_PHY_CTRL(uint64_t a) __attribute__ ((pure, always_inline));
ODY_SPIX_PHY_CTB_RFILE_PHY_CTRL(uint64_t a)2299 static inline uint64_t ODY_SPIX_PHY_CTB_RFILE_PHY_CTRL(uint64_t a)
2300 {
2301 if (a <= 1)
2302 return 0x804000002080ll + 0x1000000000ll * ((a) & 0x1);
2303 __ody_csr_fatal("SPIX_PHY_CTB_RFILE_PHY_CTRL", 1, a, 0, 0, 0, 0, 0);
2304 }
2305
2306 #define typedef_ODY_SPIX_PHY_CTB_RFILE_PHY_CTRL(a) ody_spix_phy_ctb_rfile_phy_ctrl_t
2307 #define bustype_ODY_SPIX_PHY_CTB_RFILE_PHY_CTRL(a) CSR_TYPE_NCB32b
2308 #define basename_ODY_SPIX_PHY_CTB_RFILE_PHY_CTRL(a) "SPIX_PHY_CTB_RFILE_PHY_CTRL"
2309 #define device_bar_ODY_SPIX_PHY_CTB_RFILE_PHY_CTRL(a) 0x0 /* PF_BAR0 */
2310 #define busnum_ODY_SPIX_PHY_CTB_RFILE_PHY_CTRL(a) (a)
2311 #define arguments_ODY_SPIX_PHY_CTB_RFILE_PHY_CTRL(a) (a), -1, -1, -1
2312
2313 /**
2314 * Register (NCB32b) spi#_phy_ctb_rfile_phy_gpio_ctrl_0
2315 *
2316 * SPI PHY Ctb Rfile PHY Gpio Control 0 Register
2317 * This register is a general purpose register. The [31:0]vector is brought to the PHY I/Os. User may
2318 * choose to use these pins to control any static settings that may be required for
2319 * connected I/O pads.
2320 */
2321 union ody_spix_phy_ctb_rfile_phy_gpio_ctrl_0 {
2322 uint32_t u;
2323 struct ody_spix_phy_ctb_rfile_phy_gpio_ctrl_0_s {
2324 uint32_t phy_gpio_ctrl_0_value : 32;
2325 } s;
2326 /* struct ody_spix_phy_ctb_rfile_phy_gpio_ctrl_0_s cn; */
2327 };
2328 typedef union ody_spix_phy_ctb_rfile_phy_gpio_ctrl_0 ody_spix_phy_ctb_rfile_phy_gpio_ctrl_0_t;
2329
2330 static inline uint64_t ODY_SPIX_PHY_CTB_RFILE_PHY_GPIO_CTRL_0(uint64_t a) __attribute__ ((pure, always_inline));
ODY_SPIX_PHY_CTB_RFILE_PHY_GPIO_CTRL_0(uint64_t a)2331 static inline uint64_t ODY_SPIX_PHY_CTB_RFILE_PHY_GPIO_CTRL_0(uint64_t a)
2332 {
2333 if (a <= 1)
2334 return 0x804000002088ll + 0x1000000000ll * ((a) & 0x1);
2335 __ody_csr_fatal("SPIX_PHY_CTB_RFILE_PHY_GPIO_CTRL_0", 1, a, 0, 0, 0, 0, 0);
2336 }
2337
2338 #define typedef_ODY_SPIX_PHY_CTB_RFILE_PHY_GPIO_CTRL_0(a) ody_spix_phy_ctb_rfile_phy_gpio_ctrl_0_t
2339 #define bustype_ODY_SPIX_PHY_CTB_RFILE_PHY_GPIO_CTRL_0(a) CSR_TYPE_NCB32b
2340 #define basename_ODY_SPIX_PHY_CTB_RFILE_PHY_GPIO_CTRL_0(a) "SPIX_PHY_CTB_RFILE_PHY_GPIO_CTRL_0"
2341 #define device_bar_ODY_SPIX_PHY_CTB_RFILE_PHY_GPIO_CTRL_0(a) 0x0 /* PF_BAR0 */
2342 #define busnum_ODY_SPIX_PHY_CTB_RFILE_PHY_GPIO_CTRL_0(a) (a)
2343 #define arguments_ODY_SPIX_PHY_CTB_RFILE_PHY_GPIO_CTRL_0(a) (a), -1, -1, -1
2344
2345 /**
2346 * Register (NCB32b) spi#_phy_ctb_rfile_phy_gpio_ctrl_1
2347 *
2348 * SPI PHY Ctb Rfile PHY Gpio Control 1 Register
2349 * This register is a general purpose register. The [31:0] vector is brought to the PHY I/Os. User may
2350 * choose to use these pins to control any static settings that may be required for the
2351 * connected I/O pads.
2352 */
2353 union ody_spix_phy_ctb_rfile_phy_gpio_ctrl_1 {
2354 uint32_t u;
2355 struct ody_spix_phy_ctb_rfile_phy_gpio_ctrl_1_s {
2356 uint32_t phy_gpio_ctrl_1_value : 32;
2357 } s;
2358 /* struct ody_spix_phy_ctb_rfile_phy_gpio_ctrl_1_s cn; */
2359 };
2360 typedef union ody_spix_phy_ctb_rfile_phy_gpio_ctrl_1 ody_spix_phy_ctb_rfile_phy_gpio_ctrl_1_t;
2361
2362 static inline uint64_t ODY_SPIX_PHY_CTB_RFILE_PHY_GPIO_CTRL_1(uint64_t a) __attribute__ ((pure, always_inline));
ODY_SPIX_PHY_CTB_RFILE_PHY_GPIO_CTRL_1(uint64_t a)2363 static inline uint64_t ODY_SPIX_PHY_CTB_RFILE_PHY_GPIO_CTRL_1(uint64_t a)
2364 {
2365 if (a <= 1)
2366 return 0x80400000208cll + 0x1000000000ll * ((a) & 0x1);
2367 __ody_csr_fatal("SPIX_PHY_CTB_RFILE_PHY_GPIO_CTRL_1", 1, a, 0, 0, 0, 0, 0);
2368 }
2369
2370 #define typedef_ODY_SPIX_PHY_CTB_RFILE_PHY_GPIO_CTRL_1(a) ody_spix_phy_ctb_rfile_phy_gpio_ctrl_1_t
2371 #define bustype_ODY_SPIX_PHY_CTB_RFILE_PHY_GPIO_CTRL_1(a) CSR_TYPE_NCB32b
2372 #define basename_ODY_SPIX_PHY_CTB_RFILE_PHY_GPIO_CTRL_1(a) "SPIX_PHY_CTB_RFILE_PHY_GPIO_CTRL_1"
2373 #define device_bar_ODY_SPIX_PHY_CTB_RFILE_PHY_GPIO_CTRL_1(a) 0x0 /* PF_BAR0 */
2374 #define busnum_ODY_SPIX_PHY_CTB_RFILE_PHY_GPIO_CTRL_1(a) (a)
2375 #define arguments_ODY_SPIX_PHY_CTB_RFILE_PHY_GPIO_CTRL_1(a) (a), -1, -1, -1
2376
2377 /**
2378 * Register (NCB32b) spi#_phy_ctb_rfile_phy_gpio_status_0
2379 *
2380 * SPI PHY Ctb Rfile PHY Gpio Status 0 Register
2381 * This register is a general purpose register. A [31:0] vector is brought from the PHY I/Os to this
2382 * register. User may choose to use this as a status register.
2383 */
2384 union ody_spix_phy_ctb_rfile_phy_gpio_status_0 {
2385 uint32_t u;
2386 struct ody_spix_phy_ctb_rfile_phy_gpio_status_0_s {
2387 uint32_t phy_gpio_status_0_value : 32;
2388 } s;
2389 /* struct ody_spix_phy_ctb_rfile_phy_gpio_status_0_s cn; */
2390 };
2391 typedef union ody_spix_phy_ctb_rfile_phy_gpio_status_0 ody_spix_phy_ctb_rfile_phy_gpio_status_0_t;
2392
2393 static inline uint64_t ODY_SPIX_PHY_CTB_RFILE_PHY_GPIO_STATUS_0(uint64_t a) __attribute__ ((pure, always_inline));
ODY_SPIX_PHY_CTB_RFILE_PHY_GPIO_STATUS_0(uint64_t a)2394 static inline uint64_t ODY_SPIX_PHY_CTB_RFILE_PHY_GPIO_STATUS_0(uint64_t a)
2395 {
2396 if (a <= 1)
2397 return 0x804000002090ll + 0x1000000000ll * ((a) & 0x1);
2398 __ody_csr_fatal("SPIX_PHY_CTB_RFILE_PHY_GPIO_STATUS_0", 1, a, 0, 0, 0, 0, 0);
2399 }
2400
2401 #define typedef_ODY_SPIX_PHY_CTB_RFILE_PHY_GPIO_STATUS_0(a) ody_spix_phy_ctb_rfile_phy_gpio_status_0_t
2402 #define bustype_ODY_SPIX_PHY_CTB_RFILE_PHY_GPIO_STATUS_0(a) CSR_TYPE_NCB32b
2403 #define basename_ODY_SPIX_PHY_CTB_RFILE_PHY_GPIO_STATUS_0(a) "SPIX_PHY_CTB_RFILE_PHY_GPIO_STATUS_0"
2404 #define device_bar_ODY_SPIX_PHY_CTB_RFILE_PHY_GPIO_STATUS_0(a) 0x0 /* PF_BAR0 */
2405 #define busnum_ODY_SPIX_PHY_CTB_RFILE_PHY_GPIO_STATUS_0(a) (a)
2406 #define arguments_ODY_SPIX_PHY_CTB_RFILE_PHY_GPIO_STATUS_0(a) (a), -1, -1, -1
2407
2408 /**
2409 * Register (NCB32b) spi#_phy_ctb_rfile_phy_gpio_status_1
2410 *
2411 * SPI PHY Ctb Rfile PHY Gpio Status 1 Register
2412 * This register is a general purpose register. A [31:0] vector is brought from the PHY IOs to this
2413 * register. User may choose to use this as a status register.
2414 */
2415 union ody_spix_phy_ctb_rfile_phy_gpio_status_1 {
2416 uint32_t u;
2417 struct ody_spix_phy_ctb_rfile_phy_gpio_status_1_s {
2418 uint32_t phy_gpio_status_1_value : 32;
2419 } s;
2420 /* struct ody_spix_phy_ctb_rfile_phy_gpio_status_1_s cn; */
2421 };
2422 typedef union ody_spix_phy_ctb_rfile_phy_gpio_status_1 ody_spix_phy_ctb_rfile_phy_gpio_status_1_t;
2423
2424 static inline uint64_t ODY_SPIX_PHY_CTB_RFILE_PHY_GPIO_STATUS_1(uint64_t a) __attribute__ ((pure, always_inline));
ODY_SPIX_PHY_CTB_RFILE_PHY_GPIO_STATUS_1(uint64_t a)2425 static inline uint64_t ODY_SPIX_PHY_CTB_RFILE_PHY_GPIO_STATUS_1(uint64_t a)
2426 {
2427 if (a <= 1)
2428 return 0x804000002094ll + 0x1000000000ll * ((a) & 0x1);
2429 __ody_csr_fatal("SPIX_PHY_CTB_RFILE_PHY_GPIO_STATUS_1", 1, a, 0, 0, 0, 0, 0);
2430 }
2431
2432 #define typedef_ODY_SPIX_PHY_CTB_RFILE_PHY_GPIO_STATUS_1(a) ody_spix_phy_ctb_rfile_phy_gpio_status_1_t
2433 #define bustype_ODY_SPIX_PHY_CTB_RFILE_PHY_GPIO_STATUS_1(a) CSR_TYPE_NCB32b
2434 #define basename_ODY_SPIX_PHY_CTB_RFILE_PHY_GPIO_STATUS_1(a) "SPIX_PHY_CTB_RFILE_PHY_GPIO_STATUS_1"
2435 #define device_bar_ODY_SPIX_PHY_CTB_RFILE_PHY_GPIO_STATUS_1(a) 0x0 /* PF_BAR0 */
2436 #define busnum_ODY_SPIX_PHY_CTB_RFILE_PHY_GPIO_STATUS_1(a) (a)
2437 #define arguments_ODY_SPIX_PHY_CTB_RFILE_PHY_GPIO_STATUS_1(a) (a), -1, -1, -1
2438
2439 /**
2440 * Register (NCB32b) spi#_phy_ctb_rfile_phy_tsel
2441 *
2442 * SPI PHY Ctb Rfile PHY Tsel Register
2443 * This register handles the global control settings for the termination selects for reads.
2444 * For SD and XSPI controllers this should be disabled.
2445 */
2446 union ody_spix_phy_ctb_rfile_phy_tsel {
2447 uint32_t u;
2448 struct ody_spix_phy_ctb_rfile_phy_tsel_s {
2449 uint32_t reserved_0_7 : 8;
2450 uint32_t tsel_rd_value_dqs : 4;
2451 uint32_t tsel_off_value_dqs : 4;
2452 uint32_t tsel_rd_value_data : 4;
2453 uint32_t tsel_off_value_data : 4;
2454 uint32_t reserved_24_31 : 8;
2455 } s;
2456 /* struct ody_spix_phy_ctb_rfile_phy_tsel_s cn; */
2457 };
2458 typedef union ody_spix_phy_ctb_rfile_phy_tsel ody_spix_phy_ctb_rfile_phy_tsel_t;
2459
2460 static inline uint64_t ODY_SPIX_PHY_CTB_RFILE_PHY_TSEL(uint64_t a) __attribute__ ((pure, always_inline));
ODY_SPIX_PHY_CTB_RFILE_PHY_TSEL(uint64_t a)2461 static inline uint64_t ODY_SPIX_PHY_CTB_RFILE_PHY_TSEL(uint64_t a)
2462 {
2463 if (a <= 1)
2464 return 0x804000002084ll + 0x1000000000ll * ((a) & 0x1);
2465 __ody_csr_fatal("SPIX_PHY_CTB_RFILE_PHY_TSEL", 1, a, 0, 0, 0, 0, 0);
2466 }
2467
2468 #define typedef_ODY_SPIX_PHY_CTB_RFILE_PHY_TSEL(a) ody_spix_phy_ctb_rfile_phy_tsel_t
2469 #define bustype_ODY_SPIX_PHY_CTB_RFILE_PHY_TSEL(a) CSR_TYPE_NCB32b
2470 #define basename_ODY_SPIX_PHY_CTB_RFILE_PHY_TSEL(a) "SPIX_PHY_CTB_RFILE_PHY_TSEL"
2471 #define device_bar_ODY_SPIX_PHY_CTB_RFILE_PHY_TSEL(a) 0x0 /* PF_BAR0 */
2472 #define busnum_ODY_SPIX_PHY_CTB_RFILE_PHY_TSEL(a) (a)
2473 #define arguments_ODY_SPIX_PHY_CTB_RFILE_PHY_TSEL(a) (a), -1, -1, -1
2474
2475 /**
2476 * Register (NCB32b) spi#_phy_dataslice_rfile_phy_dll_master_ctrl
2477 *
2478 * SPI PHY Dataslice Rfile PHY DLL Master Control Register
2479 * This register holds the control for the master DLL logic.
2480 */
2481 union ody_spix_phy_dataslice_rfile_phy_dll_master_ctrl {
2482 uint32_t u;
2483 struct ody_spix_phy_dataslice_rfile_phy_dll_master_ctrl_s {
2484 uint32_t param_dll_start_point : 8;
2485 uint32_t reserved_8_15 : 8;
2486 uint32_t param_dll_lock_num : 3;
2487 uint32_t reserved_19 : 1;
2488 uint32_t param_phase_detect_sel : 3;
2489 uint32_t param_dll_bypass_mode : 1;
2490 uint32_t reserved_24_31 : 8;
2491 } s;
2492 /* struct ody_spix_phy_dataslice_rfile_phy_dll_master_ctrl_s cn; */
2493 };
2494 typedef union ody_spix_phy_dataslice_rfile_phy_dll_master_ctrl ody_spix_phy_dataslice_rfile_phy_dll_master_ctrl_t;
2495
2496 static inline uint64_t ODY_SPIX_PHY_DATASLICE_RFILE_PHY_DLL_MASTER_CTRL(uint64_t a) __attribute__ ((pure, always_inline));
ODY_SPIX_PHY_DATASLICE_RFILE_PHY_DLL_MASTER_CTRL(uint64_t a)2497 static inline uint64_t ODY_SPIX_PHY_DATASLICE_RFILE_PHY_DLL_MASTER_CTRL(uint64_t a)
2498 {
2499 if (a <= 1)
2500 return 0x80400000200cll + 0x1000000000ll * ((a) & 0x1);
2501 __ody_csr_fatal("SPIX_PHY_DATASLICE_RFILE_PHY_DLL_MASTER_CTRL", 1, a, 0, 0, 0, 0, 0);
2502 }
2503
2504 #define typedef_ODY_SPIX_PHY_DATASLICE_RFILE_PHY_DLL_MASTER_CTRL(a) ody_spix_phy_dataslice_rfile_phy_dll_master_ctrl_t
2505 #define bustype_ODY_SPIX_PHY_DATASLICE_RFILE_PHY_DLL_MASTER_CTRL(a) CSR_TYPE_NCB32b
2506 #define basename_ODY_SPIX_PHY_DATASLICE_RFILE_PHY_DLL_MASTER_CTRL(a) "SPIX_PHY_DATASLICE_RFILE_PHY_DLL_MASTER_CTRL"
2507 #define device_bar_ODY_SPIX_PHY_DATASLICE_RFILE_PHY_DLL_MASTER_CTRL(a) 0x0 /* PF_BAR0 */
2508 #define busnum_ODY_SPIX_PHY_DATASLICE_RFILE_PHY_DLL_MASTER_CTRL(a) (a)
2509 #define arguments_ODY_SPIX_PHY_DATASLICE_RFILE_PHY_DLL_MASTER_CTRL(a) (a), -1, -1, -1
2510
2511 /**
2512 * Register (NCB32b) spi#_phy_dataslice_rfile_phy_dll_obs_reg_0
2513 *
2514 * SPI PHY Dataslice Rfile PHY DLL Obs Reg 0 Register
2515 * This register holds the following observable points in the PHY.
2516 */
2517 union ody_spix_phy_dataslice_rfile_phy_dll_obs_reg_0 {
2518 uint32_t u;
2519 struct ody_spix_phy_dataslice_rfile_phy_dll_obs_reg_0_s {
2520 uint32_t dll_lock : 1;
2521 uint32_t dll_locked_mode : 2;
2522 uint32_t dll_unlock_cnt : 5;
2523 uint32_t dll_lock_value : 8;
2524 uint32_t lock_dec_dbg : 8;
2525 uint32_t lock_inc_dbg : 8;
2526 } s;
2527 /* struct ody_spix_phy_dataslice_rfile_phy_dll_obs_reg_0_s cn; */
2528 };
2529 typedef union ody_spix_phy_dataslice_rfile_phy_dll_obs_reg_0 ody_spix_phy_dataslice_rfile_phy_dll_obs_reg_0_t;
2530
2531 static inline uint64_t ODY_SPIX_PHY_DATASLICE_RFILE_PHY_DLL_OBS_REG_0(uint64_t a) __attribute__ ((pure, always_inline));
ODY_SPIX_PHY_DATASLICE_RFILE_PHY_DLL_OBS_REG_0(uint64_t a)2532 static inline uint64_t ODY_SPIX_PHY_DATASLICE_RFILE_PHY_DLL_OBS_REG_0(uint64_t a)
2533 {
2534 if (a <= 1)
2535 return 0x80400000201cll + 0x1000000000ll * ((a) & 0x1);
2536 __ody_csr_fatal("SPIX_PHY_DATASLICE_RFILE_PHY_DLL_OBS_REG_0", 1, a, 0, 0, 0, 0, 0);
2537 }
2538
2539 #define typedef_ODY_SPIX_PHY_DATASLICE_RFILE_PHY_DLL_OBS_REG_0(a) ody_spix_phy_dataslice_rfile_phy_dll_obs_reg_0_t
2540 #define bustype_ODY_SPIX_PHY_DATASLICE_RFILE_PHY_DLL_OBS_REG_0(a) CSR_TYPE_NCB32b
2541 #define basename_ODY_SPIX_PHY_DATASLICE_RFILE_PHY_DLL_OBS_REG_0(a) "SPIX_PHY_DATASLICE_RFILE_PHY_DLL_OBS_REG_0"
2542 #define device_bar_ODY_SPIX_PHY_DATASLICE_RFILE_PHY_DLL_OBS_REG_0(a) 0x0 /* PF_BAR0 */
2543 #define busnum_ODY_SPIX_PHY_DATASLICE_RFILE_PHY_DLL_OBS_REG_0(a) (a)
2544 #define arguments_ODY_SPIX_PHY_DATASLICE_RFILE_PHY_DLL_OBS_REG_0(a) (a), -1, -1, -1
2545
2546 /**
2547 * Register (NCB32b) spi#_phy_dataslice_rfile_phy_dll_obs_reg_1
2548 *
2549 * SPI PHY Dataslice Rfile PHY DLL Obs Reg 1 Register
2550 * This register holds the following observable points in the PHY.
2551 */
2552 union ody_spix_phy_dataslice_rfile_phy_dll_obs_reg_1 {
2553 uint32_t u;
2554 struct ody_spix_phy_dataslice_rfile_phy_dll_obs_reg_1_s {
2555 uint32_t decoder_out_rd : 8;
2556 uint32_t decoder_out_rd_cmd : 8;
2557 uint32_t decoder_out_wr : 8;
2558 uint32_t reserved_24_31 : 8;
2559 } s;
2560 /* struct ody_spix_phy_dataslice_rfile_phy_dll_obs_reg_1_s cn; */
2561 };
2562 typedef union ody_spix_phy_dataslice_rfile_phy_dll_obs_reg_1 ody_spix_phy_dataslice_rfile_phy_dll_obs_reg_1_t;
2563
2564 static inline uint64_t ODY_SPIX_PHY_DATASLICE_RFILE_PHY_DLL_OBS_REG_1(uint64_t a) __attribute__ ((pure, always_inline));
ODY_SPIX_PHY_DATASLICE_RFILE_PHY_DLL_OBS_REG_1(uint64_t a)2565 static inline uint64_t ODY_SPIX_PHY_DATASLICE_RFILE_PHY_DLL_OBS_REG_1(uint64_t a)
2566 {
2567 if (a <= 1)
2568 return 0x804000002020ll + 0x1000000000ll * ((a) & 0x1);
2569 __ody_csr_fatal("SPIX_PHY_DATASLICE_RFILE_PHY_DLL_OBS_REG_1", 1, a, 0, 0, 0, 0, 0);
2570 }
2571
2572 #define typedef_ODY_SPIX_PHY_DATASLICE_RFILE_PHY_DLL_OBS_REG_1(a) ody_spix_phy_dataslice_rfile_phy_dll_obs_reg_1_t
2573 #define bustype_ODY_SPIX_PHY_DATASLICE_RFILE_PHY_DLL_OBS_REG_1(a) CSR_TYPE_NCB32b
2574 #define basename_ODY_SPIX_PHY_DATASLICE_RFILE_PHY_DLL_OBS_REG_1(a) "SPIX_PHY_DATASLICE_RFILE_PHY_DLL_OBS_REG_1"
2575 #define device_bar_ODY_SPIX_PHY_DATASLICE_RFILE_PHY_DLL_OBS_REG_1(a) 0x0 /* PF_BAR0 */
2576 #define busnum_ODY_SPIX_PHY_DATASLICE_RFILE_PHY_DLL_OBS_REG_1(a) (a)
2577 #define arguments_ODY_SPIX_PHY_DATASLICE_RFILE_PHY_DLL_OBS_REG_1(a) (a), -1, -1, -1
2578
2579 /**
2580 * Register (NCB32b) spi#_phy_dataslice_rfile_phy_dll_obs_reg_2
2581 *
2582 * SPI PHY Dataslice Rfile PHY DLL Obs Reg 2 Register
2583 * This register holds the following observable points in the PHY.
2584 */
2585 union ody_spix_phy_dataslice_rfile_phy_dll_obs_reg_2 {
2586 uint32_t u;
2587 struct ody_spix_phy_dataslice_rfile_phy_dll_obs_reg_2_s {
2588 uint32_t decoder_out_wrdqs : 8;
2589 uint32_t reserved_8_31 : 24;
2590 } s;
2591 /* struct ody_spix_phy_dataslice_rfile_phy_dll_obs_reg_2_s cn; */
2592 };
2593 typedef union ody_spix_phy_dataslice_rfile_phy_dll_obs_reg_2 ody_spix_phy_dataslice_rfile_phy_dll_obs_reg_2_t;
2594
2595 static inline uint64_t ODY_SPIX_PHY_DATASLICE_RFILE_PHY_DLL_OBS_REG_2(uint64_t a) __attribute__ ((pure, always_inline));
ODY_SPIX_PHY_DATASLICE_RFILE_PHY_DLL_OBS_REG_2(uint64_t a)2596 static inline uint64_t ODY_SPIX_PHY_DATASLICE_RFILE_PHY_DLL_OBS_REG_2(uint64_t a)
2597 {
2598 if (a <= 1)
2599 return 0x804000002024ll + 0x1000000000ll * ((a) & 0x1);
2600 __ody_csr_fatal("SPIX_PHY_DATASLICE_RFILE_PHY_DLL_OBS_REG_2", 1, a, 0, 0, 0, 0, 0);
2601 }
2602
2603 #define typedef_ODY_SPIX_PHY_DATASLICE_RFILE_PHY_DLL_OBS_REG_2(a) ody_spix_phy_dataslice_rfile_phy_dll_obs_reg_2_t
2604 #define bustype_ODY_SPIX_PHY_DATASLICE_RFILE_PHY_DLL_OBS_REG_2(a) CSR_TYPE_NCB32b
2605 #define basename_ODY_SPIX_PHY_DATASLICE_RFILE_PHY_DLL_OBS_REG_2(a) "SPIX_PHY_DATASLICE_RFILE_PHY_DLL_OBS_REG_2"
2606 #define device_bar_ODY_SPIX_PHY_DATASLICE_RFILE_PHY_DLL_OBS_REG_2(a) 0x0 /* PF_BAR0 */
2607 #define busnum_ODY_SPIX_PHY_DATASLICE_RFILE_PHY_DLL_OBS_REG_2(a) (a)
2608 #define arguments_ODY_SPIX_PHY_DATASLICE_RFILE_PHY_DLL_OBS_REG_2(a) (a), -1, -1, -1
2609
2610 /**
2611 * Register (NCB32b) spi#_phy_dataslice_rfile_phy_dll_slave_ctrl
2612 *
2613 * SPI PHY Dataslice Rfile PHY DLL Slave Control Register
2614 * This register holds the control for the slave DLL logic.
2615 */
2616 union ody_spix_phy_dataslice_rfile_phy_dll_slave_ctrl {
2617 uint32_t u;
2618 struct ody_spix_phy_dataslice_rfile_phy_dll_slave_ctrl_s {
2619 uint32_t read_dqs_delay : 8;
2620 uint32_t clk_wr_delay : 8;
2621 uint32_t clk_wrdqs_delay : 8;
2622 uint32_t read_dqs_cmd_delay : 8;
2623 } s;
2624 /* struct ody_spix_phy_dataslice_rfile_phy_dll_slave_ctrl_s cn; */
2625 };
2626 typedef union ody_spix_phy_dataslice_rfile_phy_dll_slave_ctrl ody_spix_phy_dataslice_rfile_phy_dll_slave_ctrl_t;
2627
2628 static inline uint64_t ODY_SPIX_PHY_DATASLICE_RFILE_PHY_DLL_SLAVE_CTRL(uint64_t a) __attribute__ ((pure, always_inline));
ODY_SPIX_PHY_DATASLICE_RFILE_PHY_DLL_SLAVE_CTRL(uint64_t a)2629 static inline uint64_t ODY_SPIX_PHY_DATASLICE_RFILE_PHY_DLL_SLAVE_CTRL(uint64_t a)
2630 {
2631 if (a <= 1)
2632 return 0x804000002010ll + 0x1000000000ll * ((a) & 0x1);
2633 __ody_csr_fatal("SPIX_PHY_DATASLICE_RFILE_PHY_DLL_SLAVE_CTRL", 1, a, 0, 0, 0, 0, 0);
2634 }
2635
2636 #define typedef_ODY_SPIX_PHY_DATASLICE_RFILE_PHY_DLL_SLAVE_CTRL(a) ody_spix_phy_dataslice_rfile_phy_dll_slave_ctrl_t
2637 #define bustype_ODY_SPIX_PHY_DATASLICE_RFILE_PHY_DLL_SLAVE_CTRL(a) CSR_TYPE_NCB32b
2638 #define basename_ODY_SPIX_PHY_DATASLICE_RFILE_PHY_DLL_SLAVE_CTRL(a) "SPIX_PHY_DATASLICE_RFILE_PHY_DLL_SLAVE_CTRL"
2639 #define device_bar_ODY_SPIX_PHY_DATASLICE_RFILE_PHY_DLL_SLAVE_CTRL(a) 0x0 /* PF_BAR0 */
2640 #define busnum_ODY_SPIX_PHY_DATASLICE_RFILE_PHY_DLL_SLAVE_CTRL(a) (a)
2641 #define arguments_ODY_SPIX_PHY_DATASLICE_RFILE_PHY_DLL_SLAVE_CTRL(a) (a), -1, -1, -1
2642
2643 /**
2644 * Register (NCB32b) spi#_phy_dataslice_rfile_phy_dq_timing
2645 *
2646 * SPI PHY Dataslice Rfile PHY Dq Timing Register
2647 * This register controls the DQ related timing.
2648 */
2649 union ody_spix_phy_dataslice_rfile_phy_dq_timing {
2650 uint32_t u;
2651 struct ody_spix_phy_dataslice_rfile_phy_dq_timing_s {
2652 uint32_t data_select_oe_end : 3;
2653 uint32_t reserved_3 : 1;
2654 uint32_t data_select_oe_start : 3;
2655 uint32_t reserved_7 : 1;
2656 uint32_t data_select_tsel_end : 4;
2657 uint32_t data_select_tsel_start : 4;
2658 uint32_t data_clkperiod_delay : 8;
2659 uint32_t io_mask_start : 3;
2660 uint32_t io_mask_end : 3;
2661 uint32_t reserved_30 : 1;
2662 uint32_t io_mask_always_on : 1;
2663 } s;
2664 /* struct ody_spix_phy_dataslice_rfile_phy_dq_timing_s cn; */
2665 };
2666 typedef union ody_spix_phy_dataslice_rfile_phy_dq_timing ody_spix_phy_dataslice_rfile_phy_dq_timing_t;
2667
2668 static inline uint64_t ODY_SPIX_PHY_DATASLICE_RFILE_PHY_DQ_TIMING(uint64_t a) __attribute__ ((pure, always_inline));
ODY_SPIX_PHY_DATASLICE_RFILE_PHY_DQ_TIMING(uint64_t a)2669 static inline uint64_t ODY_SPIX_PHY_DATASLICE_RFILE_PHY_DQ_TIMING(uint64_t a)
2670 {
2671 if (a <= 1)
2672 return 0x804000002000ll + 0x1000000000ll * ((a) & 0x1);
2673 __ody_csr_fatal("SPIX_PHY_DATASLICE_RFILE_PHY_DQ_TIMING", 1, a, 0, 0, 0, 0, 0);
2674 }
2675
2676 #define typedef_ODY_SPIX_PHY_DATASLICE_RFILE_PHY_DQ_TIMING(a) ody_spix_phy_dataslice_rfile_phy_dq_timing_t
2677 #define bustype_ODY_SPIX_PHY_DATASLICE_RFILE_PHY_DQ_TIMING(a) CSR_TYPE_NCB32b
2678 #define basename_ODY_SPIX_PHY_DATASLICE_RFILE_PHY_DQ_TIMING(a) "SPIX_PHY_DATASLICE_RFILE_PHY_DQ_TIMING"
2679 #define device_bar_ODY_SPIX_PHY_DATASLICE_RFILE_PHY_DQ_TIMING(a) 0x0 /* PF_BAR0 */
2680 #define busnum_ODY_SPIX_PHY_DATASLICE_RFILE_PHY_DQ_TIMING(a) (a)
2681 #define arguments_ODY_SPIX_PHY_DATASLICE_RFILE_PHY_DQ_TIMING(a) (a), -1, -1, -1
2682
2683 /**
2684 * Register (NCB32b) spi#_phy_dataslice_rfile_phy_dqs_timing
2685 *
2686 * SPI PHY Dataslice Rfile PHY DQS Timing Register
2687 * This register controls the DQS related timing.
2688 */
2689 union ody_spix_phy_dataslice_rfile_phy_dqs_timing {
2690 uint32_t u;
2691 struct ody_spix_phy_dataslice_rfile_phy_dqs_timing_s {
2692 uint32_t dqs_select_oe_end : 4;
2693 uint32_t dqs_select_oe_start : 4;
2694 uint32_t dqs_select_tsel_end : 4;
2695 uint32_t dqs_select_tsel_start : 4;
2696 uint32_t phony_dqs_sel : 1;
2697 uint32_t reserved_17_18 : 2;
2698 uint32_t use_phony_dqs_cmd : 1;
2699 uint32_t use_phony_dqs : 1;
2700 uint32_t use_lpbk_dqs : 1;
2701 uint32_t use_ext_lpbk_dqs : 1;
2702 uint32_t dqs_clkperiod_delay : 1;
2703 uint32_t reserved_24_31 : 8;
2704 } s;
2705 /* struct ody_spix_phy_dataslice_rfile_phy_dqs_timing_s cn; */
2706 };
2707 typedef union ody_spix_phy_dataslice_rfile_phy_dqs_timing ody_spix_phy_dataslice_rfile_phy_dqs_timing_t;
2708
2709 static inline uint64_t ODY_SPIX_PHY_DATASLICE_RFILE_PHY_DQS_TIMING(uint64_t a) __attribute__ ((pure, always_inline));
ODY_SPIX_PHY_DATASLICE_RFILE_PHY_DQS_TIMING(uint64_t a)2710 static inline uint64_t ODY_SPIX_PHY_DATASLICE_RFILE_PHY_DQS_TIMING(uint64_t a)
2711 {
2712 if (a <= 1)
2713 return 0x804000002004ll + 0x1000000000ll * ((a) & 0x1);
2714 __ody_csr_fatal("SPIX_PHY_DATASLICE_RFILE_PHY_DQS_TIMING", 1, a, 0, 0, 0, 0, 0);
2715 }
2716
2717 #define typedef_ODY_SPIX_PHY_DATASLICE_RFILE_PHY_DQS_TIMING(a) ody_spix_phy_dataslice_rfile_phy_dqs_timing_t
2718 #define bustype_ODY_SPIX_PHY_DATASLICE_RFILE_PHY_DQS_TIMING(a) CSR_TYPE_NCB32b
2719 #define basename_ODY_SPIX_PHY_DATASLICE_RFILE_PHY_DQS_TIMING(a) "SPIX_PHY_DATASLICE_RFILE_PHY_DQS_TIMING"
2720 #define device_bar_ODY_SPIX_PHY_DATASLICE_RFILE_PHY_DQS_TIMING(a) 0x0 /* PF_BAR0 */
2721 #define busnum_ODY_SPIX_PHY_DATASLICE_RFILE_PHY_DQS_TIMING(a) (a)
2722 #define arguments_ODY_SPIX_PHY_DATASLICE_RFILE_PHY_DQS_TIMING(a) (a), -1, -1, -1
2723
2724 /**
2725 * Register (NCB32b) spi#_phy_dataslice_rfile_phy_features
2726 *
2727 * SPI PHY Dataslice Rfile PHY Features Register
2728 * This register shows available hardware features.
2729 */
2730 union ody_spix_phy_dataslice_rfile_phy_features {
2731 uint32_t u;
2732 struct ody_spix_phy_dataslice_rfile_phy_features_s {
2733 uint32_t onfi_40 : 1;
2734 uint32_t onfi_41 : 1;
2735 uint32_t sdr_16bit : 1;
2736 uint32_t spi : 1;
2737 uint32_t sd_emmc : 1;
2738 uint32_t bank_num : 2;
2739 uint32_t dll_tap_num : 1;
2740 uint32_t aging : 1;
2741 uint32_t dfi_clock_ratio : 1;
2742 uint32_t per_bit_deskew : 1;
2743 uint32_t reg_intf : 1;
2744 uint32_t ext_lpbk_dqs : 1;
2745 uint32_t jtag_sup : 1;
2746 uint32_t pll_sup : 1;
2747 uint32_t asf_sup : 1;
2748 uint32_t reserved_16_31 : 16;
2749 } s;
2750 /* struct ody_spix_phy_dataslice_rfile_phy_features_s cn; */
2751 };
2752 typedef union ody_spix_phy_dataslice_rfile_phy_features ody_spix_phy_dataslice_rfile_phy_features_t;
2753
2754 static inline uint64_t ODY_SPIX_PHY_DATASLICE_RFILE_PHY_FEATURES(uint64_t a) __attribute__ ((pure, always_inline));
ODY_SPIX_PHY_DATASLICE_RFILE_PHY_FEATURES(uint64_t a)2755 static inline uint64_t ODY_SPIX_PHY_DATASLICE_RFILE_PHY_FEATURES(uint64_t a)
2756 {
2757 if (a <= 1)
2758 return 0x804000002074ll + 0x1000000000ll * ((a) & 0x1);
2759 __ody_csr_fatal("SPIX_PHY_DATASLICE_RFILE_PHY_FEATURES", 1, a, 0, 0, 0, 0, 0);
2760 }
2761
2762 #define typedef_ODY_SPIX_PHY_DATASLICE_RFILE_PHY_FEATURES(a) ody_spix_phy_dataslice_rfile_phy_features_t
2763 #define bustype_ODY_SPIX_PHY_DATASLICE_RFILE_PHY_FEATURES(a) CSR_TYPE_NCB32b
2764 #define basename_ODY_SPIX_PHY_DATASLICE_RFILE_PHY_FEATURES(a) "SPIX_PHY_DATASLICE_RFILE_PHY_FEATURES"
2765 #define device_bar_ODY_SPIX_PHY_DATASLICE_RFILE_PHY_FEATURES(a) 0x0 /* PF_BAR0 */
2766 #define busnum_ODY_SPIX_PHY_DATASLICE_RFILE_PHY_FEATURES(a) (a)
2767 #define arguments_ODY_SPIX_PHY_DATASLICE_RFILE_PHY_FEATURES(a) (a), -1, -1, -1
2768
2769 /**
2770 * Register (NCB32b) spi#_phy_dataslice_rfile_phy_gate_lpbk_ctrl
2771 *
2772 * SPI PHY Dataslice Rfile PHY Gate Lpbk Control Register
2773 * This register controls the gate and loopback control related timing.
2774 */
2775 union ody_spix_phy_dataslice_rfile_phy_gate_lpbk_ctrl {
2776 uint32_t u;
2777 struct ody_spix_phy_dataslice_rfile_phy_gate_lpbk_ctrl_s {
2778 uint32_t gate_cfg : 4;
2779 uint32_t gate_cfg_close : 2;
2780 uint32_t gate_cfg_always_on : 1;
2781 uint32_t reserved_7 : 1;
2782 uint32_t lpbk_en : 1;
2783 uint32_t lpbk_internal : 1;
2784 uint32_t loopback_control : 2;
2785 uint32_t lpbk_fail_muxsel : 1;
2786 uint32_t lpbk_err_check_timing : 3;
2787 uint32_t rd_del_sel_empty : 1;
2788 uint32_t reserved_17 : 1;
2789 uint32_t underrun_suppress : 1;
2790 uint32_t rd_del_sel : 6;
2791 uint32_t param_phase_detect_sel_oe : 3;
2792 uint32_t sw_half_cycle_shift : 1;
2793 uint32_t en_sw_half_cycle : 1;
2794 uint32_t sw_dqs_phase_bypass : 1;
2795 uint32_t sync_method : 1;
2796 } s;
2797 /* struct ody_spix_phy_dataslice_rfile_phy_gate_lpbk_ctrl_s cn; */
2798 };
2799 typedef union ody_spix_phy_dataslice_rfile_phy_gate_lpbk_ctrl ody_spix_phy_dataslice_rfile_phy_gate_lpbk_ctrl_t;
2800
2801 static inline uint64_t ODY_SPIX_PHY_DATASLICE_RFILE_PHY_GATE_LPBK_CTRL(uint64_t a) __attribute__ ((pure, always_inline));
ODY_SPIX_PHY_DATASLICE_RFILE_PHY_GATE_LPBK_CTRL(uint64_t a)2802 static inline uint64_t ODY_SPIX_PHY_DATASLICE_RFILE_PHY_GATE_LPBK_CTRL(uint64_t a)
2803 {
2804 if (a <= 1)
2805 return 0x804000002008ll + 0x1000000000ll * ((a) & 0x1);
2806 __ody_csr_fatal("SPIX_PHY_DATASLICE_RFILE_PHY_GATE_LPBK_CTRL", 1, a, 0, 0, 0, 0, 0);
2807 }
2808
2809 #define typedef_ODY_SPIX_PHY_DATASLICE_RFILE_PHY_GATE_LPBK_CTRL(a) ody_spix_phy_dataslice_rfile_phy_gate_lpbk_ctrl_t
2810 #define bustype_ODY_SPIX_PHY_DATASLICE_RFILE_PHY_GATE_LPBK_CTRL(a) CSR_TYPE_NCB32b
2811 #define basename_ODY_SPIX_PHY_DATASLICE_RFILE_PHY_GATE_LPBK_CTRL(a) "SPIX_PHY_DATASLICE_RFILE_PHY_GATE_LPBK_CTRL"
2812 #define device_bar_ODY_SPIX_PHY_DATASLICE_RFILE_PHY_GATE_LPBK_CTRL(a) 0x0 /* PF_BAR0 */
2813 #define busnum_ODY_SPIX_PHY_DATASLICE_RFILE_PHY_GATE_LPBK_CTRL(a) (a)
2814 #define arguments_ODY_SPIX_PHY_DATASLICE_RFILE_PHY_GATE_LPBK_CTRL(a) (a), -1, -1, -1
2815
2816 /**
2817 * Register (NCB32b) spi#_phy_dataslice_rfile_phy_ie_timing
2818 *
2819 * SPI PHY Dataslice Rfile PHY Ie Timing Register
2820 * This register controls the DQS related timing.
2821 */
2822 union ody_spix_phy_dataslice_rfile_phy_ie_timing {
2823 uint32_t u;
2824 struct ody_spix_phy_dataslice_rfile_phy_ie_timing_s {
2825 uint32_t rddata_en_ie_dly : 4;
2826 uint32_t dqs_ie_stop : 3;
2827 uint32_t reserved_7 : 1;
2828 uint32_t dqs_ie_start : 3;
2829 uint32_t reserved_11 : 1;
2830 uint32_t dq_ie_stop : 3;
2831 uint32_t reserved_15 : 1;
2832 uint32_t dq_ie_start : 3;
2833 uint32_t reserved_19 : 1;
2834 uint32_t ie_always_on : 1;
2835 uint32_t reserved_21_31 : 11;
2836 } s;
2837 /* struct ody_spix_phy_dataslice_rfile_phy_ie_timing_s cn; */
2838 };
2839 typedef union ody_spix_phy_dataslice_rfile_phy_ie_timing ody_spix_phy_dataslice_rfile_phy_ie_timing_t;
2840
2841 static inline uint64_t ODY_SPIX_PHY_DATASLICE_RFILE_PHY_IE_TIMING(uint64_t a) __attribute__ ((pure, always_inline));
ODY_SPIX_PHY_DATASLICE_RFILE_PHY_IE_TIMING(uint64_t a)2842 static inline uint64_t ODY_SPIX_PHY_DATASLICE_RFILE_PHY_IE_TIMING(uint64_t a)
2843 {
2844 if (a <= 1)
2845 return 0x804000002014ll + 0x1000000000ll * ((a) & 0x1);
2846 __ody_csr_fatal("SPIX_PHY_DATASLICE_RFILE_PHY_IE_TIMING", 1, a, 0, 0, 0, 0, 0);
2847 }
2848
2849 #define typedef_ODY_SPIX_PHY_DATASLICE_RFILE_PHY_IE_TIMING(a) ody_spix_phy_dataslice_rfile_phy_ie_timing_t
2850 #define bustype_ODY_SPIX_PHY_DATASLICE_RFILE_PHY_IE_TIMING(a) CSR_TYPE_NCB32b
2851 #define basename_ODY_SPIX_PHY_DATASLICE_RFILE_PHY_IE_TIMING(a) "SPIX_PHY_DATASLICE_RFILE_PHY_IE_TIMING"
2852 #define device_bar_ODY_SPIX_PHY_DATASLICE_RFILE_PHY_IE_TIMING(a) 0x0 /* PF_BAR0 */
2853 #define busnum_ODY_SPIX_PHY_DATASLICE_RFILE_PHY_IE_TIMING(a) (a)
2854 #define arguments_ODY_SPIX_PHY_DATASLICE_RFILE_PHY_IE_TIMING(a) (a), -1, -1, -1
2855
2856 /**
2857 * Register (NCB32b) spi#_phy_dataslice_rfile_phy_obs_reg_0
2858 *
2859 * SPI PHY Dataslice Rfile PHY Obs Reg 0 Register
2860 * This register holds the following observable points in the PHY.
2861 */
2862 union ody_spix_phy_dataslice_rfile_phy_obs_reg_0 {
2863 uint32_t u;
2864 struct ody_spix_phy_dataslice_rfile_phy_obs_reg_0_s {
2865 uint32_t lpbk_status : 2;
2866 uint32_t reserved_2_7 : 6;
2867 uint32_t lpbk_dq_data : 16;
2868 uint32_t dqs_underrun : 1;
2869 uint32_t dqs_overflow : 1;
2870 uint32_t dqs_cmd_underrun : 1;
2871 uint32_t dqs_cmd_overflow : 1;
2872 uint32_t reserved_28_31 : 4;
2873 } s;
2874 /* struct ody_spix_phy_dataslice_rfile_phy_obs_reg_0_s cn; */
2875 };
2876 typedef union ody_spix_phy_dataslice_rfile_phy_obs_reg_0 ody_spix_phy_dataslice_rfile_phy_obs_reg_0_t;
2877
2878 static inline uint64_t ODY_SPIX_PHY_DATASLICE_RFILE_PHY_OBS_REG_0(uint64_t a) __attribute__ ((pure, always_inline));
ODY_SPIX_PHY_DATASLICE_RFILE_PHY_OBS_REG_0(uint64_t a)2879 static inline uint64_t ODY_SPIX_PHY_DATASLICE_RFILE_PHY_OBS_REG_0(uint64_t a)
2880 {
2881 if (a <= 1)
2882 return 0x804000002018ll + 0x1000000000ll * ((a) & 0x1);
2883 __ody_csr_fatal("SPIX_PHY_DATASLICE_RFILE_PHY_OBS_REG_0", 1, a, 0, 0, 0, 0, 0);
2884 }
2885
2886 #define typedef_ODY_SPIX_PHY_DATASLICE_RFILE_PHY_OBS_REG_0(a) ody_spix_phy_dataslice_rfile_phy_obs_reg_0_t
2887 #define bustype_ODY_SPIX_PHY_DATASLICE_RFILE_PHY_OBS_REG_0(a) CSR_TYPE_NCB32b
2888 #define basename_ODY_SPIX_PHY_DATASLICE_RFILE_PHY_OBS_REG_0(a) "SPIX_PHY_DATASLICE_RFILE_PHY_OBS_REG_0"
2889 #define device_bar_ODY_SPIX_PHY_DATASLICE_RFILE_PHY_OBS_REG_0(a) 0x0 /* PF_BAR0 */
2890 #define busnum_ODY_SPIX_PHY_DATASLICE_RFILE_PHY_OBS_REG_0(a) (a)
2891 #define arguments_ODY_SPIX_PHY_DATASLICE_RFILE_PHY_OBS_REG_0(a) (a), -1, -1, -1
2892
2893 /**
2894 * Register (NCB32b) spi#_phy_dataslice_rfile_phy_rd_deskew
2895 *
2896 * SPI PHY Dataslice Rfile PHY Rd Deskew Register
2897 * This register holds the values of delay of each DQ bit on the read path.
2898 */
2899 union ody_spix_phy_dataslice_rfile_phy_rd_deskew {
2900 uint32_t u;
2901 struct ody_spix_phy_dataslice_rfile_phy_rd_deskew_s {
2902 uint32_t rd_dq0_deskew_delay : 4;
2903 uint32_t rd_dq1_deskew_delay : 4;
2904 uint32_t rd_dq2_deskew_delay : 4;
2905 uint32_t rd_dq3_deskew_delay : 4;
2906 uint32_t rd_dq4_deskew_delay : 4;
2907 uint32_t rd_dq5_deskew_delay : 4;
2908 uint32_t rd_dq6_deskew_delay : 4;
2909 uint32_t rd_dq7_deskew_delay : 4;
2910 } s;
2911 /* struct ody_spix_phy_dataslice_rfile_phy_rd_deskew_s cn; */
2912 };
2913 typedef union ody_spix_phy_dataslice_rfile_phy_rd_deskew ody_spix_phy_dataslice_rfile_phy_rd_deskew_t;
2914
2915 static inline uint64_t ODY_SPIX_PHY_DATASLICE_RFILE_PHY_RD_DESKEW(uint64_t a) __attribute__ ((pure, always_inline));
ODY_SPIX_PHY_DATASLICE_RFILE_PHY_RD_DESKEW(uint64_t a)2916 static inline uint64_t ODY_SPIX_PHY_DATASLICE_RFILE_PHY_RD_DESKEW(uint64_t a)
2917 {
2918 if (a <= 1)
2919 return 0x80400000203cll + 0x1000000000ll * ((a) & 0x1);
2920 __ody_csr_fatal("SPIX_PHY_DATASLICE_RFILE_PHY_RD_DESKEW", 1, a, 0, 0, 0, 0, 0);
2921 }
2922
2923 #define typedef_ODY_SPIX_PHY_DATASLICE_RFILE_PHY_RD_DESKEW(a) ody_spix_phy_dataslice_rfile_phy_rd_deskew_t
2924 #define bustype_ODY_SPIX_PHY_DATASLICE_RFILE_PHY_RD_DESKEW(a) CSR_TYPE_NCB32b
2925 #define basename_ODY_SPIX_PHY_DATASLICE_RFILE_PHY_RD_DESKEW(a) "SPIX_PHY_DATASLICE_RFILE_PHY_RD_DESKEW"
2926 #define device_bar_ODY_SPIX_PHY_DATASLICE_RFILE_PHY_RD_DESKEW(a) 0x0 /* PF_BAR0 */
2927 #define busnum_ODY_SPIX_PHY_DATASLICE_RFILE_PHY_RD_DESKEW(a) (a)
2928 #define arguments_ODY_SPIX_PHY_DATASLICE_RFILE_PHY_RD_DESKEW(a) (a), -1, -1, -1
2929
2930 /**
2931 * Register (NCB32b) spi#_phy_dataslice_rfile_phy_static_togg
2932 *
2933 * SPI PHY Dataslice Rfile PHY Static Togg Register
2934 * This register controls the static aging feature of the PHY.
2935 */
2936 union ody_spix_phy_dataslice_rfile_phy_static_togg {
2937 uint32_t u;
2938 struct ody_spix_phy_dataslice_rfile_phy_static_togg_s {
2939 uint32_t static_tog_clk_div : 16;
2940 uint32_t static_togg_global_enable : 1;
2941 uint32_t reserved_17_19 : 3;
2942 uint32_t static_togg_enable : 4;
2943 uint32_t read_dqs_togg_enable : 1;
2944 uint32_t reserved_25_31 : 7;
2945 } s;
2946 /* struct ody_spix_phy_dataslice_rfile_phy_static_togg_s cn; */
2947 };
2948 typedef union ody_spix_phy_dataslice_rfile_phy_static_togg ody_spix_phy_dataslice_rfile_phy_static_togg_t;
2949
2950 static inline uint64_t ODY_SPIX_PHY_DATASLICE_RFILE_PHY_STATIC_TOGG(uint64_t a) __attribute__ ((pure, always_inline));
ODY_SPIX_PHY_DATASLICE_RFILE_PHY_STATIC_TOGG(uint64_t a)2951 static inline uint64_t ODY_SPIX_PHY_DATASLICE_RFILE_PHY_STATIC_TOGG(uint64_t a)
2952 {
2953 if (a <= 1)
2954 return 0x804000002028ll + 0x1000000000ll * ((a) & 0x1);
2955 __ody_csr_fatal("SPIX_PHY_DATASLICE_RFILE_PHY_STATIC_TOGG", 1, a, 0, 0, 0, 0, 0);
2956 }
2957
2958 #define typedef_ODY_SPIX_PHY_DATASLICE_RFILE_PHY_STATIC_TOGG(a) ody_spix_phy_dataslice_rfile_phy_static_togg_t
2959 #define bustype_ODY_SPIX_PHY_DATASLICE_RFILE_PHY_STATIC_TOGG(a) CSR_TYPE_NCB32b
2960 #define basename_ODY_SPIX_PHY_DATASLICE_RFILE_PHY_STATIC_TOGG(a) "SPIX_PHY_DATASLICE_RFILE_PHY_STATIC_TOGG"
2961 #define device_bar_ODY_SPIX_PHY_DATASLICE_RFILE_PHY_STATIC_TOGG(a) 0x0 /* PF_BAR0 */
2962 #define busnum_ODY_SPIX_PHY_DATASLICE_RFILE_PHY_STATIC_TOGG(a) (a)
2963 #define arguments_ODY_SPIX_PHY_DATASLICE_RFILE_PHY_STATIC_TOGG(a) (a), -1, -1, -1
2964
2965 /**
2966 * Register (NCB32b) spi#_phy_dataslice_rfile_phy_version
2967 *
2968 * SPI PHY Dataslice Rfile PHY Version Register
2969 * This register contains release identification number.
2970 */
2971 union ody_spix_phy_dataslice_rfile_phy_version {
2972 uint32_t u;
2973 struct ody_spix_phy_dataslice_rfile_phy_version_s {
2974 uint32_t phy_rev : 8;
2975 uint32_t phy_fix : 8;
2976 uint32_t combo_phy_magic_number : 16;
2977 } s;
2978 /* struct ody_spix_phy_dataslice_rfile_phy_version_s cn; */
2979 };
2980 typedef union ody_spix_phy_dataslice_rfile_phy_version ody_spix_phy_dataslice_rfile_phy_version_t;
2981
2982 static inline uint64_t ODY_SPIX_PHY_DATASLICE_RFILE_PHY_VERSION(uint64_t a) __attribute__ ((pure, always_inline));
ODY_SPIX_PHY_DATASLICE_RFILE_PHY_VERSION(uint64_t a)2983 static inline uint64_t ODY_SPIX_PHY_DATASLICE_RFILE_PHY_VERSION(uint64_t a)
2984 {
2985 if (a <= 1)
2986 return 0x804000002070ll + 0x1000000000ll * ((a) & 0x1);
2987 __ody_csr_fatal("SPIX_PHY_DATASLICE_RFILE_PHY_VERSION", 1, a, 0, 0, 0, 0, 0);
2988 }
2989
2990 #define typedef_ODY_SPIX_PHY_DATASLICE_RFILE_PHY_VERSION(a) ody_spix_phy_dataslice_rfile_phy_version_t
2991 #define bustype_ODY_SPIX_PHY_DATASLICE_RFILE_PHY_VERSION(a) CSR_TYPE_NCB32b
2992 #define basename_ODY_SPIX_PHY_DATASLICE_RFILE_PHY_VERSION(a) "SPIX_PHY_DATASLICE_RFILE_PHY_VERSION"
2993 #define device_bar_ODY_SPIX_PHY_DATASLICE_RFILE_PHY_VERSION(a) 0x0 /* PF_BAR0 */
2994 #define busnum_ODY_SPIX_PHY_DATASLICE_RFILE_PHY_VERSION(a) (a)
2995 #define arguments_ODY_SPIX_PHY_DATASLICE_RFILE_PHY_VERSION(a) (a), -1, -1, -1
2996
2997 /**
2998 * Register (NCB32b) spi#_phy_dataslice_rfile_phy_wr_deskew
2999 *
3000 * SPI PHY Dataslice Rfile PHY Wr Deskew Register
3001 * This register holds the values of delay of each DQ bit on the write path.
3002 */
3003 union ody_spix_phy_dataslice_rfile_phy_wr_deskew {
3004 uint32_t u;
3005 struct ody_spix_phy_dataslice_rfile_phy_wr_deskew_s {
3006 uint32_t wr_dq0_deskew_delay : 4;
3007 uint32_t wr_dq1_deskew_delay : 4;
3008 uint32_t wr_dq2_deskew_delay : 4;
3009 uint32_t wr_dq3_deskew_delay : 4;
3010 uint32_t wr_dq4_deskew_delay : 4;
3011 uint32_t wr_dq5_deskew_delay : 4;
3012 uint32_t wr_dq6_deskew_delay : 4;
3013 uint32_t wr_dq7_deskew_delay : 4;
3014 } s;
3015 /* struct ody_spix_phy_dataslice_rfile_phy_wr_deskew_s cn; */
3016 };
3017 typedef union ody_spix_phy_dataslice_rfile_phy_wr_deskew ody_spix_phy_dataslice_rfile_phy_wr_deskew_t;
3018
3019 static inline uint64_t ODY_SPIX_PHY_DATASLICE_RFILE_PHY_WR_DESKEW(uint64_t a) __attribute__ ((pure, always_inline));
ODY_SPIX_PHY_DATASLICE_RFILE_PHY_WR_DESKEW(uint64_t a)3020 static inline uint64_t ODY_SPIX_PHY_DATASLICE_RFILE_PHY_WR_DESKEW(uint64_t a)
3021 {
3022 if (a <= 1)
3023 return 0x80400000202cll + 0x1000000000ll * ((a) & 0x1);
3024 __ody_csr_fatal("SPIX_PHY_DATASLICE_RFILE_PHY_WR_DESKEW", 1, a, 0, 0, 0, 0, 0);
3025 }
3026
3027 #define typedef_ODY_SPIX_PHY_DATASLICE_RFILE_PHY_WR_DESKEW(a) ody_spix_phy_dataslice_rfile_phy_wr_deskew_t
3028 #define bustype_ODY_SPIX_PHY_DATASLICE_RFILE_PHY_WR_DESKEW(a) CSR_TYPE_NCB32b
3029 #define basename_ODY_SPIX_PHY_DATASLICE_RFILE_PHY_WR_DESKEW(a) "SPIX_PHY_DATASLICE_RFILE_PHY_WR_DESKEW"
3030 #define device_bar_ODY_SPIX_PHY_DATASLICE_RFILE_PHY_WR_DESKEW(a) 0x0 /* PF_BAR0 */
3031 #define busnum_ODY_SPIX_PHY_DATASLICE_RFILE_PHY_WR_DESKEW(a) (a)
3032 #define arguments_ODY_SPIX_PHY_DATASLICE_RFILE_PHY_WR_DESKEW(a) (a), -1, -1, -1
3033
3034 /**
3035 * Register (NCB32b) spi#_phy_dataslice_rfile_phy_wr_deskew_pd_ctrl_0
3036 *
3037 * SPI PHY Dataslice Rfile PHY Wr Deskew Pd Control 0 Register
3038 * This register holds the values of phase detect block for each DQ bit on the write path.
3039 */
3040 union ody_spix_phy_dataslice_rfile_phy_wr_deskew_pd_ctrl_0 {
3041 uint32_t u;
3042 struct ody_spix_phy_dataslice_rfile_phy_wr_deskew_pd_ctrl_0_s {
3043 uint32_t dq0_phase_detect_sel : 3;
3044 uint32_t reserved_3 : 1;
3045 uint32_t dq0_sw_half_cycle_shift : 1;
3046 uint32_t dq0_en_sw_half_cycle : 1;
3047 uint32_t dq0_sw_dq_phase_bypass : 1;
3048 uint32_t reserved_7 : 1;
3049 uint32_t dq1_phase_detect_sel : 3;
3050 uint32_t reserved_11 : 1;
3051 uint32_t dq1_sw_half_cycle_shift : 1;
3052 uint32_t dq1_en_sw_half_cycle : 1;
3053 uint32_t dq1_sw_dq_phase_bypass : 1;
3054 uint32_t reserved_15 : 1;
3055 uint32_t dq2_phase_detect_sel : 3;
3056 uint32_t reserved_19 : 1;
3057 uint32_t dq2_sw_half_cycle_shift : 1;
3058 uint32_t dq2_en_sw_half_cycle : 1;
3059 uint32_t dq2_sw_dq_phase_bypass : 1;
3060 uint32_t reserved_23 : 1;
3061 uint32_t dq3_phase_detect_sel : 3;
3062 uint32_t reserved_27 : 1;
3063 uint32_t dq3_sw_half_cycle_shift : 1;
3064 uint32_t dq3_en_sw_half_cycle : 1;
3065 uint32_t dq3_sw_dq_phase_bypass : 1;
3066 uint32_t reserved_31 : 1;
3067 } s;
3068 /* struct ody_spix_phy_dataslice_rfile_phy_wr_deskew_pd_ctrl_0_s cn; */
3069 };
3070 typedef union ody_spix_phy_dataslice_rfile_phy_wr_deskew_pd_ctrl_0 ody_spix_phy_dataslice_rfile_phy_wr_deskew_pd_ctrl_0_t;
3071
3072 static inline uint64_t ODY_SPIX_PHY_DATASLICE_RFILE_PHY_WR_DESKEW_PD_CTRL_0(uint64_t a) __attribute__ ((pure, always_inline));
ODY_SPIX_PHY_DATASLICE_RFILE_PHY_WR_DESKEW_PD_CTRL_0(uint64_t a)3073 static inline uint64_t ODY_SPIX_PHY_DATASLICE_RFILE_PHY_WR_DESKEW_PD_CTRL_0(uint64_t a)
3074 {
3075 if (a <= 1)
3076 return 0x804000002034ll + 0x1000000000ll * ((a) & 0x1);
3077 __ody_csr_fatal("SPIX_PHY_DATASLICE_RFILE_PHY_WR_DESKEW_PD_CTRL_0", 1, a, 0, 0, 0, 0, 0);
3078 }
3079
3080 #define typedef_ODY_SPIX_PHY_DATASLICE_RFILE_PHY_WR_DESKEW_PD_CTRL_0(a) ody_spix_phy_dataslice_rfile_phy_wr_deskew_pd_ctrl_0_t
3081 #define bustype_ODY_SPIX_PHY_DATASLICE_RFILE_PHY_WR_DESKEW_PD_CTRL_0(a) CSR_TYPE_NCB32b
3082 #define basename_ODY_SPIX_PHY_DATASLICE_RFILE_PHY_WR_DESKEW_PD_CTRL_0(a) "SPIX_PHY_DATASLICE_RFILE_PHY_WR_DESKEW_PD_CTRL_0"
3083 #define device_bar_ODY_SPIX_PHY_DATASLICE_RFILE_PHY_WR_DESKEW_PD_CTRL_0(a) 0x0 /* PF_BAR0 */
3084 #define busnum_ODY_SPIX_PHY_DATASLICE_RFILE_PHY_WR_DESKEW_PD_CTRL_0(a) (a)
3085 #define arguments_ODY_SPIX_PHY_DATASLICE_RFILE_PHY_WR_DESKEW_PD_CTRL_0(a) (a), -1, -1, -1
3086
3087 /**
3088 * Register (NCB32b) spi#_phy_dataslice_rfile_phy_wr_deskew_pd_ctrl_1
3089 *
3090 * SPI PHY Dataslice Rfile PHY Wr Deskew Pd Control 1 Register
3091 * This register holds the values of phase detect block for each DQ bit on the write path.
3092 */
3093 union ody_spix_phy_dataslice_rfile_phy_wr_deskew_pd_ctrl_1 {
3094 uint32_t u;
3095 struct ody_spix_phy_dataslice_rfile_phy_wr_deskew_pd_ctrl_1_s {
3096 uint32_t dq4_phase_detect_sel : 3;
3097 uint32_t reserved_3 : 1;
3098 uint32_t dq4_sw_half_cycle_shift : 1;
3099 uint32_t dq4_en_sw_half_cycle : 1;
3100 uint32_t dq4_sw_dq_phase_bypass : 1;
3101 uint32_t reserved_7 : 1;
3102 uint32_t dq5_phase_detect_sel : 3;
3103 uint32_t reserved_11 : 1;
3104 uint32_t dq5_sw_half_cycle_shift : 1;
3105 uint32_t dq5_en_sw_half_cycle : 1;
3106 uint32_t dq5_sw_dq_phase_bypass : 1;
3107 uint32_t reserved_15 : 1;
3108 uint32_t dq6_phase_detect_sel : 3;
3109 uint32_t reserved_19 : 1;
3110 uint32_t dq6_sw_half_cycle_shift : 1;
3111 uint32_t dq6_en_sw_half_cycle : 1;
3112 uint32_t dq6_sw_dq_phase_bypass : 1;
3113 uint32_t reserved_23 : 1;
3114 uint32_t dq7_phase_detect_sel : 3;
3115 uint32_t reserved_27 : 1;
3116 uint32_t dq7_sw_half_cycle_shift : 1;
3117 uint32_t dq7_en_sw_half_cycle : 1;
3118 uint32_t dq7_sw_dq_phase_bypass : 1;
3119 uint32_t reserved_31 : 1;
3120 } s;
3121 /* struct ody_spix_phy_dataslice_rfile_phy_wr_deskew_pd_ctrl_1_s cn; */
3122 };
3123 typedef union ody_spix_phy_dataslice_rfile_phy_wr_deskew_pd_ctrl_1 ody_spix_phy_dataslice_rfile_phy_wr_deskew_pd_ctrl_1_t;
3124
3125 static inline uint64_t ODY_SPIX_PHY_DATASLICE_RFILE_PHY_WR_DESKEW_PD_CTRL_1(uint64_t a) __attribute__ ((pure, always_inline));
ODY_SPIX_PHY_DATASLICE_RFILE_PHY_WR_DESKEW_PD_CTRL_1(uint64_t a)3126 static inline uint64_t ODY_SPIX_PHY_DATASLICE_RFILE_PHY_WR_DESKEW_PD_CTRL_1(uint64_t a)
3127 {
3128 if (a <= 1)
3129 return 0x804000002038ll + 0x1000000000ll * ((a) & 0x1);
3130 __ody_csr_fatal("SPIX_PHY_DATASLICE_RFILE_PHY_WR_DESKEW_PD_CTRL_1", 1, a, 0, 0, 0, 0, 0);
3131 }
3132
3133 #define typedef_ODY_SPIX_PHY_DATASLICE_RFILE_PHY_WR_DESKEW_PD_CTRL_1(a) ody_spix_phy_dataslice_rfile_phy_wr_deskew_pd_ctrl_1_t
3134 #define bustype_ODY_SPIX_PHY_DATASLICE_RFILE_PHY_WR_DESKEW_PD_CTRL_1(a) CSR_TYPE_NCB32b
3135 #define basename_ODY_SPIX_PHY_DATASLICE_RFILE_PHY_WR_DESKEW_PD_CTRL_1(a) "SPIX_PHY_DATASLICE_RFILE_PHY_WR_DESKEW_PD_CTRL_1"
3136 #define device_bar_ODY_SPIX_PHY_DATASLICE_RFILE_PHY_WR_DESKEW_PD_CTRL_1(a) 0x0 /* PF_BAR0 */
3137 #define busnum_ODY_SPIX_PHY_DATASLICE_RFILE_PHY_WR_DESKEW_PD_CTRL_1(a) (a)
3138 #define arguments_ODY_SPIX_PHY_DATASLICE_RFILE_PHY_WR_DESKEW_PD_CTRL_1(a) (a), -1, -1, -1
3139
3140 /**
3141 * Register (NCB32b) spi#_phy_dataslice_rfile_phy_wr_rd_deskew_cmd
3142 *
3143 * SPI PHY Dataslice Rfile PHY Wr Rd Deskew Command Register
3144 * This register holds the values of delay of CMD bit on the write and read path as
3145 * well as the values of
3146 * phase detect block for CMD bit on the write path.
3147 */
3148 union ody_spix_phy_dataslice_rfile_phy_wr_rd_deskew_cmd {
3149 uint32_t u;
3150 struct ody_spix_phy_dataslice_rfile_phy_wr_rd_deskew_cmd_s {
3151 uint32_t wr_cmd_deskew_delay : 4;
3152 uint32_t reserved_4_7 : 4;
3153 uint32_t cmd_phase_detect_sel : 3;
3154 uint32_t reserved_11 : 1;
3155 uint32_t cmd_sw_half_cycle_shift : 1;
3156 uint32_t cmd_en_sw_half_cycle : 1;
3157 uint32_t cmd_sw_dq_phase_bypass : 1;
3158 uint32_t reserved_15 : 1;
3159 uint32_t cmd_clkperiod_delay : 1;
3160 uint32_t reserved_17_23 : 7;
3161 uint32_t rd_cmd_deskew_delay : 4;
3162 uint32_t reserved_28_31 : 4;
3163 } s;
3164 /* struct ody_spix_phy_dataslice_rfile_phy_wr_rd_deskew_cmd_s cn; */
3165 };
3166 typedef union ody_spix_phy_dataslice_rfile_phy_wr_rd_deskew_cmd ody_spix_phy_dataslice_rfile_phy_wr_rd_deskew_cmd_t;
3167
3168 static inline uint64_t ODY_SPIX_PHY_DATASLICE_RFILE_PHY_WR_RD_DESKEW_CMD(uint64_t a) __attribute__ ((pure, always_inline));
ODY_SPIX_PHY_DATASLICE_RFILE_PHY_WR_RD_DESKEW_CMD(uint64_t a)3169 static inline uint64_t ODY_SPIX_PHY_DATASLICE_RFILE_PHY_WR_RD_DESKEW_CMD(uint64_t a)
3170 {
3171 if (a <= 1)
3172 return 0x804000002030ll + 0x1000000000ll * ((a) & 0x1);
3173 __ody_csr_fatal("SPIX_PHY_DATASLICE_RFILE_PHY_WR_RD_DESKEW_CMD", 1, a, 0, 0, 0, 0, 0);
3174 }
3175
3176 #define typedef_ODY_SPIX_PHY_DATASLICE_RFILE_PHY_WR_RD_DESKEW_CMD(a) ody_spix_phy_dataslice_rfile_phy_wr_rd_deskew_cmd_t
3177 #define bustype_ODY_SPIX_PHY_DATASLICE_RFILE_PHY_WR_RD_DESKEW_CMD(a) CSR_TYPE_NCB32b
3178 #define basename_ODY_SPIX_PHY_DATASLICE_RFILE_PHY_WR_RD_DESKEW_CMD(a) "SPIX_PHY_DATASLICE_RFILE_PHY_WR_RD_DESKEW_CMD"
3179 #define device_bar_ODY_SPIX_PHY_DATASLICE_RFILE_PHY_WR_RD_DESKEW_CMD(a) 0x0 /* PF_BAR0 */
3180 #define busnum_ODY_SPIX_PHY_DATASLICE_RFILE_PHY_WR_RD_DESKEW_CMD(a) (a)
3181 #define arguments_ODY_SPIX_PHY_DATASLICE_RFILE_PHY_WR_RD_DESKEW_CMD(a) (a), -1, -1, -1
3182
3183 /**
3184 * Register (NCB32b) spi#_rf_minictrl_regs_clock_mode_settings
3185 *
3186 * SPI Rf Minictrl Regs Clock Mode Settings Register
3187 * SPI clock mode.
3188 */
3189 union ody_spix_rf_minictrl_regs_clock_mode_settings {
3190 uint32_t u;
3191 struct ody_spix_rf_minictrl_regs_clock_mode_settings_s {
3192 uint32_t spi_clock_mode : 1;
3193 uint32_t reserved_1_31 : 31;
3194 } s;
3195 /* struct ody_spix_rf_minictrl_regs_clock_mode_settings_s cn; */
3196 };
3197 typedef union ody_spix_rf_minictrl_regs_clock_mode_settings ody_spix_rf_minictrl_regs_clock_mode_settings_t;
3198
3199 static inline uint64_t ODY_SPIX_RF_MINICTRL_REGS_CLOCK_MODE_SETTINGS(uint64_t a) __attribute__ ((pure, always_inline));
ODY_SPIX_RF_MINICTRL_REGS_CLOCK_MODE_SETTINGS(uint64_t a)3200 static inline uint64_t ODY_SPIX_RF_MINICTRL_REGS_CLOCK_MODE_SETTINGS(uint64_t a)
3201 {
3202 if (a <= 1)
3203 return 0x804000001008ll + 0x1000000000ll * ((a) & 0x1);
3204 __ody_csr_fatal("SPIX_RF_MINICTRL_REGS_CLOCK_MODE_SETTINGS", 1, a, 0, 0, 0, 0, 0);
3205 }
3206
3207 #define typedef_ODY_SPIX_RF_MINICTRL_REGS_CLOCK_MODE_SETTINGS(a) ody_spix_rf_minictrl_regs_clock_mode_settings_t
3208 #define bustype_ODY_SPIX_RF_MINICTRL_REGS_CLOCK_MODE_SETTINGS(a) CSR_TYPE_NCB32b
3209 #define basename_ODY_SPIX_RF_MINICTRL_REGS_CLOCK_MODE_SETTINGS(a) "SPIX_RF_MINICTRL_REGS_CLOCK_MODE_SETTINGS"
3210 #define device_bar_ODY_SPIX_RF_MINICTRL_REGS_CLOCK_MODE_SETTINGS(a) 0x0 /* PF_BAR0 */
3211 #define busnum_ODY_SPIX_RF_MINICTRL_REGS_CLOCK_MODE_SETTINGS(a) (a)
3212 #define arguments_ODY_SPIX_RF_MINICTRL_REGS_CLOCK_MODE_SETTINGS(a) (a), -1, -1, -1
3213
3214 /**
3215 * Register (NCB32b) spi#_rf_minictrl_regs_dev_active_max_reg
3216 *
3217 * SPI Rf Minictrl Regs Dev Active Max Register
3218 * "This register is used to introduce maximum number of xspi_clk cycles through which
3219 * CS# will be kept
3220 * active (low) on memory interface."
3221 */
3222 union ody_spix_rf_minictrl_regs_dev_active_max_reg {
3223 uint32_t u;
3224 struct ody_spix_rf_minictrl_regs_dev_active_max_reg_s {
3225 uint32_t dev_active_max : 32;
3226 } s;
3227 /* struct ody_spix_rf_minictrl_regs_dev_active_max_reg_s cn; */
3228 };
3229 typedef union ody_spix_rf_minictrl_regs_dev_active_max_reg ody_spix_rf_minictrl_regs_dev_active_max_reg_t;
3230
3231 static inline uint64_t ODY_SPIX_RF_MINICTRL_REGS_DEV_ACTIVE_MAX_REG(uint64_t a) __attribute__ ((pure, always_inline));
ODY_SPIX_RF_MINICTRL_REGS_DEV_ACTIVE_MAX_REG(uint64_t a)3232 static inline uint64_t ODY_SPIX_RF_MINICTRL_REGS_DEV_ACTIVE_MAX_REG(uint64_t a)
3233 {
3234 if (a <= 1)
3235 return 0x804000001018ll + 0x1000000000ll * ((a) & 0x1);
3236 __ody_csr_fatal("SPIX_RF_MINICTRL_REGS_DEV_ACTIVE_MAX_REG", 1, a, 0, 0, 0, 0, 0);
3237 }
3238
3239 #define typedef_ODY_SPIX_RF_MINICTRL_REGS_DEV_ACTIVE_MAX_REG(a) ody_spix_rf_minictrl_regs_dev_active_max_reg_t
3240 #define bustype_ODY_SPIX_RF_MINICTRL_REGS_DEV_ACTIVE_MAX_REG(a) CSR_TYPE_NCB32b
3241 #define basename_ODY_SPIX_RF_MINICTRL_REGS_DEV_ACTIVE_MAX_REG(a) "SPIX_RF_MINICTRL_REGS_DEV_ACTIVE_MAX_REG"
3242 #define device_bar_ODY_SPIX_RF_MINICTRL_REGS_DEV_ACTIVE_MAX_REG(a) 0x0 /* PF_BAR0 */
3243 #define busnum_ODY_SPIX_RF_MINICTRL_REGS_DEV_ACTIVE_MAX_REG(a) (a)
3244 #define arguments_ODY_SPIX_RF_MINICTRL_REGS_DEV_ACTIVE_MAX_REG(a) (a), -1, -1, -1
3245
3246 /**
3247 * Register (NCB32b) spi#_rf_minictrl_regs_dev_delay_reg
3248 *
3249 * SPI Rf Minictrl Regs Dev Delay Register
3250 * This register is used to introduce relative device selection delays with respect to generated xSPI
3251 * Flash Interface.
3252 */
3253 union ody_spix_rf_minictrl_regs_dev_delay_reg {
3254 uint32_t u;
3255 struct ody_spix_rf_minictrl_regs_dev_delay_reg_s {
3256 uint32_t cssot_delay : 8;
3257 uint32_t cseot_delay : 8;
3258 uint32_t reserved_16_23 : 8;
3259 uint32_t csda_min_delay : 8;
3260 } s;
3261 /* struct ody_spix_rf_minictrl_regs_dev_delay_reg_s cn; */
3262 };
3263 typedef union ody_spix_rf_minictrl_regs_dev_delay_reg ody_spix_rf_minictrl_regs_dev_delay_reg_t;
3264
3265 static inline uint64_t ODY_SPIX_RF_MINICTRL_REGS_DEV_DELAY_REG(uint64_t a) __attribute__ ((pure, always_inline));
ODY_SPIX_RF_MINICTRL_REGS_DEV_DELAY_REG(uint64_t a)3266 static inline uint64_t ODY_SPIX_RF_MINICTRL_REGS_DEV_DELAY_REG(uint64_t a)
3267 {
3268 if (a <= 1)
3269 return 0x804000001010ll + 0x1000000000ll * ((a) & 0x1);
3270 __ody_csr_fatal("SPIX_RF_MINICTRL_REGS_DEV_DELAY_REG", 1, a, 0, 0, 0, 0, 0);
3271 }
3272
3273 #define typedef_ODY_SPIX_RF_MINICTRL_REGS_DEV_DELAY_REG(a) ody_spix_rf_minictrl_regs_dev_delay_reg_t
3274 #define bustype_ODY_SPIX_RF_MINICTRL_REGS_DEV_DELAY_REG(a) CSR_TYPE_NCB32b
3275 #define basename_ODY_SPIX_RF_MINICTRL_REGS_DEV_DELAY_REG(a) "SPIX_RF_MINICTRL_REGS_DEV_DELAY_REG"
3276 #define device_bar_ODY_SPIX_RF_MINICTRL_REGS_DEV_DELAY_REG(a) 0x0 /* PF_BAR0 */
3277 #define busnum_ODY_SPIX_RF_MINICTRL_REGS_DEV_DELAY_REG(a) (a)
3278 #define arguments_ODY_SPIX_RF_MINICTRL_REGS_DEV_DELAY_REG(a) (a), -1, -1, -1
3279
3280 /**
3281 * Register (NCB32b) spi#_rf_minictrl_regs_dll_phy_ctrl
3282 *
3283 * SPI Rf Minictrl Regs DLL PHY Control Register
3284 * Configuration of the resynchronization of slave DLL of PHY. When the PHY is used
3285 * with the xSPI
3286 * controller, this register is automatically updated by the device discovery module during
3287 * initialization.
3288 */
3289 union ody_spix_rf_minictrl_regs_dll_phy_ctrl {
3290 uint32_t u;
3291 struct ody_spix_rf_minictrl_regs_dll_phy_ctrl_s {
3292 uint32_t resync_idle_cnt : 8;
3293 uint32_t resync_high_wait_cnt : 4;
3294 uint32_t reserved_12_15 : 4;
3295 uint32_t extended_rd_mode : 1;
3296 uint32_t extended_wr_mode : 1;
3297 uint32_t reserved_18_19 : 2;
3298 uint32_t dqs_last_data_drop_en : 1;
3299 uint32_t sdr_edge_active : 1;
3300 uint32_t reserved_22_23 : 2;
3301 uint32_t dll_rst_n : 1;
3302 uint32_t dfi_ctrlupd_req : 1;
3303 uint32_t reserved_26_31 : 6;
3304 } s;
3305 /* struct ody_spix_rf_minictrl_regs_dll_phy_ctrl_s cn; */
3306 };
3307 typedef union ody_spix_rf_minictrl_regs_dll_phy_ctrl ody_spix_rf_minictrl_regs_dll_phy_ctrl_t;
3308
3309 static inline uint64_t ODY_SPIX_RF_MINICTRL_REGS_DLL_PHY_CTRL(uint64_t a) __attribute__ ((pure, always_inline));
ODY_SPIX_RF_MINICTRL_REGS_DLL_PHY_CTRL(uint64_t a)3310 static inline uint64_t ODY_SPIX_RF_MINICTRL_REGS_DLL_PHY_CTRL(uint64_t a)
3311 {
3312 if (a <= 1)
3313 return 0x804000001034ll + 0x1000000000ll * ((a) & 0x1);
3314 __ody_csr_fatal("SPIX_RF_MINICTRL_REGS_DLL_PHY_CTRL", 1, a, 0, 0, 0, 0, 0);
3315 }
3316
3317 #define typedef_ODY_SPIX_RF_MINICTRL_REGS_DLL_PHY_CTRL(a) ody_spix_rf_minictrl_regs_dll_phy_ctrl_t
3318 #define bustype_ODY_SPIX_RF_MINICTRL_REGS_DLL_PHY_CTRL(a) CSR_TYPE_NCB32b
3319 #define basename_ODY_SPIX_RF_MINICTRL_REGS_DLL_PHY_CTRL(a) "SPIX_RF_MINICTRL_REGS_DLL_PHY_CTRL"
3320 #define device_bar_ODY_SPIX_RF_MINICTRL_REGS_DLL_PHY_CTRL(a) 0x0 /* PF_BAR0 */
3321 #define busnum_ODY_SPIX_RF_MINICTRL_REGS_DLL_PHY_CTRL(a) (a)
3322 #define arguments_ODY_SPIX_RF_MINICTRL_REGS_DLL_PHY_CTRL(a) (a), -1, -1, -1
3323
3324 /**
3325 * Register (NCB32b) spi#_rf_minictrl_regs_dll_phy_update_cnt
3326 *
3327 * SPI Rf Minictrl Regs DLL PHY Update Cnt Register
3328 * Configuration of the resynchronization of slave DLL of PHY.
3329 */
3330 union ody_spix_rf_minictrl_regs_dll_phy_update_cnt {
3331 uint32_t u;
3332 struct ody_spix_rf_minictrl_regs_dll_phy_update_cnt_s {
3333 uint32_t resync_cnt : 32;
3334 } s;
3335 /* struct ody_spix_rf_minictrl_regs_dll_phy_update_cnt_s cn; */
3336 };
3337 typedef union ody_spix_rf_minictrl_regs_dll_phy_update_cnt ody_spix_rf_minictrl_regs_dll_phy_update_cnt_t;
3338
3339 static inline uint64_t ODY_SPIX_RF_MINICTRL_REGS_DLL_PHY_UPDATE_CNT(uint64_t a) __attribute__ ((pure, always_inline));
ODY_SPIX_RF_MINICTRL_REGS_DLL_PHY_UPDATE_CNT(uint64_t a)3340 static inline uint64_t ODY_SPIX_RF_MINICTRL_REGS_DLL_PHY_UPDATE_CNT(uint64_t a)
3341 {
3342 if (a <= 1)
3343 return 0x804000001030ll + 0x1000000000ll * ((a) & 0x1);
3344 __ody_csr_fatal("SPIX_RF_MINICTRL_REGS_DLL_PHY_UPDATE_CNT", 1, a, 0, 0, 0, 0, 0);
3345 }
3346
3347 #define typedef_ODY_SPIX_RF_MINICTRL_REGS_DLL_PHY_UPDATE_CNT(a) ody_spix_rf_minictrl_regs_dll_phy_update_cnt_t
3348 #define bustype_ODY_SPIX_RF_MINICTRL_REGS_DLL_PHY_UPDATE_CNT(a) CSR_TYPE_NCB32b
3349 #define basename_ODY_SPIX_RF_MINICTRL_REGS_DLL_PHY_UPDATE_CNT(a) "SPIX_RF_MINICTRL_REGS_DLL_PHY_UPDATE_CNT"
3350 #define device_bar_ODY_SPIX_RF_MINICTRL_REGS_DLL_PHY_UPDATE_CNT(a) 0x0 /* PF_BAR0 */
3351 #define busnum_ODY_SPIX_RF_MINICTRL_REGS_DLL_PHY_UPDATE_CNT(a) (a)
3352 #define arguments_ODY_SPIX_RF_MINICTRL_REGS_DLL_PHY_UPDATE_CNT(a) (a), -1, -1, -1
3353
3354 /**
3355 * Register (NCB32b) spi#_rf_minictrl_regs_hf_offset_reg
3356 *
3357 * SPI Rf Minictrl Regs Hf Offset Register
3358 * This register is used to decode Legacy Hyper Flash and xSPI Profile 2.0 address into
3359 * interface address
3360 * taking into account "reserved" area in command format.
3361 */
3362 union ody_spix_rf_minictrl_regs_hf_offset_reg {
3363 uint32_t u;
3364 struct ody_spix_rf_minictrl_regs_hf_offset_reg_s {
3365 uint32_t hf_offset_index : 6;
3366 uint32_t reserved_6_7 : 2;
3367 uint32_t hf_offset_size : 6;
3368 uint32_t reserved_14_31 : 18;
3369 } s;
3370 /* struct ody_spix_rf_minictrl_regs_hf_offset_reg_s cn; */
3371 };
3372 typedef union ody_spix_rf_minictrl_regs_hf_offset_reg ody_spix_rf_minictrl_regs_hf_offset_reg_t;
3373
3374 static inline uint64_t ODY_SPIX_RF_MINICTRL_REGS_HF_OFFSET_REG(uint64_t a) __attribute__ ((pure, always_inline));
ODY_SPIX_RF_MINICTRL_REGS_HF_OFFSET_REG(uint64_t a)3375 static inline uint64_t ODY_SPIX_RF_MINICTRL_REGS_HF_OFFSET_REG(uint64_t a)
3376 {
3377 if (a <= 1)
3378 return 0x804000001020ll + 0x1000000000ll * ((a) & 0x1);
3379 __ody_csr_fatal("SPIX_RF_MINICTRL_REGS_HF_OFFSET_REG", 1, a, 0, 0, 0, 0, 0);
3380 }
3381
3382 #define typedef_ODY_SPIX_RF_MINICTRL_REGS_HF_OFFSET_REG(a) ody_spix_rf_minictrl_regs_hf_offset_reg_t
3383 #define bustype_ODY_SPIX_RF_MINICTRL_REGS_HF_OFFSET_REG(a) CSR_TYPE_NCB32b
3384 #define basename_ODY_SPIX_RF_MINICTRL_REGS_HF_OFFSET_REG(a) "SPIX_RF_MINICTRL_REGS_HF_OFFSET_REG"
3385 #define device_bar_ODY_SPIX_RF_MINICTRL_REGS_HF_OFFSET_REG(a) 0x0 /* PF_BAR0 */
3386 #define busnum_ODY_SPIX_RF_MINICTRL_REGS_HF_OFFSET_REG(a) (a)
3387 #define arguments_ODY_SPIX_RF_MINICTRL_REGS_HF_OFFSET_REG(a) (a), -1, -1, -1
3388
3389 /**
3390 * Register (NCB32b) spi#_rf_minictrl_regs_jedec_rst_timing_reg
3391 *
3392 * SPI Rf Minictrl Regs Jedec Rst Timing Register
3393 * This register is used to introduce relative device selection delays applicable for JEDEC reset
3394 * instruction.
3395 */
3396 union ody_spix_rf_minictrl_regs_jedec_rst_timing_reg {
3397 uint32_t u;
3398 struct ody_spix_rf_minictrl_regs_jedec_rst_timing_reg_s {
3399 uint32_t tcsh_delay : 8;
3400 uint32_t tcsl_delay : 8;
3401 uint32_t reserved_16_31 : 16;
3402 } s;
3403 /* struct ody_spix_rf_minictrl_regs_jedec_rst_timing_reg_s cn; */
3404 };
3405 typedef union ody_spix_rf_minictrl_regs_jedec_rst_timing_reg ody_spix_rf_minictrl_regs_jedec_rst_timing_reg_t;
3406
3407 static inline uint64_t ODY_SPIX_RF_MINICTRL_REGS_JEDEC_RST_TIMING_REG(uint64_t a) __attribute__ ((pure, always_inline));
ODY_SPIX_RF_MINICTRL_REGS_JEDEC_RST_TIMING_REG(uint64_t a)3408 static inline uint64_t ODY_SPIX_RF_MINICTRL_REGS_JEDEC_RST_TIMING_REG(uint64_t a)
3409 {
3410 if (a <= 1)
3411 return 0x80400000100cll + 0x1000000000ll * ((a) & 0x1);
3412 __ody_csr_fatal("SPIX_RF_MINICTRL_REGS_JEDEC_RST_TIMING_REG", 1, a, 0, 0, 0, 0, 0);
3413 }
3414
3415 #define typedef_ODY_SPIX_RF_MINICTRL_REGS_JEDEC_RST_TIMING_REG(a) ody_spix_rf_minictrl_regs_jedec_rst_timing_reg_t
3416 #define bustype_ODY_SPIX_RF_MINICTRL_REGS_JEDEC_RST_TIMING_REG(a) CSR_TYPE_NCB32b
3417 #define basename_ODY_SPIX_RF_MINICTRL_REGS_JEDEC_RST_TIMING_REG(a) "SPIX_RF_MINICTRL_REGS_JEDEC_RST_TIMING_REG"
3418 #define device_bar_ODY_SPIX_RF_MINICTRL_REGS_JEDEC_RST_TIMING_REG(a) 0x0 /* PF_BAR0 */
3419 #define busnum_ODY_SPIX_RF_MINICTRL_REGS_JEDEC_RST_TIMING_REG(a) (a)
3420 #define arguments_ODY_SPIX_RF_MINICTRL_REGS_JEDEC_RST_TIMING_REG(a) (a), -1, -1, -1
3421
3422 /**
3423 * Register (NCB32b) spi#_rf_minictrl_regs_reset_pin_settings
3424 *
3425 * SPI Rf Minictrl Regs Reset Pin Settings Register
3426 * Software-controlled hardware RESET.
3427 */
3428 union ody_spix_rf_minictrl_regs_reset_pin_settings {
3429 uint32_t u;
3430 struct ody_spix_rf_minictrl_regs_reset_pin_settings_s {
3431 uint32_t sw_ctrled_hw_rst : 1;
3432 uint32_t rst_dq3_enable : 1;
3433 uint32_t reserved_2_3 : 2;
3434 uint32_t sw_ctrled_hw_rst_option : 1;
3435 uint32_t reserved_5_7 : 3;
3436 uint32_t sw_ctrled_hw_rst_bank0 : 1;
3437 uint32_t sw_ctrled_hw_rst_bank1 : 1;
3438 uint32_t sw_ctrled_hw_rst_bank2 : 1;
3439 uint32_t sw_ctrled_hw_rst_bank3 : 1;
3440 uint32_t sw_ctrled_hw_rst_bank4 : 1;
3441 uint32_t sw_ctrled_hw_rst_bank5 : 1;
3442 uint32_t sw_ctrled_hw_rst_bank6 : 1;
3443 uint32_t sw_ctrled_hw_rst_bank7 : 1;
3444 uint32_t reserved_16_31 : 16;
3445 } s;
3446 /* struct ody_spix_rf_minictrl_regs_reset_pin_settings_s cn; */
3447 };
3448 typedef union ody_spix_rf_minictrl_regs_reset_pin_settings ody_spix_rf_minictrl_regs_reset_pin_settings_t;
3449
3450 static inline uint64_t ODY_SPIX_RF_MINICTRL_REGS_RESET_PIN_SETTINGS(uint64_t a) __attribute__ ((pure, always_inline));
ODY_SPIX_RF_MINICTRL_REGS_RESET_PIN_SETTINGS(uint64_t a)3451 static inline uint64_t ODY_SPIX_RF_MINICTRL_REGS_RESET_PIN_SETTINGS(uint64_t a)
3452 {
3453 if (a <= 1)
3454 return 0x804000001004ll + 0x1000000000ll * ((a) & 0x1);
3455 __ody_csr_fatal("SPIX_RF_MINICTRL_REGS_RESET_PIN_SETTINGS", 1, a, 0, 0, 0, 0, 0);
3456 }
3457
3458 #define typedef_ODY_SPIX_RF_MINICTRL_REGS_RESET_PIN_SETTINGS(a) ody_spix_rf_minictrl_regs_reset_pin_settings_t
3459 #define bustype_ODY_SPIX_RF_MINICTRL_REGS_RESET_PIN_SETTINGS(a) CSR_TYPE_NCB32b
3460 #define basename_ODY_SPIX_RF_MINICTRL_REGS_RESET_PIN_SETTINGS(a) "SPIX_RF_MINICTRL_REGS_RESET_PIN_SETTINGS"
3461 #define device_bar_ODY_SPIX_RF_MINICTRL_REGS_RESET_PIN_SETTINGS(a) 0x0 /* PF_BAR0 */
3462 #define busnum_ODY_SPIX_RF_MINICTRL_REGS_RESET_PIN_SETTINGS(a) (a)
3463 #define arguments_ODY_SPIX_RF_MINICTRL_REGS_RESET_PIN_SETTINGS(a) (a), -1, -1, -1
3464
3465 /**
3466 * Register (NCB32b) spi#_rf_minictrl_regs_rst_recovery_reg
3467 *
3468 * SPI Rf Minictrl Regs Rst Recovery Register
3469 * This register is used to introduce relative reset recovery delay with respect to
3470 * generated xSPI Flash
3471 * Interface.
3472 */
3473 union ody_spix_rf_minictrl_regs_rst_recovery_reg {
3474 uint32_t u;
3475 struct ody_spix_rf_minictrl_regs_rst_recovery_reg_s {
3476 uint32_t rst_recovery : 32;
3477 } s;
3478 /* struct ody_spix_rf_minictrl_regs_rst_recovery_reg_s cn; */
3479 };
3480 typedef union ody_spix_rf_minictrl_regs_rst_recovery_reg ody_spix_rf_minictrl_regs_rst_recovery_reg_t;
3481
3482 static inline uint64_t ODY_SPIX_RF_MINICTRL_REGS_RST_RECOVERY_REG(uint64_t a) __attribute__ ((pure, always_inline));
ODY_SPIX_RF_MINICTRL_REGS_RST_RECOVERY_REG(uint64_t a)3483 static inline uint64_t ODY_SPIX_RF_MINICTRL_REGS_RST_RECOVERY_REG(uint64_t a)
3484 {
3485 if (a <= 1)
3486 return 0x804000001014ll + 0x1000000000ll * ((a) & 0x1);
3487 __ody_csr_fatal("SPIX_RF_MINICTRL_REGS_RST_RECOVERY_REG", 1, a, 0, 0, 0, 0, 0);
3488 }
3489
3490 #define typedef_ODY_SPIX_RF_MINICTRL_REGS_RST_RECOVERY_REG(a) ody_spix_rf_minictrl_regs_rst_recovery_reg_t
3491 #define bustype_ODY_SPIX_RF_MINICTRL_REGS_RST_RECOVERY_REG(a) CSR_TYPE_NCB32b
3492 #define basename_ODY_SPIX_RF_MINICTRL_REGS_RST_RECOVERY_REG(a) "SPIX_RF_MINICTRL_REGS_RST_RECOVERY_REG"
3493 #define device_bar_ODY_SPIX_RF_MINICTRL_REGS_RST_RECOVERY_REG(a) 0x0 /* PF_BAR0 */
3494 #define busnum_ODY_SPIX_RF_MINICTRL_REGS_RST_RECOVERY_REG(a) (a)
3495 #define arguments_ODY_SPIX_RF_MINICTRL_REGS_RST_RECOVERY_REG(a) (a), -1, -1, -1
3496
3497 /**
3498 * Register (NCB32b) spi#_rf_minictrl_regs_wp_settings
3499 *
3500 * SPI Rf Minictrl Regs Wp Settings Register
3501 * Write Protect.
3502 */
3503 union ody_spix_rf_minictrl_regs_wp_settings {
3504 uint32_t u;
3505 struct ody_spix_rf_minictrl_regs_wp_settings_s {
3506 uint32_t wp : 1;
3507 uint32_t wp_enable : 1;
3508 uint32_t reserved_2_31 : 30;
3509 } s;
3510 /* struct ody_spix_rf_minictrl_regs_wp_settings_s cn; */
3511 };
3512 typedef union ody_spix_rf_minictrl_regs_wp_settings ody_spix_rf_minictrl_regs_wp_settings_t;
3513
3514 static inline uint64_t ODY_SPIX_RF_MINICTRL_REGS_WP_SETTINGS(uint64_t a) __attribute__ ((pure, always_inline));
ODY_SPIX_RF_MINICTRL_REGS_WP_SETTINGS(uint64_t a)3515 static inline uint64_t ODY_SPIX_RF_MINICTRL_REGS_WP_SETTINGS(uint64_t a)
3516 {
3517 if (a <= 1)
3518 return 0x804000001000ll + 0x1000000000ll * ((a) & 0x1);
3519 __ody_csr_fatal("SPIX_RF_MINICTRL_REGS_WP_SETTINGS", 1, a, 0, 0, 0, 0, 0);
3520 }
3521
3522 #define typedef_ODY_SPIX_RF_MINICTRL_REGS_WP_SETTINGS(a) ody_spix_rf_minictrl_regs_wp_settings_t
3523 #define bustype_ODY_SPIX_RF_MINICTRL_REGS_WP_SETTINGS(a) CSR_TYPE_NCB32b
3524 #define basename_ODY_SPIX_RF_MINICTRL_REGS_WP_SETTINGS(a) "SPIX_RF_MINICTRL_REGS_WP_SETTINGS"
3525 #define device_bar_ODY_SPIX_RF_MINICTRL_REGS_WP_SETTINGS(a) 0x0 /* PF_BAR0 */
3526 #define busnum_ODY_SPIX_RF_MINICTRL_REGS_WP_SETTINGS(a) (a)
3527 #define arguments_ODY_SPIX_RF_MINICTRL_REGS_WP_SETTINGS(a) (a), -1, -1, -1
3528
3529 /**
3530 * Register (NCB) spi#_shim_cfg
3531 *
3532 * SPI Shim Configuration Register
3533 * This register allows configuration of various shim (xSPI) features. The fields XS_NCB_OOB_*
3534 * are captured when there are no outstanding OOB errors indicated in INTSTAT and a new OOB error
3535 * arrives. The fields XS_BAD_DMA_* are captured when there are no outstanding DMA errors
3536 * indicated in INTSTAT and a new DMA error arrives.
3537 */
3538 union ody_spix_shim_cfg {
3539 uint64_t u;
3540 struct ody_spix_shim_cfg_s {
3541 uint64_t reserved_0_9 : 10;
3542 uint64_t dma_write_cmd : 1;
3543 uint64_t reserved_11 : 1;
3544 uint64_t dma_read_cmd : 2;
3545 uint64_t reserved_14_39 : 26;
3546 uint64_t xm_bad_dma_type : 4;
3547 uint64_t reserved_44_46 : 3;
3548 uint64_t xm_bad_dma_wrn : 1;
3549 uint64_t xs_ncb_oob_osrc : 12;
3550 uint64_t reserved_60_62 : 3;
3551 uint64_t xs_ncb_oob_wrn : 1;
3552 } s;
3553 /* struct ody_spix_shim_cfg_s cn; */
3554 };
3555 typedef union ody_spix_shim_cfg ody_spix_shim_cfg_t;
3556
3557 static inline uint64_t ODY_SPIX_SHIM_CFG(uint64_t a) __attribute__ ((pure, always_inline));
ODY_SPIX_SHIM_CFG(uint64_t a)3558 static inline uint64_t ODY_SPIX_SHIM_CFG(uint64_t a)
3559 {
3560 if (a <= 1)
3561 return 0x804000001050ll + 0x1000000000ll * ((a) & 0x1);
3562 __ody_csr_fatal("SPIX_SHIM_CFG", 1, a, 0, 0, 0, 0, 0);
3563 }
3564
3565 #define typedef_ODY_SPIX_SHIM_CFG(a) ody_spix_shim_cfg_t
3566 #define bustype_ODY_SPIX_SHIM_CFG(a) CSR_TYPE_NCB
3567 #define basename_ODY_SPIX_SHIM_CFG(a) "SPIX_SHIM_CFG"
3568 #define device_bar_ODY_SPIX_SHIM_CFG(a) 0x0 /* PF_BAR0 */
3569 #define busnum_ODY_SPIX_SHIM_CFG(a) (a)
3570 #define arguments_ODY_SPIX_SHIM_CFG(a) (a), -1, -1, -1
3571
3572 /**
3573 * Register (NCB) spi#_spare_reg#
3574 *
3575 * SPI Transfer Function Read Data Register
3576 * This register has the read data from SPI device
3577 */
3578 union ody_spix_spare_regx {
3579 uint64_t u;
3580 struct ody_spix_spare_regx_s {
3581 uint64_t spare : 64;
3582 } s;
3583 /* struct ody_spix_spare_regx_s cn; */
3584 };
3585 typedef union ody_spix_spare_regx ody_spix_spare_regx_t;
3586
3587 static inline uint64_t ODY_SPIX_SPARE_REGX(uint64_t a, uint64_t b) __attribute__ ((pure, always_inline));
ODY_SPIX_SPARE_REGX(uint64_t a,uint64_t b)3588 static inline uint64_t ODY_SPIX_SPARE_REGX(uint64_t a, uint64_t b)
3589 {
3590 if ((a <= 1) && (b <= 1))
3591 return 0x804000008220ll + 0x1000000000ll * ((a) & 0x1) + 8ll * ((b) & 0x1);
3592 __ody_csr_fatal("SPIX_SPARE_REGX", 2, a, b, 0, 0, 0, 0);
3593 }
3594
3595 #define typedef_ODY_SPIX_SPARE_REGX(a, b) ody_spix_spare_regx_t
3596 #define bustype_ODY_SPIX_SPARE_REGX(a, b) CSR_TYPE_NCB
3597 #define basename_ODY_SPIX_SPARE_REGX(a, b) "SPIX_SPARE_REGX"
3598 #define device_bar_ODY_SPIX_SPARE_REGX(a, b) 0x0 /* PF_BAR0 */
3599 #define busnum_ODY_SPIX_SPARE_REGX(a, b) (a)
3600 #define arguments_ODY_SPIX_SPARE_REGX(a, b) (a), (b), -1, -1
3601
3602 /**
3603 * Register (NCB) spi#_xfer_const
3604 *
3605 * SPI Constants Register
3606 */
3607 union ody_spix_xfer_const {
3608 uint64_t u;
3609 struct ody_spix_xfer_const_s {
3610 uint64_t has_xfer_support : 1;
3611 uint64_t read_buf_depth : 5;
3612 uint64_t reserved_6_63 : 58;
3613 } s;
3614 /* struct ody_spix_xfer_const_s cn; */
3615 };
3616 typedef union ody_spix_xfer_const ody_spix_xfer_const_t;
3617
3618 static inline uint64_t ODY_SPIX_XFER_CONST(uint64_t a) __attribute__ ((pure, always_inline));
ODY_SPIX_XFER_CONST(uint64_t a)3619 static inline uint64_t ODY_SPIX_XFER_CONST(uint64_t a)
3620 {
3621 if (a <= 1)
3622 return 0x804000008230ll + 0x1000000000ll * ((a) & 0x1);
3623 __ody_csr_fatal("SPIX_XFER_CONST", 1, a, 0, 0, 0, 0, 0);
3624 }
3625
3626 #define typedef_ODY_SPIX_XFER_CONST(a) ody_spix_xfer_const_t
3627 #define bustype_ODY_SPIX_XFER_CONST(a) CSR_TYPE_NCB
3628 #define basename_ODY_SPIX_XFER_CONST(a) "SPIX_XFER_CONST"
3629 #define device_bar_ODY_SPIX_XFER_CONST(a) 0x0 /* PF_BAR0 */
3630 #define busnum_ODY_SPIX_XFER_CONST(a) (a)
3631 #define arguments_ODY_SPIX_XFER_CONST(a) (a), -1, -1, -1
3632
3633 /**
3634 * Register (NCB) spi#_xfer_func_cmd
3635 *
3636 * SPI XFER Function Command Register
3637 * This register is used to issue the command for TX_RX_MODE, where the Xfer State Machine
3638 * is used to drive MOSI.
3639 */
3640 union ody_spix_xfer_func_cmd {
3641 uint64_t u;
3642 struct ody_spix_xfer_func_cmd_s {
3643 uint64_t dir : 1;
3644 uint64_t reserved_1 : 1;
3645 uint64_t size : 6;
3646 uint64_t addr : 24;
3647 uint64_t wdata : 32;
3648 } s;
3649 /* struct ody_spix_xfer_func_cmd_s cn; */
3650 };
3651 typedef union ody_spix_xfer_func_cmd ody_spix_xfer_func_cmd_t;
3652
3653 static inline uint64_t ODY_SPIX_XFER_FUNC_CMD(uint64_t a) __attribute__ ((pure, always_inline));
ODY_SPIX_XFER_FUNC_CMD(uint64_t a)3654 static inline uint64_t ODY_SPIX_XFER_FUNC_CMD(uint64_t a)
3655 {
3656 if (a <= 1)
3657 return 0x804000008200ll + 0x1000000000ll * ((a) & 0x1);
3658 __ody_csr_fatal("SPIX_XFER_FUNC_CMD", 1, a, 0, 0, 0, 0, 0);
3659 }
3660
3661 #define typedef_ODY_SPIX_XFER_FUNC_CMD(a) ody_spix_xfer_func_cmd_t
3662 #define bustype_ODY_SPIX_XFER_FUNC_CMD(a) CSR_TYPE_NCB
3663 #define basename_ODY_SPIX_XFER_FUNC_CMD(a) "SPIX_XFER_FUNC_CMD"
3664 #define device_bar_ODY_SPIX_XFER_FUNC_CMD(a) 0x0 /* PF_BAR0 */
3665 #define busnum_ODY_SPIX_XFER_FUNC_CMD(a) (a)
3666 #define arguments_ODY_SPIX_XFER_FUNC_CMD(a) (a), -1, -1, -1
3667
3668 /**
3669 * Register (NCB) spi#_xfer_func_ctrl
3670 *
3671 * SPI XFER Function Control Register
3672 * This register is used to control the Xfer State Machine for both the modes.
3673 */
3674 union ody_spix_xfer_func_ctrl {
3675 uint64_t u;
3676 struct ody_spix_xfer_func_ctrl_s {
3677 uint64_t xfer_func_start : 1;
3678 uint64_t clk_drive_pol : 1;
3679 uint64_t clk_capture_pol : 1;
3680 uint64_t xfer_func_enable : 1;
3681 uint64_t receive_enable : 1;
3682 uint64_t tpm_device : 1;
3683 uint64_t cs_n_hold : 4;
3684 uint64_t flush_read_buf : 1;
3685 uint64_t soft_reset : 1;
3686 uint64_t read_buf_watermark : 6;
3687 uint64_t reserved_18_63 : 46;
3688 } s;
3689 /* struct ody_spix_xfer_func_ctrl_s cn; */
3690 };
3691 typedef union ody_spix_xfer_func_ctrl ody_spix_xfer_func_ctrl_t;
3692
3693 static inline uint64_t ODY_SPIX_XFER_FUNC_CTRL(uint64_t a) __attribute__ ((pure, always_inline));
ODY_SPIX_XFER_FUNC_CTRL(uint64_t a)3694 static inline uint64_t ODY_SPIX_XFER_FUNC_CTRL(uint64_t a)
3695 {
3696 if (a <= 1)
3697 return 0x804000008210ll + 0x1000000000ll * ((a) & 0x1);
3698 __ody_csr_fatal("SPIX_XFER_FUNC_CTRL", 1, a, 0, 0, 0, 0, 0);
3699 }
3700
3701 #define typedef_ODY_SPIX_XFER_FUNC_CTRL(a) ody_spix_xfer_func_ctrl_t
3702 #define bustype_ODY_SPIX_XFER_FUNC_CTRL(a) CSR_TYPE_NCB
3703 #define basename_ODY_SPIX_XFER_FUNC_CTRL(a) "SPIX_XFER_FUNC_CTRL"
3704 #define device_bar_ODY_SPIX_XFER_FUNC_CTRL(a) 0x0 /* PF_BAR0 */
3705 #define busnum_ODY_SPIX_XFER_FUNC_CTRL(a) (a)
3706 #define arguments_ODY_SPIX_XFER_FUNC_CTRL(a) (a), -1, -1, -1
3707
3708 /**
3709 * Register (NCB) spi#_xfer_func_ctrl_read_data#
3710 *
3711 * SPI Transfer Function Read Data Register
3712 * This register has the read data from SPI device
3713 */
3714 union ody_spix_xfer_func_ctrl_read_datax {
3715 uint64_t u;
3716 struct ody_spix_xfer_func_ctrl_read_datax_s {
3717 uint64_t rdata : 64;
3718 } s;
3719 /* struct ody_spix_xfer_func_ctrl_read_datax_s cn; */
3720 };
3721 typedef union ody_spix_xfer_func_ctrl_read_datax ody_spix_xfer_func_ctrl_read_datax_t;
3722
3723 static inline uint64_t ODY_SPIX_XFER_FUNC_CTRL_READ_DATAX(uint64_t a, uint64_t b) __attribute__ ((pure, always_inline));
ODY_SPIX_XFER_FUNC_CTRL_READ_DATAX(uint64_t a,uint64_t b)3724 static inline uint64_t ODY_SPIX_XFER_FUNC_CTRL_READ_DATAX(uint64_t a, uint64_t b)
3725 {
3726 if ((a <= 1) && (b <= 31))
3727 return 0x804000008000ll + 0x1000000000ll * ((a) & 0x1) + 8ll * ((b) & 0x1f);
3728 __ody_csr_fatal("SPIX_XFER_FUNC_CTRL_READ_DATAX", 2, a, b, 0, 0, 0, 0);
3729 }
3730
3731 #define typedef_ODY_SPIX_XFER_FUNC_CTRL_READ_DATAX(a, b) ody_spix_xfer_func_ctrl_read_datax_t
3732 #define bustype_ODY_SPIX_XFER_FUNC_CTRL_READ_DATAX(a, b) CSR_TYPE_NCB
3733 #define basename_ODY_SPIX_XFER_FUNC_CTRL_READ_DATAX(a, b) "SPIX_XFER_FUNC_CTRL_READ_DATAX"
3734 #define device_bar_ODY_SPIX_XFER_FUNC_CTRL_READ_DATAX(a, b) 0x0 /* PF_BAR0 */
3735 #define busnum_ODY_SPIX_XFER_FUNC_CTRL_READ_DATAX(a, b) (a)
3736 #define arguments_ODY_SPIX_XFER_FUNC_CTRL_READ_DATAX(a, b) (a), (b), -1, -1
3737
3738 /**
3739 * Register (NCB) spi#_xfer_func_sts
3740 *
3741 * SPI XFER Function Control Read and write status Register
3742 * This register holds the status of the Xfer State Machine. This register should be
3743 * polled by software
3744 * to know read write operation is complete etc.
3745 */
3746 union ody_spix_xfer_func_sts {
3747 uint64_t u;
3748 struct ody_spix_xfer_func_sts_s {
3749 uint64_t read_done : 1;
3750 uint64_t write_done : 1;
3751 uint64_t receive_buf_full : 1;
3752 uint64_t receive_buf_empty : 1;
3753 uint64_t xfer_ctrl_busy : 1;
3754 uint64_t xfer_cur_state : 3;
3755 uint64_t ready_received : 1;
3756 uint64_t water_mark_reached : 1;
3757 uint64_t write_buf_full : 1;
3758 uint64_t write_buf_empty : 1;
3759 uint64_t num_entries_write_buf : 5;
3760 uint64_t num_entries_read_buf : 6;
3761 uint64_t reserved_23_63 : 41;
3762 } s;
3763 /* struct ody_spix_xfer_func_sts_s cn; */
3764 };
3765 typedef union ody_spix_xfer_func_sts ody_spix_xfer_func_sts_t;
3766
3767 static inline uint64_t ODY_SPIX_XFER_FUNC_STS(uint64_t a) __attribute__ ((pure, always_inline));
ODY_SPIX_XFER_FUNC_STS(uint64_t a)3768 static inline uint64_t ODY_SPIX_XFER_FUNC_STS(uint64_t a)
3769 {
3770 if (a <= 1)
3771 return 0x804000008218ll + 0x1000000000ll * ((a) & 0x1);
3772 __ody_csr_fatal("SPIX_XFER_FUNC_STS", 1, a, 0, 0, 0, 0, 0);
3773 }
3774
3775 #define typedef_ODY_SPIX_XFER_FUNC_STS(a) ody_spix_xfer_func_sts_t
3776 #define bustype_ODY_SPIX_XFER_FUNC_STS(a) CSR_TYPE_NCB
3777 #define basename_ODY_SPIX_XFER_FUNC_STS(a) "SPIX_XFER_FUNC_STS"
3778 #define device_bar_ODY_SPIX_XFER_FUNC_STS(a) 0x0 /* PF_BAR0 */
3779 #define busnum_ODY_SPIX_XFER_FUNC_STS(a) (a)
3780 #define arguments_ODY_SPIX_XFER_FUNC_STS(a) (a), -1, -1, -1
3781
3782 /**
3783 * Register (NCB) spi#_xfer_func_wdata
3784 *
3785 * SPI XFER Function Write Data Register
3786 * This register is used in TX_RX_MODE of Xfer State Machine when the SIZE is more than
3787 * 4 bytes and upto 64 bytes.
3788 */
3789 union ody_spix_xfer_func_wdata {
3790 uint64_t u;
3791 struct ody_spix_xfer_func_wdata_s {
3792 uint64_t wdata : 64;
3793 } s;
3794 /* struct ody_spix_xfer_func_wdata_s cn; */
3795 };
3796 typedef union ody_spix_xfer_func_wdata ody_spix_xfer_func_wdata_t;
3797
3798 static inline uint64_t ODY_SPIX_XFER_FUNC_WDATA(uint64_t a) __attribute__ ((pure, always_inline));
ODY_SPIX_XFER_FUNC_WDATA(uint64_t a)3799 static inline uint64_t ODY_SPIX_XFER_FUNC_WDATA(uint64_t a)
3800 {
3801 if (a <= 1)
3802 return 0x804000008208ll + 0x1000000000ll * ((a) & 0x1);
3803 __ody_csr_fatal("SPIX_XFER_FUNC_WDATA", 1, a, 0, 0, 0, 0, 0);
3804 }
3805
3806 #define typedef_ODY_SPIX_XFER_FUNC_WDATA(a) ody_spix_xfer_func_wdata_t
3807 #define bustype_ODY_SPIX_XFER_FUNC_WDATA(a) CSR_TYPE_NCB
3808 #define basename_ODY_SPIX_XFER_FUNC_WDATA(a) "SPIX_XFER_FUNC_WDATA"
3809 #define device_bar_ODY_SPIX_XFER_FUNC_WDATA(a) 0x0 /* PF_BAR0 */
3810 #define busnum_ODY_SPIX_XFER_FUNC_WDATA(a) (a)
3811 #define arguments_ODY_SPIX_XFER_FUNC_WDATA(a) (a), -1, -1, -1
3812
3813 #endif /* __ODY_CSRS_SPI_H__ */
3814