fix(cpus): workaround for C1-Pro erratum 3300099

C1-Pro erratum 3300099 is a Cat B erratum that applies
to revisions r0p0, r1p0, and is fixed in r1p1.

This is workaround for accessing ICH_VMCR_EL2.

fix(cpus): workaround for C1-Pro erratum 3300099

C1-Pro erratum 3300099 is a Cat B erratum that applies
to revisions r0p0, r1p0, and is fixed in r1p1.

This is workaround for accessing ICH_VMCR_EL2.
When ICH_VMCR_EL2.VBPR1 is written in Secure state (SCR_EL3.NS==0)
and then subsequently read in Non-secure state (SCR_EL3.NS==1), a
wrong value might be returned. The same issue exists in the opposite way.

Adding workaround in EL3 software that performs context save/restore
on a change of Security state to use a value of SCR_EL3.NS when
accessing ICH_VMCR_EL2 that reflects the Security state that owns the
data being saved or restored. For example, EL3 software should set
SCR_EL3.NS to 1 when saving or restoring the value ICH_VMCR_EL2 for
Non-secure(or Realm) state. EL3 software should clear
SCR_EL3.NS to 0 when saving or restoring the value ICH_VMCR_EL2 for
Secure state.

SDEN documentation:
https://developer.arm.com/documentation/SDEN-3273080/1300/?lang=en

Change-Id: If24d3230c4b4e87fcb831d446cf0d0c68c95ea18
Signed-off-by: Xialin Liu <xialin.liu@arm.com>

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fix(cpus): workaround for Neoverse-V3 erratum 3312417

Neoverse-V3 erratum 3312417 is a Cat B erratum that applies
to revisions r0p0 and r0p1, and is fixed in r0p2.

This errata can be avoided by add

fix(cpus): workaround for Neoverse-V3 erratum 3312417

Neoverse-V3 erratum 3312417 is a Cat B erratum that applies
to revisions r0p0 and r0p1, and is fixed in r0p2.

This errata can be avoided by adding a speculation barrier
instruction following writes to the SSBS register to
ensure the new value of PSTATE.SSBS affects the subsequent
instructions in the execution stream under speculation.

SDEN documentation:
https://developer.arm.com/documentation/SDEN-2891958

Change-Id: I78a7682cbdf3dbc4c31fcca8cbd892350b998cf4
Signed-off-by: John Powell <john.powell@arm.com>

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fix(cpus): workaround for Neoverse V3 erratum 3878291

Neoverse V3 erratum 3878291 is a Cat B erratum that applies to
revisions r0p0, r0p1 and r0p2, and is still open.

The erratum can be avoided by

fix(cpus): workaround for Neoverse V3 erratum 3878291

Neoverse V3 erratum 3878291 is a Cat B erratum that applies to
revisions r0p0, r0p1 and r0p2, and is still open.

The erratum can be avoided by setting CPUACTLR4_EL1[57]. Setting this
bit causes the PE to treat GPT invalidations as TLBI PAALL, thereby
invalidating all GPT entries. If the physical memory map does not use
addresses with bits 46 or 47 set, then no workaround is necessary.

SDEN documentation:
https://developer.arm.com/documentation/SDEN-2891958

Change-Id: I0ebab877b6481a18bec963b95cf2f37c97d8de65
Signed-off-by: John Powell <john.powell@arm.com>

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fix(cpus): workaround for Neoverse V3 erratum 3864536

Neoverse V3 erratum 3864536 is a Cat B erratum that applies to
revisions r0p0, r0p1 and r0p2, and is still open.

The erratum can be avoided by

fix(cpus): workaround for Neoverse V3 erratum 3864536

Neoverse V3 erratum 3864536 is a Cat B erratum that applies to
revisions r0p0, r0p1 and r0p2, and is still open.

The erratum can be avoided by setting CPUACTLR2[22] to 1'b1 which will
disable linking multiple Non-Cacheable or Device GRE loads to the same
read request for the cache-line. This might have a significant
performance impact to Non-cacheable and Device GRE read bandwidth for
streaming scenarios.

SDEN documentation:
https://developer.arm.com/documentation/SDEN-2891958

Change-Id: If4b20d941d628b92748b14d027b8127f74005eff
Signed-off-by: John Powell <john.powell@arm.com>

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fix(cpus): workaround for Neoverse V3 erratum 3782181

Neoverse V3 erratum 3782181 is a Cat B erratum that applies to
revision r0p1 and is fixed in r0p2.

If the erratum condition occurs, then the co

fix(cpus): workaround for Neoverse V3 erratum 3782181

Neoverse V3 erratum 3782181 is a Cat B erratum that applies to
revision r0p1 and is fixed in r0p2.

If the erratum condition occurs, then the core will not leave the
FULL_RET power mode, which will cause the system to deadlock. The
FULL_RET power mode should not be enabled. This can be done by setting
both IMP_CPUPWRCTLR_EL1.WFE_RET_CTL and IMP_CPUPWRCTLR_EL1.WFI_RET_CTL
to 0b000 which is the default value.

SDEN documentation:
https://developer.arm.com/documentation/SDEN-2891958

Change-Id: Icfa463cf4888bd48f16a218e7ad399528feca55e
Signed-off-by: John Powell <john.powell@arm.com>

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fix(cpus): workaround for Neoverse V3 erratum 3734562

Neoverse V3 erratum 3734562 is a Cat B erratum that applies to
revisions r0p0 and r0p1, and is fixed in r0p2.

This erratum can be avoided throu

fix(cpus): workaround for Neoverse V3 erratum 3734562

Neoverse V3 erratum 3734562 is a Cat B erratum that applies to
revisions r0p0 and r0p1, and is fixed in r0p2.

This erratum can be avoided through the following write sequence to
several IMPLEMENTATION DEFINED registers, which will execute a PSB
instruction following the TSB CSYNC instruction. The code sequence
should be applied early in the boot sequence prior to executing a TSB
CSYNC instruction.

SDEN documentation:
https://developer.arm.com/documentation/SDEN-2891958

Change-Id: Ib3c35c7e619e6a836c974b7016bb6a4d66da48d6
Signed-off-by: John Powell <john.powell@arm.com>

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fix(cpus): workaround for Neoverse V3 erratum 3696307

Neoverse V3 erratum 3696307 is a Cat B erratum that applies to
revisions r0p0 and r0p1, and is fixed in r0p2.

The erratum can be avoided by dis

fix(cpus): workaround for Neoverse V3 erratum 3696307

Neoverse V3 erratum 3696307 is a Cat B erratum that applies to
revisions r0p0 and r0p1, and is fixed in r0p2.

The erratum can be avoided by disabling the affected prefetcher by
setting CPUACTLR6_EL1[41].

SDEN documentation:
https://developer.arm.com/documentation/SDEN-2891958

Change-Id: If274749621549356e41485d0bf09682281df3a9b
Signed-off-by: John Powell <john.powell@arm.com>

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fix(cpus): workaround for C1-Pro erratum 3338470

C1-Pro erratum 3338470 is a Cat B erratum that applies
to revision r0p0, and is fixed in r1p0.

This errata can be avoid by having a speculation barr

fix(cpus): workaround for C1-Pro erratum 3338470

C1-Pro erratum 3338470 is a Cat B erratum that applies
to revision r0p0, and is fixed in r1p0.

This errata can be avoid by having a speculation barrier
instruction following writes to the SSBS register to
ensure the new value of PSTATE.SSBS affects the subsequent
instructions in the execution stream under speculation.

SDEN documentation:
https://developer.arm.com/documentation/SDEN-3273080/1300/?lang=en

Change-Id: I86e2b8f70ceb468c75c0386a790641d51eeea9cb
Signed-off-by: Xialin Liu <xialin.liu@arm.com>

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fix(cpus): workaround for C1-Pro erratum 3362007

C1-Pro erratum 3362007 is a Cat B erratum that applies to
CPU revision r0p0 and is fixed in r1p0.

This erratum can be avoided by setting CPUACTLR2_E

fix(cpus): workaround for C1-Pro erratum 3362007

C1-Pro erratum 3362007 is a Cat B erratum that applies to
CPU revision r0p0 and is fixed in r1p0.

This erratum can be avoided by setting CPUACTLR2_EL1[27] to 1.
Only a minor increase in power consumption is expected.

SDEN documentation:
https://developer.arm.com/documentation/SDEN-3273080/1300/?lang=en

Change-Id: I529e9812bddffe927c986f9b5ee135f4866aa455
Signed-off-by: Xialin Liu <xialin.liu@arm.com>

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fix(cpus): workaround for C1-Pro erratum 3684268

C1-Pro erratum 3684268 is a Cat B erratum that applies
to revisions r0p0, r1p0 and it is fixed in r1p1.

The erratum is avoided by disabling the affe

fix(cpus): workaround for C1-Pro erratum 3684268

C1-Pro erratum 3684268 is a Cat B erratum that applies
to revisions r0p0, r1p0 and it is fixed in r1p1.

The erratum is avoided by disabling the affected prefetcher,
which is done by setting CPUECTLR2_EL1[49] to 1.

SDEN documentation:
https://developer.arm.com/documentation/SDEN-3273080/1300/?lang=en

Change-Id: I7929e931572471370b1a899d412b11f1c4d206c8
Signed-off-by: Xialin Liu <xialin.liu@arm.com>

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fix(cpus): workaround for C1-Pro erratum 3694158

C1-Pro erratum 3694158 is a Cat B erratum that applies
to revisions r0p0, r1p0 and r1p1, it is fixed in r1p2.

This erratum can be avoided by inserti

fix(cpus): workaround for C1-Pro erratum 3694158

C1-Pro erratum 3694158 is a Cat B erratum that applies
to revisions r0p0, r1p0 and r1p1, it is fixed in r1p2.

This erratum can be avoided by inserting a DMB LD after
each DSB ST instruction with a CPU implementation specific
patch sequence.

SDEN documentation:
https://developer.arm.com/documentation/SDEN-3273080/1300/?lang=en

Change-Id: I38f0fb6565110c579ab16b76e0f4ca601fa1b912
Signed-off-by: Xialin Liu <xialin.liu@arm.com>

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fix(cpus): workaround for C1-Pro erratum 3706576

C1-Pro erratum 3706576 is a Cat B erratum that applies to
CPU revisions r0p0 and r1p0, and is fixed in r1p1.

This erratum might cause data corruptio

fix(cpus): workaround for C1-Pro erratum 3706576

C1-Pro erratum 3706576 is a Cat B erratum that applies to
CPU revisions r0p0 and r1p0, and is fixed in r1p1.

This erratum might cause data corruption when Memory read
effect crossing a 64B boundary, which can be avoided by
setting CPUACTLR2_EL1[37] to 1. Setting this bit is expected
to have a negligible performance impact.

SDEN documentation:
https://developer.arm.com/documentation/SDEN-3273080/1300/?lang=en

Change-Id: Ie427e56c682065bdf82da9b11e71da6383db4e73
Signed-off-by: Xialin Liu <xialin.liu@arm.com>

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Merge changes from topic "ssbs_errata_catchup" into integration

* changes:
fix(cpus): workaround for Cortex-A720AE erratum 3456103
fix(cpus): workaround for Cortex-A720 erratum 3456091
fix(cpu

Merge changes from topic "ssbs_errata_catchup" into integration

* changes:
fix(cpus): workaround for Cortex-A720AE erratum 3456103
fix(cpus): workaround for Cortex-A720 erratum 3456091
fix(cpus): workaround for Cortex-A715 erratum 3456084
fix(cpus): workaround for Cortex-X2 erratum 3324338
fix(cpus): workaround for Cortex-A710 erratum 3324338

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fix(docs): fixing the name for C1 premium errata 3324333

The macro name for C1 premium errata was incorrect and
thus fixing the naming.

Change-Id: I33256e618e199c6113578bc920019015a0c51284
Signed-o

fix(docs): fixing the name for C1 premium errata 3324333

The macro name for C1 premium errata was incorrect and
thus fixing the naming.

Change-Id: I33256e618e199c6113578bc920019015a0c51284
Signed-off-by: Xialin Liu <xialin.liu@arm.com>

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fix(cpus): workaround for C1-Premium erratum 3324333

C1-Premium erratum 3324333 is a Cat B erratum that applies
to revision r0p0, and it is fixed in r1p0.

This errata can be avoided by having a spe

fix(cpus): workaround for C1-Premium erratum 3324333

C1-Premium erratum 3324333 is a Cat B erratum that applies
to revision r0p0, and it is fixed in r1p0.

This errata can be avoided by having a speculation barrier instruction
to ensure the new value of PSTATE.SSBS affects the subsequent
instructions in the execution stream under speculation.

SDEN documentation:
https://developer.arm.com/documentation/111078/latest

Change-Id: Ic9f09c56e7cc94f3d45e86d284971ee2b4b0fb40
Signed-off-by: Xialin Liu <xialin.liu@arm.com>
Signed-off-by: Govindraj Raja <govindraj.raja@arm.com>

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fix(cpus): workaround for C1-Premium erratum 4102704

C1-Premium erratum 4102704 is a Cat B erratum that applies
to revisions r0p0, r1p0 and it is still open.

The erratum can be avoided by setting C

fix(cpus): workaround for C1-Premium erratum 4102704

C1-Premium erratum 4102704 is a Cat B erratum that applies
to revisions r0p0, r1p0 and it is still open.

The erratum can be avoided by setting CPUACTLR4_EL1[23] to 1.
Overall expected performance degradation is ~1.36%, but
isolated benchmark components might see higher or lower impact.

SDEN documentation:
https://developer.arm.com/documentation/111078/latest

Change-Id: Id9b73799696a5ce04e656e07e4ddb548c5a7b042
Signed-off-by: Xialin Liu <xialin.liu@arm.com>

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fix(cpus): workaround for C1-Premium erratum 3926381

C1-Premium erratum 3926381 is a Cat B erratum that applies
to revision r1p0 and is still open.

This errata can be avoided by converting WFx and

fix(cpus): workaround for C1-Premium erratum 3926381

C1-Premium erratum 3926381 is a Cat B erratum that applies
to revision r1p0 and is still open.

This errata can be avoided by converting WFx and WFxT
instructions to NOP when PSTATE.SM=1. After it is applied,
the code only converts WFx and WFxT instructions to NOP when
PSTATE.SM=1 or when PSTATE.ZA=1.

SDEN documentation:
https://developer.arm.com/documentation/111078/8-0/?lang=en

Change-Id: I24483fa88c6292f6dbe2950ebef88eebb5cc4e8d
Signed-off-by: Xialin Liu <xialin.liu@arm.com>

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fix(cpus): workaround for C1-Premium erratum 3865171

C1-Premium erratum 3865171 is a Cat B erratum that applies
to revisions r0p0, r1p0 and is still open.

The erratum can be avoided by setting CPUA

fix(cpus): workaround for C1-Premium erratum 3865171

C1-Premium erratum 3865171 is a Cat B erratum that applies
to revisions r0p0, r1p0 and is still open.

The erratum can be avoided by setting CPUACTLR2_EL1[22] to 1,
which will disable linking multiple Non-Cacheable or Device
GRE loads to the same read request for the cache-line. This
might have a significant performance impact to Non-cacheable
and Device GRE read bandwidth for streaming scenarios.

SDEN documentation:
https://developer.arm.com/documentation/111078/latest

Change-Id: I0b97dfc1dd989e4d3e35716b0163b99c9719a0e6
Signed-off-by: Xialin Liu <xialin.liu@arm.com>

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fix(cpus): workaround for C1-Premium erratum 3815514

C1-Premium erratum 3815514 is a Cat B erratum that applies
to revisions r0p0, r1p0 and is still open.

The erratum can be avoided by setting CPUA

fix(cpus): workaround for C1-Premium erratum 3815514

C1-Premium erratum 3815514 is a Cat B erratum that applies
to revisions r0p0, r1p0 and is still open.

The erratum can be avoided by setting CPUACTLR5[13] to 1.
This is expected to result in a small performance degradation
for workloads that use MTE. The degradation might be
approximately 1.6% when using MTE imprecise mode or 0.9% for
MTE precise mode.

SDEN documentation:
https://developer.arm.com/documentation/111078/latest

Change-Id: Id52a1a077459bd16de16b1ae00fc783250d197ed
Signed-off-by: Xialin Liu <xialin.liu@arm.com>

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fix(cpus): workaround for C1-Premium erratum 3705939

C1-Premium erratum 3705939 is a Cat B erratum that applies
to revisions r0p0, r1p0 and is still open.

The erratum can be avoided by setting CPUA

fix(cpus): workaround for C1-Premium erratum 3705939

C1-Premium erratum 3705939 is a Cat B erratum that applies
to revisions r0p0, r1p0 and is still open.

The erratum can be avoided by setting CPUACTLR_EL1[48] to 1,
which disables a RDFFR optimization. Setting this bit has
negligible impact on GB6/SPECint performance, but will have an impact
on SVE RDFFR performance. Please contact Arm for more details.

SDEN documentation:
https://developer.arm.com/documentation/111078/latest

Change-Id: I4dc68f8fcb6275eab158c7fa6491536c62060ac0
Signed-off-by: Xialin Liu <xialin.liu@arm.com>

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fix(cpus): workaround for C1-Premium erratum 3684152

C1-Premium erratum 3684152 is a Cat B erratum that applies
to revision r0p0, and it is fixed in r1p0.

The erratum can be avoided by setting CPUA

fix(cpus): workaround for C1-Premium erratum 3684152

C1-Premium erratum 3684152 is a Cat B erratum that applies
to revision r0p0, and it is fixed in r1p0.

The erratum can be avoided by setting CPUACTLR_EL1[60:58] to
3'b001, which has a small performance impact.

SDEN documentation:
https://developer.arm.com/documentation/111078/latest

Change-Id: I2e677b0e6cf3ce453eae54300c5c0072d734a341
Signed-off-by: Xialin Liu <xialin.liu@arm.com>

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fix(cpus): workaround for C1-Premium erratum 3651221

C1-Premium erratum 3651221 is a Cat B erratum that applies
to revision r0p0, and it is fixed in r1p0.

The erratum can be avoided by disabling th

fix(cpus): workaround for C1-Premium erratum 3651221

C1-Premium erratum 3651221 is a Cat B erratum that applies
to revision r0p0, and it is fixed in r1p0.

The erratum can be avoided by disabling the affected prefetcher
setting CPUACTLR6_EL1[41] to 1.

SDEN documentation:
https://developer.arm.com/documentation/111078/latest

Change-Id: I5ebe282be8f88fb2fcc1d33cec9c1db144316077
Signed-off-by: Xialin Liu <xialin.liu@arm.com>

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fix(cpus): workaround for C1-Premium erratum 3502731

C1-Premium erratum 3502731 is a Cat B erratum that applies
to revision r0p0, and it is fixed in r1p0.

The erratum can be avoided by setting CPUA

fix(cpus): workaround for C1-Premium erratum 3502731

C1-Premium erratum 3502731 is a Cat B erratum that applies
to revision r0p0, and it is fixed in r1p0.

The erratum can be avoided by setting CPUACTLR4[23] to 1,
which will disable Memory Renaming optimization.
The performance impact of setting this chicken bit is about
0.82% in GB6.

SDEN documentation:
https://developer.arm.com/documentation/111078/latest

Change-Id: Idc6ec2a742ed0f974d026aa63d7c9c5b248ef33b
Signed-off-by: Xialin Liu <xialin.liu@arm.com>

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fix(cpus): workaround for Cortex-A720AE erratum 3456103

Cortex-A720AE erratum 3456103 is a Cat B erratum that applies
to revisions r0p0 and r0p1, and is still open.

This errata can be avoided by ad

fix(cpus): workaround for Cortex-A720AE erratum 3456103

Cortex-A720AE erratum 3456103 is a Cat B erratum that applies
to revisions r0p0 and r0p1, and is still open.

This errata can be avoided by adding a speculation barrier
instruction following writes to the SSBS register to
ensure the new value of PSTATE.SSBS affects the subsequent
instructions in the execution stream under speculation.

SDEN documentation:
https://developer.arm.com/documentation/SDEN-3090091

Change-Id: Ia240a697d8e99bd4fbf4c92720d5228513080088
Signed-off-by: John Powell <john.powell@arm.com>

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fix(cpus): workaround for Cortex-A720 erratum 3456091

Cortex-A720 erratum 3456091 is a Cat B erratum that applies
to revisions r0p0, r0p1 and r0p2, and is still open.

This errata can be avoided by

fix(cpus): workaround for Cortex-A720 erratum 3456091

Cortex-A720 erratum 3456091 is a Cat B erratum that applies
to revisions r0p0, r0p1 and r0p2, and is still open.

This errata can be avoided by adding a speculation barrier
instruction following writes to the SSBS register to
ensure the new value of PSTATE.SSBS affects the subsequent
instructions in the execution stream under speculation.

SDEN documentation:
https://developer.arm.com/documentation/SDEN-2439421

Change-Id: Ia22a0d6bb98d1a0edb11d2469beab22c7f7aba3a
Signed-off-by: John Powell <john.powell@arm.com>

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