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Searched refs:REG_G2VP9_BASE (Results 1 – 25 of 28) sorted by relevance

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/utopia/UTPA2-700.0.x/modules/vdec_v3/hal/messi/hvd_v3/
H A DregHVD_EX.h233 #define REG_G2VP9_BASE (0x60E00) macro
416 #define VP9_REG_RESET (REG_G2VP9_BASE + ((0x0001) << 1))
H A DhalHVD_EX.c6109 pHVDHalContext->_stHVDStream[u8Idx].u32RegBase = REG_G2VP9_BASE; in HAL_HVD_EX_SetHwRegBase()
/utopia/UTPA2-700.0.x/modules/vdec_v3/hal/M7821/hvd_v3/
H A DregHVD_EX.h233 #define REG_G2VP9_BASE (0x60E00) macro
417 #define VP9_REG_RESET (REG_G2VP9_BASE + ((0x0001) << 1))
/utopia/UTPA2-700.0.x/modules/vdec_v3/hal/M7621/hvd_v3/
H A DregHVD_EX.h233 #define REG_G2VP9_BASE (0x60E00) macro
433 #define VP9_REG_RESET (REG_G2VP9_BASE + ((0x0001) << 1))
H A DhalHVD_EX.c6437 pHVDHalContext->_stHVDStream[u8Idx].u32RegBase = REG_G2VP9_BASE; in HAL_HVD_EX_SetHwRegBase()
/utopia/UTPA2-700.0.x/modules/vdec_v3/hal/manhattan/hvd_v3/
H A DregHVD_EX.h233 #define REG_G2VP9_BASE (0x60E00) macro
417 #define VP9_REG_RESET (REG_G2VP9_BASE + ((0x0001) << 1))
H A DhalHVD_EX.c6112 pHVDHalContext->_stHVDStream[u8Idx].u32RegBase = REG_G2VP9_BASE; in HAL_HVD_EX_SetHwRegBase()
/utopia/UTPA2-700.0.x/modules/vdec_v3/hal/macan/hvd_v3/
H A DregHVD_EX.h233 #define REG_G2VP9_BASE (0x60E00) macro
418 #define VP9_REG_RESET (REG_G2VP9_BASE + ((0x0001) << 1))
H A DhalHVD_EX.c6310 pHVDHalContext->_stHVDStream[u8Idx].u32RegBase = REG_G2VP9_BASE; in HAL_HVD_EX_SetHwRegBase()
/utopia/UTPA2-700.0.x/modules/vdec_v3/hal/mainz/hvd_v3/
H A DregHVD_EX.h233 #define REG_G2VP9_BASE (0x60E00) macro
416 #define VP9_REG_RESET (REG_G2VP9_BASE + ((0x0001) << 1))
H A DhalHVD_EX.c6109 pHVDHalContext->_stHVDStream[u8Idx].u32RegBase = REG_G2VP9_BASE; in HAL_HVD_EX_SetHwRegBase()
/utopia/UTPA2-700.0.x/modules/vdec_v3/hal/maxim/hvd_v3/
H A DregHVD_EX.h233 #define REG_G2VP9_BASE (0x60E00) macro
433 #define VP9_REG_RESET (REG_G2VP9_BASE + ((0x0001) << 1))
H A DhalHVD_EX.c6494 pHVDHalContext->_stHVDStream[u8Idx].u32RegBase = REG_G2VP9_BASE; in HAL_HVD_EX_SetHwRegBase()
/utopia/UTPA2-700.0.x/modules/vdec_v3/hal/maserati/hvd_v3/
H A DregHVD_EX.h233 #define REG_G2VP9_BASE (0x60E00) macro
417 #define VP9_REG_RESET (REG_G2VP9_BASE + ((0x0001) << 1))
H A DhalHVD_EX.c6513 pHVDHalContext->_stHVDStream[u8Idx].u32RegBase = REG_G2VP9_BASE; in HAL_HVD_EX_SetHwRegBase()
/utopia/UTPA2-700.0.x/modules/vdec_lite/hal/kano/hvd_lite/
H A DregHVD_EX.h243 #define REG_G2VP9_BASE (0x60E00) macro
433 #define VP9_REG_RESET (REG_G2VP9_BASE + ((0x0001) << 1))
/utopia/UTPA2-700.0.x/modules/vdec_v3/hal/mooney/hvd_v3/
H A DregHVD_EX.h233 #define REG_G2VP9_BASE (0x60E00) macro
445 #define VP9_REG_RESET (REG_G2VP9_BASE + ((0x0001) << 1))
H A DhalHVD_EX.c6296 pHVDHalContext->_stHVDStream[u8Idx].u32RegBase = REG_G2VP9_BASE; in HAL_HVD_EX_SetHwRegBase()
/utopia/UTPA2-700.0.x/modules/vdec_v3/hal/k6/hvd_v3/
H A DregHVD_EX.h234 #define REG_G2VP9_BASE (0x60E00) macro
580 #define VP9_REG_RESET (REG_G2VP9_BASE + ((0x0001) << 1))
/utopia/UTPA2-700.0.x/modules/vdec_v3/hal/curry/hvd_v3/
H A DregHVD_EX.h234 #define REG_G2VP9_BASE (0x60E00) macro
580 #define VP9_REG_RESET (REG_G2VP9_BASE + ((0x0001) << 1))
H A DhalHVD_EX.c7311 pHVDHalContext->_stHVDStream[u8Idx].u32RegBase = REG_G2VP9_BASE; in HAL_HVD_EX_SetHwRegBase()
/utopia/UTPA2-700.0.x/modules/vdec_v3/hal/k6lite/hvd_v3/
H A DregHVD_EX.h234 #define REG_G2VP9_BASE (0x60E00) macro
580 #define VP9_REG_RESET (REG_G2VP9_BASE + ((0x0001) << 1))
H A DhalHVD_EX.c7529 pHVDHalContext->_stHVDStream[u8Idx].u32RegBase = REG_G2VP9_BASE; in HAL_HVD_EX_SetHwRegBase()
/utopia/UTPA2-700.0.x/modules/vdec_v3/hal/maldives/hvd_v3/
H A DhalHVD_EX.c5879 pHVDHalContext->_stHVDStream[u8Idx].u32RegBase = REG_G2VP9_BASE; in HAL_HVD_EX_SetHwRegBase()
/utopia/UTPA2-700.0.x/modules/vdec_v3/hal/mustang/hvd_v3/
H A DhalHVD_EX.c6234 pHVDHalContext->_stHVDStream[u8Idx].u32RegBase = REG_G2VP9_BASE; in HAL_HVD_EX_SetHwRegBase()

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