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Searched refs:reg_base (Results 1 – 25 of 32) sorted by relevance

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/rk3399_ARM-atf/drivers/rpi3/sdhost/
H A Drpi3_sdhost.c50 uintptr_t reg_base = rpi3_sdhost_params.reg_base; in rpi3_sdhost_waitcommand() local
54 while ((mmio_read_32(reg_base + HC_COMMAND) & HC_CMD_ENABLE) in rpi3_sdhost_waitcommand()
73 uintptr_t reg_base = rpi3_sdhost_params.reg_base; in send_command_raw() local
79 status = mmio_read_32(reg_base + HC_HOSTSTATUS); in send_command_raw()
81 mmio_write_32(reg_base + HC_HOSTSTATUS, status); in send_command_raw()
87 mmio_write_32(reg_base + HC_ARGUMENT, arg); in send_command_raw()
88 mmio_write_32(reg_base + HC_COMMAND, cmd | HC_CMD_ENABLE); in send_command_raw()
137 uintptr_t reg_base = rpi3_sdhost_params.reg_base; in rpi3_drain_fifo() local
142 while (mmio_read_32(reg_base + HC_HOSTSTATUS) & HC_HSTST_HAVEDATA) { in rpi3_drain_fifo()
143 mmio_read_32(reg_base + HC_DATAPORT); in rpi3_drain_fifo()
[all …]
/rk3399_ARM-atf/drivers/imx/usdhc/
H A Dimx_usdhc.c98 uintptr_t reg_base = imx_usdhc_params.reg_base; in imx_usdhc_write_buf_data() local
105 mmio_write_32(reg_base + DSADDR, addr); in imx_usdhc_write_buf_data()
106 mmio_write_32(reg_base + BLKATT, BLKATT_BLKCNT(blks) | in imx_usdhc_write_buf_data()
114 uintptr_t reg_base = imx_usdhc_params.reg_base; in imx_usdhc_set_clk() local
132 ret = mmio_read_32_poll_timeout(reg_base + PSTATE, pstate, in imx_usdhc_set_clk()
140 mmio_clrbits32(reg_base + VENDSPEC, VENDSPEC_CARD_CLKEN); in imx_usdhc_set_clk()
141 mmio_clrsetbits32(reg_base + SYSCTRL, SYSCTRL_CLOCK_MASK, clk); in imx_usdhc_set_clk()
144 mmio_setbits32(reg_base + VENDSPEC, VENDSPEC_PER_CLKEN | VENDSPEC_CARD_CLKEN); in imx_usdhc_set_clk()
151 uintptr_t reg_base = imx_usdhc_params.reg_base; in imx_usdhc_initialize() local
155 assert((imx_usdhc_params.reg_base & MMC_BLOCK_MASK) == 0); in imx_usdhc_initialize()
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/rk3399_ARM-atf/drivers/cadence/emmc/
H A Dcdns_sdmmc.c119 mmio_write_32((cdns_params.reg_base + SDHC_CDNS_HRS00), SDHC_CDNS_HRS00_SWR); in cdns_program_phy_reg()
129 } while (((mmio_read_32(cdns_params.reg_base + SDHC_CDNS_HRS00) & in cdns_program_phy_reg()
133 value = mmio_read_32(cdns_params.reg_base + SDHC_CDNS_HRS09); in cdns_program_phy_reg()
135 mmio_write_32(cdns_params.reg_base + SDHC_CDNS_HRS09, value); in cdns_program_phy_reg()
142 ret = cdns_sdmmc_write_phy_reg(cdns_params.reg_base + SDHC_CDNS_HRS04, in cdns_program_phy_reg()
144 cdns_params.reg_base + SDHC_CDNS_HRS05, value); in cdns_program_phy_reg()
155 ret = cdns_sdmmc_write_phy_reg(cdns_params.reg_base + SDHC_CDNS_HRS04, in cdns_program_phy_reg()
157 cdns_params.reg_base + SDHC_CDNS_HRS05, value); in cdns_program_phy_reg()
165 ret = cdns_sdmmc_write_phy_reg(cdns_params.reg_base + SDHC_CDNS_HRS04, in cdns_program_phy_reg()
167 cdns_params.reg_base + SDHC_CDNS_HRS05, value); in cdns_program_phy_reg()
[all …]
/rk3399_ARM-atf/drivers/rpi3/gpio/
H A Drpi3_gpio.c16 static uintptr_t reg_base; variable
50 uintptr_t reg_sel = reg_base + RPI3_GPIO_GPFSEL(regN); in rpi3_gpio_get_select()
75 uintptr_t reg_sel = reg_base + RPI3_GPIO_GPFSEL(regN); in rpi3_gpio_set_select()
111 uintptr_t reg_lev = reg_base + RPI3_GPIO_GPLEV(regN); in rpi3_gpio_get_value()
123 uintptr_t reg_set = reg_base + RPI3_GPIO_GPSET(regN); in rpi3_gpio_set_value()
124 uintptr_t reg_clr = reg_base + RPI3_GPIO_GPCLR(regN); in rpi3_gpio_set_value()
140 uintptr_t reg_pud = reg_base + RPI3_GPIO_GPPUD; in rpi3_gpio_set_pull()
141 uintptr_t reg_clk = reg_base + RPI3_GPIO_GPPUDCLK(regN); in rpi3_gpio_set_pull()
163 reg_base = RPI3_GPIO_BASE; in rpi3_gpio_init()
/rk3399_ARM-atf/plat/socionext/uniphier/
H A Duniphier_nand.c52 uintptr_t reg_base; member
88 mmio_write_32(nand->reg_base + DENALI_ECC_ENABLE, 0); in uniphier_nand_block_isbad()
90 mmio_write_32(nand->reg_base + DENALI_INTR_STATUS0, -1); in uniphier_nand_block_isbad()
103 status = mmio_read_32(nand->reg_base + DENALI_INTR_STATUS0); in uniphier_nand_block_isbad()
125 mmio_write_32(nand->reg_base + DENALI_ECC_ENABLE, 1); in uniphier_nand_read_pages()
126 mmio_write_32(nand->reg_base + DENALI_DMA_ENABLE, 1); in uniphier_nand_read_pages()
128 mmio_write_32(nand->reg_base + DENALI_INTR_STATUS0, -1); in uniphier_nand_read_pages()
148 status = mmio_read_32(nand->reg_base + DENALI_INTR_STATUS0); in uniphier_nand_read_pages()
151 mmio_write_32(nand->reg_base + DENALI_DMA_ENABLE, 0); in uniphier_nand_read_pages()
241 nand->reg_base = nand->host_base + 0x100000; in uniphier_nand_hw_init()
[all …]
/rk3399_ARM-atf/drivers/synopsys/emmc/
H A Ddw_mmc.c145 mmio_write_32(dw_params.reg_base + DWMMC_CMD, in dw_update_clk()
149 data = mmio_read_32(dw_params.reg_base + DWMMC_CMD); in dw_update_clk()
152 data = mmio_read_32(dw_params.reg_base + DWMMC_RINTSTS); in dw_update_clk()
173 data = mmio_read_32(dw_params.reg_base + DWMMC_STATUS); in dw_set_clk()
177 mmio_write_32(dw_params.reg_base + DWMMC_CLKENA, 0); in dw_set_clk()
180 mmio_write_32(dw_params.reg_base + DWMMC_CLKDIV, div); in dw_set_clk()
184 mmio_write_32(dw_params.reg_base + DWMMC_CLKENA, 1); in dw_set_clk()
185 mmio_write_32(dw_params.reg_base + DWMMC_CLKSRC, 0); in dw_set_clk()
194 assert((dw_params.reg_base & MMC_BLOCK_MASK) == 0); in dw_init()
196 base = dw_params.reg_base; in dw_init()
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/rk3399_ARM-atf/drivers/ufs/
H A Dufs.c47 data = mmio_read_32(ufs_params.reg_base + UECPA); in ufs_uic_error_handler()
58 data = mmio_read_32(ufs_params.reg_base + UECDL); in ufs_uic_error_handler()
67 data = mmio_read_32(ufs_params.reg_base + UECN); in ufs_uic_error_handler()
72 data = mmio_read_32(ufs_params.reg_base + UECT); in ufs_uic_error_handler()
77 data = mmio_read_32(ufs_params.reg_base + UECDME); in ufs_uic_error_handler()
134 interrupts_enabled = mmio_read_32(ufs_params.reg_base + IE); in ufs_wait_for_int_status()
136 interrupt_status = mmio_read_32(ufs_params.reg_base + IS) & interrupts_enabled; in ufs_wait_for_int_status()
138 mmio_write_32(ufs_params.reg_base + IS, interrupt_status & UFS_INT_ERR); in ufs_wait_for_int_status()
155 mmio_write_32(ufs_params.reg_base + IS, expected_status); in ufs_wait_for_int_status()
201 assert(ufs_params.reg_base != 0); in ufshc_dme_get()
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/rk3399_ARM-atf/drivers/marvell/comphy/
H A Dphy-comphy-3700.c614 uintptr_t reg_base = 0; in mvebu_a3700_comphy_usb3_power_on() local
632 reg_base = COMPHY_INDIRECT_REG; in mvebu_a3700_comphy_usb3_power_on()
636 reg_base = USB3_GBE1_PHY; in mvebu_a3700_comphy_usb3_power_on()
649 usb3_reg_set(reg_base, COMPHY_LANE_CFG0, PRD_TXDEEMPH0_MASK, mask); in mvebu_a3700_comphy_usb3_power_on()
661 usb3_reg_set(reg_base, COMPHY_LANE_CFG1, data, mask); in mvebu_a3700_comphy_usb3_power_on()
666 usb3_reg_set(reg_base, COMPHY_LANE_CFG4, in mvebu_a3700_comphy_usb3_power_on()
673 usb3_reg_set(reg_base, COMPHY_TEST_MODE_CTRL, in mvebu_a3700_comphy_usb3_power_on()
680 usb3_reg_set(reg_base, COMPHY_CLK_SRC_LO, 0x0, in mvebu_a3700_comphy_usb3_power_on()
688 usb3_reg_set(reg_base, COMPHY_GEN2_SET2, in mvebu_a3700_comphy_usb3_power_on()
697 usb3_reg_set(reg_base, COMPHY_GEN3_SET2, in mvebu_a3700_comphy_usb3_power_on()
[all …]
/rk3399_ARM-atf/drivers/synopsys/ufs/
H A Ddw_ufs.c23 assert((params != NULL) && (params->reg_base != 0)); in dwufs_phy_init()
25 base = params->reg_base; in dwufs_phy_init()
103 assert((params != NULL) && (params->reg_base != 0)); in dwufs_phy_set_pwr_mode()
105 base = params->reg_base; in dwufs_phy_set_pwr_mode()
196 ufs_params.reg_base = params->reg_base; in dw_ufs_init()
/rk3399_ARM-atf/drivers/imx/timer/
H A Dimx_gpt.h12 void imx_gpt_ops_init(uintptr_t reg_base);
/rk3399_ARM-atf/include/drivers/synopsys/
H A Ddw_mmc.h13 uintptr_t reg_base; member
/rk3399_ARM-atf/include/drivers/st/
H A Dstm32_sdmmc2.h16 uintptr_t reg_base; member
/rk3399_ARM-atf/drivers/st/mmc/
H A Dstm32_sdmmc2.c175 uintptr_t base = sdmmc2_params.reg_base; in stm32_sdmmc2_init()
237 uintptr_t base = sdmmc2_params.reg_base; in stm32_sdmmc2_send_cmd_req()
483 uintptr_t base = sdmmc2_params.reg_base; in stm32_sdmmc2_set_ios()
537 uintptr_t base = sdmmc2_params.reg_base; in stm32_sdmmc2_prepare()
603 uintptr_t base = sdmmc2_params.reg_base; in stm32_sdmmc2_read()
708 sdmmc2_params.reg_base); in stm32_sdmmc2_dt_get_config()
771 ((params->reg_base & MMC_BLOCK_MASK) == 0U) && in stm32_sdmmc2_mmc_init()
/rk3399_ARM-atf/plat/intel/soc/common/include/
H A Dsocfpga_private.h21 .reg_base = SOCFPGA_MMC_REG_BASE \
/rk3399_ARM-atf/include/drivers/
H A Ddw_ufs.h102 uintptr_t reg_base; member
/rk3399_ARM-atf/plat/hisilicon/poplar/include/
H A Dhi3798cv200.h79 .reg_base = REG_BASE_MCI, \
/rk3399_ARM-atf/plat/st/common/
H A Dbl2_io_storage.c234 params.reg_base = STM32MP_SDMMC1_BASE; in boot_mmc()
237 params.reg_base = STM32MP_SDMMC2_BASE; in boot_mmc()
240 params.reg_base = STM32MP_SDMMC3_BASE; in boot_mmc()
245 params.reg_base = STM32MP_SDMMC1_BASE; in boot_mmc()
247 params.reg_base = STM32MP_SDMMC2_BASE; in boot_mmc()
/rk3399_ARM-atf/include/drivers/rpi3/sdhost/
H A Drpi3_sdhost.h16 uintptr_t reg_base; member
/rk3399_ARM-atf/plat/imx/imx8m/imx8mm/
H A Dimx8mm_bl2_el3_setup.c46 params.reg_base = PLAT_IMX8MM_BOOT_MMC_BASE; in imx8mm_usdhc_setup()
/rk3399_ARM-atf/plat/imx/imx7/warp7/
H A Dwarp7_bl2_el3_setup.c106 params.reg_base = PLAT_WARP7_BOOT_MMC_BASE; in warp7_usdhc_setup()
/rk3399_ARM-atf/plat/hisilicon/hikey/
H A Dhikey_bl1_setup.c98 params.reg_base = DWMMC0_BASE; in bl1_platform_setup()
/rk3399_ARM-atf/plat/imx/imx7/picopi/
H A Dpicopi_bl2_el3_setup.c100 params.reg_base = PLAT_PICOPI_BOOT_MMC_BASE; in picopi_usdhc_setup()
/rk3399_ARM-atf/plat/rpi/rpi3/
H A Drpi3_bl2_setup.c42 params.reg_base = RPI3_SDHOST_BASE; in rpi3_sdhost_setup()
/rk3399_ARM-atf/plat/nxp/s32/s32g274ardb2/
H A Dplat_bl2_el3_setup.c86 params.reg_base = S32G_USDHC_BASE; in init_s32g_usdhc()
/rk3399_ARM-atf/drivers/st/spi/
H A Dstm32_qspi.c109 uintptr_t reg_base; member
120 return stm32_qspi.reg_base; in qspi_base()
470 &stm32_qspi.reg_base, &size); in stm32_qspi_init()

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