Lines Matching refs:reg_base
98 uintptr_t reg_base = imx_usdhc_params.reg_base; in imx_usdhc_write_buf_data() local
105 mmio_write_32(reg_base + DSADDR, addr); in imx_usdhc_write_buf_data()
106 mmio_write_32(reg_base + BLKATT, BLKATT_BLKCNT(blks) | in imx_usdhc_write_buf_data()
114 uintptr_t reg_base = imx_usdhc_params.reg_base; in imx_usdhc_set_clk() local
132 ret = mmio_read_32_poll_timeout(reg_base + PSTATE, pstate, in imx_usdhc_set_clk()
140 mmio_clrbits32(reg_base + VENDSPEC, VENDSPEC_CARD_CLKEN); in imx_usdhc_set_clk()
141 mmio_clrsetbits32(reg_base + SYSCTRL, SYSCTRL_CLOCK_MASK, clk); in imx_usdhc_set_clk()
144 mmio_setbits32(reg_base + VENDSPEC, VENDSPEC_PER_CLKEN | VENDSPEC_CARD_CLKEN); in imx_usdhc_set_clk()
151 uintptr_t reg_base = imx_usdhc_params.reg_base; in imx_usdhc_initialize() local
155 assert((imx_usdhc_params.reg_base & MMC_BLOCK_MASK) == 0); in imx_usdhc_initialize()
158 mmio_setbits32(reg_base + SYSCTRL, SYSCTRL_RSTA); in imx_usdhc_initialize()
161 ret = mmio_read_32_poll_timeout(reg_base + SYSCTRL, sysctrl, in imx_usdhc_initialize()
169 mmio_write_32(reg_base + MMCBOOT, 0); in imx_usdhc_initialize()
170 mmio_write_32(reg_base + MIXCTRL, 0); in imx_usdhc_initialize()
171 mmio_write_32(reg_base + CLKTUNECTRLSTS, 0); in imx_usdhc_initialize()
173 mmio_write_32(reg_base + VENDSPEC, VENDSPEC_INIT); in imx_usdhc_initialize()
174 mmio_write_32(reg_base + DLLCTRL, 0); in imx_usdhc_initialize()
175 mmio_setbits32(reg_base + VENDSPEC, VENDSPEC_IPG_CLKEN | VENDSPEC_PER_CLKEN); in imx_usdhc_initialize()
186 mmio_clrbits32(reg_base + INTSTATEN, INTSTATEN_BRR | INTSTATEN_BWR); in imx_usdhc_initialize()
189 mmio_write_32(reg_base + PROTCTRL, PROTCTRL_LE); in imx_usdhc_initialize()
192 mmio_clrsetbits32(reg_base + SYSCTRL, SYSCTRL_TIMEOUT_MASK, in imx_usdhc_initialize()
196 mmio_clrsetbits32(reg_base + WATERMARKLEV, WMKLV_MASK, 16 | (16 << 16)); in imx_usdhc_initialize()
208 uintptr_t reg_base = imx_usdhc_params.reg_base; in is_data_transfer_cmd() local
212 xfer_type = mmio_read_32(reg_base + XFERTYPE); in is_data_transfer_cmd()
263 uintptr_t reg_base = imx_usdhc_params.reg_base; in imx_usdhc_send_cmd() local
280 mmio_write_32(reg_base + INTSTAT, 0xffffffff); in imx_usdhc_send_cmd()
283 err = mmio_read_32_poll_timeout(reg_base + PSTATE, pstate, in imx_usdhc_send_cmd()
291 err = mmio_read_32_poll_timeout(reg_base + PSTATE, pstate, in imx_usdhc_send_cmd()
299 mmio_write_32(reg_base + INTSIGEN, 0); in imx_usdhc_send_cmd()
319 mmio_write_32(reg_base + CMDARG, cmd->cmd_arg); in imx_usdhc_send_cmd()
320 mmio_clrsetbits32(reg_base + MIXCTRL, MIXCTRL_DATMASK, mixctl); in imx_usdhc_send_cmd()
321 mmio_write_32(reg_base + XFERTYPE, xfertype); in imx_usdhc_send_cmd()
324 err = mmio_read_32_poll_timeout(reg_base + INTSTAT, intstat, in imx_usdhc_send_cmd()
340 cmdrsp3 = mmio_read_32(reg_base + CMDRSP3); in imx_usdhc_send_cmd()
341 cmdrsp2 = mmio_read_32(reg_base + CMDRSP2); in imx_usdhc_send_cmd()
342 cmdrsp1 = mmio_read_32(reg_base + CMDRSP1); in imx_usdhc_send_cmd()
343 cmdrsp0 = mmio_read_32(reg_base + CMDRSP0); in imx_usdhc_send_cmd()
349 cmd->resp_data[0] = mmio_read_32(reg_base + CMDRSP0); in imx_usdhc_send_cmd()
355 err = mmio_read_32_poll_timeout(reg_base + INTSTAT, intstat, in imx_usdhc_send_cmd()
374 mmio_setbits32(reg_base + SYSCTRL, SYSCTRL_RSTC); in imx_usdhc_send_cmd()
375 ret = mmio_read_32_poll_timeout(reg_base + SYSCTRL, sysctrl, in imx_usdhc_send_cmd()
383 mmio_setbits32(reg_base + SYSCTRL, SYSCTRL_RSTD); in imx_usdhc_send_cmd()
384 ret = mmio_read_32_poll_timeout(reg_base + SYSCTRL, sysctrl, in imx_usdhc_send_cmd()
394 mmio_write_32(reg_base + INTSTAT, 0xffffffff); in imx_usdhc_send_cmd()
401 uintptr_t reg_base = imx_usdhc_params.reg_base; in imx_usdhc_set_ios() local
410 mmio_clrsetbits32(reg_base + PROTCTRL, PROTCTRL_WIDTH_MASK, in imx_usdhc_set_ios()
413 mmio_clrsetbits32(reg_base + PROTCTRL, PROTCTRL_WIDTH_MASK, in imx_usdhc_set_ios()
442 ((params->reg_base & MMC_BLOCK_MASK) == 0) && in imx_usdhc_init()
448 ret = mmap_add_dynamic_region(params->reg_base, params->reg_base, in imx_usdhc_init()