| #
e85e73de |
| 05-Aug-2025 |
Lauren Wehrmeister <lauren.wehrmeister@arm.com> |
Merge changes I1bb556a8,Ie450acf7 into integration
* changes:
fix(intel): remove wfi polling when performing cpu on
fix(intel): fix socfpga_psci for cpu on off function
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| #
8f7575ef |
| 14-May-2025 |
Boon Khai Ng <boon.khai.ng@altera.com> |
fix(intel): fix socfpga_psci for cpu on off function
Fix for CPU ON / OFF Function calling from Linux Kernel.
Change-Id: Ie450acf7e537ed60ef4b2e8d785e62d94e52482f
Signed-off-by: Boon Khai Ng <boon.
fix(intel): fix socfpga_psci for cpu on off function
Fix for CPU ON / OFF Function calling from Linux Kernel.
Change-Id: Ie450acf7e537ed60ef4b2e8d785e62d94e52482f
Signed-off-by: Boon Khai Ng <boon.khai.ng@altera.com>
Signed-off-by: Jit Loon Lim <jit.loon.lim@altera.com>
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| #
8681f772 |
| 27-May-2025 |
Mark Dykes <mark.dykes@arm.com> |
Merge "feat(intel): update CPUECTLR_EL1 to boost ethernet performance" into integration
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| #
bb9e34f9 |
| 07-Mar-2025 |
Jit Loon Lim <jit.loon.lim@altera.com> |
feat(intel): update CPUECTLR_EL1 to boost ethernet performance
This patch is the workaround for Agilex5 Ethernet for performance
boost.
Change-Id: I702f0cb0beff8b3ea119205ec41dd4e825e9126b
Signed-o
feat(intel): update CPUECTLR_EL1 to boost ethernet performance
This patch is the workaround for Agilex5 Ethernet for performance
boost.
Change-Id: I702f0cb0beff8b3ea119205ec41dd4e825e9126b
Signed-off-by: Jit Loon Lim <jit.loon.lim@altera.com>
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| #
2c878eb6 |
| 28-Oct-2024 |
Mark Dykes <mark.dykes@arm.com> |
Merge "feat(intel): add build option for boot source" into integration
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| #
ef8b05f5 |
| 24-Oct-2024 |
Sieu Mun Tang <sieu.mun.tang@intel.com> |
feat(intel): add build option for boot source
Existing boot source is hardcoded in socfpga_plat_def.h.
To change boot source, user need to update code.
Thus adding this will remove the code update n
feat(intel): add build option for boot source
Existing boot source is hardcoded in socfpga_plat_def.h.
To change boot source, user need to update code.
Thus adding this will remove the code update needed when
need to change boot source.
Also, it will have ARM_LINUX_KERNEL_AS_BL33 flag for each
platform in platform.mk. This will be easily to control
based on platform build.
Change-Id: I383beb8cbca5ec0f247221ad42796554adc3daae
Signed-off-by: Jit Loon Lim <jit.loon.lim@intel.com>
Signed-off-by: Sieu Mun Tang <sieu.mun.tang@intel.com>
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| #
1b979524 |
| 22-Oct-2024 |
Mark Dykes <mark.dykes@arm.com> |
Merge "fix(intel): fix CCU for cache maintenance" into integration
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| #
5dda797f |
| 22-Oct-2024 |
Mark Dykes <mark.dykes@arm.com> |
Merge "fix(intel): flush L1/L2/L3/Sys cache before HPS cold reset" into integration
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| #
f06fdb14 |
| 21-Oct-2024 |
Sieu Mun Tang <sieu.mun.tang@intel.com> |
fix(intel): fix CCU for cache maintenance
Fix CCU settings for cache maintenance.
Change-Id: I9af35a6ab7aa9ee20e05ba82d0a042948ac29a93
Signed-off-by: Sieu Mun Tang <sieu.mun.tang@intel.com>
Signed-
fix(intel): fix CCU for cache maintenance
Fix CCU settings for cache maintenance.
Change-Id: I9af35a6ab7aa9ee20e05ba82d0a042948ac29a93
Signed-off-by: Sieu Mun Tang <sieu.mun.tang@intel.com>
Signed-off-by: Jit Loon Lim <jit.loon.lim@intel.com>
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| #
7ac7dadb |
| 21-Oct-2024 |
Sieu Mun Tang <sieu.mun.tang@intel.com> |
fix(intel): flush L1/L2/L3/Sys cache before HPS cold reset
This fix is to flush and invalidate the caches before cold reset.
Issue happen where Agilex5 hardware does not support the caches flush.
Th
fix(intel): flush L1/L2/L3/Sys cache before HPS cold reset
This fix is to flush and invalidate the caches before cold reset.
Issue happen where Agilex5 hardware does not support the caches flush.
Thus software workaround is needed.
Change-Id: Ibfeecbc611d238a069ca72f8b833f319e794cd38
Signed-off-by: Jit Loon Lim <jit.loon.lim@intel.com>
Signed-off-by: Sieu Mun Tang <sieu.mun.tang@intel.com>
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| #
b3a7396d |
| 19-Jan-2024 |
Sandrine Bailleux <sandrine.bailleux@arm.com> |
Merge changes Iaa189c54,I8856b495 into integration
* changes:
feat(intel): enable query of fip offset on RSU
feat(intel): support query of fip offset using RSU
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| #
6cbe2c5d |
| 22-Aug-2023 |
Mahesh Rao <mahesh.rao@intel.com> |
feat(intel): enable query of fip offset on RSU
Enable query of fip offset from QSPI on RSU boot for
Intel agilex and intel agilex5 platform
Change-Id: Iaa189c54723a8656b9691da5849fd86b9986cfa1
Sign
feat(intel): enable query of fip offset on RSU
Enable query of fip offset from QSPI on RSU boot for
Intel agilex and intel agilex5 platform
Change-Id: Iaa189c54723a8656b9691da5849fd86b9986cfa1
Signed-off-by: Mahesh Rao <mahesh.rao@intel.com>
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| #
9118bdf4 |
| 19-Dec-2023 |
Sandrine Bailleux <sandrine.bailleux@arm.com> |
Merge "fix(intel): fix hardcoded mpu frequency ticks" into integration
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| #
150d2be0 |
| 07-Jul-2023 |
Jit Loon Lim <jit.loon.lim@intel.com> |
fix(intel): fix hardcoded mpu frequency ticks
This patch is used to update the hardcoded mpu freq ticks
to obtain the freqq from the hardware setting itself.
Change-Id: I7b9eb49f2512b85fb477110f06a
fix(intel): fix hardcoded mpu frequency ticks
This patch is used to update the hardcoded mpu freq ticks
to obtain the freqq from the hardware setting itself.
Change-Id: I7b9eb49f2512b85fb477110f06ae86ef289aee58
Signed-off-by: Jit Loon Lim <jit.loon.lim@intel.com>
Signed-off-by: Sieu Mun Tang <sieu.mun.tang@intel.com>
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| #
026dfed8 |
| 06-May-2022 |
Manish Pandey <manish.pandey2@arm.com> |
Merge "feat(intel): implement timer init divider via cpu frequency. (#1)" into integration
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| #
f65bdf3a |
| 06-Apr-2022 |
BenjaminLimJL <jit.loon.lim@intel.com> |
feat(intel): implement timer init divider via cpu frequency. (#1)
Get cpu frequency and update the timer init div with it.
The timer is vary based on the cpu frequency instead of hardcoded.
The impl
feat(intel): implement timer init divider via cpu frequency. (#1)
Get cpu frequency and update the timer init div with it.
The timer is vary based on the cpu frequency instead of hardcoded.
The implementation shall apply to only Agilex and S10
Signed-off-by: Jit Loon Lim <jit.loon.lim@intel.com>
Change-Id: I61684d9762ad34e5a60b8b176b60c8848db4b422
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| #
4962385e |
| 18-Dec-2019 |
Soby Mathew <soby.mathew@arm.com> |
Merge changes from topic "nonbl2-boot" into integration
* changes:
intel: stratix10: Modify BL31 parameter handling
intel: Modify BL31 address mapping
intel: stratix10: Enable uboot entrypoint
Merge changes from topic "nonbl2-boot" into integration
* changes:
intel: stratix10: Modify BL31 parameter handling
intel: Modify BL31 address mapping
intel: stratix10: Enable uboot entrypoint support
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| #
2db1e766 |
| 22-Oct-2019 |
Hadi Asyrafi <muhammad.hadi.asyrafi.abdul.halim@intel.com> |
intel: stratix10: Enable uboot entrypoint support
This patch will provide an entrypoint for uboot's spl into BL31.
BL31 will also handle secondary cpu state during uboot's cold boot
Signed-off-by:
intel: stratix10: Enable uboot entrypoint support
This patch will provide an entrypoint for uboot's spl into BL31.
BL31 will also handle secondary cpu state during uboot's cold boot
Signed-off-by: Hadi Asyrafi <muhammad.hadi.asyrafi.abdul.halim@intel.com>
Change-Id: I661bdb782c2d793d5fc3c7f78dd7ff746e33b7a3
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| #
b33772eb |
| 04-Dec-2019 |
Mark Dykes <mardyk01@review.trustedfirmware.org> |
Merge changes from topic "platform-refactor" into integration
* changes:
intel: Refactor common platform code [4/5]
intel: Refactor common platform code [3/5]
intel: Refactor common platform c
Merge changes from topic "platform-refactor" into integration
* changes:
intel: Refactor common platform code [4/5]
intel: Refactor common platform code [3/5]
intel: Refactor common platform code [2/5]
intel: Refactor common platform code [1/5]
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| #
e9b5e360 |
| 23-Oct-2019 |
Hadi Asyrafi <muhammad.hadi.asyrafi.abdul.halim@intel.com> |
intel: Refactor common platform code [2/5]
Share socfpga private definitions and storage driver between Agilex and
Stratix 10 platform.
Signed-off-by: Hadi Asyrafi <muhammad.hadi.asyrafi.abdul.hali
intel: Refactor common platform code [2/5]
Share socfpga private definitions and storage driver between Agilex and
Stratix 10 platform.
Signed-off-by: Hadi Asyrafi <muhammad.hadi.asyrafi.abdul.halim@intel.com>
Change-Id: I6da147f4d2df4a97c505d4bbcffadf63bc3bf4a5
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| #
5119fa7b |
| 07-Aug-2019 |
Sandrine Bailleux <sandrine.bailleux@arm.com> |
Merge changes from topic "intel-plat-refactor" into integration
* changes:
intel: Platform common code refactor
intel: Platform common code refactor
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| #
3f7b1490 |
| 01-Aug-2019 |
Hadi Asyrafi <muhammad.hadi.asyrafi.abdul.halim@intel.com> |
intel: Platform common code refactor
Pull out common code from aarch64 and include
Signed-off-by: Hadi Asyrafi <muhammad.hadi.asyrafi.abdul.halim@intel.com>
Change-Id: I4d0f5e1bb01bcdacbedf8e6c359d
intel: Platform common code refactor
Pull out common code from aarch64 and include
Signed-off-by: Hadi Asyrafi <muhammad.hadi.asyrafi.abdul.halim@intel.com>
Change-Id: I4d0f5e1bb01bcdacbedf8e6c359de594239b645f
show more ...
|