Merge "fix(intel): fix eMMC driver issues in boot flow on agilex5" into integration

fix(intel): fix eMMC driver issues in boot flow on agilex5

Fixed issue where reading the EXT_CSD register via CMD8
with DMA enabled returned 0 value. Updated the read mode
to handle this case correc

fix(intel): fix eMMC driver issues in boot flow on agilex5

Fixed issue where reading the EXT_CSD register via CMD8
with DMA enabled returned 0 value. Updated the read mode
to handle this case correctly.

Added polling for the ICS bit after enabling ICE when
setting the SDCLK rate. Introduced delay to ensure
proper clock stabilization.

Corrected SD_HOST_CLK to data driven from the clock manager
as sdmclk.

eMMC operates in legacy mode, which has a maximum
supported clock rate of 26 MHz. Updated the clock
setting to 25 MHz to meet this requirement.

Change-Id: I4ac2b9b69b5dec2c8166d06c736d9c2c549607de
Signed-off-by: Boon Khai Ng <boon.khai.ng@altera.com>
Signed-off-by: Jit Loon Lim <jit.loon.lim@altera.com>

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Merge "fix(intel): add memory alignment at cadence SD/eMMC driver's descriptor" into integration

fix(intel): add memory alignment at cadence SD/eMMC driver's descriptor

When compile using arm gcc compiler with versions 12 above,
the cadence SD/eMMC driver will failed with ADMA error. When
sendi

fix(intel): add memory alignment at cadence SD/eMMC driver's descriptor

When compile using arm gcc compiler with versions 12 above,
the cadence SD/eMMC driver will failed with ADMA error. When
sending MMC command. The memory is not aligned correctly
when using different version of gcc.

The descriptor memory must be aligned to 4 byte boundary
with 2 least significant bits set to 0 in 32-bit ADMA
addressing mode and aligned to 8 byte boundary with
3 least significant bits set to 0 in 64-bit ADMA
addresing mode.

Since 8 byte boundary is common to both 4 byte and
8 byte boundary hence aligning the descriptor
memory with 8 byte boundary.

Change-Id: Ie56d2aef22b4e4ef0fa516b9cda53b33d6316cb7
Signed-off-by: Boon Khai Ng <boon.khai.ng@altera.com>
Signed-off-by: Jit Loon Lim <jit.loon.lim@altera.com>

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Merge "fix(intel): refactor SDMMC driver for Altera products" into integration

fix(intel): refactor SDMMC driver for Altera products

Refactor to be more robust. Removed duplicated and not used functions.
Add in ADMA read.

Change-Id: I1a5a00397ece6f9ccc5916225ab5317010b01b52
S

fix(intel): refactor SDMMC driver for Altera products

Refactor to be more robust. Removed duplicated and not used functions.
Add in ADMA read.

Change-Id: I1a5a00397ece6f9ccc5916225ab5317010b01b52
Signed-off-by: Jit Loon Lim <jit.loon.lim@intel.com>
Signed-off-by: Sieu Mun Tang <sieu.mun.tang@intel.com>

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Merge changes from topic "agilex5" into integration

* changes:
feat(intel): platform enablement for Agilex5 SoC FPGA
feat(intel): ccu driver for Agilex5 SoC FPGA
feat(intel): vab support for A

Merge changes from topic "agilex5" into integration

* changes:
feat(intel): platform enablement for Agilex5 SoC FPGA
feat(intel): ccu driver for Agilex5 SoC FPGA
feat(intel): vab support for Agilex5 SoC FPGA
feat(intel): sdmmc/nand/combo-phy/qspi driver for Agilex5 SoC FPGA
feat(intel): ddr driver for Agilex5 SoC FPGA
feat(intel): power manager for Agilex5 SoC FPGA
feat(intel): cold/warm reset and smp support for Agilex5 SoC FPGA
feat(intel): reset manager support for Agilex5 SoC FPGA
feat(intel): mailbox and SMC support for Agilex5 SoC FPGA
feat(intel): system manager support for Agilex5 SoC FPGA
feat(intel): memory controller support for Agilex5 SoC FPGA
feat(intel): clock manager support for Agilex5 SoC FPGA
feat(intel): mmc support for Agilex5 SoC FPGA
feat(intel): uart support for Agilex5 SoC FPGA
feat(intel): pinmux, peripheral and Handoff support for Agilex5 SoC FPGA

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feat(intel): sdmmc/nand/combo-phy/qspi driver for Agilex5 SoC FPGA

This patch is used to implement sdmmc/nand/combo-phy
driver to support Cadence IP for Agilex5 SoC FPGA.
1. Added SDMMC/NAND/COMBO-

feat(intel): sdmmc/nand/combo-phy/qspi driver for Agilex5 SoC FPGA

This patch is used to implement sdmmc/nand/combo-phy
driver to support Cadence IP for Agilex5 SoC FPGA.
1. Added SDMMC/NAND/COMBO-PHY support.
2. Updated product name -> Agilex5
3. Updated QSPI base address

Signed-off-by: Jit Loon Lim <jit.loon.lim@intel.com>
Change-Id: I6db689d2b784c9f59a25701ab34517f6f6b0a0e6

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