| #
15ff61f5 |
| 11-May-2022 |
Madhukar Pappireddy <madhukar.pappireddy@arm.com> |
Merge changes from topic "fix_st_spi" into integration
* changes: fix(st-spi): remove SR_BUSY bit check before sending command fix(st-spi): always check SR_TCF flags in stm32_qspi_wait_cmd()
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| #
5993b915 |
| 04-May-2022 |
Christophe Kerello <christophe.kerello@foss.st.com> |
fix(st-spi): remove SR_BUSY bit check before sending command
Waiting for SR_BUSY bit when receiving a new command is not needed. SR_BUSY bit is already managed in the previous command treatment.
Ch
fix(st-spi): remove SR_BUSY bit check before sending command
Waiting for SR_BUSY bit when receiving a new command is not needed. SR_BUSY bit is already managed in the previous command treatment.
Change-Id: I736e8488d354cb165ae765022d864cca1dbdc9ee Signed-off-by: Christophe Kerello <christophe.kerello@foss.st.com>
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| #
55de5832 |
| 04-May-2022 |
Christophe Kerello <christophe.kerello@foss.st.com> |
fix(st-spi): always check SR_TCF flags in stm32_qspi_wait_cmd()
Currently, SR_TCF flag is checked in case there is data, this criteria is not correct.
SR_TCF flags is set when programmed number of
fix(st-spi): always check SR_TCF flags in stm32_qspi_wait_cmd()
Currently, SR_TCF flag is checked in case there is data, this criteria is not correct.
SR_TCF flags is set when programmed number of bytes have been transferred to the memory device ("bytes" comprised command and data send to the SPI device). So even if there is no data, we must check SR_TCF flag.
Change-Id: I99c4145e639c1b842feb3690dd78329179c18132 Signed-off-by: Christophe Kerello <christophe.kerello@foss.st.com>
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| #
0ca4b4b7 |
| 22-Dec-2021 |
Madhukar Pappireddy <madhukar.pappireddy@arm.com> |
Merge changes from topic "clock_framework" into integration
* changes: feat(st): use newly introduced clock framework feat(clk): add a minimal clock framework
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| #
33667d29 |
| 30-Aug-2021 |
Yann Gautier <yann.gautier@foss.st.com> |
feat(st): use newly introduced clock framework
Replace calls to stm32mp_clk_enable() / stm32mp_clk_disable() / stm32mp_clk_get_rate() with clk_enable() / clk_disable() / clk_get_rate().
Change-Id:
feat(st): use newly introduced clock framework
Replace calls to stm32mp_clk_enable() / stm32mp_clk_disable() / stm32mp_clk_get_rate() with clk_enable() / clk_disable() / clk_get_rate().
Change-Id: I15d2ce57b9499211fa522a1b53eeee9cf584c111 Signed-off-by: Gabriel Fernandez <gabriel.fernandez@st.com>
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| #
2242773d |
| 12-Nov-2021 |
Manish Pandey <manish.pandey2@arm.com> |
Merge "fix: use correct printf format for uint64_t" into integration
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| #
4ef449c1 |
| 12-Nov-2021 |
Manish Pandey <manish.pandey2@arm.com> |
fix: use correct printf format for uint64_t
sha 4ce3e99a3 introduced printf format specifiers for fixed width types, which uses PRI*64 instead of "ll" for 64 bit values.
Signed-off-by: Manish Pande
fix: use correct printf format for uint64_t
sha 4ce3e99a3 introduced printf format specifiers for fixed width types, which uses PRI*64 instead of "ll" for 64 bit values.
Signed-off-by: Manish Pandey <manish.pandey2@arm.com> Change-Id: Ic6811cc1788c698adde0807e5f8ab5290a900a26
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| #
ec29ce67 |
| 01-Jun-2020 |
Mark Dykes <mardyk01@review.trustedfirmware.org> |
Merge "drivers: stm32_reset adapt interface to timeout argument" into integration
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| #
45c70e68 |
| 08-Dec-2019 |
Etienne Carriere <etienne.carriere@st.com> |
drivers: stm32_reset adapt interface to timeout argument
Changes stm32mp1 reset driver to API to add a timeout argument to stm32mp_reset_assert() and stm32mp_reset_deassert() and a return value.
Wi
drivers: stm32_reset adapt interface to timeout argument
Changes stm32mp1 reset driver to API to add a timeout argument to stm32mp_reset_assert() and stm32mp_reset_deassert() and a return value.
With a supplied timeout, the functions wait the target reset state is reached before returning. With a timeout of zero, the functions simply load target reset state in SoC interface and return without waiting.
Helper functions stm32mp_reset_set() and stm32mp_reset_release() use a zero timeout and return without a return code.
This change updates few stm32 drivers and plat/stm32mp1 blé_plat_setup.c accordingly without any functional change. functional change.
Change-Id: Ia1a73a15125d3055fd8739c125b70bcb9562c27f Signed-off-by: Etienne Carriere <etienne.carriere@st.com>
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| #
85838f48 |
| 07-May-2020 |
Sandrine Bailleux <sandrine.bailleux@arm.com> |
Merge changes from topic "fdt_wrappers_rework" into integration
* changes: plat/stm32: Use generic fdt_get_stdout_node_offset() fdt/wrappers: Introduce code to find UART DT node plat/stm32: Us
Merge changes from topic "fdt_wrappers_rework" into integration
* changes: plat/stm32: Use generic fdt_get_stdout_node_offset() fdt/wrappers: Introduce code to find UART DT node plat/stm32: Use generic fdt_get_reg_props_by_name()
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| #
7ad6d362 |
| 26-Mar-2020 |
Andre Przywara <andre.przywara@arm.com> |
plat/stm32: Use generic fdt_get_reg_props_by_name()
The STM32 platform port parse DT nodes to find base address to peripherals. It does this by using its own implementation, even though this functio
plat/stm32: Use generic fdt_get_reg_props_by_name()
The STM32 platform port parse DT nodes to find base address to peripherals. It does this by using its own implementation, even though this functionality is generic and actually widely useful outside of the STM32 code.
Re-implement fdt_get_reg_props_by_name() on top of the newly introduced fdt_get_reg_props_by_index() function, and move it to fdt_wrapper.c. This is removes the assumption that #address-cells and #size-cells are always one.
Change-Id: I6d584930262c732b6e0356d98aea50b2654f789d Signed-off-by: Andre Przywara <andre.przywara@arm.com>
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| #
92ce719b |
| 23-Mar-2020 |
Manish Pandey <manish.pandey2@arm.com> |
Merge changes from topic "static_analysis" into integration
* changes: io: io_stm32image: correct possible NULL pointer dereference plat/st: correctly check pwr-regulators node nand: stm32_fmc
Merge changes from topic "static_analysis" into integration
* changes: io: io_stm32image: correct possible NULL pointer dereference plat/st: correctly check pwr-regulators node nand: stm32_fmc2_nand: correct xor_ecc.val assigned value plat/st: correct static analysis tool warning raw_nand: correct static analysis tool warning spi: stm32_qspi: correct static analysis issues
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| #
9d22d310 |
| 11-Mar-2020 |
Yann Gautier <yann.gautier@st.com> |
spi: stm32_qspi: correct static analysis issues
Sparse issue: drivers/st/spi/stm32_qspi.c:445:5: warning: symbol 'stm32_qspi_init' was not declared. Should it be static?
Cppcheck issue: [drivers/s
spi: stm32_qspi: correct static analysis issues
Sparse issue: drivers/st/spi/stm32_qspi.c:445:5: warning: symbol 'stm32_qspi_init' was not declared. Should it be static?
Cppcheck issue: [drivers/st/spi/stm32_qspi.c:175] -> [drivers/st/spi/stm32_qspi.c:187]: (style) Variable 'len' is reassigned a value before the old one has been used. [drivers/st/spi/stm32_qspi.c:178]: (style) The scope of the variable 'timeout' can be reduced.
Change-Id: I575fb50766355a6717cbd193fc4a80ff1923014c Signed-off-by: Yann Gautier <yann.gautier@st.com>
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| #
0a910952 |
| 20-Jan-2020 |
Soby Mathew <soby.mathew@arm.com> |
Merge changes from topic "ld/mtd_framework" into integration
* changes: doc: stm32mp1: Update build command line fdts: stm32mp1: remove second QSPI flash instance stm32mp1: Add support for SPI
Merge changes from topic "ld/mtd_framework" into integration
* changes: doc: stm32mp1: Update build command line fdts: stm32mp1: remove second QSPI flash instance stm32mp1: Add support for SPI-NOR boot device stm32mp1: Add support for SPI-NAND boot device spi: stm32_qspi: Add QSPI support fdts: stm32mp1: update for FMC2 pin muxing stm32mp1: Add support for raw NAND boot device fmc: stm32_fmc2_nand: Add FMC2 driver support stm32mp1: Reduce MAX_XLAT_TABLES to 4 io: stm32image: fix device_size type stm32mp: add DT helper for reg by name stm32mp1: add compilation flags for boot devices lib: utils_def: add CLAMP macro compiler_rt: Import popcountdi2.c and popcountsi2.c files Add SPI-NOR framework Add SPI-NAND framework Add SPI-MEM framework Add raw NAND framework
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| #
0581a887 |
| 24-Sep-2019 |
Lionel Debieve <lionel.debieve@st.com> |
spi: stm32_qspi: Add QSPI support
Add QSPI support (limited to read interface). Implements the memory map and indirect modes. Low level driver based on SPI-MEM operations.
Change-Id: Ied698e6de3c17
spi: stm32_qspi: Add QSPI support
Add QSPI support (limited to read interface). Implements the memory map and indirect modes. Low level driver based on SPI-MEM operations.
Change-Id: Ied698e6de3c17d977f8b497c81f2e4a0a27c0961 Signed-off-by: Lionel Debieve <lionel.debieve@st.com> Signed-off-by: Christophe Kerello <christophe.kerello@st.com>
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