1 /*
2 * Copyright (c) 2015-2025, Arm Limited and Contributors. All rights reserved.
3 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 */
6
7 #include <assert.h>
8 #include <string.h>
9
10 #include <arch_helpers.h>
11 #include <common/debug.h>
12 #include <common/desc_image_load.h>
13 #include <drivers/fwu/fwu.h>
14 #include <drivers/fwu/fwu_metadata.h>
15 #include <drivers/io/io_block.h>
16 #include <drivers/io/io_driver.h>
17 #include <drivers/io/io_encrypted.h>
18 #include <drivers/io/io_fip.h>
19 #include <drivers/io/io_memmap.h>
20 #include <drivers/io/io_mtd.h>
21 #include <drivers/io/io_storage.h>
22 #include <drivers/mmc.h>
23 #include <drivers/partition/efi.h>
24 #include <drivers/partition/partition.h>
25 #include <drivers/raw_nand.h>
26 #include <drivers/spi_nand.h>
27 #include <drivers/spi_nor.h>
28 #include <drivers/st/stm32_fmc2_nand.h>
29 #include <drivers/st/stm32_qspi.h>
30 #include <drivers/st/stm32_sdmmc2.h>
31 #include <drivers/usb_device.h>
32 #include <lib/fconf/fconf.h>
33 #include <lib/mmio.h>
34 #include <lib/utils.h>
35 #include <plat/common/platform.h>
36 #include <tools_share/firmware_image_package.h>
37 #include <platform_def.h>
38 #include <stm32cubeprogrammer.h>
39 #include <stm32mp_efi.h>
40 #include <stm32mp_fconf_getter.h>
41 #include <stm32mp_io_storage.h>
42 #include <usb_dfu.h>
43
44 /* IO devices */
45 uintptr_t fip_dev_handle;
46 uintptr_t storage_dev_handle;
47
48 static const io_dev_connector_t *fip_dev_con;
49 static uint32_t nand_block_sz __maybe_unused;
50
51 #ifndef DECRYPTION_SUPPORT_none
52 static const io_dev_connector_t *enc_dev_con;
53 uintptr_t enc_dev_handle;
54 #endif
55
56 #if STM32MP_SDMMC || STM32MP_EMMC
57 static struct mmc_device_info mmc_info;
58
59 static uint8_t block_buffer[MMC_BLOCK_SIZE] __aligned(MMC_BLOCK_SIZE);
60
61 static io_block_dev_spec_t mmc_block_dev_spec = {
62 /* It's used as temp buffer in block driver */
63 .buffer = {
64 .offset = (size_t)&block_buffer,
65 .length = MMC_BLOCK_SIZE,
66 },
67 .ops = {
68 .read = mmc_read_blocks,
69 .write = NULL,
70 },
71 .block_size = MMC_BLOCK_SIZE,
72 };
73
74 static const io_dev_connector_t *mmc_dev_con;
75 #endif /* STM32MP_SDMMC || STM32MP_EMMC */
76
77 #if STM32MP_SPI_NOR
78 static io_mtd_dev_spec_t spi_nor_dev_spec = {
79 .ops = {
80 .init = spi_nor_init,
81 .read = spi_nor_read,
82 },
83 };
84 #endif
85
86 #if STM32MP_RAW_NAND
87 static io_mtd_dev_spec_t nand_dev_spec = {
88 .ops = {
89 .init = nand_raw_init,
90 .read = nand_read,
91 .seek = nand_seek_bb
92 },
93 };
94
95 static const io_dev_connector_t *nand_dev_con;
96 #endif
97
98 #if STM32MP_SPI_NAND
99 static io_mtd_dev_spec_t spi_nand_dev_spec = {
100 .ops = {
101 .init = spi_nand_init,
102 .read = nand_read,
103 .seek = nand_seek_bb
104 },
105 };
106 #endif
107
108 #if STM32MP_SPI_NAND || STM32MP_SPI_NOR
109 static const io_dev_connector_t *spi_dev_con;
110 #endif
111
112 #if STM32MP_UART_PROGRAMMER || STM32MP_USB_PROGRAMMER
113 static const io_dev_connector_t *memmap_dev_con;
114 #endif
115
116 io_block_spec_t image_block_spec = {
117 .offset = 0U,
118 .length = 0U,
119 };
120
open_fip(const uintptr_t spec)121 int open_fip(const uintptr_t spec)
122 {
123 return io_dev_init(fip_dev_handle, (uintptr_t)FIP_IMAGE_ID);
124 }
125
126 #ifndef DECRYPTION_SUPPORT_none
open_enc_fip(const uintptr_t spec)127 int open_enc_fip(const uintptr_t spec)
128 {
129 int result;
130 uintptr_t local_image_handle;
131
132 result = io_dev_init(enc_dev_handle, (uintptr_t)ENC_IMAGE_ID);
133 if (result != 0) {
134 return result;
135 }
136
137 result = io_open(enc_dev_handle, spec, &local_image_handle);
138 if (result != 0) {
139 return result;
140 }
141
142 VERBOSE("Using encrypted FIP\n");
143 io_close(local_image_handle);
144
145 return 0;
146 }
147 #endif
148
open_storage(const uintptr_t spec)149 int open_storage(const uintptr_t spec)
150 {
151 return io_dev_init(storage_dev_handle, 0);
152 }
153
154 #if STM32MP_EMMC_BOOT
get_boot_part_fip_header(void)155 static uint32_t get_boot_part_fip_header(void)
156 {
157 io_block_spec_t emmc_boot_fip_block_spec = {
158 .offset = STM32MP_EMMC_BOOT_FIP_OFFSET,
159 .length = MMC_BLOCK_SIZE, /* We are interested only in first 4 bytes */
160 };
161 uint32_t magic = 0U;
162 int io_result;
163 size_t bytes_read;
164 uintptr_t fip_hdr_handle;
165
166 io_result = io_open(storage_dev_handle, (uintptr_t)&emmc_boot_fip_block_spec,
167 &fip_hdr_handle);
168 assert(io_result == 0);
169
170 io_result = io_read(fip_hdr_handle, (uintptr_t)&magic, sizeof(magic),
171 &bytes_read);
172 if ((io_result != 0) || (bytes_read != sizeof(magic))) {
173 panic();
174 }
175
176 io_close(fip_hdr_handle);
177
178 VERBOSE("%s: eMMC boot magic at offset 256K: %08x\n",
179 __func__, magic);
180
181 return magic;
182 }
183 #endif
184
print_boot_device(boot_api_context_t * boot_context)185 static void print_boot_device(boot_api_context_t *boot_context)
186 {
187 switch (boot_context->boot_interface_selected) {
188 case BOOT_API_CTX_BOOT_INTERFACE_SEL_FLASH_SD:
189 INFO("Using SDMMC\n");
190 break;
191 case BOOT_API_CTX_BOOT_INTERFACE_SEL_FLASH_EMMC:
192 INFO("Using EMMC\n");
193 break;
194 case BOOT_API_CTX_BOOT_INTERFACE_SEL_FLASH_NOR_SPI:
195 INFO("Using SPI NOR\n");
196 break;
197 case BOOT_API_CTX_BOOT_INTERFACE_SEL_FLASH_NAND_FMC:
198 INFO("Using FMC NAND\n");
199 break;
200 case BOOT_API_CTX_BOOT_INTERFACE_SEL_FLASH_NAND_SPI:
201 INFO("Using SPI NAND\n");
202 break;
203 case BOOT_API_CTX_BOOT_INTERFACE_SEL_SERIAL_UART:
204 INFO("Using UART\n");
205 break;
206 case BOOT_API_CTX_BOOT_INTERFACE_SEL_SERIAL_USB:
207 INFO("Using USB\n");
208 break;
209 default:
210 ERROR("Boot interface %u not found\n",
211 boot_context->boot_interface_selected);
212 panic();
213 break;
214 }
215
216 if (boot_context->boot_interface_instance != 0U) {
217 INFO(" Instance %d\n", boot_context->boot_interface_instance);
218 }
219 }
220
221 #if STM32MP_SDMMC || STM32MP_EMMC
boot_mmc(enum mmc_device_type mmc_dev_type,uint16_t boot_interface_instance)222 static void boot_mmc(enum mmc_device_type mmc_dev_type,
223 uint16_t boot_interface_instance)
224 {
225 int io_result __maybe_unused;
226 struct stm32_sdmmc2_params params;
227
228 zeromem(¶ms, sizeof(struct stm32_sdmmc2_params));
229
230 mmc_info.mmc_dev_type = mmc_dev_type;
231
232 switch (boot_interface_instance) {
233 case 1:
234 params.reg_base = STM32MP_SDMMC1_BASE;
235 break;
236 case 2:
237 params.reg_base = STM32MP_SDMMC2_BASE;
238 break;
239 case 3:
240 params.reg_base = STM32MP_SDMMC3_BASE;
241 break;
242 default:
243 WARN("SDMMC instance not found, using default\n");
244 if (mmc_dev_type == MMC_IS_SD) {
245 params.reg_base = STM32MP_SDMMC1_BASE;
246 } else {
247 params.reg_base = STM32MP_SDMMC2_BASE;
248 }
249 break;
250 }
251
252 if (mmc_dev_type != MMC_IS_EMMC) {
253 params.flags = MMC_FLAG_SD_CMD6;
254 }
255
256 params.device_info = &mmc_info;
257 if (stm32_sdmmc2_mmc_init(¶ms) != 0) {
258 ERROR("SDMMC%u init failed\n", boot_interface_instance);
259 panic();
260 }
261
262 /* Open MMC as a block device to read FIP */
263 io_result = register_io_dev_block(&mmc_dev_con);
264 if (io_result != 0) {
265 panic();
266 }
267
268 io_result = io_dev_open(mmc_dev_con, (uintptr_t)&mmc_block_dev_spec,
269 &storage_dev_handle);
270 assert(io_result == 0);
271
272 #if STM32MP_EMMC_BOOT
273 if (mmc_dev_type == MMC_IS_EMMC) {
274 io_result = mmc_part_switch_current_boot();
275 assert(io_result == 0);
276
277 if (get_boot_part_fip_header() != TOC_HEADER_NAME) {
278 WARN("%s: Can't find FIP header on eMMC boot partition. Trying GPT\n",
279 __func__);
280 io_result = mmc_part_switch_user();
281 assert(io_result == 0);
282 return;
283 }
284
285 VERBOSE("%s: FIP header found on eMMC boot partition\n",
286 __func__);
287 image_block_spec.offset = STM32MP_EMMC_BOOT_FIP_OFFSET;
288 image_block_spec.length = mmc_boot_part_size() - STM32MP_EMMC_BOOT_FIP_OFFSET;
289 }
290 #endif
291 }
292 #endif /* STM32MP_SDMMC || STM32MP_EMMC */
293
294 #if STM32MP_SPI_NOR
boot_spi_nor(boot_api_context_t * boot_context)295 static void boot_spi_nor(boot_api_context_t *boot_context)
296 {
297 int io_result __maybe_unused;
298
299 io_result = stm32_qspi_init();
300 assert(io_result == 0);
301
302 io_result = register_io_dev_mtd(&spi_dev_con);
303 assert(io_result == 0);
304
305 /* Open connections to device */
306 io_result = io_dev_open(spi_dev_con,
307 (uintptr_t)&spi_nor_dev_spec,
308 &storage_dev_handle);
309 assert(io_result == 0);
310 }
311 #endif /* STM32MP_SPI_NOR */
312
313 #if STM32MP_RAW_NAND || STM32MP_SPI_NAND
314 /*
315 * This function returns 0 if it can find an alternate
316 * image to be loaded or a negative errno otherwise.
317 */
try_nand_backup_partitions(unsigned int image_id)318 static int try_nand_backup_partitions(unsigned int image_id)
319 {
320 static unsigned int backup_id;
321 static unsigned int backup_block_nb;
322
323 /* Check if NAND storage used */
324 if (nand_block_sz == 0U) {
325 return -ENODEV;
326 }
327
328 if (backup_id != image_id) {
329 backup_block_nb = PLATFORM_MTD_MAX_PART_SIZE / nand_block_sz;
330 backup_id = image_id;
331 }
332
333 if (backup_block_nb-- == 0U) {
334 return -ENOSPC;
335 }
336
337 #if PSA_FWU_SUPPORT
338 if (((image_block_spec.offset < STM32MP_NAND_FIP_B_OFFSET) &&
339 ((image_block_spec.offset + nand_block_sz) >= STM32MP_NAND_FIP_B_OFFSET)) ||
340 (image_block_spec.offset + nand_block_sz >= STM32MP_NAND_FIP_B_MAX_OFFSET)) {
341 return 0;
342 }
343 #endif
344
345 image_block_spec.offset += nand_block_sz;
346
347 return 0;
348 }
349
350 static const struct plat_try_images_ops try_img_ops = {
351 .next_instance = try_nand_backup_partitions,
352 };
353 #endif /* STM32MP_RAW_NAND || STM32MP_SPI_NAND */
354
355 #if STM32MP_RAW_NAND
boot_fmc2_nand(boot_api_context_t * boot_context)356 static void boot_fmc2_nand(boot_api_context_t *boot_context)
357 {
358 int io_result __maybe_unused;
359
360 plat_setup_try_img_ops(&try_img_ops);
361
362 io_result = stm32_fmc2_init();
363 assert(io_result == 0);
364
365 /* Register the IO device on this platform */
366 io_result = register_io_dev_mtd(&nand_dev_con);
367 assert(io_result == 0);
368
369 /* Open connections to device */
370 io_result = io_dev_open(nand_dev_con, (uintptr_t)&nand_dev_spec,
371 &storage_dev_handle);
372 assert(io_result == 0);
373
374 nand_block_sz = nand_dev_spec.erase_size;
375 }
376 #endif /* STM32MP_RAW_NAND */
377
378 #if STM32MP_SPI_NAND
boot_spi_nand(boot_api_context_t * boot_context)379 static void boot_spi_nand(boot_api_context_t *boot_context)
380 {
381 int io_result __maybe_unused;
382
383 plat_setup_try_img_ops(&try_img_ops);
384
385 io_result = stm32_qspi_init();
386 assert(io_result == 0);
387
388 io_result = register_io_dev_mtd(&spi_dev_con);
389 assert(io_result == 0);
390
391 /* Open connections to device */
392 io_result = io_dev_open(spi_dev_con,
393 (uintptr_t)&spi_nand_dev_spec,
394 &storage_dev_handle);
395 assert(io_result == 0);
396
397 nand_block_sz = spi_nand_dev_spec.erase_size;
398 }
399 #endif /* STM32MP_SPI_NAND */
400
401 #if STM32MP_UART_PROGRAMMER || STM32MP_USB_PROGRAMMER
mmap_io_setup(void)402 static void mmap_io_setup(void)
403 {
404 int io_result __maybe_unused;
405
406 io_result = register_io_dev_memmap(&memmap_dev_con);
407 assert(io_result == 0);
408
409 io_result = io_dev_open(memmap_dev_con, (uintptr_t)NULL,
410 &storage_dev_handle);
411 assert(io_result == 0);
412 }
413
414 #if STM32MP_UART_PROGRAMMER
stm32cubeprogrammer_uart(uint8_t phase,uintptr_t base,size_t len)415 static void stm32cubeprogrammer_uart(uint8_t phase, uintptr_t base, size_t len)
416 {
417 int ret __maybe_unused;
418 boot_api_context_t *boot_context =
419 (boot_api_context_t *)stm32mp_get_boot_ctx_address();
420 uintptr_t uart_base;
421
422 uart_base = get_uart_address(boot_context->boot_interface_instance);
423 ret = stm32cubeprog_uart_load(uart_base, phase, base, len);
424 assert(ret == 0);
425 }
426 #endif
427
428 #if STM32MP_USB_PROGRAMMER
stm32cubeprogrammer_usb(uint8_t phase,uintptr_t base,size_t len)429 static void stm32cubeprogrammer_usb(uint8_t phase, uintptr_t base, size_t len)
430 {
431 int ret __maybe_unused;
432 static struct usb_handle *pdev;
433
434 /* Init USB on platform */
435 if (pdev == NULL) {
436 pdev = usb_dfu_plat_init();
437 }
438
439 ret = stm32cubeprog_usb_load(pdev, phase, base, len);
440 assert(ret == 0);
441 }
442 #endif
443 #endif /* STM32MP_UART_PROGRAMMER || STM32MP_USB_PROGRAMMER */
444
stm32mp_io_setup(void)445 void stm32mp_io_setup(void)
446 {
447 int io_result __maybe_unused;
448 boot_api_context_t *boot_context =
449 (boot_api_context_t *)stm32mp_get_boot_ctx_address();
450
451 print_boot_device(boot_context);
452
453 if ((boot_context->boot_partition_used_toboot == 1U) ||
454 (boot_context->boot_partition_used_toboot == 2U)) {
455 INFO("Boot used partition fsbl%u\n",
456 boot_context->boot_partition_used_toboot);
457 }
458
459 io_result = register_io_dev_fip(&fip_dev_con);
460 assert(io_result == 0);
461
462 io_result = io_dev_open(fip_dev_con, (uintptr_t)NULL, &fip_dev_handle);
463
464 #ifndef DECRYPTION_SUPPORT_none
465 io_result = register_io_dev_enc(&enc_dev_con);
466 assert(io_result == 0);
467
468 io_result = io_dev_open(enc_dev_con, (uintptr_t)NULL, &enc_dev_handle);
469 assert(io_result == 0);
470 #endif
471
472 switch (boot_context->boot_interface_selected) {
473 #if STM32MP_SDMMC
474 case BOOT_API_CTX_BOOT_INTERFACE_SEL_FLASH_SD:
475 dmbsy();
476 boot_mmc(MMC_IS_SD, boot_context->boot_interface_instance);
477 break;
478 #endif
479 #if STM32MP_EMMC
480 case BOOT_API_CTX_BOOT_INTERFACE_SEL_FLASH_EMMC:
481 dmbsy();
482 boot_mmc(MMC_IS_EMMC, boot_context->boot_interface_instance);
483 break;
484 #endif
485 #if STM32MP_SPI_NOR
486 case BOOT_API_CTX_BOOT_INTERFACE_SEL_FLASH_NOR_SPI:
487 dmbsy();
488 boot_spi_nor(boot_context);
489 break;
490 #endif
491 #if STM32MP_RAW_NAND
492 case BOOT_API_CTX_BOOT_INTERFACE_SEL_FLASH_NAND_FMC:
493 dmbsy();
494 boot_fmc2_nand(boot_context);
495 break;
496 #endif
497 #if STM32MP_SPI_NAND
498 case BOOT_API_CTX_BOOT_INTERFACE_SEL_FLASH_NAND_SPI:
499 dmbsy();
500 boot_spi_nand(boot_context);
501 break;
502 #endif
503 #if STM32MP_UART_PROGRAMMER || STM32MP_USB_PROGRAMMER
504 #if STM32MP_UART_PROGRAMMER
505 case BOOT_API_CTX_BOOT_INTERFACE_SEL_SERIAL_UART:
506 #endif
507 #if STM32MP_USB_PROGRAMMER
508 case BOOT_API_CTX_BOOT_INTERFACE_SEL_SERIAL_USB:
509 #endif
510 dmbsy();
511 mmap_io_setup();
512 break;
513 #endif
514
515 default:
516 ERROR("Boot interface %d not supported\n",
517 boot_context->boot_interface_selected);
518 panic();
519 break;
520 }
521 }
522
bl2_plat_handle_pre_image_load(unsigned int image_id)523 int bl2_plat_handle_pre_image_load(unsigned int image_id)
524 {
525 static bool gpt_init_done __maybe_unused;
526 uint16_t boot_itf = stm32mp_get_boot_itf_selected();
527
528 switch (boot_itf) {
529 #if STM32MP_SDMMC || STM32MP_EMMC
530 case BOOT_API_CTX_BOOT_INTERFACE_SEL_FLASH_EMMC:
531 #if STM32MP_EMMC_BOOT
532 if (image_block_spec.offset == STM32MP_EMMC_BOOT_FIP_OFFSET) {
533 break;
534 }
535 #endif
536 /* fallthrough */
537 case BOOT_API_CTX_BOOT_INTERFACE_SEL_FLASH_SD:
538 if (!gpt_init_done) {
539 /*
540 * With FWU Multi Bank feature enabled, the selection of
541 * the image to boot will be done by fwu_init calling the
542 * platform hook, plat_fwu_set_images_source.
543 */
544 #if !PSA_FWU_SUPPORT
545 const partition_entry_t *entry;
546 const struct efi_guid fip_guid = STM32MP_FIP_GUID;
547
548 partition_init(GPT_IMAGE_ID);
549 entry = get_partition_entry_by_type(&fip_guid);
550 if (entry == NULL) {
551 entry = get_partition_entry(FIP_IMAGE_NAME);
552 if (entry == NULL) {
553 ERROR("Could NOT find the %s partition!\n",
554 FIP_IMAGE_NAME);
555
556 return -ENOENT;
557 }
558 }
559
560 image_block_spec.offset = entry->start;
561 image_block_spec.length = entry->length;
562 #endif
563 gpt_init_done = true;
564 } else {
565 bl_mem_params_node_t *bl_mem_params = get_bl_mem_params_node(image_id);
566
567 assert(bl_mem_params != NULL);
568
569 mmc_block_dev_spec.buffer.offset = bl_mem_params->image_info.image_base;
570 mmc_block_dev_spec.buffer.length = bl_mem_params->image_info.image_max_size;
571 }
572
573 break;
574 #endif
575
576 #if STM32MP_RAW_NAND || STM32MP_SPI_NAND
577 #if STM32MP_RAW_NAND
578 case BOOT_API_CTX_BOOT_INTERFACE_SEL_FLASH_NAND_FMC:
579 #endif
580 #if STM32MP_SPI_NAND
581 case BOOT_API_CTX_BOOT_INTERFACE_SEL_FLASH_NAND_SPI:
582 #endif
583 /*
584 * With FWU Multi Bank feature enabled, the selection of
585 * the image to boot will be done by fwu_init calling the
586 * platform hook, plat_fwu_set_images_source.
587 */
588 #if !PSA_FWU_SUPPORT
589 image_block_spec.offset = STM32MP_NAND_FIP_OFFSET;
590 #endif
591 break;
592 #endif
593
594 #if STM32MP_SPI_NOR
595 case BOOT_API_CTX_BOOT_INTERFACE_SEL_FLASH_NOR_SPI:
596 /*
597 * With FWU Multi Bank feature enabled, the selection of
598 * the image to boot will be done by fwu_init calling the
599 * platform hook, plat_fwu_set_images_source.
600 */
601 #if !PSA_FWU_SUPPORT
602 image_block_spec.offset = STM32MP_NOR_FIP_OFFSET;
603 #endif
604 break;
605 #endif
606
607 #if STM32MP_UART_PROGRAMMER
608 case BOOT_API_CTX_BOOT_INTERFACE_SEL_SERIAL_UART:
609 #if STM32MP_DDR_FIP_IO_STORAGE
610 if (image_id == DDR_FW_ID) {
611 stm32cubeprogrammer_uart(PHASE_DDR_FW,
612 DWL_DDR_BUFFER_BASE,
613 DWL_DDR_BUFFER_SIZE);
614 /* FIP loaded at DWL address */
615 image_block_spec.offset = DWL_DDR_BUFFER_BASE;
616 image_block_spec.length = DWL_DDR_BUFFER_SIZE;
617 }
618 #endif
619 if (image_id == FW_CONFIG_ID) {
620 stm32cubeprogrammer_uart(PHASE_SSBL, DWL_BUFFER_BASE,
621 DWL_BUFFER_SIZE);
622 /* FIP loaded at DWL address */
623 image_block_spec.offset = DWL_BUFFER_BASE;
624 image_block_spec.length = DWL_BUFFER_SIZE;
625 }
626 break;
627 #endif
628 #if STM32MP_USB_PROGRAMMER
629 case BOOT_API_CTX_BOOT_INTERFACE_SEL_SERIAL_USB:
630 #if STM32MP_DDR_FIP_IO_STORAGE
631 if (image_id == DDR_FW_ID) {
632 stm32cubeprogrammer_usb(PHASE_DDR_FW,
633 DWL_DDR_BUFFER_BASE,
634 DWL_DDR_BUFFER_SIZE);
635 /* FIP loaded at DWL address */
636 image_block_spec.offset = DWL_DDR_BUFFER_BASE;
637 image_block_spec.length = DWL_DDR_BUFFER_SIZE;
638 }
639 #endif
640 if (image_id == FW_CONFIG_ID) {
641 stm32cubeprogrammer_usb(PHASE_SSBL, DWL_BUFFER_BASE,
642 DWL_BUFFER_SIZE);
643 /* FIP loaded at DWL address */
644 image_block_spec.offset = DWL_BUFFER_BASE;
645 image_block_spec.length = DWL_BUFFER_SIZE;
646 }
647 break;
648 #endif
649
650 default:
651 ERROR("FIP Not found\n");
652 panic();
653 }
654
655 return 0;
656 }
657
658 /*
659 * Return an IO device handle and specification which can be used to access
660 * an image. Use this to enforce platform load policy.
661 */
plat_get_image_source(unsigned int image_id,uintptr_t * dev_handle,uintptr_t * image_spec)662 int plat_get_image_source(unsigned int image_id, uintptr_t *dev_handle,
663 uintptr_t *image_spec)
664 {
665 int rc;
666 const struct plat_io_policy *policy;
667
668 policy = FCONF_GET_PROPERTY(stm32mp, io_policies, image_id);
669 rc = policy->check(policy->image_spec);
670 if (rc == 0) {
671 *image_spec = policy->image_spec;
672 *dev_handle = *(policy->dev_handle);
673 }
674
675 return rc;
676 }
677
678 #if PSA_FWU_SUPPORT
679 /*
680 * In each boot in non-trial mode, we set the BKP register to
681 * FWU_MAX_TRIAL_REBOOT, and return the active_index from metadata.
682 *
683 * As long as the update agent didn't update the "accepted" field in metadata
684 * (i.e. we are in trial mode), we select the new active_index.
685 * To avoid infinite boot loop at trial boot we decrement a BKP register.
686 * If this counter is 0:
687 * - an unexpected TAMPER event raised (that resets the BKP registers to 0)
688 * - a power-off occurs before the update agent was able to update the
689 * "accepted' field
690 * - we already boot FWU_MAX_TRIAL_REBOOT times in trial mode.
691 * we select the previous_active_index.
692 */
plat_fwu_get_boot_idx(void)693 uint32_t plat_fwu_get_boot_idx(void)
694 {
695 /*
696 * Select boot index and update boot counter only once per boot
697 * even if this function is called several times.
698 */
699 static uint32_t boot_idx = INVALID_BOOT_IDX;
700
701 if (boot_idx == INVALID_BOOT_IDX) {
702 const struct fwu_metadata *data = fwu_get_metadata();
703
704 boot_idx = data->active_index;
705
706 if (data->bank_state[boot_idx] == FWU_BANK_STATE_VALID) {
707 if (stm32_get_and_dec_fwu_trial_boot_cnt() == 0U) {
708 WARN("Trial FWU fails %u times\n",
709 FWU_MAX_TRIAL_REBOOT);
710 boot_idx = fwu_get_alternate_boot_bank();
711 }
712 } else if (data->bank_state[boot_idx] ==
713 FWU_BANK_STATE_ACCEPTED) {
714 stm32_set_max_fwu_trial_boot_cnt();
715 } else {
716 ERROR("The active bank(%u) of the platform is in Invalid State.\n",
717 boot_idx);
718 boot_idx = fwu_get_alternate_boot_bank();
719 stm32_clear_fwu_trial_boot_cnt();
720 }
721 }
722
723 return boot_idx;
724 }
725
stm32_get_image_spec(const struct efi_guid * img_type_guid)726 static void *stm32_get_image_spec(const struct efi_guid *img_type_guid)
727 {
728 unsigned int i;
729
730 for (i = 0U; i < MAX_NUMBER_IDS; i++) {
731 if ((guidcmp(&policies[i].img_type_guid, img_type_guid)) == 0) {
732 return (void *)policies[i].image_spec;
733 }
734 }
735
736 return NULL;
737 }
738
plat_fwu_set_images_source(const struct fwu_metadata * metadata)739 void plat_fwu_set_images_source(const struct fwu_metadata *metadata)
740 {
741 unsigned int i;
742 uint32_t boot_idx;
743 const partition_entry_t *entry __maybe_unused;
744 const struct fwu_image_entry *img_entry;
745 const void *img_type_guid;
746 const void *img_guid;
747 io_block_spec_t *image_spec;
748 const uint16_t boot_itf = stm32mp_get_boot_itf_selected();
749
750 boot_idx = plat_fwu_get_boot_idx();
751 assert(boot_idx < NR_OF_FW_BANKS);
752 VERBOSE("Selecting to boot from bank %u\n", boot_idx);
753
754 img_entry = (void *)&metadata->fw_desc.img_entry;
755 for (i = 0U; i < NR_OF_IMAGES_IN_FW_BANK; i++) {
756 img_type_guid = &img_entry[i].img_type_guid;
757
758 img_guid = &img_entry[i].img_bank_info[boot_idx].img_guid;
759
760 image_spec = stm32_get_image_spec(img_type_guid);
761 if (image_spec == NULL) {
762 ERROR("Unable to get image spec for the image in the metadata\n");
763 panic();
764 }
765
766 switch (boot_itf) {
767 #if (STM32MP_SDMMC || STM32MP_EMMC)
768 case BOOT_API_CTX_BOOT_INTERFACE_SEL_FLASH_SD:
769 case BOOT_API_CTX_BOOT_INTERFACE_SEL_FLASH_EMMC:
770 entry = get_partition_entry_by_guid(img_guid);
771 if (entry == NULL) {
772 ERROR("No partition with the uuid mentioned in metadata\n");
773 panic();
774 }
775
776 image_spec->offset = entry->start;
777 image_spec->length = entry->length;
778 break;
779 #endif
780 #if STM32MP_SPI_NOR
781 case BOOT_API_CTX_BOOT_INTERFACE_SEL_FLASH_NOR_SPI:
782 if (guidcmp(img_guid, &STM32MP_NOR_FIP_A_GUID) == 0) {
783 image_spec->offset = STM32MP_NOR_FIP_A_OFFSET;
784 } else if (guidcmp(img_guid, &STM32MP_NOR_FIP_B_GUID) == 0) {
785 image_spec->offset = STM32MP_NOR_FIP_B_OFFSET;
786 } else {
787 ERROR("Invalid uuid mentioned in metadata\n");
788 panic();
789 }
790 break;
791 #endif
792 #if (STM32MP_RAW_NAND || STM32MP_SPI_NAND)
793 case BOOT_API_CTX_BOOT_INTERFACE_SEL_FLASH_NAND_FMC:
794 case BOOT_API_CTX_BOOT_INTERFACE_SEL_FLASH_NAND_SPI:
795 if (guidcmp(img_guid, &STM32MP_NAND_FIP_A_GUID) == 0) {
796 image_spec->offset = STM32MP_NAND_FIP_A_OFFSET;
797 } else if (guidcmp(img_guid, &STM32MP_NAND_FIP_B_GUID) == 0) {
798 image_spec->offset = STM32MP_NAND_FIP_B_OFFSET;
799 } else {
800 ERROR("Invalid uuid mentioned in metadata\n");
801 panic();
802 }
803 break;
804 #endif
805 default:
806 panic();
807 break;
808 }
809 }
810 }
811
set_metadata_image_source(unsigned int image_id,uintptr_t * handle,uintptr_t * image_spec)812 static int set_metadata_image_source(unsigned int image_id,
813 uintptr_t *handle,
814 uintptr_t *image_spec)
815 {
816 struct plat_io_policy *policy;
817 io_block_spec_t *spec __maybe_unused;
818 const partition_entry_t *entry __maybe_unused;
819 const uint16_t boot_itf = stm32mp_get_boot_itf_selected();
820
821 policy = &policies[image_id];
822 spec = (io_block_spec_t *)policy->image_spec;
823
824 switch (boot_itf) {
825 #if (STM32MP_SDMMC || STM32MP_EMMC)
826 case BOOT_API_CTX_BOOT_INTERFACE_SEL_FLASH_SD:
827 case BOOT_API_CTX_BOOT_INTERFACE_SEL_FLASH_EMMC:
828 partition_init(GPT_IMAGE_ID);
829
830 if (image_id == FWU_METADATA_IMAGE_ID) {
831 entry = get_partition_entry(METADATA_PART_1);
832 } else {
833 entry = get_partition_entry(METADATA_PART_2);
834 }
835
836 if (entry == NULL) {
837 ERROR("Unable to find a metadata partition\n");
838 return -ENOENT;
839 }
840
841 spec->offset = entry->start;
842 spec->length = entry->length;
843 break;
844 #endif
845
846 #if STM32MP_SPI_NOR
847 case BOOT_API_CTX_BOOT_INTERFACE_SEL_FLASH_NOR_SPI:
848 if (image_id == FWU_METADATA_IMAGE_ID) {
849 spec->offset = STM32MP_NOR_METADATA1_OFFSET;
850 } else {
851 spec->offset = STM32MP_NOR_METADATA2_OFFSET;
852 }
853
854 spec->length = sizeof(struct fwu_metadata);
855 break;
856 #endif
857
858 #if (STM32MP_RAW_NAND || STM32MP_SPI_NAND)
859 case BOOT_API_CTX_BOOT_INTERFACE_SEL_FLASH_NAND_FMC:
860 case BOOT_API_CTX_BOOT_INTERFACE_SEL_FLASH_NAND_SPI:
861 if (image_id == FWU_METADATA_IMAGE_ID) {
862 spec->offset = STM32MP_NAND_METADATA1_OFFSET;
863 } else {
864 spec->offset = STM32MP_NAND_METADATA2_OFFSET;
865 }
866
867 spec->length = sizeof(struct fwu_metadata);
868 break;
869 #endif
870 default:
871 panic();
872 break;
873 }
874
875 *image_spec = policy->image_spec;
876 *handle = *policy->dev_handle;
877
878 return 0;
879 }
880
plat_fwu_set_metadata_image_source(unsigned int image_id,uintptr_t * handle,uintptr_t * image_spec)881 int plat_fwu_set_metadata_image_source(unsigned int image_id,
882 uintptr_t *handle,
883 uintptr_t *image_spec)
884 {
885 assert((image_id == FWU_METADATA_IMAGE_ID) ||
886 (image_id == BKUP_FWU_METADATA_IMAGE_ID));
887
888 return set_metadata_image_source(image_id, handle, image_spec);
889 }
890 #endif /* PSA_FWU_SUPPORT */
891