xref: /rk3399_ARM-atf/plat/imx/imx7/picopi/picopi_bl2_setup.c (revision 23e15fadc34fca8aae33246348f023a6146f96c1)
1*8c824273SArunachalam Ganapathy /*
2*8c824273SArunachalam Ganapathy  * Copyright (c) 2018-2021, ARM Limited and Contributors. All rights reserved.
3*8c824273SArunachalam Ganapathy  *
4*8c824273SArunachalam Ganapathy  * SPDX-License-Identifier: BSD-3-Clause
5*8c824273SArunachalam Ganapathy  */
6*8c824273SArunachalam Ganapathy 
7*8c824273SArunachalam Ganapathy #include <assert.h>
8*8c824273SArunachalam Ganapathy 
9*8c824273SArunachalam Ganapathy #include <platform_def.h>
10*8c824273SArunachalam Ganapathy 
11*8c824273SArunachalam Ganapathy #include <common/debug.h>
12*8c824273SArunachalam Ganapathy #include <drivers/console.h>
13*8c824273SArunachalam Ganapathy #include <drivers/mmc.h>
14*8c824273SArunachalam Ganapathy #include <lib/utils.h>
15*8c824273SArunachalam Ganapathy 
16*8c824273SArunachalam Ganapathy #include <imx_caam.h>
17*8c824273SArunachalam Ganapathy #include <imx_clock.h>
18*8c824273SArunachalam Ganapathy #include <imx_io_mux.h>
19*8c824273SArunachalam Ganapathy #include <imx_uart.h>
20*8c824273SArunachalam Ganapathy #include <imx_usdhc.h>
21*8c824273SArunachalam Ganapathy #include <imx7_def.h>
22*8c824273SArunachalam Ganapathy 
23*8c824273SArunachalam Ganapathy #define UART5_CLK_SELECT (CCM_TARGET_ROOT_ENABLE |\
24*8c824273SArunachalam Ganapathy 			  CCM_TRGT_MUX_UART5_CLK_ROOT_OSC_24M)
25*8c824273SArunachalam Ganapathy 
26*8c824273SArunachalam Ganapathy #define USDHC_CLK_SELECT (CCM_TARGET_ROOT_ENABLE |\
27*8c824273SArunachalam Ganapathy 			  CCM_TRGT_MUX_NAND_USDHC_BUS_CLK_ROOT_AHB |\
28*8c824273SArunachalam Ganapathy 			  CCM_TARGET_POST_PODF(2))
29*8c824273SArunachalam Ganapathy 
30*8c824273SArunachalam Ganapathy #define USB_CLK_SELECT (CCM_TARGET_ROOT_ENABLE |\
31*8c824273SArunachalam Ganapathy 			CCM_TRGT_MUX_USB_HSIC_CLK_ROOT_SYS_PLL)
32*8c824273SArunachalam Ganapathy 
33*8c824273SArunachalam Ganapathy #define PICOPI_UART5_RX_MUX \
34*8c824273SArunachalam Ganapathy 	IOMUXC_SW_MUX_CTL_PAD_I2C4_SCL_ALT1_UART5_RX_DATA
35*8c824273SArunachalam Ganapathy 
36*8c824273SArunachalam Ganapathy #define PICOPI_UART5_TX_MUX \
37*8c824273SArunachalam Ganapathy 	IOMUXC_SW_MUX_CTL_PAD_I2C4_SDA_ALT1_UART5_TX_DATA
38*8c824273SArunachalam Ganapathy 
39*8c824273SArunachalam Ganapathy #define PICOPI_SD3_FEATURES \
40*8c824273SArunachalam Ganapathy 	(IOMUXC_SW_PAD_CTL_PAD_SD3_PU_47K            | \
41*8c824273SArunachalam Ganapathy 	 IOMUXC_SW_PAD_CTL_PAD_SD3_PE                | \
42*8c824273SArunachalam Ganapathy 	 IOMUXC_SW_PAD_CTL_PAD_SD3_HYS               | \
43*8c824273SArunachalam Ganapathy 	 IOMUXC_SW_PAD_CTL_PAD_SD3_SLEW_SLOW         | \
44*8c824273SArunachalam Ganapathy 	 IOMUXC_SW_PAD_CTL_PAD_SD3_DSE_3_X6)
45*8c824273SArunachalam Ganapathy 
46*8c824273SArunachalam Ganapathy static struct mmc_device_info mmc_info;
47*8c824273SArunachalam Ganapathy 
picopi_setup_pinmux(void)48*8c824273SArunachalam Ganapathy static void picopi_setup_pinmux(void)
49*8c824273SArunachalam Ganapathy {
50*8c824273SArunachalam Ganapathy 	/* Configure UART5 TX */
51*8c824273SArunachalam Ganapathy 	imx_io_muxc_set_pad_alt_function(IOMUXC_SW_MUX_CTL_PAD_I2C4_SDA_OFFSET,
52*8c824273SArunachalam Ganapathy 					 PICOPI_UART5_TX_MUX);
53*8c824273SArunachalam Ganapathy 	/* Configure UART5 RX */
54*8c824273SArunachalam Ganapathy 	imx_io_muxc_set_pad_alt_function(IOMUXC_SW_MUX_CTL_PAD_I2C4_SCL_OFFSET,
55*8c824273SArunachalam Ganapathy 					 PICOPI_UART5_RX_MUX);
56*8c824273SArunachalam Ganapathy 
57*8c824273SArunachalam Ganapathy 	/* Configure USDHC3 */
58*8c824273SArunachalam Ganapathy 	imx_io_muxc_set_pad_alt_function(IOMUXC_SW_MUX_CTL_PAD_SD3_CLK_OFFSET, 0);
59*8c824273SArunachalam Ganapathy 	imx_io_muxc_set_pad_alt_function(IOMUXC_SW_MUX_CTL_PAD_SD3_CMD_OFFSET, 0);
60*8c824273SArunachalam Ganapathy 	imx_io_muxc_set_pad_alt_function(IOMUXC_SW_MUX_CTL_PAD_SD3_DATA0_OFFSET, 0);
61*8c824273SArunachalam Ganapathy 	imx_io_muxc_set_pad_alt_function(IOMUXC_SW_MUX_CTL_PAD_SD3_DATA1_OFFSET, 0);
62*8c824273SArunachalam Ganapathy 	imx_io_muxc_set_pad_alt_function(IOMUXC_SW_MUX_CTL_PAD_SD3_DATA2_OFFSET, 0);
63*8c824273SArunachalam Ganapathy 	imx_io_muxc_set_pad_alt_function(IOMUXC_SW_MUX_CTL_PAD_SD3_DATA3_OFFSET, 0);
64*8c824273SArunachalam Ganapathy 	imx_io_muxc_set_pad_alt_function(IOMUXC_SW_MUX_CTL_PAD_SD3_DATA4_OFFSET, 0);
65*8c824273SArunachalam Ganapathy 	imx_io_muxc_set_pad_alt_function(IOMUXC_SW_MUX_CTL_PAD_SD3_DATA5_OFFSET, 0);
66*8c824273SArunachalam Ganapathy 	imx_io_muxc_set_pad_alt_function(IOMUXC_SW_MUX_CTL_PAD_SD3_DATA6_OFFSET, 0);
67*8c824273SArunachalam Ganapathy 	imx_io_muxc_set_pad_alt_function(IOMUXC_SW_MUX_CTL_PAD_SD3_DATA7_OFFSET, 0);
68*8c824273SArunachalam Ganapathy 	imx_io_muxc_set_pad_alt_function(IOMUXC_SW_MUX_CTL_PAD_GPIO1_IO14_OFFSET,
69*8c824273SArunachalam Ganapathy 					 IOMUXC_SW_MUX_CTL_PAD_GPIO1_IO14_ALT1_SD3_CD_B);
70*8c824273SArunachalam Ganapathy 
71*8c824273SArunachalam Ganapathy 	imx_io_muxc_set_pad_features(IOMUXC_SW_PAD_CTL_PAD_SD3_CLK_OFFSET,
72*8c824273SArunachalam Ganapathy 				     PICOPI_SD3_FEATURES);
73*8c824273SArunachalam Ganapathy 	imx_io_muxc_set_pad_features(IOMUXC_SW_PAD_CTL_PAD_SD3_CMD_OFFSET,
74*8c824273SArunachalam Ganapathy 				     PICOPI_SD3_FEATURES);
75*8c824273SArunachalam Ganapathy 	imx_io_muxc_set_pad_features(IOMUXC_SW_PAD_CTL_PAD_SD3_DATA0_OFFSET,
76*8c824273SArunachalam Ganapathy 				     PICOPI_SD3_FEATURES);
77*8c824273SArunachalam Ganapathy 	imx_io_muxc_set_pad_features(IOMUXC_SW_PAD_CTL_PAD_SD3_DATA1_OFFSET,
78*8c824273SArunachalam Ganapathy 				     PICOPI_SD3_FEATURES);
79*8c824273SArunachalam Ganapathy 	imx_io_muxc_set_pad_features(IOMUXC_SW_PAD_CTL_PAD_SD3_DATA2_OFFSET,
80*8c824273SArunachalam Ganapathy 				     PICOPI_SD3_FEATURES);
81*8c824273SArunachalam Ganapathy 	imx_io_muxc_set_pad_features(IOMUXC_SW_PAD_CTL_PAD_SD3_DATA3_OFFSET,
82*8c824273SArunachalam Ganapathy 				     PICOPI_SD3_FEATURES);
83*8c824273SArunachalam Ganapathy 	imx_io_muxc_set_pad_features(IOMUXC_SW_PAD_CTL_PAD_SD3_DATA4_OFFSET,
84*8c824273SArunachalam Ganapathy 				     PICOPI_SD3_FEATURES);
85*8c824273SArunachalam Ganapathy 	imx_io_muxc_set_pad_features(IOMUXC_SW_PAD_CTL_PAD_SD3_DATA5_OFFSET,
86*8c824273SArunachalam Ganapathy 				     PICOPI_SD3_FEATURES);
87*8c824273SArunachalam Ganapathy 	imx_io_muxc_set_pad_features(IOMUXC_SW_PAD_CTL_PAD_SD3_DATA6_OFFSET,
88*8c824273SArunachalam Ganapathy 				     PICOPI_SD3_FEATURES);
89*8c824273SArunachalam Ganapathy 	imx_io_muxc_set_pad_features(IOMUXC_SW_PAD_CTL_PAD_SD3_DATA7_OFFSET,
90*8c824273SArunachalam Ganapathy 				     PICOPI_SD3_FEATURES);
91*8c824273SArunachalam Ganapathy 	imx_io_muxc_set_pad_features(IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO14_OFFSET,
92*8c824273SArunachalam Ganapathy 				     PICOPI_SD3_FEATURES);
93*8c824273SArunachalam Ganapathy }
94*8c824273SArunachalam Ganapathy 
picopi_usdhc_setup(void)95*8c824273SArunachalam Ganapathy static void picopi_usdhc_setup(void)
96*8c824273SArunachalam Ganapathy {
97*8c824273SArunachalam Ganapathy 	imx_usdhc_params_t params;
98*8c824273SArunachalam Ganapathy 
99*8c824273SArunachalam Ganapathy 	zeromem(&params, sizeof(imx_usdhc_params_t));
100*8c824273SArunachalam Ganapathy 	params.reg_base = PLAT_PICOPI_BOOT_MMC_BASE;
101*8c824273SArunachalam Ganapathy 	params.clk_rate = 25000000;
102*8c824273SArunachalam Ganapathy 	params.bus_width = MMC_BUS_WIDTH_8;
103*8c824273SArunachalam Ganapathy 	mmc_info.mmc_dev_type = MMC_IS_EMMC;
104*8c824273SArunachalam Ganapathy 	imx_usdhc_init(&params, &mmc_info);
105*8c824273SArunachalam Ganapathy }
106*8c824273SArunachalam Ganapathy 
picopi_setup_usb_clocks(void)107*8c824273SArunachalam Ganapathy static void picopi_setup_usb_clocks(void)
108*8c824273SArunachalam Ganapathy {
109*8c824273SArunachalam Ganapathy 	uint32_t usb_en_bits = (uint32_t)USB_CLK_SELECT;
110*8c824273SArunachalam Ganapathy 
111*8c824273SArunachalam Ganapathy 	imx_clock_set_usb_clk_root_bits(usb_en_bits);
112*8c824273SArunachalam Ganapathy 	imx_clock_enable_usb(CCM_CCGR_ID_USB_IPG);
113*8c824273SArunachalam Ganapathy 	imx_clock_enable_usb(CCM_CCGR_ID_USB_PHY_480MCLK);
114*8c824273SArunachalam Ganapathy 	imx_clock_enable_usb(CCM_CCGR_ID_USB_OTG1_PHY);
115*8c824273SArunachalam Ganapathy 	imx_clock_enable_usb(CCM_CCGR_ID_USB_OTG2_PHY);
116*8c824273SArunachalam Ganapathy }
117*8c824273SArunachalam Ganapathy 
imx7_platform_setup(u_register_t arg1,u_register_t arg2,u_register_t arg3,u_register_t arg4)118*8c824273SArunachalam Ganapathy void imx7_platform_setup(u_register_t arg1, u_register_t arg2,
119*8c824273SArunachalam Ganapathy 			 u_register_t arg3, u_register_t arg4)
120*8c824273SArunachalam Ganapathy {
121*8c824273SArunachalam Ganapathy 	uint32_t uart5_en_bits = (uint32_t)UART5_CLK_SELECT;
122*8c824273SArunachalam Ganapathy 	uint32_t usdhc_clock_sel = PLAT_PICOPI_SD - 1;
123*8c824273SArunachalam Ganapathy 
124*8c824273SArunachalam Ganapathy 	/* Initialize clocks etc */
125*8c824273SArunachalam Ganapathy 	imx_clock_enable_uart(4, uart5_en_bits);
126*8c824273SArunachalam Ganapathy 	imx_clock_enable_usdhc(usdhc_clock_sel, USDHC_CLK_SELECT);
127*8c824273SArunachalam Ganapathy 
128*8c824273SArunachalam Ganapathy 	picopi_setup_usb_clocks();
129*8c824273SArunachalam Ganapathy 
130*8c824273SArunachalam Ganapathy 	/* Setup pin-muxes */
131*8c824273SArunachalam Ganapathy 	picopi_setup_pinmux();
132*8c824273SArunachalam Ganapathy 
133*8c824273SArunachalam Ganapathy 	picopi_usdhc_setup();
134*8c824273SArunachalam Ganapathy }
135