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Searched refs:ULL (Results 1 – 25 of 187) sorted by relevance

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/rk3399_ARM-atf/include/arch/aarch64/
H A Darch.h33 #define MPIDR_MT_MASK (ULL(1) << 24)
37 #define MPIDR_AFFLVL_MASK ULL(0xff)
43 #define MPIDR_AFFINITY_MASK ULL(0xff00ffffff)
45 #define MPIDR_AFFLVL0 ULL(0x0)
46 #define MPIDR_AFFLVL1 ULL(0x1)
47 #define MPIDR_AFFLVL2 ULL(0x2)
48 #define MPIDR_AFFLVL3 ULL(0x3)
101 #define ICC_PPI_DOMAINR_FIELD_MASK ULL(0x3)
191 #define ID_REG_FIELD_MASK ULL(0xf)
220 #define ID_AA64PFR0_AMU_MASK ULL(0xf)
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/rk3399_ARM-atf/include/lib/cpus/aarch64/
H A Dcortex_a72.h23 #define CORTEX_A72_ECTLR_SMP_BIT (ULL(1) << 6)
24 #define CORTEX_A72_ECTLR_DIS_TWD_ACC_PFTCH_BIT (ULL(1) << 38)
25 #define CORTEX_A72_ECTLR_L2_IPFTCH_DIST_MASK (ULL(0x3) << 35)
26 #define CORTEX_A72_ECTLR_L2_DPFTCH_DIST_MASK (ULL(0x3) << 32)
38 #define CORTEX_A72_CPUACTLR_EL1_DISABLE_L1_DCACHE_HW_PFTCH (ULL(1) << 56)
39 #define CORTEX_A72_CPUACTLR_EL1_DIS_LOAD_PASS_STORE (ULL(1) << 55)
40 #define CORTEX_A72_CPUACTLR_EL1_NO_ALLOC_WBWA (ULL(1) << 49)
41 #define CORTEX_A72_CPUACTLR_EL1_DCC_AS_DCCI (ULL(1) << 44)
42 #define CORTEX_A72_CPUACTLR_EL1_DIS_INSTR_PREFETCH (ULL(1) << 32)
43 #define CORTEX_A72_CPUACTLR_EL1_DELAY_EXCLUSIVE_SNOOP (ULL(1) << 31)
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H A Dneoverse_n2.h20 #define NEOVERSE_N2_CORE_PWRDN_EN_BIT (ULL(1) << 0)
26 #define NEOVERSE_N2_CPUECTLR_EL1_EXTLLC_BIT (ULL(1) << 0)
27 #define NEOVERSE_N2_CPUECTLR_EL1_PFSTIDIS_BIT (ULL(1) << 8)
28 #define NEOVERSE_N2_CPUECTLR_EL1_PFDIS_BIT (ULL(1) << 15)
34 #define NEOVERSE_N2_CPUACTLR_EL1_BIT_46 (ULL(1) << 46)
35 #define NEOVERSE_N2_CPUACTLR_EL1_BIT_22 (ULL(1) << 22)
41 #define NEOVERSE_N2_CPUACTLR2_EL1_BIT_0 (ULL(1) << 0)
42 #define NEOVERSE_N2_CPUACTLR2_EL1_BIT_2 (ULL(1) << 2)
43 #define NEOVERSE_N2_CPUACTLR2_EL1_BIT_36 (ULL(1) << 36)
44 #define NEOVERSE_N2_CPUACTLR2_EL1_BIT_40 (ULL(1) << 40)
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H A Dcortex_a57.h30 #define CORTEX_A57_ECTLR_SMP_BIT (ULL(1) << 6)
31 #define CORTEX_A57_ECTLR_DIS_TWD_ACC_PFTCH_BIT (ULL(1) << 38)
32 #define CORTEX_A57_ECTLR_L2_IPFTCH_DIST_MASK (ULL(0x3) << 35)
33 #define CORTEX_A57_ECTLR_L2_DPFTCH_DIST_MASK (ULL(0x3) << 32)
36 #define CORTEX_A57_ECTLR_CPU_RET_CTRL_MASK (ULL(0x7) << CORTEX_A57_ECTLR_CPU_RET_CTRL_SHIFT)
48 #define CORTEX_A57_CPUACTLR_EL1_DIS_LOAD_PASS_DMB (ULL(1) << 59)
49 #define CORTEX_A57_CPUACTLR_EL1_DIS_DMB_NULLIFICATION (ULL(1) << 58)
50 #define CORTEX_A57_CPUACTLR_EL1_DIS_LOAD_PASS_STORE (ULL(1) << 55)
51 #define CORTEX_A57_CPUACTLR_EL1_GRE_NGRE_AS_NGNRE (ULL(1) << 54)
52 #define CORTEX_A57_CPUACTLR_EL1_DIS_OVERREAD (ULL(1) << 52)
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H A Dneoverse_n1.h39 #define NEOVERSE_N1_WS_THR_L2_MASK (ULL(3) << 24)
40 #define NEOVERSE_N1_CPUECTLR_EL1_MM_TLBPF_DIS_BIT (ULL(1) << 51)
41 #define NEOVERSE_N1_CPUECTLR_EL1_EXTLLC_BIT (ULL(1) << 0)
48 #define NEOVERSE_N1_CPUACTLR_EL1_BIT_6 (ULL(1) << 6)
49 #define NEOVERSE_N1_CPUACTLR_EL1_BIT_13 (ULL(1) << 13)
53 #define NEOVERSE_N1_CPUACTLR2_EL1_BIT_0 (ULL(1) << 0)
54 #define NEOVERSE_N1_CPUACTLR2_EL1_BIT_2 (ULL(1) << 2)
55 #define NEOVERSE_N1_CPUACTLR2_EL1_BIT_11 (ULL(1) << 11)
56 #define NEOVERSE_N1_CPUACTLR2_EL1_BIT_15 (ULL(1) << 15)
57 #define NEOVERSE_N1_CPUACTLR2_EL1_BIT_16 (ULL(1) << 16)
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H A Drainier.h36 #define RAINIER_WS_THR_L2_MASK (ULL(3) << 24)
37 #define RAINIER_CPUECTLR_EL1_MM_TLBPF_DIS_BIT (ULL(1) << 51)
44 #define RAINIER_CPUACTLR_EL1_BIT_6 (ULL(1) << 6)
45 #define RAINIER_CPUACTLR_EL1_BIT_13 (ULL(1) << 13)
49 #define RAINIER_CPUACTLR2_EL1_BIT_0 (ULL(1) << 0)
50 #define RAINIER_CPUACTLR2_EL1_BIT_2 (ULL(1) << 2)
51 #define RAINIER_CPUACTLR2_EL1_BIT_11 (ULL(1) << 11)
52 #define RAINIER_CPUACTLR2_EL1_BIT_15 (ULL(1) << 15)
53 #define RAINIER_CPUACTLR2_EL1_BIT_16 (ULL(1) << 16)
54 #define RAINIER_CPUACTLR2_EL1_BIT_59 (ULL(1) << 59)
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H A Dneoverse_v1.h23 #define NEOVERSE_V1_CPUECTLR_EL1_BIT_8 (ULL(1) << 8)
24 #define NEOVERSE_V1_CPUECTLR_EL1_BIT_53 (ULL(1) << 53)
36 #define NEOVERSE_V1_ACTLR2_EL1_BIT_0 ULL(1)
37 #define NEOVERSE_V1_ACTLR2_EL1_BIT_2 (ULL(1) << 2)
38 #define NEOVERSE_V1_ACTLR2_EL1_BIT_28 (ULL(1) << 28)
39 #define NEOVERSE_V1_ACTLR2_EL1_BIT_40 (ULL(1) << 40)
42 #define NEOVERSE_V1_ACTLR3_EL1_BIT_47 (ULL(1) << 47)
45 #define NEOVERSE_V1_ACTLR5_EL1_BIT_55 (ULL(1) << 55)
46 #define NEOVERSE_V1_ACTLR5_EL1_BIT_56 (ULL(1) << 56)
47 #define NEOVERSE_V1_ACTLR5_EL1_BIT_61 (ULL(1) << 61)
H A Dcortex_a76.h24 #define CORTEX_A76_CPUECTLR_EL1_WS_THR_L2 (ULL(3) << 24)
25 #define CORTEX_A76_CPUECTLR_EL1_BIT_51 (ULL(1) << 51)
32 #define CORTEX_A76_CPUACTLR_EL1_DISABLE_STATIC_PREDICTION (ULL(1) << 6)
34 #define CORTEX_A76_CPUACTLR_EL1_BIT_13 (ULL(1) << 13)
38 #define CORTEX_A76_CPUACTLR2_EL1_BIT_2 (ULL(1) << 2)
39 #define CORTEX_A76_CPUACTLR2_EL1_BIT_59 (ULL(1) << 59)
41 #define CORTEX_A76_CPUACTLR2_EL1_DISABLE_LOAD_PASS_STORE (ULL(1) << 16)
45 #define CORTEX_A76_CPUACTLR3_EL1_BIT_10 (ULL(1) << 10)
H A Dcortex_a710.h19 #define CORTEX_A710_CPUECTLR_EL1_PFSTIDIS_BIT (ULL(1) << 8)
31 #define CORTEX_A710_CPUACTLR_EL1_BIT_46 (ULL(1) << 46)
32 #define CORTEX_A710_CPUACTLR_EL1_BIT_22 (ULL(1) << 22)
38 #define CORTEX_A710_CPUACTLR2_EL1_BIT_40 (ULL(1) << 40)
39 #define CORTEX_A710_CPUACTLR2_EL1_BIT_36 (ULL(1) << 36)
55 #define CORTEX_A710_CPUACTLR5_EL1_BIT_13 (ULL(1) << 13)
56 #define CORTEX_A710_CPUACTLR5_EL1_BIT_17 (ULL(1) << 17)
57 #define CORTEX_A710_CPUACTLR5_EL1_BIT_44 (ULL(1) << 44)
H A Dneoverse_v2.h19 #define NEOVERSE_V2_CPUECTLR_EL1_EXTLLC_BIT (ULL(1) << 0)
35 #define NEOVERSE_V2_CPUECTLR2_EL1_TXREQ_STATIC_FULL ULL(0)
48 #define NEOVERSE_V2_CPUACTLR2_EL1_BIT_0 (ULL(1) << 0)
54 #define NEOVERSE_V2_CPUACTLR3_EL1_BIT_47 (ULL(1) << 47)
60 #define NEOVERSE_V2_CPUACTLR5_EL1_BIT_56 (ULL(1) << 56)
61 #define NEOVERSE_V2_CPUACTLR5_EL1_BIT_55 (ULL(1) << 55)
72 #define NEOVERSE_V2_CPUACTLR_EL1_BIT_36 (ULL(1) << 36)
H A Dcortex_a53.h29 #define CORTEX_A53_ECTLR_SMP_BIT (ULL(1) << 6)
32 #define CORTEX_A53_ECTLR_CPU_RET_CTRL_MASK (ULL(0x7) << CORTEX_A53_ECTLR_CPU_RET_CTRL_SHIFT)
35 #define CORTEX_A53_ECTLR_FPU_RET_CTRL_MASK (ULL(0x7) << CORTEX_A53_ECTLR_FPU_RET_CTRL_SHIFT)
48 #define CORTEX_A53_CPUACTLR_EL1_ENDCCASCI (ULL(1) << CORTEX_A53_CPUACTLR_EL1_ENDCCASCI_SHIFT)
50 #define CORTEX_A53_CPUACTLR_EL1_RADIS (ULL(3) << CORTEX_A53_CPUACTLR_EL1_RADIS_SHIFT)
52 #define CORTEX_A53_CPUACTLR_EL1_L1RADIS (ULL(3) << CORTEX_A53_CPUACTLR_EL1_L1RADIS_SHIFT)
54 #define CORTEX_A53_CPUACTLR_EL1_DTAH (ULL(1) << CORTEX_A53_CPUACTLR_EL1_DTAH_SHIFT)
56 #define CORTEX_A53_CPUACTLR_EL1_L1PCTL (ULL(7) << CORTEX_A53_CPUACTLR_EL1_L1PCTL_SHIFT)
H A Dcortex_a78.h21 #define CORTEX_A78_CPUECTLR_EL1_BIT_8 (ULL(1) << 8)
32 #define CORTEX_A78_ACTLR_TAM_BIT (ULL(1) << 30)
35 #define CORTEX_A78_ACTLR2_EL1_BIT_0 (ULL(1) << 0)
36 #define CORTEX_A78_ACTLR2_EL1_BIT_1 (ULL(1) << 1)
37 #define CORTEX_A78_ACTLR2_EL1_BIT_2 (ULL(1) << 2)
38 #define CORTEX_A78_ACTLR2_EL1_BIT_40 (ULL(1) << 40)
/rk3399_ARM-atf/plat/rpi/rpi3/include/
H A Dplatform_def.h18 #define RPI3_BL31_PLAT_PARAM_VAL ULL(0x0F1E2D3C4B5A6978)
20 #define PLATFORM_STACK_SIZE ULL(0x1000)
67 #define SEC_ROM_BASE ULL(0x00000000)
68 #define SEC_ROM_SIZE ULL(0x00010000)
71 #define PLAT_RPI3_FIP_BASE ULL(0x00020000)
72 #define PLAT_RPI3_FIP_MAX_SIZE ULL(0x00010000)
75 #define SEC_SRAM_BASE ULL(0x00200000)
76 #define SEC_SRAM_SIZE ULL(0x00100000)
78 #define SEC_DRAM0_BASE ULL(0x00300000)
79 #define SEC_DRAM0_SIZE ULL(0x00100000)
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H A Drpi_hw.h16 #define RPI_IO_BASE ULL(0x3F000000)
17 #define RPI_IO_SIZE ULL(0x01000000)
22 #define RPI3_MBOX_OFFSET ULL(0x0000B880)
28 #define RPI3_IO_PM_OFFSET ULL(0x00100000)
34 #define RPI3_IO_RNG_OFFSET ULL(0x00104000)
42 #define RPI3_IO_MINI_UART_OFFSET ULL(0x00215040)
44 #define RPI3_IO_PL011_UART_OFFSET ULL(0x00201000)
46 #define RPI3_PL011_UART_CLOCK ULL(48000000)
51 #define RPI3_IO_GPIO_OFFSET ULL(0x00200000)
57 #define RPI3_IO_SDHOST_OFFSET ULL(0x00202000)
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/rk3399_ARM-atf/plat/rpi/rpi4/include/
H A Drpi_hw.h16 #define RPI_IO_BASE ULL(0xFC000000)
17 #define RPI_IO_SIZE ULL(0x04000000)
19 #define RPI_LEGACY_BASE (ULL(0x02000000) + RPI_IO_BASE)
24 #define RPI3_MBOX_OFFSET ULL(0x0000B880)
30 #define RPI3_IO_PM_OFFSET ULL(0x00100000)
36 #define RPI3_IO_RNG_OFFSET ULL(0x00104000)
44 #define RPI4_IO_MINI_UART_OFFSET ULL(0x00215040)
46 #define RPI4_IO_PL011_UART_OFFSET ULL(0x00201000)
48 #define RPI4_PL011_UART_CLOCK ULL(48000000)
53 #define RPI3_IO_GPIO_OFFSET ULL(0x00200000)
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H A Dplatform_def.h18 #define RPI3_BL31_PLAT_PARAM_VAL ULL(0x0F1E2D3C4B5A6978)
20 #define PLATFORM_STACK_SIZE ULL(0x1000)
82 #define PLAT_RPI3_TM_ENTRYPOINT_SIZE ULL(8)
87 #define PLAT_RPI3_TM_HOLD_ENTRY_SIZE ULL(8)
94 #define PLAT_RPI3_TM_HOLD_STATE_WAIT ULL(0)
95 #define PLAT_RPI3_TM_HOLD_STATE_GO ULL(1)
96 #define PLAT_RPI3_TM_HOLD_STATE_BSP_OFF ULL(2)
104 #define PLAT_MAX_BL31_SIZE ULL(0x80000)
106 #define BL31_BASE ULL(0x1000)
107 #define BL31_LIMIT ULL(0x80000)
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/rk3399_ARM-atf/plat/rpi/rpi5/include/
H A Drpi_hw.h17 #define RPI_IO_BASE ULL(0x1000000000)
18 #define RPI_IO_SIZE ULL(0x1000000000)
23 #define RPI3_MBOX_BASE (RPI_IO_BASE + ULL(0x7c013880))
28 #define RPI3_PM_BASE (RPI_IO_BASE + ULL(0x7d200000))
33 #define RPI3_RNG_BASE (RPI_IO_BASE + ULL(0x7d208000))
38 #define RPI4_PL011_UART_BASE (RPI_IO_BASE + ULL(0x7d001000))
39 #define RPI4_PL011_UART_CLOCK ULL(44000000)
45 #define RPI4_GIC_GICD_BASE (RPI_IO_BASE + ULL(0x7fff9000))
46 #define RPI4_GIC_GICC_BASE (RPI_IO_BASE + ULL(0x7fffa000))
48 #define RPI4_LOCAL_CONTROL_BASE_ADDRESS (RPI_IO_BASE + ULL(0x7c280000))
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H A Dplatform_def.h19 #define RPI3_BL31_PLAT_PARAM_VAL ULL(0x0F1E2D3C4B5A6978)
21 #define PLATFORM_STACK_SIZE ULL(0x1000)
83 #define PLAT_RPI3_TM_ENTRYPOINT_SIZE ULL(8)
88 #define PLAT_RPI3_TM_HOLD_ENTRY_SIZE ULL(8)
95 #define PLAT_RPI3_TM_HOLD_STATE_WAIT ULL(0)
96 #define PLAT_RPI3_TM_HOLD_STATE_GO ULL(1)
97 #define PLAT_RPI3_TM_HOLD_STATE_BSP_OFF ULL(2)
105 #define PLAT_MAX_BL31_SIZE ULL(0x80000)
107 #define BL31_BASE ULL(0x1000)
108 #define BL31_LIMIT ULL(0x80000)
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/rk3399_ARM-atf/include/lib/cpus/aarch32/
H A Dcortex_a57.h29 #define CORTEX_A57_ECTLR_SMP_BIT (ULL(1) << 6)
30 #define CORTEX_A57_ECTLR_DIS_TWD_ACC_PFTCH_BIT (ULL(1) << 38)
31 #define CORTEX_A57_ECTLR_L2_IPFTCH_DIST_MASK (ULL(0x3) << 35)
32 #define CORTEX_A57_ECTLR_L2_DPFTCH_DIST_MASK (ULL(0x3) << 32)
35 #define CORTEX_A57_ECTLR_CPU_RET_CTRL_MASK (ULL(0x7) << CORTEX_A57_ECTLR_CPU_RET_CTRL_SHIFT)
47 #define CORTEX_A57_CPUACTLR_DIS_LOAD_PASS_DMB (ULL(1) << 59)
48 #define CORTEX_A57_CPUACTLR_DIS_DMB_NULLIFICATION (ULL(1) << 58)
49 #define CORTEX_A57_CPUACTLR_DIS_LOAD_PASS_STORE (ULL(1) << 55)
50 #define CORTEX_A57_CPUACTLR_GRE_NGRE_AS_NGNRE (ULL(1) << 54)
51 #define CORTEX_A57_CPUACTLR_DIS_OVERREAD (ULL(1) << 52)
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H A Dcortex_a72.h20 #define CORTEX_A72_ECTLR_SMP_BIT (ULL(1) << 6)
21 #define CORTEX_A72_ECTLR_DIS_TWD_ACC_PFTCH_BIT (ULL(1) << 38)
22 #define CORTEX_A72_ECTLR_L2_IPFTCH_DIST_MASK (ULL(0x3) << 35)
23 #define CORTEX_A72_ECTLR_L2_DPFTCH_DIST_MASK (ULL(0x3) << 32)
35 #define CORTEX_A72_CPUACTLR_DISABLE_L1_DCACHE_HW_PFTCH (ULL(1) << 56)
36 #define CORTEX_A72_CPUACTLR_DIS_LOAD_PASS_STORE (ULL(1) << 55)
37 #define CORTEX_A72_CPUACTLR_NO_ALLOC_WBWA (ULL(1) << 49)
38 #define CORTEX_A72_CPUACTLR_DCC_AS_DCCI (ULL(1) << 44)
39 #define CORTEX_A72_CPUACTLR_DIS_INSTR_PREFETCH (ULL(1) << 32)
40 #define CORTEX_A72_CPUACTLR_DELAY_EXCLUSIVE_SNOOP (ULL(1) << 31)
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/rk3399_ARM-atf/include/services/
H A Ddrtm_svc.h74 #define ARM_DRTM_FUNC_MASK ULL(0x1)
77 #define ARM_DRTM_FEAT_ID_MASK ULL(0xff)
84 #define ARM_DRTM_TPM_FEATURES_PCR_SCHEMA_MASK ULL(0xF)
85 #define ARM_DRTM_TPM_FEATURES_PCR_SCHEMA_DEFAULT ULL(0x1)
88 #define ARM_DRTM_TPM_FEATURES_TPM_HASH_MASK ULL(0x1)
89 #define ARM_DRTM_TPM_FEATURES_TPM_HASH_NOT_SUPPORTED ULL(0x0)
90 #define ARM_DRTM_TPM_FEATURES_TPM_HASH_SUPPORTED ULL(0x1)
93 #define ARM_DRTM_TPM_FEATURES_FW_HASH_MASK ULL(0xFFFF)
94 #define ARM_DRTM_TPM_FEATURES_FW_HASH_SHA256 ULL(0xB)
95 #define ARM_DRTM_TPM_FEATURES_FW_HASH_SHA384 ULL(0xC)
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/rk3399_ARM-atf/include/drivers/rpi3/mailbox/
H A Drpi3_mbox.h20 #define RPI3_MBOX0_READ_OFFSET ULL(0x00000000)
21 #define RPI3_MBOX0_PEEK_OFFSET ULL(0x00000010)
22 #define RPI3_MBOX0_SENDER_OFFSET ULL(0x00000014)
23 #define RPI3_MBOX0_STATUS_OFFSET ULL(0x00000018)
24 #define RPI3_MBOX0_CONFIG_OFFSET ULL(0x0000001C)
26 #define RPI3_MBOX1_WRITE_OFFSET ULL(0x00000020)
27 #define RPI3_MBOX1_PEEK_OFFSET ULL(0x00000030)
28 #define RPI3_MBOX1_SENDER_OFFSET ULL(0x00000034)
29 #define RPI3_MBOX1_STATUS_OFFSET ULL(0x00000038)
30 #define RPI3_MBOX1_CONFIG_OFFSET ULL(0x0000003C)
/rk3399_ARM-atf/include/lib/xlat_tables/
H A Dxlat_tables_defs.h52 #define XN (ULL(1) << 2)
54 #define UXN (ULL(1) << 2)
55 #define PXN (ULL(1) << 1)
56 #define CONT_HINT (ULL(1) << 0)
57 #define UPPER_ATTRS(x) (((x) & ULL(0x7)) << 52)
66 #define GP (ULL(1) << 50)
68 #define TABLE_ADDR_MASK ULL(0x0000FFFFFFFFF000)
114 (((virtual_addr) >> XLAT_ADDR_SHIFT(level)) & ULL(0x1FF))
125 #define AP2_RO ULL(0x1)
126 #define AP2_RW ULL(0x0)
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/rk3399_ARM-atf/plat/arm/board/fvp/
H A Dfvp_drtm_stub.c19 return 0ULL; in plat_drtm_get_min_size_normal_world_dce()
24 return 0ULL; in plat_drtm_get_imp_def_dlme_region_size()
29 return 0ULL; in plat_drtm_get_tcb_hash_features()
34 return 0ULL; in plat_drtm_get_tcb_hash_table_size()
39 return 0ULL; in plat_drtm_get_acpi_tables_region_size()
44 return 0ULL; in plat_drtm_get_dlme_img_auth_features()
/rk3399_ARM-atf/include/bl32/payloads/
H A Dtlk.h39 #define TLK_REQUEST_DONE (0x32000001 | (ULL(1) << 31))
40 #define TLK_PREEMPTED (0x32000002 | (ULL(1) << 31))
41 #define TLK_ENTRY_DONE (0x32000003 | (ULL(1) << 31))
42 #define TLK_VA_TRANSLATE (0x32000004 | (ULL(1) << 31))
43 #define TLK_SUSPEND_DONE (0x32000005 | (ULL(1) << 31))
44 #define TLK_RESUME_DONE (0x32000006 | (ULL(1) << 31))
45 #define TLK_IRQ_DONE (0x32000008 | (ULL(1) << 31))

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