1b04ea14bSJohn Tsichritzis /* 2*4c700c15SGovindraj Raja * Copyright (c) 2017-2022, Arm Limited and Contributors. All rights reserved. 3b04ea14bSJohn Tsichritzis * 4b04ea14bSJohn Tsichritzis * SPDX-License-Identifier: BSD-3-Clause 5b04ea14bSJohn Tsichritzis */ 6b04ea14bSJohn Tsichritzis 7da6d75a0SJohn Tsichritzis #ifndef NEOVERSE_N1_H 8da6d75a0SJohn Tsichritzis #define NEOVERSE_N1_H 9b04ea14bSJohn Tsichritzis 10b04ea14bSJohn Tsichritzis #include <lib/utils_def.h> 11b04ea14bSJohn Tsichritzis 12da6d75a0SJohn Tsichritzis /* Neoverse N1 MIDR for revision 0 */ 13da6d75a0SJohn Tsichritzis #define NEOVERSE_N1_MIDR U(0x410fd0c0) 14b04ea14bSJohn Tsichritzis 151fe4a9d1SBipin Ravi /* Neoverse N1 loop count for CVE-2022-23960 mitigation */ 161fe4a9d1SBipin Ravi #define NEOVERSE_N1_BHB_LOOP_COUNT U(24) 171fe4a9d1SBipin Ravi 1880942622Slaurenw-arm /* Exception Syndrome register EC code for IC Trap */ 1980942622Slaurenw-arm #define NEOVERSE_N1_EC_IC_TRAP U(0x1f) 2080942622Slaurenw-arm 21b04ea14bSJohn Tsichritzis /******************************************************************************* 22632ab3ebSLouis Mayencourt * CPU Power Control register specific definitions. 23b04ea14bSJohn Tsichritzis ******************************************************************************/ 24da6d75a0SJohn Tsichritzis #define NEOVERSE_N1_CPUPWRCTLR_EL1 S3_0_C15_C2_7 25b04ea14bSJohn Tsichritzis 26da6d75a0SJohn Tsichritzis /* Definitions of register field mask in NEOVERSE_N1_CPUPWRCTLR_EL1 */ 27da6d75a0SJohn Tsichritzis #define NEOVERSE_N1_CORE_PWRDN_EN_MASK U(0x1) 28b04ea14bSJohn Tsichritzis 29da6d75a0SJohn Tsichritzis #define NEOVERSE_N1_ACTLR_AMEN_BIT (U(1) << 4) 30b04ea14bSJohn Tsichritzis 31da6d75a0SJohn Tsichritzis #define NEOVERSE_N1_AMU_NR_COUNTERS U(5) 32da6d75a0SJohn Tsichritzis #define NEOVERSE_N1_AMU_GROUP0_MASK U(0x1f) 33b04ea14bSJohn Tsichritzis 34632ab3ebSLouis Mayencourt /******************************************************************************* 35632ab3ebSLouis Mayencourt * CPU Extended Control register specific definitions. 36632ab3ebSLouis Mayencourt ******************************************************************************/ 37632ab3ebSLouis Mayencourt #define NEOVERSE_N1_CPUECTLR_EL1 S3_0_C15_C1_4 38632ab3ebSLouis Mayencourt 399eceb020Slauwal01 #define NEOVERSE_N1_WS_THR_L2_MASK (ULL(3) << 24) 4011c48370Slauwal01 #define NEOVERSE_N1_CPUECTLR_EL1_MM_TLBPF_DIS_BIT (ULL(1) << 51) 41f2d6b4eeSManish Pandey #define NEOVERSE_N1_CPUECTLR_EL1_EXTLLC_BIT (ULL(1) << 0) 429eceb020Slauwal01 43632ab3ebSLouis Mayencourt /******************************************************************************* 44632ab3ebSLouis Mayencourt * CPU Auxiliary Control register specific definitions. 45632ab3ebSLouis Mayencourt ******************************************************************************/ 46a601afe1Slauwal01 #define NEOVERSE_N1_CPUACTLR_EL1 S3_0_C15_C1_0 47a601afe1Slauwal01 48a601afe1Slauwal01 #define NEOVERSE_N1_CPUACTLR_EL1_BIT_6 (ULL(1) << 6) 49411f4959Slauwal01 #define NEOVERSE_N1_CPUACTLR_EL1_BIT_13 (ULL(1) << 13) 50a601afe1Slauwal01 51632ab3ebSLouis Mayencourt #define NEOVERSE_N1_CPUACTLR2_EL1 S3_0_C15_C1_1 52632ab3ebSLouis Mayencourt 532017ab24Slauwal01 #define NEOVERSE_N1_CPUACTLR2_EL1_BIT_0 (ULL(1) << 0) 54632ab3ebSLouis Mayencourt #define NEOVERSE_N1_CPUACTLR2_EL1_BIT_2 (ULL(1) << 2) 55ef5fa7d4Slauwal01 #define NEOVERSE_N1_CPUACTLR2_EL1_BIT_11 (ULL(1) << 11) 562017ab24Slauwal01 #define NEOVERSE_N1_CPUACTLR2_EL1_BIT_15 (ULL(1) << 15) 575f5d0763SAndre Przywara #define NEOVERSE_N1_CPUACTLR2_EL1_BIT_16 (ULL(1) << 16) 58e34606f2Slauwal01 #define NEOVERSE_N1_CPUACTLR2_EL1_BIT_59 (ULL(1) << 59) 59e34606f2Slauwal01 60335b3c79Slauwal01 #define NEOVERSE_N1_CPUACTLR3_EL1 S3_0_C15_C1_2 61335b3c79Slauwal01 62335b3c79Slauwal01 #define NEOVERSE_N1_CPUACTLR3_EL1_BIT_10 (ULL(1) << 10) 63632ab3ebSLouis Mayencourt 64b04ea14bSJohn Tsichritzis /* Instruction patching registers */ 65b04ea14bSJohn Tsichritzis #define CPUPSELR_EL3 S3_6_C15_C8_0 66b04ea14bSJohn Tsichritzis #define CPUPCR_EL3 S3_6_C15_C8_1 67b04ea14bSJohn Tsichritzis #define CPUPOR_EL3 S3_6_C15_C8_2 68b04ea14bSJohn Tsichritzis #define CPUPMR_EL3 S3_6_C15_C8_3 69b04ea14bSJohn Tsichritzis 70da6d75a0SJohn Tsichritzis #endif /* NEOVERSE_N1_H */ 71