12b357c31SManoj Kumar /* 22b357c31SManoj Kumar * Copyright (c) 2020, Arm Limited. All rights reserved. 32b357c31SManoj Kumar * 42b357c31SManoj Kumar * SPDX-License-Identifier: BSD-3-Clause 52b357c31SManoj Kumar */ 62b357c31SManoj Kumar 72b357c31SManoj Kumar #ifndef RAINIER_H 82b357c31SManoj Kumar #define RAINIER_H 92b357c31SManoj Kumar 102b357c31SManoj Kumar #include <lib/utils_def.h> 112b357c31SManoj Kumar 122b357c31SManoj Kumar /* RAINIER MIDR for revision 0 */ 13*3e0a861eSJagadeesh Ujja #define RAINIER_MIDR U(0x3f0f4120) 142b357c31SManoj Kumar 152b357c31SManoj Kumar /* Exception Syndrome register EC code for IC Trap */ 162b357c31SManoj Kumar #define RAINIER_EC_IC_TRAP U(0x1f) 172b357c31SManoj Kumar 182b357c31SManoj Kumar /******************************************************************************* 192b357c31SManoj Kumar * CPU Power Control register specific definitions. 202b357c31SManoj Kumar ******************************************************************************/ 212b357c31SManoj Kumar #define RAINIER_CPUPWRCTLR_EL1 S3_0_C15_C2_7 222b357c31SManoj Kumar 232b357c31SManoj Kumar /* Definitions of register field mask in RAINIER_CPUPWRCTLR_EL1 */ 242b357c31SManoj Kumar #define RAINIER_CORE_PWRDN_EN_MASK U(0x1) 252b357c31SManoj Kumar 262b357c31SManoj Kumar #define RAINIER_ACTLR_AMEN_BIT (U(1) << 4) 272b357c31SManoj Kumar 282b357c31SManoj Kumar #define RAINIER_AMU_NR_COUNTERS U(5) 292b357c31SManoj Kumar #define RAINIER_AMU_GROUP0_MASK U(0x1f) 302b357c31SManoj Kumar 312b357c31SManoj Kumar /******************************************************************************* 322b357c31SManoj Kumar * CPU Extended Control register specific definitions. 332b357c31SManoj Kumar ******************************************************************************/ 342b357c31SManoj Kumar #define RAINIER_CPUECTLR_EL1 S3_0_C15_C1_4 352b357c31SManoj Kumar 362b357c31SManoj Kumar #define RAINIER_WS_THR_L2_MASK (ULL(3) << 24) 372b357c31SManoj Kumar #define RAINIER_CPUECTLR_EL1_MM_TLBPF_DIS_BIT (ULL(1) << 51) 382b357c31SManoj Kumar 392b357c31SManoj Kumar /******************************************************************************* 402b357c31SManoj Kumar * CPU Auxiliary Control register specific definitions. 412b357c31SManoj Kumar ******************************************************************************/ 422b357c31SManoj Kumar #define RAINIER_CPUACTLR_EL1 S3_0_C15_C1_0 432b357c31SManoj Kumar 442b357c31SManoj Kumar #define RAINIER_CPUACTLR_EL1_BIT_6 (ULL(1) << 6) 452b357c31SManoj Kumar #define RAINIER_CPUACTLR_EL1_BIT_13 (ULL(1) << 13) 462b357c31SManoj Kumar 472b357c31SManoj Kumar #define RAINIER_CPUACTLR2_EL1 S3_0_C15_C1_1 482b357c31SManoj Kumar 492b357c31SManoj Kumar #define RAINIER_CPUACTLR2_EL1_BIT_0 (ULL(1) << 0) 502b357c31SManoj Kumar #define RAINIER_CPUACTLR2_EL1_BIT_2 (ULL(1) << 2) 512b357c31SManoj Kumar #define RAINIER_CPUACTLR2_EL1_BIT_11 (ULL(1) << 11) 522b357c31SManoj Kumar #define RAINIER_CPUACTLR2_EL1_BIT_15 (ULL(1) << 15) 532b357c31SManoj Kumar #define RAINIER_CPUACTLR2_EL1_BIT_16 (ULL(1) << 16) 542b357c31SManoj Kumar #define RAINIER_CPUACTLR2_EL1_BIT_59 (ULL(1) << 59) 552b357c31SManoj Kumar 562b357c31SManoj Kumar #define RAINIER_CPUACTLR3_EL1 S3_0_C15_C1_2 572b357c31SManoj Kumar 582b357c31SManoj Kumar #define RAINIER_CPUACTLR3_EL1_BIT_10 (ULL(1) << 10) 592b357c31SManoj Kumar 602b357c31SManoj Kumar /* Instruction patching registers */ 612b357c31SManoj Kumar #define CPUPSELR_EL3 S3_6_C15_C8_0 622b357c31SManoj Kumar #define CPUPCR_EL3 S3_6_C15_C8_1 632b357c31SManoj Kumar #define CPUPOR_EL3 S3_6_C15_C8_2 642b357c31SManoj Kumar #define CPUPMR_EL3 S3_6_C15_C8_3 652b357c31SManoj Kumar 662b357c31SManoj Kumar #endif /* RAINIER_H */ 67