1dc787588SYatharth Kochar /* 2*4c700c15SGovindraj Raja * Copyright (c) 2017-2019, Arm Limited and Contributors. All rights reserved. 3dc787588SYatharth Kochar * 482cb2c1aSdp-arm * SPDX-License-Identifier: BSD-3-Clause 5dc787588SYatharth Kochar */ 6dc787588SYatharth Kochar 7c3cf06f1SAntonio Nino Diaz #ifndef CORTEX_A72_H 8c3cf06f1SAntonio Nino Diaz #define CORTEX_A72_H 909d40e0eSAntonio Nino Diaz 1009d40e0eSAntonio Nino Diaz #include <lib/utils_def.h> 11dc787588SYatharth Kochar 12dc787588SYatharth Kochar /* Cortex-A72 midr for revision 0 */ 131a74e4a8SAntonio Nino Diaz #define CORTEX_A72_MIDR U(0x410FD080) 14dc787588SYatharth Kochar 15dc787588SYatharth Kochar /******************************************************************************* 16dc787588SYatharth Kochar * CPU Extended Control register specific definitions. 17dc787588SYatharth Kochar ******************************************************************************/ 18fb7d32e5SVarun Wadekar #define CORTEX_A72_ECTLR p15, 1, c15 19dc787588SYatharth Kochar 20e4e6c4beSEleanor Bonnici #define CORTEX_A72_ECTLR_SMP_BIT (ULL(1) << 6) 21e4e6c4beSEleanor Bonnici #define CORTEX_A72_ECTLR_DIS_TWD_ACC_PFTCH_BIT (ULL(1) << 38) 22e4e6c4beSEleanor Bonnici #define CORTEX_A72_ECTLR_L2_IPFTCH_DIST_MASK (ULL(0x3) << 35) 23e4e6c4beSEleanor Bonnici #define CORTEX_A72_ECTLR_L2_DPFTCH_DIST_MASK (ULL(0x3) << 32) 24dc787588SYatharth Kochar 25dc787588SYatharth Kochar /******************************************************************************* 26dc787588SYatharth Kochar * CPU Memory Error Syndrome register specific definitions. 27dc787588SYatharth Kochar ******************************************************************************/ 28fb7d32e5SVarun Wadekar #define CORTEX_A72_MERRSR p15, 2, c15 29dc787588SYatharth Kochar 30dc787588SYatharth Kochar /******************************************************************************* 31dc787588SYatharth Kochar * CPU Auxiliary Control register specific definitions. 32dc787588SYatharth Kochar ******************************************************************************/ 3380bcf981SEleanor Bonnici #define CORTEX_A72_CPUACTLR p15, 0, c15 34dc787588SYatharth Kochar 3580bcf981SEleanor Bonnici #define CORTEX_A72_CPUACTLR_DISABLE_L1_DCACHE_HW_PFTCH (ULL(1) << 56) 36e0865708SDimitris Papastamos #define CORTEX_A72_CPUACTLR_DIS_LOAD_PASS_STORE (ULL(1) << 55) 3780bcf981SEleanor Bonnici #define CORTEX_A72_CPUACTLR_NO_ALLOC_WBWA (ULL(1) << 49) 3880bcf981SEleanor Bonnici #define CORTEX_A72_CPUACTLR_DCC_AS_DCCI (ULL(1) << 44) 396de9b336SEleanor Bonnici #define CORTEX_A72_CPUACTLR_DIS_INSTR_PREFETCH (ULL(1) << 32) 405668db72SAndrew Davis #define CORTEX_A72_CPUACTLR_DELAY_EXCLUSIVE_SNOOP (ULL(1) << 31) 41dc787588SYatharth Kochar 42dc787588SYatharth Kochar /******************************************************************************* 43dc787588SYatharth Kochar * L2 Control register specific definitions. 44dc787588SYatharth Kochar ******************************************************************************/ 45f9688f27SDimitris Papastamos #define CORTEX_A72_L2CTLR p15, 1, c9, c0, 2 46dc787588SYatharth Kochar 4781858a35SAndrew Davis #define CORTEX_A72_L2CTLR_EL1_ECC_AND_PARITY_ENABLE (ULL(1) << 21) 4881858a35SAndrew Davis #define CORTEX_A72_L2CTLR_EL1_DATA_INLINE_ECC_ENABLE (ULL(1) << 20) 4981858a35SAndrew Davis 501a74e4a8SAntonio Nino Diaz #define CORTEX_A72_L2CTLR_DATA_RAM_LATENCY_SHIFT U(0) 511a74e4a8SAntonio Nino Diaz #define CORTEX_A72_L2CTLR_TAG_RAM_LATENCY_SHIFT U(6) 52dc787588SYatharth Kochar 531a74e4a8SAntonio Nino Diaz #define CORTEX_A72_L2_DATA_RAM_LATENCY_3_CYCLES U(0x2) 54aee2f33aSAndrew Davis #define CORTEX_A72_L2_DATA_RAM_LATENCY_4_CYCLES U(0x3) 551a74e4a8SAntonio Nino Diaz #define CORTEX_A72_L2_TAG_RAM_LATENCY_2_CYCLES U(0x1) 561a74e4a8SAntonio Nino Diaz #define CORTEX_A72_L2_TAG_RAM_LATENCY_3_CYCLES U(0x2) 57dc787588SYatharth Kochar 58dc787588SYatharth Kochar /******************************************************************************* 59dc787588SYatharth Kochar * L2 Memory Error Syndrome register specific definitions. 60dc787588SYatharth Kochar ******************************************************************************/ 61fb7d32e5SVarun Wadekar #define CORTEX_A72_L2MERRSR p15, 3, c15 62dc787588SYatharth Kochar 63c3cf06f1SAntonio Nino Diaz #endif /* CORTEX_A72_H */ 64