1467937b6SJimmy Brisson /* 2*ac9f4b4dSGovindraj Raja * Copyright (c) 2019-2025, Arm Limited. All rights reserved. 3467937b6SJimmy Brisson * 4467937b6SJimmy Brisson * SPDX-License-Identifier: BSD-3-Clause 5467937b6SJimmy Brisson */ 6467937b6SJimmy Brisson 7467937b6SJimmy Brisson #ifndef NEOVERSE_V1_H 8467937b6SJimmy Brisson #define NEOVERSE_V1_H 9467937b6SJimmy Brisson 10467937b6SJimmy Brisson #define NEOVERSE_V1_MIDR U(0x410FD400) 11467937b6SJimmy Brisson 121fe4a9d1SBipin Ravi /* Neoverse V1 loop count for CVE-2022-23960 mitigation */ 131fe4a9d1SBipin Ravi #define NEOVERSE_V1_BHB_LOOP_COUNT U(32) 141fe4a9d1SBipin Ravi 15467937b6SJimmy Brisson /******************************************************************************* 16467937b6SJimmy Brisson * CPU Extended Control register specific definitions. 17467937b6SJimmy Brisson ******************************************************************************/ 18467937b6SJimmy Brisson #define NEOVERSE_V1_CPUECTLR_EL1 S3_0_C15_C1_4 1914a6fed5SJuan Pablo Conde #define NEOVERSE_V1_CPUPSELR_EL3 S3_6_C15_C8_0 2014a6fed5SJuan Pablo Conde #define NEOVERSE_V1_CPUPOR_EL3 S3_6_C15_C8_2 2114a6fed5SJuan Pablo Conde #define NEOVERSE_V1_CPUPMR_EL3 S3_6_C15_C8_3 2214a6fed5SJuan Pablo Conde #define NEOVERSE_V1_CPUPCR_EL3 S3_6_C15_C8_1 23741dd04cSlaurenw-arm #define NEOVERSE_V1_CPUECTLR_EL1_BIT_8 (ULL(1) << 8) 244789cf66Slaurenw-arm #define NEOVERSE_V1_CPUECTLR_EL1_BIT_53 (ULL(1) << 53) 25467937b6SJimmy Brisson 26467937b6SJimmy Brisson /******************************************************************************* 27467937b6SJimmy Brisson * CPU Power Control register specific definitions 28467937b6SJimmy Brisson ******************************************************************************/ 29467937b6SJimmy Brisson #define NEOVERSE_V1_CPUPWRCTLR_EL1 S3_0_C15_C2_7 30467937b6SJimmy Brisson #define NEOVERSE_V1_CPUPWRCTLR_EL1_CORE_PWRDN_BIT U(1) 31467937b6SJimmy Brisson 3233e3e925Sjohpow01 /******************************************************************************* 3333e3e925Sjohpow01 * CPU Auxiliary Control register specific definitions. 3433e3e925Sjohpow01 ******************************************************************************/ 3533e3e925Sjohpow01 #define NEOVERSE_V1_ACTLR2_EL1 S3_0_C15_C1_1 3639eb5ddbSBipin Ravi #define NEOVERSE_V1_ACTLR2_EL1_BIT_0 ULL(1) 3733e3e925Sjohpow01 #define NEOVERSE_V1_ACTLR2_EL1_BIT_2 (ULL(1) << 2) 38143b1965Slaurenw-arm #define NEOVERSE_V1_ACTLR2_EL1_BIT_28 (ULL(1) << 28) 3957b73d55SBipin Ravi #define NEOVERSE_V1_ACTLR2_EL1_BIT_40 (ULL(1) << 40) 4033e3e925Sjohpow01 412757da06SSona Mathew #define NEOVERSE_V1_ACTLR3_EL1 S3_0_C15_C1_2 42f6af2185SArvind Ram Prakash #define NEOVERSE_V1_ACTLR3_EL1_BIT_47 (ULL(1) << 47) 432757da06SSona Mathew 44f1c3eae9SSona Mathew #define NEOVERSE_V1_ACTLR5_EL1 S3_0_C15_C9_0 45f6af2185SArvind Ram Prakash #define NEOVERSE_V1_ACTLR5_EL1_BIT_55 (ULL(1) << 55) 46f6af2185SArvind Ram Prakash #define NEOVERSE_V1_ACTLR5_EL1_BIT_56 (ULL(1) << 56) 4771ed9173SSona Mathew #define NEOVERSE_V1_ACTLR5_EL1_BIT_61 (ULL(1) << 61) 48f1c3eae9SSona Mathew 49467937b6SJimmy Brisson #endif /* NEOVERSE_V1_H */ 50