1c6ac4df6Sjohpow01 /* 2463b5b4aSGovindraj Raja * Copyright (c) 2021-2025, Arm Limited. All rights reserved. 3c6ac4df6Sjohpow01 * 4c6ac4df6Sjohpow01 * SPDX-License-Identifier: BSD-3-Clause 5c6ac4df6Sjohpow01 */ 6c6ac4df6Sjohpow01 7c6ac4df6Sjohpow01 #ifndef CORTEX_A710_H 8c6ac4df6Sjohpow01 #define CORTEX_A710_H 9c6ac4df6Sjohpow01 10c6ac4df6Sjohpow01 #define CORTEX_A710_MIDR U(0x410FD470) 11c6ac4df6Sjohpow01 121fe4a9d1SBipin Ravi /* Cortex-A710 loop count for CVE-2022-23960 mitigation */ 131fe4a9d1SBipin Ravi #define CORTEX_A710_BHB_LOOP_COUNT U(32) 141fe4a9d1SBipin Ravi 15c6ac4df6Sjohpow01 /******************************************************************************* 16c6ac4df6Sjohpow01 * CPU Extended Control register specific definitions 17c6ac4df6Sjohpow01 ******************************************************************************/ 18c6ac4df6Sjohpow01 #define CORTEX_A710_CPUECTLR_EL1 S3_0_C15_C1_4 19afc2ed63SBipin Ravi #define CORTEX_A710_CPUECTLR_EL1_PFSTIDIS_BIT (ULL(1) << 8) 20c6ac4df6Sjohpow01 21c6ac4df6Sjohpow01 /******************************************************************************* 22c6ac4df6Sjohpow01 * CPU Power Control register specific definitions 23c6ac4df6Sjohpow01 ******************************************************************************/ 24c6ac4df6Sjohpow01 #define CORTEX_A710_CPUPWRCTLR_EL1 S3_0_C15_C2_7 25c6ac4df6Sjohpow01 #define CORTEX_A710_CPUPWRCTLR_EL1_CORE_PWRDN_BIT U(1) 26c6ac4df6Sjohpow01 27213afde9SBipin Ravi /******************************************************************************* 28213afde9SBipin Ravi * CPU Auxiliary Control register specific definitions. 29213afde9SBipin Ravi ******************************************************************************/ 30213afde9SBipin Ravi #define CORTEX_A710_CPUACTLR_EL1 S3_0_C15_C1_0 31213afde9SBipin Ravi #define CORTEX_A710_CPUACTLR_EL1_BIT_46 (ULL(1) << 46) 32cfe1a8f7SBipin Ravi #define CORTEX_A710_CPUACTLR_EL1_BIT_22 (ULL(1) << 22) 3395fe195dSnayanpatel-arm 3495fe195dSnayanpatel-arm /******************************************************************************* 35ef934cd1Sjohpow01 * CPU Auxiliary Control register 2 specific definitions. 36ef934cd1Sjohpow01 ******************************************************************************/ 37ef934cd1Sjohpow01 #define CORTEX_A710_CPUACTLR2_EL1 S3_0_C15_C1_1 383220f05eSBipin Ravi #define CORTEX_A710_CPUACTLR2_EL1_BIT_40 (ULL(1) << 40) 39888eafa0SBoyan Karatotev #define CORTEX_A710_CPUACTLR2_EL1_BIT_36 (ULL(1) << 36) 40ef934cd1Sjohpow01 41ef934cd1Sjohpow01 /******************************************************************************* 42c9508d6aSSona Mathew * CPU Auxiliary Control register 3 specific definitions. 43c9508d6aSSona Mathew ******************************************************************************/ 44c9508d6aSSona Mathew #define CORTEX_A710_CPUACTLR3_EL1 S3_0_C15_C1_2 45c9508d6aSSona Mathew 46c9508d6aSSona Mathew /******************************************************************************* 47*4467348bSJohn Powell * CPU Auxiliary Control register 4 specific definitions. 48*4467348bSJohn Powell ******************************************************************************/ 49*4467348bSJohn Powell #define CORTEX_A710_CPUACTLR4_EL1 S3_0_C15_C1_3 50*4467348bSJohn Powell 51*4467348bSJohn Powell /******************************************************************************* 52ef934cd1Sjohpow01 * CPU Auxiliary Control register 5 specific definitions. 5395fe195dSnayanpatel-arm ******************************************************************************/ 5495fe195dSnayanpatel-arm #define CORTEX_A710_CPUACTLR5_EL1 S3_0_C15_C8_0 5595fe195dSnayanpatel-arm #define CORTEX_A710_CPUACTLR5_EL1_BIT_13 (ULL(1) << 13) 56b781fcf1SJayanth Dodderi Chidanand #define CORTEX_A710_CPUACTLR5_EL1_BIT_17 (ULL(1) << 17) 578a855bd2SBipin Ravi #define CORTEX_A710_CPUACTLR5_EL1_BIT_44 (ULL(1) << 44) 58744bdbf7Snayanpatel-arm 59744bdbf7Snayanpatel-arm /******************************************************************************* 60b781fcf1SJayanth Dodderi Chidanand * CPU Selected Instruction Private register specific definitions. 61b781fcf1SJayanth Dodderi Chidanand ******************************************************************************/ 62b781fcf1SJayanth Dodderi Chidanand #define CORTEX_A710_CPUPSELR_EL3 S3_6_C15_C8_0 63b781fcf1SJayanth Dodderi Chidanand #define CORTEX_A710_CPUPCR_EL3 S3_6_C15_C8_1 64b781fcf1SJayanth Dodderi Chidanand #define CORTEX_A710_CPUPOR_EL3 S3_6_C15_C8_2 65b781fcf1SJayanth Dodderi Chidanand #define CORTEX_A710_CPUPMR_EL3 S3_6_C15_C8_3 66b781fcf1SJayanth Dodderi Chidanand 67463b5b4aSGovindraj Raja #ifndef __ASSEMBLER__ 68463b5b4aSGovindraj Raja long check_erratum_cortex_a710_3701772(long cpu_rev); 69463b5b4aSGovindraj Raja #endif /* __ASSEMBLER__ */ 70463b5b4aSGovindraj Raja 71c6ac4df6Sjohpow01 #endif /* CORTEX_A710_H */ 72