Lines Matching refs:ULL
33 #define MPIDR_MT_MASK (ULL(1) << 24)
37 #define MPIDR_AFFLVL_MASK ULL(0xff)
43 #define MPIDR_AFFINITY_MASK ULL(0xff00ffffff)
45 #define MPIDR_AFFLVL0 ULL(0x0)
46 #define MPIDR_AFFLVL1 ULL(0x1)
47 #define MPIDR_AFFLVL2 ULL(0x2)
48 #define MPIDR_AFFLVL3 ULL(0x3)
101 #define ICC_PPI_DOMAINR_FIELD_MASK ULL(0x3)
191 #define ID_REG_FIELD_MASK ULL(0xf)
220 #define ID_AA64PFR0_AMU_MASK ULL(0xf)
221 #define ID_AA64PFR0_AMU_V1 ULL(0x1)
224 #define ID_AA64PFR0_ELX_MASK ULL(0xf)
232 #define ID_AA64PFR0_GIC_MASK ULL(0xf)
235 #define ID_AA64PFR0_SVE_MASK ULL(0xf)
237 #define SVE_IMPLEMENTED ULL(0x1)
240 #define ID_AA64PFR0_SEL2_MASK ULL(0xf)
243 #define ID_AA64PFR0_MPAM_MASK ULL(0xf)
246 #define ID_AA64PFR0_DIT_MASK ULL(0xf)
248 #define DIT_IMPLEMENTED ULL(1)
251 #define ID_AA64PFR0_CSV2_MASK ULL(0xf)
253 #define CSV2_2_IMPLEMENTED ULL(0x2)
254 #define CSV2_3_IMPLEMENTED ULL(0x3)
257 #define ID_AA64PFR0_FEAT_RME_MASK ULL(0xf)
259 #define RME_NOT_IMPLEMENTED ULL(0)
260 #define RME_GPC2_IMPLEMENTED ULL(0x2)
263 #define ID_AA64PFR0_RAS_MASK ULL(0xf)
267 #define EL_IMPL_NONE ULL(0)
268 #define EL_IMPL_A64ONLY ULL(1)
269 #define EL_IMPL_A64_A32 ULL(2)
273 #define ID_AA64DFR0_DEBUGVER_MASK ULL(0xf)
274 #define DEBUGVER_V8P9_IMPLEMENTED ULL(0xb)
278 #define ID_AA64DFR0_TRACEVER_MASK ULL(0xf)
284 #define TRACEFILT_IMPLEMENTED ULL(1)
295 #define ID_AA64DFR0_SEBEP_MASK ULL(0xf)
296 #define SEBEP_IMPLEMENTED ULL(1)
300 #define ID_AA64DFR0_PMS_MASK ULL(0xf)
301 #define SPE_IMPLEMENTED ULL(0x1)
302 #define SPE_NOT_IMPLEMENTED ULL(0x0)
306 #define ID_AA64DFR0_TRACEBUFFER_MASK ULL(0xf)
307 #define TRACEBUFFER_IMPLEMENTED ULL(1)
311 #define ID_AA64DFR0_MTPMU_MASK ULL(0xf)
312 #define MTPMU_IMPLEMENTED ULL(1)
313 #define MTPMU_NOT_IMPLEMENTED ULL(15)
317 #define ID_AA64DFR0_BRBE_MASK ULL(0xf)
318 #define BRBE_IMPLEMENTED ULL(1)
322 #define ID_AA64DFR1_EBEP_MASK ULL(0xf)
323 #define EBEP_IMPLEMENTED ULL(1)
335 #define ID_AA64ISAR0_ATOMIC_MASK ULL(0xf)
337 #define ID_AA64ISAR0_RNDR_MASK ULL(0xf)
343 #define ID_AA64ISAR1_LS64_MASK ULL(0xf)
344 #define LS64_ACCDATA_IMPLEMENTED ULL(0x3)
345 #define LS64_V_IMPLEMENTED ULL(0x2)
346 #define LS64_IMPLEMENTED ULL(0x1)
347 #define LS64_NOT_IMPLEMENTED ULL(0x0)
350 #define ID_AA64ISAR1_SB_MASK ULL(0xf)
351 #define SB_IMPLEMENTED ULL(0x1)
352 #define SB_NOT_IMPLEMENTED ULL(0x0)
355 #define ID_AA64ISAR1_GPI_MASK ULL(0xf)
357 #define ID_AA64ISAR1_GPA_MASK ULL(0xf)
360 #define ID_AA64ISAR1_API_MASK ULL(0xf)
362 #define ID_AA64ISAR1_APA_MASK ULL(0xf)
367 #define ID_AA64ISAR2_EL1_MOPS_MASK ULL(0xf)
369 #define MOPS_IMPLEMENTED ULL(0x1)
372 #define ID_AA64ISAR2_GPA3_MASK ULL(0xf)
375 #define ID_AA64ISAR2_APA3_MASK ULL(0xf)
378 #define ID_AA64ISAR2_CLRBHB_MASK ULL(0xf)
381 #define ID_AA64ISAR2_SYSREG128_MASK ULL(0xf)
386 #define ID_AA64ISAR3_EL1_CPA_MASK ULL(0xf)
388 #define CPA2_IMPLEMENTED ULL(0x2)
392 #define ID_AA64MMFR0_EL1_PARANGE_MASK ULL(0xf)
404 #define ID_AA64MMFR0_EL1_ECV_MASK ULL(0xf)
405 #define ID_AA64MMFR0_EL1_ECV_SELF_SYNCH ULL(0x2)
406 #define ECV_IMPLEMENTED ULL(0x1)
409 #define ID_AA64MMFR0_EL1_FGT_MASK ULL(0xf)
410 #define FGT2_IMPLEMENTED ULL(0x2)
411 #define FGT_IMPLEMENTED ULL(0x1)
412 #define FGT_NOT_IMPLEMENTED ULL(0x0)
415 #define ID_AA64MMFR0_EL1_TGRAN4_MASK ULL(0xf)
418 #define ID_AA64MMFR0_EL1_TGRAN64_MASK ULL(0xf)
421 #define ID_AA64MMFR0_EL1_TGRAN16_MASK ULL(0xf)
422 #define TGRAN16_IMPLEMENTED ULL(0x1)
426 #define ID_AA64MMFR1_EL1_TWED_MASK ULL(0xf)
427 #define TWED_IMPLEMENTED ULL(0x1)
430 #define ID_AA64MMFR1_EL1_PAN_MASK ULL(0xf)
431 #define PAN_IMPLEMENTED ULL(0x1)
432 #define PAN2_IMPLEMENTED ULL(0x2)
433 #define PAN3_IMPLEMENTED ULL(0x3)
436 #define ID_AA64MMFR1_EL1_VHE_MASK ULL(0xf)
439 #define ID_AA64MMFR1_EL1_HCX_MASK ULL(0xf)
440 #define HCX_IMPLEMENTED ULL(0x1)
446 #define ID_AA64MMFR2_EL1_IDS_MASK ULL(0xf)
449 #define ID_AA64MMFR2_EL1_ST_MASK ULL(0xf)
452 #define ID_AA64MMFR2_EL1_CCIDX_MASK ULL(0xf)
456 #define ID_AA64MMFR2_EL1_UAO_MASK ULL(0xf)
459 #define ID_AA64MMFR2_EL1_CNP_MASK ULL(0xf)
462 #define ID_AA64MMFR2_EL1_NV_MASK ULL(0xf)
463 #define NV2_IMPLEMENTED ULL(0x2)
469 #define ID_AA64MMFR3_EL1_D128_MASK ULL(0xf)
470 #define D128_IMPLEMENTED ULL(0x1)
473 #define ID_AA64MMFR3_EL1_MEC_MASK ULL(0xf)
476 #define ID_AA64MMFR3_EL1_AIE_MASK ULL(0xf)
479 #define ID_AA64MMFR3_EL1_S2POE_MASK ULL(0xf)
482 #define ID_AA64MMFR3_EL1_S1POE_MASK ULL(0xf)
485 #define ID_AA64MMFR3_EL1_S2PIE_MASK ULL(0xf)
488 #define ID_AA64MMFR3_EL1_S1PIE_MASK ULL(0xf)
491 #define ID_AA64MMFR3_EL1_SCTLR2_MASK ULL(0xf)
492 #define SCTLR2_IMPLEMENTED ULL(1)
495 #define ID_AA64MMFR3_EL1_TCRX_MASK ULL(0xf)
501 #define ID_AA64MMFR4_EL1_FGWTE3_MASK ULL(0xf)
502 #define FGWTE3_IMPLEMENTED ULL(0x1)
505 #define ID_AA64MMFR4_EL1_RME_GDI_MASK ULL(0xf)
507 #define RME_GDI_IMPLEMENTED ULL(0x1)
512 #define ID_AA64PFR1_EL1_BT_MASK ULL(0xf)
513 #define BTI_IMPLEMENTED ULL(1) /* The BTI mechanism is implemented */
516 #define ID_AA64PFR1_EL1_SSBS_MASK ULL(0xf)
517 #define SSBS_NOT_IMPLEMENTED ULL(0) /* No architectural SSBS support */
520 #define ID_AA64PFR1_EL1_MTE_MASK ULL(0xf)
524 #define RNG_TRAP_IMPLEMENTED ULL(0x1)
527 #define ID_AA64PFR1_EL1_NMI_MASK ULL(0xf)
528 #define NMI_IMPLEMENTED ULL(1)
531 #define ID_AA64PFR1_EL1_GCS_MASK ULL(0xf)
532 #define GCS_IMPLEMENTED ULL(1)
535 #define ID_AA64PFR1_EL1_THE_MASK ULL(0xf)
536 #define THE_IMPLEMENTED ULL(1)
539 #define ID_AA64PFR1_EL1_PFAR_MASK ULL(0xf)
546 #define ID_AA64PFR2_EL1_MTEPERM_MASK ULL(0xf)
549 #define ID_AA64PFR2_EL1_MTESTOREONLY_MASK ULL(0xf)
552 #define ID_AA64PFR2_EL1_MTEFAR_MASK ULL(0xf)
555 #define ID_AA64PFR2_EL1_UINJ_MASK ULL(0xf)
556 #define UINJ_IMPLEMENTED ULL(0x1)
559 #define ID_AA64PFR2_EL1_FPMR_MASK ULL(0xf)
561 #define FPMR_IMPLEMENTED ULL(0x1)
578 #define ID_AA64PFR1_MPAM_FRAC_SHIFT ULL(16)
579 #define ID_AA64PFR1_MPAM_FRAC_MASK ULL(0xf)
582 #define ID_AA64PFR1_EL1_SME_MASK ULL(0xf)
584 #define SME_IMPLEMENTED ULL(0x1)
585 #define SME2_IMPLEMENTED ULL(0x2)
586 #define SME_NOT_IMPLEMENTED ULL(0x0)
591 #define ID_AA64PFR2_EL1_GCIE_MASK ULL(0xf)
615 #define SCTLR_M_BIT (ULL(1) << 0)
616 #define SCTLR_A_BIT (ULL(1) << 1)
617 #define SCTLR_C_BIT (ULL(1) << 2)
618 #define SCTLR_SA_BIT (ULL(1) << 3)
619 #define SCTLR_SA0_BIT (ULL(1) << 4)
620 #define SCTLR_CP15BEN_BIT (ULL(1) << 5)
621 #define SCTLR_nAA_BIT (ULL(1) << 6)
622 #define SCTLR_ITD_BIT (ULL(1) << 7)
623 #define SCTLR_SED_BIT (ULL(1) << 8)
624 #define SCTLR_UMA_BIT (ULL(1) << 9)
625 #define SCTLR_EnRCTX_BIT (ULL(1) << 10)
626 #define SCTLR_EOS_BIT (ULL(1) << 11)
627 #define SCTLR_I_BIT (ULL(1) << 12)
628 #define SCTLR_EnDB_BIT (ULL(1) << 13)
629 #define SCTLR_DZE_BIT (ULL(1) << 14)
630 #define SCTLR_UCT_BIT (ULL(1) << 15)
631 #define SCTLR_NTWI_BIT (ULL(1) << 16)
632 #define SCTLR_NTWE_BIT (ULL(1) << 18)
633 #define SCTLR_WXN_BIT (ULL(1) << 19)
634 #define SCTLR_TSCXT_BIT (ULL(1) << 20)
635 #define SCTLR_IESB_BIT (ULL(1) << 21)
636 #define SCTLR_EIS_BIT (ULL(1) << 22)
637 #define SCTLR_SPAN_BIT (ULL(1) << 23)
638 #define SCTLR_E0E_BIT (ULL(1) << 24)
639 #define SCTLR_EE_BIT (ULL(1) << 25)
640 #define SCTLR_UCI_BIT (ULL(1) << 26)
641 #define SCTLR_EnDA_BIT (ULL(1) << 27)
642 #define SCTLR_nTLSMD_BIT (ULL(1) << 28)
643 #define SCTLR_LSMAOE_BIT (ULL(1) << 29)
644 #define SCTLR_EnIB_BIT (ULL(1) << 30)
645 #define SCTLR_EnIA_BIT (ULL(1) << 31)
646 #define SCTLR_BT0_BIT (ULL(1) << 35)
647 #define SCTLR_BT1_BIT (ULL(1) << 36)
648 #define SCTLR_BT_BIT (ULL(1) << 36)
649 #define SCTLR_ITFSB_BIT (ULL(1) << 37)
651 #define SCTLR_TCF0_MASK ULL(3)
652 #define SCTLR_ENTP2_BIT (ULL(1) << 60)
653 #define SCTLR_SPINTMASK_BIT (ULL(1) << 62)
668 #define SCTLR_TCF_MASK ULL(3)
682 #define SCTLR_ATA0_BIT (ULL(1) << 42)
683 #define SCTLR_ATA_BIT (ULL(1) << 43)
685 #define SCTLR_DSSBS_BIT (ULL(1) << SCTLR_DSSBS_SHIFT)
686 #define SCTLR_TWEDEn_BIT (ULL(1) << 45)
688 #define SCTLR_TWEDEL_MASK ULL(0xf)
689 #define SCTLR_EnASR_BIT (ULL(1) << 54)
690 #define SCTLR_EnAS0_BIT (ULL(1) << 55)
691 #define SCTLR_EnALS_BIT (ULL(1) << 56)
692 #define SCTLR_EPAN_BIT (ULL(1) << 57)
695 #define SCTLR2_EnPACM_BIT (ULL(1) << 7)
696 #define SCTLR2_CPTA_BIT (ULL(1) << 9)
697 #define SCTLR2_CPTM_BIT (ULL(1) << 11)
700 #define SCTLR2_RESET_VAL ULL(0)
708 #define CPACR_EL1_SMEN_MASK ULL(0x3)
717 #define SCR_NSE_BIT (ULL(1) << SCR_NSE_SHIFT)
720 #define SCR_EnFPM_BIT (ULL(1) << 50)
726 #define SCR_TWEDEL_MASK ULL(0xf)
767 #define MDCR_EBWE_BIT (ULL(1) << 43)
768 #define MDCR_EnPMS3_BIT (ULL(1) << 42)
770 #define MDCR_PMEE_CTRL_EL2 ULL(0x1)
771 #define MDCR_E3BREC_BIT (ULL(1) << 38)
772 #define MDCR_E3BREW_BIT (ULL(1) << 37)
773 #define MDCR_EnPMSN_BIT (ULL(1) << 36)
774 #define MDCR_MPMX_BIT (ULL(1) << 35)
775 #define MDCR_MCCD_BIT (ULL(1) << 34)
778 #define MDCR_SBRBE_ALL ULL(0x3)
779 #define MDCR_SBRBE_NS ULL(0x1)
780 #define MDCR_NSTB_EN_BIT (ULL(1) << 24)
781 #define MDCR_NSTB_SS_BIT (ULL(1) << 25)
782 #define MDCR_NSTBE_BIT (ULL(1) << 26)
783 #define MDCR_MTPME_BIT (ULL(1) << 28)
784 #define MDCR_TDCC_BIT (ULL(1) << 27)
785 #define MDCR_SCCD_BIT (ULL(1) << 23)
786 #define MDCR_EPMAD_BIT (ULL(1) << 21)
787 #define MDCR_EDAD_BIT (ULL(1) << 20)
788 #define MDCR_TTRF_BIT (ULL(1) << 19)
789 #define MDCR_STE_BIT (ULL(1) << 18)
790 #define MDCR_SPME_BIT (ULL(1) << 17)
791 #define MDCR_SDD_BIT (ULL(1) << 16)
793 #define MDCR_SPD32_LEGACY ULL(0x0)
794 #define MDCR_SPD32_DISABLE ULL(0x2)
795 #define MDCR_SPD32_ENABLE ULL(0x3)
796 #define MDCR_NSPB_SS_BIT (ULL(1) << 13)
797 #define MDCR_NSPB_EN_BIT (ULL(1) << 12)
798 #define MDCR_NSPBE_BIT (ULL(1) << 11)
799 #define MDCR_TDOSA_BIT (ULL(1) << 10)
800 #define MDCR_TDA_BIT (ULL(1) << 9)
801 #define MDCR_EnPM2_BIT (ULL(1) << 7)
802 #define MDCR_TPM_BIT (ULL(1) << 6)
803 #define MDCR_RLTE_BIT (ULL(1) << 0)
807 #define MDCR_EL2_MTPME (ULL(1) << 28)
808 #define MDCR_EL2_HLP_BIT (ULL(1) << 26)
809 #define MDCR_EL2_E2TB(x) ULL((x) << 24)
810 #define MDCR_EL2_E2TB_EL1 ULL(0x3)
811 #define MDCR_EL2_HCCD_BIT (ULL(1) << 23)
812 #define MDCR_EL2_TTRF (ULL(1) << 19)
813 #define MDCR_EL2_HPMD_BIT (ULL(1) << 17)
814 #define MDCR_EL2_TPMS (ULL(1) << 14)
815 #define MDCR_EL2_E2PB(x) ULL((x) << 12)
816 #define MDCR_EL2_E2PB_EL1 ULL(0x3)
817 #define MDCR_EL2_TDRA_BIT (ULL(1) << 11)
818 #define MDCR_EL2_TDOSA_BIT (ULL(1) << 10)
819 #define MDCR_EL2_TDA_BIT (ULL(1) << 9)
820 #define MDCR_EL2_TDE_BIT (ULL(1) << 8)
821 #define MDCR_EL2_HPME_BIT (ULL(1) << 7)
822 #define MDCR_EL2_TPM_BIT (ULL(1) << 6)
823 #define MDCR_EL2_TPMCR_BIT (ULL(1) << 5)
824 #define MDCR_EL2_HPMN_MASK ULL(0x1f)
825 #define MDCR_EL2_RESET_VAL ULL(0x0)
836 #define VTTBR_RESET_VAL ULL(0x0)
837 #define VTTBR_VMID_MASK ULL(0xff)
839 #define VTTBR_BADDR_MASK ULL(0xffffffffffff)
843 #define HCR_RESET_VAL ULL(0x0)
845 #define HCR_AMVOFFEN_BIT (ULL(1) << HCR_AMVOFFEN_SHIFT)
846 #define HCR_TEA_BIT (ULL(1) << 47)
847 #define HCR_API_BIT (ULL(1) << 41)
848 #define HCR_APK_BIT (ULL(1) << 40)
849 #define HCR_E2H_BIT (ULL(1) << 34)
850 #define HCR_HCD_BIT (ULL(1) << 29)
851 #define HCR_TGE_BIT (ULL(1) << 27)
853 #define HCR_RW_BIT (ULL(1) << HCR_RW_SHIFT)
854 #define HCR_TWE_BIT (ULL(1) << 14)
855 #define HCR_TWI_BIT (ULL(1) << 13)
856 #define HCR_AMO_BIT (ULL(1) << 5)
857 #define HCR_IMO_BIT (ULL(1) << 4)
858 #define HCR_FMO_BIT (ULL(1) << 3)
898 #define CPTR_EL2_SMEN_MASK ULL(0x3)
901 #define CPTR_EL2_ZEN_MASK ULL(0x3)
904 #define CPTR_EL2_TFP_BIT (ULL(1) << 10)
905 #define CPTR_EL2_TZ_BIT (ULL(1) << 8)
950 #define SPSR_SSBS_BIT_AARCH64 (ULL(1) << SPSR_SSBS_SHIFT_AARCH64)
952 #define SPSR_SSBS_BIT_AARCH32 (ULL(1) << SPSR_SSBS_SHIFT_AARCH32)
1003 #define TCR_EL3_RES1 ((ULL(1) << 31) | (ULL(1) << 23))
1004 #define TCR_EL2_RES1 ((ULL(1) << 31) | (ULL(1) << 23))
1009 #define TCR_TxSZ_MIN ULL(16)
1010 #define TCR_TxSZ_MAX ULL(39)
1011 #define TCR_TxSZ_MAX_TTST ULL(48)
1017 #define TCR_PS_BITS_4GB ULL(0x0)
1018 #define TCR_PS_BITS_64GB ULL(0x1)
1019 #define TCR_PS_BITS_1TB ULL(0x2)
1020 #define TCR_PS_BITS_4TB ULL(0x3)
1021 #define TCR_PS_BITS_16TB ULL(0x4)
1022 #define TCR_PS_BITS_256TB ULL(0x5)
1024 #define ADDR_MASK_48_TO_63 ULL(0xFFFF000000000000)
1025 #define ADDR_MASK_44_TO_47 ULL(0x0000F00000000000)
1026 #define ADDR_MASK_42_TO_43 ULL(0x00000C0000000000)
1027 #define ADDR_MASK_40_TO_41 ULL(0x0000030000000000)
1028 #define ADDR_MASK_36_TO_39 ULL(0x000000F000000000)
1029 #define ADDR_MASK_32_TO_35 ULL(0x0000000F00000000)
1031 #define TCR_RGN_INNER_NC (ULL(0x0) << 8)
1032 #define TCR_RGN_INNER_WBA (ULL(0x1) << 8)
1033 #define TCR_RGN_INNER_WT (ULL(0x2) << 8)
1034 #define TCR_RGN_INNER_WBNA (ULL(0x3) << 8)
1036 #define TCR_RGN_OUTER_NC (ULL(0x0) << 10)
1037 #define TCR_RGN_OUTER_WBA (ULL(0x1) << 10)
1038 #define TCR_RGN_OUTER_WT (ULL(0x2) << 10)
1039 #define TCR_RGN_OUTER_WBNA (ULL(0x3) << 10)
1041 #define TCR_SH_NON_SHAREABLE (ULL(0x0) << 12)
1042 #define TCR_SH_OUTER_SHAREABLE (ULL(0x2) << 12)
1043 #define TCR_SH_INNER_SHAREABLE (ULL(0x3) << 12)
1045 #define TCR_RGN1_INNER_NC (ULL(0x0) << 24)
1046 #define TCR_RGN1_INNER_WBA (ULL(0x1) << 24)
1047 #define TCR_RGN1_INNER_WT (ULL(0x2) << 24)
1048 #define TCR_RGN1_INNER_WBNA (ULL(0x3) << 24)
1050 #define TCR_RGN1_OUTER_NC (ULL(0x0) << 26)
1051 #define TCR_RGN1_OUTER_WBA (ULL(0x1) << 26)
1052 #define TCR_RGN1_OUTER_WT (ULL(0x2) << 26)
1053 #define TCR_RGN1_OUTER_WBNA (ULL(0x3) << 26)
1055 #define TCR_SH1_NON_SHAREABLE (ULL(0x0) << 28)
1056 #define TCR_SH1_OUTER_SHAREABLE (ULL(0x2) << 28)
1057 #define TCR_SH1_INNER_SHAREABLE (ULL(0x3) << 28)
1060 #define TCR_TG0_MASK ULL(3)
1061 #define TCR_TG0_4K (ULL(0) << TCR_TG0_SHIFT)
1062 #define TCR_TG0_64K (ULL(1) << TCR_TG0_SHIFT)
1063 #define TCR_TG0_16K (ULL(2) << TCR_TG0_SHIFT)
1066 #define TCR_TG1_MASK ULL(3)
1067 #define TCR_TG1_16K (ULL(1) << TCR_TG1_SHIFT)
1068 #define TCR_TG1_4K (ULL(2) << TCR_TG1_SHIFT)
1069 #define TCR_TG1_64K (ULL(3) << TCR_TG1_SHIFT)
1071 #define TCR_EPD0_BIT (ULL(1) << 7)
1072 #define TCR_EPD1_BIT (ULL(1) << 23)
1127 #define TTBR_CNP_BIT ULL(0x1)
1212 #define TLBI_ADDR_MASK ULL(0x00000FFFFFFFFFFF)
1282 #define ID_AA64SMFR0_EL1_SME_VER_MASK ULL(0xf)
1283 #define SME_INST_IMPLEMENTED ULL(0x0)
1284 #define SME2_INST_IMPLEMENTED ULL(0x1)
1298 #define MAIR_DEV_nGnRnE ULL(0x0)
1299 #define MAIR_DEV_nGnRE ULL(0x4)
1300 #define MAIR_DEV_nGRE ULL(0x8)
1301 #define MAIR_DEV_GRE ULL(0xc)
1321 #define MAIR_NORM_WT_TR_WA ULL(0x1)
1322 #define MAIR_NORM_WT_TR_RA ULL(0x2)
1323 #define MAIR_NORM_WT_TR_RWA ULL(0x3)
1324 #define MAIR_NORM_NC ULL(0x4)
1325 #define MAIR_NORM_WB_TR_WA ULL(0x5)
1326 #define MAIR_NORM_WB_TR_RA ULL(0x6)
1327 #define MAIR_NORM_WB_TR_RWA ULL(0x7)
1328 #define MAIR_NORM_WT_NTR_NA ULL(0x8)
1329 #define MAIR_NORM_WT_NTR_WA ULL(0x9)
1330 #define MAIR_NORM_WT_NTR_RA ULL(0xa)
1331 #define MAIR_NORM_WT_NTR_RWA ULL(0xb)
1332 #define MAIR_NORM_WB_NTR_NA ULL(0xc)
1333 #define MAIR_NORM_WB_NTR_WA ULL(0xd)
1334 #define MAIR_NORM_WB_NTR_RA ULL(0xe)
1335 #define MAIR_NORM_WB_NTR_RWA ULL(0xf)
1344 #define PAR_F_MASK ULL(0x1)
1362 #define MPAMIDR_EL1_VPMR_MAX_SHIFT ULL(18)
1363 #define MPAMIDR_EL1_VPMR_MAX_MASK ULL(0x7)
1426 #define AMCNTENSET0_EL0_Pn_MASK ULL(0xffff)
1430 #define AMCNTENSET1_EL0_Pn_MASK ULL(0xffff)
1434 #define AMCNTENCLR0_EL0_Pn_MASK ULL(0xffff)
1438 #define AMCNTENCLR1_EL0_Pn_MASK ULL(0xffff)
1453 #define MPAM3_EL3_MPAMEN_BIT (ULL(1) << 63)
1454 #define MPAM3_EL3_TRAPLOWER_BIT (ULL(1) << 62)
1455 #define MPAMHCR_EL2_TRAP_MPAMIDR_EL1 (ULL(1) << 31)
1458 #define MPAM2_EL2_TRAPMPAM0EL1 (ULL(1) << 49)
1459 #define MPAM2_EL2_TRAPMPAM1EL1 (ULL(1) << 48)
1461 #define MPAMIDR_HAS_BW_CTRL_BIT (ULL(1) << 56)
1462 #define MPAMIDR_HAS_HCR_BIT (ULL(1) << 17)
1466 #define MPAMBW2_EL2_HW_SCALE_ENABLE_BIT (ULL(1) << 63)
1467 #define MPAMBW2_EL2_ENABLED_BIT (ULL(1) << 62)
1468 #define MPAMBW2_EL2_HARDLIM_BIT (ULL(1) << 61)
1469 #define MPAMBW2_EL2_NTRAP_MPAMBWIDR_EL1_BIT (ULL(1) << 52)
1470 #define MPAMBW2_EL2_NTRAP_MPAMBW0_EL1_BIT (ULL(1) << 51)
1471 #define MPAMBW2_EL2_NTRAP_MPAMBW1_EL1_BIT (ULL(1) << 50)
1472 #define MPAMBW2_EL2_NTRAP_MPAMBWSM_EL1_BIT (ULL(1) << 49)
1475 #define MPAMBW3_EL3_HW_SCALE_ENABLE_BIT (ULL(1) << 63)
1476 #define MPAMBW3_EL3_ENABLED_BIT (ULL(1) << 62)
1477 #define MPAMBW3_EL3_HARDLIM_BIT (ULL(1) << 61)
1478 #define MPAMBW3_EL3_NTRAPLOWER_BIT (ULL(1) << 49)
1486 #define AMCG1IDR_CTR_MASK ULL(0xffff)
1488 #define AMCG1IDR_VOFF_MASK ULL(0xffff)
1493 #define AMCR_CG1RZ_BIT (ULL(0x1) << AMCR_CG1RZ_SHIFT)
1622 #define HCRX_EL2_INIT_VAL ULL(0x0)
1627 #define HFGITR_EL2_INIT_VAL ULL(0x180000000000000)
1628 #define HFGRTR_EL2_INIT_VAL ULL(0xC4000000000000)
1629 #define HFGWTR_EL2_INIT_VAL ULL(0xC4000000000000)