183c1584dSJimmy Brisson /* 2*ac9f4b4dSGovindraj Raja * Copyright (c) 2019-2025, Arm Limited. All rights reserved. 383c1584dSJimmy Brisson * 483c1584dSJimmy Brisson * SPDX-License-Identifier: BSD-3-Clause 583c1584dSJimmy Brisson */ 683c1584dSJimmy Brisson 73f35709cSJimmy Brisson #ifndef CORTEX_A78_H 83f35709cSJimmy Brisson #define CORTEX_A78_H 983c1584dSJimmy Brisson 1083c1584dSJimmy Brisson #include <lib/utils_def.h> 1183c1584dSJimmy Brisson 123f35709cSJimmy Brisson #define CORTEX_A78_MIDR U(0x410FD410) 1383c1584dSJimmy Brisson 141fe4a9d1SBipin Ravi /* Cortex-A78 loop count for CVE-2022-23960 mitigation */ 151fe4a9d1SBipin Ravi #define CORTEX_A78_BHB_LOOP_COUNT U(32) 161fe4a9d1SBipin Ravi 1783c1584dSJimmy Brisson /******************************************************************************* 1883c1584dSJimmy Brisson * CPU Extended Control register specific definitions. 1983c1584dSJimmy Brisson ******************************************************************************/ 203f35709cSJimmy Brisson #define CORTEX_A78_CPUECTLR_EL1 S3_0_C15_C1_4 21e26c59d2Sjohpow01 #define CORTEX_A78_CPUECTLR_EL1_BIT_8 (ULL(1) << 8) 2283c1584dSJimmy Brisson 2383c1584dSJimmy Brisson /******************************************************************************* 2483c1584dSJimmy Brisson * CPU Power Control register specific definitions 2583c1584dSJimmy Brisson ******************************************************************************/ 263f35709cSJimmy Brisson #define CORTEX_A78_CPUPWRCTLR_EL1 S3_0_C15_C2_7 273f35709cSJimmy Brisson #define CORTEX_A78_CPUPWRCTLR_EL1_CORE_PWRDN_EN_BIT U(1) 2883c1584dSJimmy Brisson 2983c1584dSJimmy Brisson /******************************************************************************* 3083c1584dSJimmy Brisson * CPU Auxiliary Control register specific definitions. 3183c1584dSJimmy Brisson ******************************************************************************/ 323f35709cSJimmy Brisson #define CORTEX_A78_ACTLR_TAM_BIT (ULL(1) << 30) 3383c1584dSJimmy Brisson 343f35709cSJimmy Brisson #define CORTEX_A78_ACTLR2_EL1 S3_0_C15_C1_1 3592e87084SVarun Wadekar #define CORTEX_A78_ACTLR2_EL1_BIT_0 (ULL(1) << 0) 363f35709cSJimmy Brisson #define CORTEX_A78_ACTLR2_EL1_BIT_1 (ULL(1) << 1) 371a691455Sjohpow01 #define CORTEX_A78_ACTLR2_EL1_BIT_2 (ULL(1) << 2) 383f4d81dfSVarun Wadekar #define CORTEX_A78_ACTLR2_EL1_BIT_40 (ULL(1) << 40) 3983c1584dSJimmy Brisson 407d1700c4SSona Mathew #define CORTEX_A78_ACTLR3_EL1 S3_0_C15_C1_2 41a63332c5SBipin Ravi 42a63332c5SBipin Ravi #define CORTEX_A78_ACTLR5_EL1 S3_0_C15_C9_0 437d1700c4SSona Mathew 4483c1584dSJimmy Brisson /******************************************************************************* 4583c1584dSJimmy Brisson * CPU Activity Monitor Unit register specific definitions. 4683c1584dSJimmy Brisson ******************************************************************************/ 4783c1584dSJimmy Brisson #define CPUAMCNTENCLR0_EL0 S3_3_C15_C2_4 4883c1584dSJimmy Brisson #define CPUAMCNTENSET0_EL0 S3_3_C15_C2_5 4983c1584dSJimmy Brisson #define CPUAMCNTENCLR1_EL0 S3_3_C15_C3_0 5083c1584dSJimmy Brisson #define CPUAMCNTENSET1_EL0 S3_3_C15_C3_1 5183c1584dSJimmy Brisson 523f35709cSJimmy Brisson #define CORTEX_A78_AMU_GROUP0_MASK U(0xF) 533f35709cSJimmy Brisson #define CORTEX_A78_AMU_GROUP1_MASK U(0x7) 5483c1584dSJimmy Brisson 553f35709cSJimmy Brisson #endif /* CORTEX_A78_H */ 56