1abbffe98SIsla Mitchell /* 2*6fb2dbd2SGovindraj Raja * Copyright (c) 2017-2023, Arm Limited and Contributors. All rights reserved. 3abbffe98SIsla Mitchell * 4abbffe98SIsla Mitchell * SPDX-License-Identifier: BSD-3-Clause 5abbffe98SIsla Mitchell */ 6abbffe98SIsla Mitchell 7c3cf06f1SAntonio Nino Diaz #ifndef CORTEX_A76_H 8c3cf06f1SAntonio Nino Diaz #define CORTEX_A76_H 9abbffe98SIsla Mitchell 101a74e4a8SAntonio Nino Diaz #include <lib/utils_def.h> 111a74e4a8SAntonio Nino Diaz 12abbffe98SIsla Mitchell /* Cortex-A76 MIDR for revision 0 */ 131a74e4a8SAntonio Nino Diaz #define CORTEX_A76_MIDR U(0x410fd0b0) 14abbffe98SIsla Mitchell 15a10a5cb6SBipin Ravi /* Cortex-A76 loop count for CVE-2022-23960 mitigation */ 16a10a5cb6SBipin Ravi #define CORTEX_A76_BHB_LOOP_COUNT U(24) 17a10a5cb6SBipin Ravi 18abbffe98SIsla Mitchell /******************************************************************************* 19abbffe98SIsla Mitchell * CPU Extended Control register specific definitions. 20abbffe98SIsla Mitchell ******************************************************************************/ 21abbffe98SIsla Mitchell #define CORTEX_A76_CPUPWRCTLR_EL1 S3_0_C15_C2_7 22abbffe98SIsla Mitchell #define CORTEX_A76_CPUECTLR_EL1 S3_0_C15_C1_4 23abbffe98SIsla Mitchell 245cc8c7baSLouis Mayencourt #define CORTEX_A76_CPUECTLR_EL1_WS_THR_L2 (ULL(3) << 24) 25e6e1d0acSSoby Mathew #define CORTEX_A76_CPUECTLR_EL1_BIT_51 (ULL(1) << 51) 265cc8c7baSLouis Mayencourt 27d6b79809SDimitris Papastamos /******************************************************************************* 28d6b79809SDimitris Papastamos * CPU Auxiliary Control register specific definitions. 29d6b79809SDimitris Papastamos ******************************************************************************/ 305c6aa01aSLouis Mayencourt #define CORTEX_A76_CPUACTLR_EL1 S3_0_C15_C1_0 315c6aa01aSLouis Mayencourt 325c6aa01aSLouis Mayencourt #define CORTEX_A76_CPUACTLR_EL1_DISABLE_STATIC_PREDICTION (ULL(1) << 6) 335c6aa01aSLouis Mayencourt 34e6e1d0acSSoby Mathew #define CORTEX_A76_CPUACTLR_EL1_BIT_13 (ULL(1) << 13) 35e6e1d0acSSoby Mathew 36d6b79809SDimitris Papastamos #define CORTEX_A76_CPUACTLR2_EL1 S3_0_C15_C1_1 37d6b79809SDimitris Papastamos 38d7b08e69Sjohpow01 #define CORTEX_A76_CPUACTLR2_EL1_BIT_2 (ULL(1) << 2) 39*6fb2dbd2SGovindraj Raja #define CORTEX_A76_CPUACTLR2_EL1_BIT_59 (ULL(1) << 59) 40d7b08e69Sjohpow01 411a74e4a8SAntonio Nino Diaz #define CORTEX_A76_CPUACTLR2_EL1_DISABLE_LOAD_PASS_STORE (ULL(1) << 16) 42d6b79809SDimitris Papastamos 43e6e1d0acSSoby Mathew #define CORTEX_A76_CPUACTLR3_EL1 S3_0_C15_C1_2 44e6e1d0acSSoby Mathew 45e6e1d0acSSoby Mathew #define CORTEX_A76_CPUACTLR3_EL1_BIT_10 (ULL(1) << 10) 46e6e1d0acSSoby Mathew 47e6e1d0acSSoby Mathew 48abbffe98SIsla Mitchell /* Definitions of register field mask in CORTEX_A76_CPUPWRCTLR_EL1 */ 491a74e4a8SAntonio Nino Diaz #define CORTEX_A76_CORE_PWRDN_EN_MASK U(0x1) 50abbffe98SIsla Mitchell 51c3cf06f1SAntonio Nino Diaz #endif /* CORTEX_A76_H */ 52