1f5cb15b0SAndre Przywara /* 27a9cdf58SMario Bălănică * Copyright (c) 2016-2024, Arm Limited and Contributors. All rights reserved. 3f5cb15b0SAndre Przywara * 4f5cb15b0SAndre Przywara * SPDX-License-Identifier: BSD-3-Clause 5f5cb15b0SAndre Przywara */ 6f5cb15b0SAndre Przywara 7f5cb15b0SAndre Przywara #ifndef RPI_HW_H 8f5cb15b0SAndre Przywara #define RPI_HW_H 9f5cb15b0SAndre Przywara 10f5cb15b0SAndre Przywara #include <lib/utils_def.h> 11f5cb15b0SAndre Przywara 12f5cb15b0SAndre Przywara /* 13f5cb15b0SAndre Przywara * Peripherals 14f5cb15b0SAndre Przywara */ 15f5cb15b0SAndre Przywara 162973dc5dSJeremy Linton #define RPI_IO_BASE ULL(0xFC000000) 172973dc5dSJeremy Linton #define RPI_IO_SIZE ULL(0x04000000) 182973dc5dSJeremy Linton 192973dc5dSJeremy Linton #define RPI_LEGACY_BASE (ULL(0x02000000) + RPI_IO_BASE) 20f5cb15b0SAndre Przywara 21f5cb15b0SAndre Przywara /* 22f5cb15b0SAndre Przywara * ARM <-> VideoCore mailboxes 23f5cb15b0SAndre Przywara */ 24f5cb15b0SAndre Przywara #define RPI3_MBOX_OFFSET ULL(0x0000B880) 252973dc5dSJeremy Linton #define RPI3_MBOX_BASE (RPI_LEGACY_BASE + RPI3_MBOX_OFFSET) 26f5cb15b0SAndre Przywara 27f5cb15b0SAndre Przywara /* 28f5cb15b0SAndre Przywara * Power management, reset controller, watchdog. 29f5cb15b0SAndre Przywara */ 30f5cb15b0SAndre Przywara #define RPI3_IO_PM_OFFSET ULL(0x00100000) 312973dc5dSJeremy Linton #define RPI3_PM_BASE (RPI_LEGACY_BASE + RPI3_IO_PM_OFFSET) 32f5cb15b0SAndre Przywara 33f5cb15b0SAndre Przywara /* 34f5cb15b0SAndre Przywara * Hardware random number generator. 35f5cb15b0SAndre Przywara */ 36f5cb15b0SAndre Przywara #define RPI3_IO_RNG_OFFSET ULL(0x00104000) 372973dc5dSJeremy Linton #define RPI3_RNG_BASE (RPI_LEGACY_BASE + RPI3_IO_RNG_OFFSET) 38f5cb15b0SAndre Przywara 39f5cb15b0SAndre Przywara /* 405e6d821cSAndre Przywara * Serial ports: 415e6d821cSAndre Przywara * 'Mini UART' in the BCM docucmentation is the 8250 compatible UART. 425e6d821cSAndre Przywara * There is also a PL011 UART, multiplexed to the same pins. 43f5cb15b0SAndre Przywara */ 44795aefe5SAndre Przywara #define RPI4_IO_MINI_UART_OFFSET ULL(0x00215040) 452973dc5dSJeremy Linton #define RPI4_MINI_UART_BASE (RPI_LEGACY_BASE + RPI4_IO_MINI_UART_OFFSET) 465e6d821cSAndre Przywara #define RPI4_IO_PL011_UART_OFFSET ULL(0x00201000) 472973dc5dSJeremy Linton #define RPI4_PL011_UART_BASE (RPI_LEGACY_BASE + RPI4_IO_PL011_UART_OFFSET) 485e6d821cSAndre Przywara #define RPI4_PL011_UART_CLOCK ULL(48000000) 49f5cb15b0SAndre Przywara 50f5cb15b0SAndre Przywara /* 51f5cb15b0SAndre Przywara * GPIO controller 52f5cb15b0SAndre Przywara */ 53f5cb15b0SAndre Przywara #define RPI3_IO_GPIO_OFFSET ULL(0x00200000) 542973dc5dSJeremy Linton #define RPI3_GPIO_BASE (RPI_LEGACY_BASE + RPI3_IO_GPIO_OFFSET) 55f5cb15b0SAndre Przywara 56f5cb15b0SAndre Przywara /* 57f5cb15b0SAndre Przywara * SDHost controller 58f5cb15b0SAndre Przywara */ 59f5cb15b0SAndre Przywara #define RPI3_IO_SDHOST_OFFSET ULL(0x00202000) 602973dc5dSJeremy Linton #define RPI3_SDHOST_BASE (RPI_LEGACY_BASE + RPI3_IO_SDHOST_OFFSET) 61f5cb15b0SAndre Przywara 62f5cb15b0SAndre Przywara /* 63f5cb15b0SAndre Przywara * GIC interrupt controller 64f5cb15b0SAndre Przywara */ 65f5cb15b0SAndre Przywara #define RPI_HAVE_GIC 66f5cb15b0SAndre Przywara #define RPI4_GIC_GICD_BASE ULL(0xff841000) 67f5cb15b0SAndre Przywara #define RPI4_GIC_GICC_BASE ULL(0xff842000) 68f5cb15b0SAndre Przywara 69f5cb15b0SAndre Przywara #define RPI4_LOCAL_CONTROL_BASE_ADDRESS ULL(0xff800000) 70f5cb15b0SAndre Przywara #define RPI4_LOCAL_CONTROL_PRESCALER ULL(0xff800008) 71f5cb15b0SAndre Przywara 72*682607fbSMario Bălănică /* 73*682607fbSMario Bălănică * PCI Express 74*682607fbSMario Bălănică */ 75*682607fbSMario Bălănică #define RPI_PCIE_RC_BASES (RPI_IO_BASE + ULL(0x01500000)) 76*682607fbSMario Bălănică 77*682607fbSMario Bălănică #define RPI_PCIE_ECAM_SERROR_QUIRK 1 78*682607fbSMario Bălănică 79f5cb15b0SAndre Przywara #endif /* RPI_HW_H */ 80