1add40351SSoby Mathew /* 2*4c700c15SGovindraj Raja * Copyright (c) 2014-2019, Arm Limited and Contributors. All rights reserved. 3cd0ea184SVarun Wadekar * Copyright (c) 2020, NVIDIA Corporation. All rights reserved. 4add40351SSoby Mathew * 582cb2c1aSdp-arm * SPDX-License-Identifier: BSD-3-Clause 6add40351SSoby Mathew */ 7add40351SSoby Mathew 8c3cf06f1SAntonio Nino Diaz #ifndef CORTEX_A57_H 9c3cf06f1SAntonio Nino Diaz #define CORTEX_A57_H 1009d40e0eSAntonio Nino Diaz 1109d40e0eSAntonio Nino Diaz #include <lib/utils_def.h> 12add40351SSoby Mathew 13add40351SSoby Mathew /* Cortex-A57 midr for revision 0 */ 14030567e6SVarun Wadekar #define CORTEX_A57_MIDR U(0x410FD070) 15add40351SSoby Mathew 16e0d913c7SVarun Wadekar /* Retention timer tick definitions */ 17030567e6SVarun Wadekar #define RETENTION_ENTRY_TICKS_2 U(0x1) 18030567e6SVarun Wadekar #define RETENTION_ENTRY_TICKS_8 U(0x2) 19030567e6SVarun Wadekar #define RETENTION_ENTRY_TICKS_32 U(0x3) 20030567e6SVarun Wadekar #define RETENTION_ENTRY_TICKS_64 U(0x4) 21030567e6SVarun Wadekar #define RETENTION_ENTRY_TICKS_128 U(0x5) 22030567e6SVarun Wadekar #define RETENTION_ENTRY_TICKS_256 U(0x6) 23030567e6SVarun Wadekar #define RETENTION_ENTRY_TICKS_512 U(0x7) 24e0d913c7SVarun Wadekar 25add40351SSoby Mathew /******************************************************************************* 26add40351SSoby Mathew * CPU Extended Control register specific definitions. 27add40351SSoby Mathew ******************************************************************************/ 28fb7d32e5SVarun Wadekar #define CORTEX_A57_ECTLR_EL1 S3_1_C15_C2_1 29d3f70af6SSoby Mathew 30a69817edSAntonio Nino Diaz #define CORTEX_A57_ECTLR_SMP_BIT (ULL(1) << 6) 31a69817edSAntonio Nino Diaz #define CORTEX_A57_ECTLR_DIS_TWD_ACC_PFTCH_BIT (ULL(1) << 38) 32a69817edSAntonio Nino Diaz #define CORTEX_A57_ECTLR_L2_IPFTCH_DIST_MASK (ULL(0x3) << 35) 33a69817edSAntonio Nino Diaz #define CORTEX_A57_ECTLR_L2_DPFTCH_DIST_MASK (ULL(0x3) << 32) 34add40351SSoby Mathew 35030567e6SVarun Wadekar #define CORTEX_A57_ECTLR_CPU_RET_CTRL_SHIFT U(0) 361a74e4a8SAntonio Nino Diaz #define CORTEX_A57_ECTLR_CPU_RET_CTRL_MASK (ULL(0x7) << CORTEX_A57_ECTLR_CPU_RET_CTRL_SHIFT) 37e0d913c7SVarun Wadekar 38d9bdaf2dSSoby Mathew /******************************************************************************* 3984629f2fSNaga Sureshkumar Relli * CPU Memory Error Syndrome register specific definitions. 4084629f2fSNaga Sureshkumar Relli ******************************************************************************/ 41fb7d32e5SVarun Wadekar #define CORTEX_A57_MERRSR_EL1 S3_1_C15_C2_2 4284629f2fSNaga Sureshkumar Relli 4384629f2fSNaga Sureshkumar Relli /******************************************************************************* 44d9bdaf2dSSoby Mathew * CPU Auxiliary Control register specific definitions. 45d9bdaf2dSSoby Mathew ******************************************************************************/ 4680bcf981SEleanor Bonnici #define CORTEX_A57_CPUACTLR_EL1 S3_1_C15_C2_0 47d9bdaf2dSSoby Mathew 4880bcf981SEleanor Bonnici #define CORTEX_A57_CPUACTLR_EL1_DIS_LOAD_PASS_DMB (ULL(1) << 59) 490f6fbbd2SAmbroise Vincent #define CORTEX_A57_CPUACTLR_EL1_DIS_DMB_NULLIFICATION (ULL(1) << 58) 50b8a25bbbSDimitris Papastamos #define CORTEX_A57_CPUACTLR_EL1_DIS_LOAD_PASS_STORE (ULL(1) << 55) 5180bcf981SEleanor Bonnici #define CORTEX_A57_CPUACTLR_EL1_GRE_NGRE_AS_NGNRE (ULL(1) << 54) 5280bcf981SEleanor Bonnici #define CORTEX_A57_CPUACTLR_EL1_DIS_OVERREAD (ULL(1) << 52) 5380bcf981SEleanor Bonnici #define CORTEX_A57_CPUACTLR_EL1_NO_ALLOC_WBWA (ULL(1) << 49) 5480bcf981SEleanor Bonnici #define CORTEX_A57_CPUACTLR_EL1_DCC_AS_DCCI (ULL(1) << 44) 5580bcf981SEleanor Bonnici #define CORTEX_A57_CPUACTLR_EL1_FORCE_FPSCR_FLUSH (ULL(1) << 38) 5645b52c20SEleanor Bonnici #define CORTEX_A57_CPUACTLR_EL1_DIS_INSTR_PREFETCH (ULL(1) << 32) 5780bcf981SEleanor Bonnici #define CORTEX_A57_CPUACTLR_EL1_DIS_STREAMING (ULL(3) << 27) 58cd0ea184SVarun Wadekar #define CORTEX_A57_CPUACTLR_EL1_EN_NC_LOAD_FWD (ULL(1) << 24) 5980bcf981SEleanor Bonnici #define CORTEX_A57_CPUACTLR_EL1_DIS_L1_STREAMING (ULL(3) << 25) 6080bcf981SEleanor Bonnici #define CORTEX_A57_CPUACTLR_EL1_DIS_INDIRECT_PREDICTOR (ULL(1) << 4) 61d9bdaf2dSSoby Mathew 6201b916bfSSandrine Bailleux /******************************************************************************* 6301b916bfSSandrine Bailleux * L2 Control register specific definitions. 6401b916bfSSandrine Bailleux ******************************************************************************/ 65fb7d32e5SVarun Wadekar #define CORTEX_A57_L2CTLR_EL1 S3_1_C11_C0_2 6601b916bfSSandrine Bailleux 67030567e6SVarun Wadekar #define CORTEX_A57_L2CTLR_DATA_RAM_LATENCY_SHIFT U(0) 68030567e6SVarun Wadekar #define CORTEX_A57_L2CTLR_TAG_RAM_LATENCY_SHIFT U(6) 6901b916bfSSandrine Bailleux 70030567e6SVarun Wadekar #define CORTEX_A57_L2_DATA_RAM_LATENCY_3_CYCLES U(0x2) 71030567e6SVarun Wadekar #define CORTEX_A57_L2_TAG_RAM_LATENCY_3_CYCLES U(0x2) 7201b916bfSSandrine Bailleux 73030567e6SVarun Wadekar #define CORTEX_A57_L2_ECC_PARITY_PROTECTION_BIT (U(1) << 21) 74018b8480SVarun Wadekar 75e0d913c7SVarun Wadekar /******************************************************************************* 76e0d913c7SVarun Wadekar * L2 Extended Control register specific definitions. 77e0d913c7SVarun Wadekar ******************************************************************************/ 78fb7d32e5SVarun Wadekar #define CORTEX_A57_L2ECTLR_EL1 S3_1_C11_C0_3 79e0d913c7SVarun Wadekar 80030567e6SVarun Wadekar #define CORTEX_A57_L2ECTLR_RET_CTRL_SHIFT U(0) 81030567e6SVarun Wadekar #define CORTEX_A57_L2ECTLR_RET_CTRL_MASK (U(0x7) << CORTEX_A57_L2ECTLR_RET_CTRL_SHIFT) 82e0d913c7SVarun Wadekar 8384629f2fSNaga Sureshkumar Relli /******************************************************************************* 8484629f2fSNaga Sureshkumar Relli * L2 Memory Error Syndrome register specific definitions. 8584629f2fSNaga Sureshkumar Relli ******************************************************************************/ 86fb7d32e5SVarun Wadekar #define CORTEX_A57_L2MERRSR_EL1 S3_1_C15_C2_3 8784629f2fSNaga Sureshkumar Relli 88c3cf06f1SAntonio Nino Diaz #endif /* CORTEX_A57_H */ 89