1add40351SSoby Mathew /* 2*4c700c15SGovindraj Raja * Copyright (c) 2014-2019, Arm Limited and Contributors. All rights reserved. 3add40351SSoby Mathew * 482cb2c1aSdp-arm * SPDX-License-Identifier: BSD-3-Clause 5add40351SSoby Mathew */ 6add40351SSoby Mathew 7c3cf06f1SAntonio Nino Diaz #ifndef CORTEX_A53_H 8c3cf06f1SAntonio Nino Diaz #define CORTEX_A53_H 9add40351SSoby Mathew 10a69817edSAntonio Nino Diaz #include <lib/utils_def.h> 11a69817edSAntonio Nino Diaz 12add40351SSoby Mathew /* Cortex-A53 midr for revision 0 */ 13030567e6SVarun Wadekar #define CORTEX_A53_MIDR U(0x410FD030) 14add40351SSoby Mathew 15e0d913c7SVarun Wadekar /* Retention timer tick definitions */ 16030567e6SVarun Wadekar #define RETENTION_ENTRY_TICKS_2 U(0x1) 17030567e6SVarun Wadekar #define RETENTION_ENTRY_TICKS_8 U(0x2) 18030567e6SVarun Wadekar #define RETENTION_ENTRY_TICKS_32 U(0x3) 19030567e6SVarun Wadekar #define RETENTION_ENTRY_TICKS_64 U(0x4) 20030567e6SVarun Wadekar #define RETENTION_ENTRY_TICKS_128 U(0x5) 21030567e6SVarun Wadekar #define RETENTION_ENTRY_TICKS_256 U(0x6) 22030567e6SVarun Wadekar #define RETENTION_ENTRY_TICKS_512 U(0x7) 23e0d913c7SVarun Wadekar 24add40351SSoby Mathew /******************************************************************************* 25add40351SSoby Mathew * CPU Extended Control register specific definitions. 26add40351SSoby Mathew ******************************************************************************/ 27fb7d32e5SVarun Wadekar #define CORTEX_A53_ECTLR_EL1 S3_1_C15_C2_1 28d3f70af6SSoby Mathew 291a74e4a8SAntonio Nino Diaz #define CORTEX_A53_ECTLR_SMP_BIT (ULL(1) << 6) 30add40351SSoby Mathew 31030567e6SVarun Wadekar #define CORTEX_A53_ECTLR_CPU_RET_CTRL_SHIFT U(0) 321a74e4a8SAntonio Nino Diaz #define CORTEX_A53_ECTLR_CPU_RET_CTRL_MASK (ULL(0x7) << CORTEX_A53_ECTLR_CPU_RET_CTRL_SHIFT) 33e0d913c7SVarun Wadekar 34030567e6SVarun Wadekar #define CORTEX_A53_ECTLR_FPU_RET_CTRL_SHIFT U(3) 351a74e4a8SAntonio Nino Diaz #define CORTEX_A53_ECTLR_FPU_RET_CTRL_MASK (ULL(0x7) << CORTEX_A53_ECTLR_FPU_RET_CTRL_SHIFT) 36e0d913c7SVarun Wadekar 376b0d97b2SJimmy Huang /******************************************************************************* 3884629f2fSNaga Sureshkumar Relli * CPU Memory Error Syndrome register specific definitions. 3984629f2fSNaga Sureshkumar Relli ******************************************************************************/ 40fb7d32e5SVarun Wadekar #define CORTEX_A53_MERRSR_EL1 S3_1_C15_C2_2 4184629f2fSNaga Sureshkumar Relli 4284629f2fSNaga Sureshkumar Relli /******************************************************************************* 436b0d97b2SJimmy Huang * CPU Auxiliary Control register specific definitions. 446b0d97b2SJimmy Huang ******************************************************************************/ 4580bcf981SEleanor Bonnici #define CORTEX_A53_CPUACTLR_EL1 S3_1_C15_C2_0 466b0d97b2SJimmy Huang 4780bcf981SEleanor Bonnici #define CORTEX_A53_CPUACTLR_EL1_ENDCCASCI_SHIFT U(44) 48a69817edSAntonio Nino Diaz #define CORTEX_A53_CPUACTLR_EL1_ENDCCASCI (ULL(1) << CORTEX_A53_CPUACTLR_EL1_ENDCCASCI_SHIFT) 4980bcf981SEleanor Bonnici #define CORTEX_A53_CPUACTLR_EL1_RADIS_SHIFT U(27) 50a69817edSAntonio Nino Diaz #define CORTEX_A53_CPUACTLR_EL1_RADIS (ULL(3) << CORTEX_A53_CPUACTLR_EL1_RADIS_SHIFT) 5180bcf981SEleanor Bonnici #define CORTEX_A53_CPUACTLR_EL1_L1RADIS_SHIFT U(25) 52a69817edSAntonio Nino Diaz #define CORTEX_A53_CPUACTLR_EL1_L1RADIS (ULL(3) << CORTEX_A53_CPUACTLR_EL1_L1RADIS_SHIFT) 5380bcf981SEleanor Bonnici #define CORTEX_A53_CPUACTLR_EL1_DTAH_SHIFT U(24) 54a69817edSAntonio Nino Diaz #define CORTEX_A53_CPUACTLR_EL1_DTAH (ULL(1) << CORTEX_A53_CPUACTLR_EL1_DTAH_SHIFT) 558bbb1d80SJiafei Pan #define CORTEX_A53_CPUACTLR_EL1_L1PCTL_SHIFT U(13) 568bbb1d80SJiafei Pan #define CORTEX_A53_CPUACTLR_EL1_L1PCTL (ULL(7) << CORTEX_A53_CPUACTLR_EL1_L1PCTL_SHIFT) 576b0d97b2SJimmy Huang 586b0d97b2SJimmy Huang /******************************************************************************* 596b0d97b2SJimmy Huang * L2 Auxiliary Control register specific definitions. 606b0d97b2SJimmy Huang ******************************************************************************/ 61fb7d32e5SVarun Wadekar #define CORTEX_A53_L2ACTLR_EL1 S3_1_C15_C0_0 626b0d97b2SJimmy Huang 63030567e6SVarun Wadekar #define CORTEX_A53_L2ACTLR_ENABLE_UNIQUECLEAN (U(1) << 14) 64030567e6SVarun Wadekar #define CORTEX_A53_L2ACTLR_DISABLE_CLEAN_PUSH (U(1) << 3) 65e0d913c7SVarun Wadekar /******************************************************************************* 66e0d913c7SVarun Wadekar * L2 Extended Control register specific definitions. 67e0d913c7SVarun Wadekar ******************************************************************************/ 68fb7d32e5SVarun Wadekar #define CORTEX_A53_L2ECTLR_EL1 S3_1_C11_C0_3 69e0d913c7SVarun Wadekar 70030567e6SVarun Wadekar #define CORTEX_A53_L2ECTLR_RET_CTRL_SHIFT U(0) 71030567e6SVarun Wadekar #define CORTEX_A53_L2ECTLR_RET_CTRL_MASK (U(0x7) << L2ECTLR_RET_CTRL_SHIFT) 72e0d913c7SVarun Wadekar 7384629f2fSNaga Sureshkumar Relli /******************************************************************************* 7484629f2fSNaga Sureshkumar Relli * L2 Memory Error Syndrome register specific definitions. 7584629f2fSNaga Sureshkumar Relli ******************************************************************************/ 76fb7d32e5SVarun Wadekar #define CORTEX_A53_L2MERRSR_EL1 S3_1_C15_C2_3 7784629f2fSNaga Sureshkumar Relli 787352f329Skenny liang /******************************************************************************* 797352f329Skenny liang * Helper function to access a53_cpuectlr_el1 register on Cortex-A53 CPUs 807352f329Skenny liang ******************************************************************************/ 8189632e6aSBalint Dobszay #ifndef __ASSEMBLER__ 827352f329Skenny liang DEFINE_RENAME_SYSREG_RW_FUNCS(a53_cpuectlr_el1, CORTEX_A53_ECTLR_EL1) 8389632e6aSBalint Dobszay #endif /* __ASSEMBLER__ */ 847352f329Skenny liang 85c3cf06f1SAntonio Nino Diaz #endif /* CORTEX_A53_H */ 86