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Searched refs:GICR_BASE (Results 1 – 17 of 17) sorted by relevance

/optee_os/core/arch/arm/plat-aspeed/
H A Dplatform_ast2700.c16 register_phys_mem(MEM_AREA_IO_SEC, GICR_BASE, GICR_SIZE);
24 gic_init_v3(0, GICD_BASE, GICR_BASE); in boot_primary_init_intc()
H A Dplatform_config.h28 #define GICR_BASE 0x12280000 macro
/optee_os/core/arch/arm/plat-versal2/
H A Dmain.c30 register_phys_mem_pgdir(MEM_AREA_IO_SEC, GICR_BASE, GIC_DIST_REG_SIZE);
36 gic_init_v3(0, GICD_BASE, GICR_BASE); in boot_primary_init_intc()
H A Dplatform_config.h24 #define GICR_BASE U(0xE2060000) macro
/optee_os/core/arch/arm/plat-corstone1000/
H A Dmain.c23 register_phys_mem_pgdir(MEM_AREA_IO_SEC, GICR_BASE, GIC_REDIST_REG_SIZE);
31 gic_init_v3(0, GICD_BASE, GICR_BASE); in boot_primary_init_intc()
H A Dplatform_config.h38 #define GICR_BASE (GIC_BASE + GICR_OFFSET) macro
/optee_os/core/arch/arm/plat-qcom/
H A Dmain.c22 register_phys_mem_pgdir(MEM_AREA_IO_SEC, GICR_BASE, GIC_DIST_REG_SIZE);
48 gic_init_v3(0, GICD_BASE, GICR_BASE); in boot_primary_init_intc()
H A Dplatform_config.h31 #define GICR_BASE UL(0x17a60000) macro
/optee_os/core/arch/arm/plat-automotive_rd/
H A Dmain.c28 register_phys_mem_pgdir(MEM_AREA_IO_SEC, GICR_BASE, GICR_SIZE);
39 gic_init_v3(0, GICD_BASE, GICR_BASE); in boot_primary_init_intc()
H A Dplatform_config.h32 #define GICR_BASE UL(0x200C0000) macro
/optee_os/core/arch/arm/plat-rockchip/
H A Dplatform_config.h53 #define GICR_BASE (GIC_BASE + SIZE_M(1)) macro
95 #define GICR_BASE (GIC_BASE + 0x80000) macro
/optee_os/core/arch/arm/plat-imx/registers/
H A Dimx95.h9 #define GICR_BASE 0x48060000 macro
H A Dimx943.h9 #define GICR_BASE 0x48060000 macro
H A Dimx93.h9 #define GICR_BASE 0x48040000 macro
H A Dimx8q.h10 #define GICR_BASE 0x51b00000 macro
H A Dimx8ulp.h11 #define GICR_BASE 0x2d440000 macro
H A Dimx8m.h12 #define GICR_BASE 0x38880000 macro