12a128a33SClement Faure /* SPDX-License-Identifier: BSD-2-Clause */ 22a128a33SClement Faure /* 32a128a33SClement Faure * Copyright 2017-2019 NXP 42a128a33SClement Faure */ 52a128a33SClement Faure 62a128a33SClement Faure #ifndef __IMX8M_H__ 72a128a33SClement Faure #define __IMX8M_H__ 82a128a33SClement Faure 978b3ea9cSJorge Ramirez-Ortiz #include <registers/imx8m-crm.h> 1078b3ea9cSJorge Ramirez-Ortiz 112a128a33SClement Faure #define GICD_BASE 0x38800000 122a128a33SClement Faure #define GICR_BASE 0x38880000 132a128a33SClement Faure #define UART1_BASE 0x30860000 142a128a33SClement Faure #define UART2_BASE 0x30890000 152a128a33SClement Faure #define UART3_BASE 0x30880000 162a128a33SClement Faure #define UART4_BASE 0x30A60000 172a128a33SClement Faure #define TZASC_BASE 0x32F80000 18a4928cf1SClement Faure #define TZASC_SIZE 0x10000 192a128a33SClement Faure #define CAAM_BASE 0x30900000 202866fd96SClement Faure #define CAAM_SIZE 0x40000 2178b3ea9cSJorge Ramirez-Ortiz #define CCM_BASE 0x30380000 220a8e42ddSClement Faure #define CCM_SIZE 0x10000 232a128a33SClement Faure #define ANATOP_BASE 0x30360000 2478b3ea9cSJorge Ramirez-Ortiz #define IOMUXC_BASE 0x30330000 250a8e42ddSClement Faure #define OCOTP_BASE 0x30350000 260a8e42ddSClement Faure #define OCOTP_SIZE 0x10000 276bd963b9SIgor Opaniuk #define SNVS_BASE 0x30370000 28e82fe154SClement Faure #define SNVS_SIZE 0x10000 29*d2f982b6SClement Faure #define SECMEM_BASE 0x00100000 30*d2f982b6SClement Faure #define SECMEM_SIZE 0x8000 312a128a33SClement Faure 3280753240SClement Faure #ifdef CFG_MX8MQ 33247f081aSClement Faure #define DIGPROG_OFFSET 0x06c 340a8e42ddSClement Faure #define OCOTP_SW_INFO_B1 0x40 350a8e42ddSClement Faure #define OCOTP_SW_MAGIC_B1 0xFF0055AA 36247f081aSClement Faure #endif 376df63c07SClement Faure #if defined(CFG_MX8MM) || defined(CFG_MX8MN) || defined(CFG_MX8MP) 38247f081aSClement Faure #define DIGPROG_OFFSET 0x800 39247f081aSClement Faure #endif 40247f081aSClement Faure 41830dc5c6SGerard Koskamp #if defined(CFG_MX8MM) || defined(CFG_MX8MQ) || defined(CFG_MX8MN) 4278b3ea9cSJorge Ramirez-Ortiz #define I2C1_BASE 0x30a20000 4378b3ea9cSJorge Ramirez-Ortiz #define I2C2_BASE 0x30a30000 4478b3ea9cSJorge Ramirez-Ortiz #define I2C3_BASE 0x30a40000 453d72b012SDevendra Devadiga #define I2C4_BASE 0x30a50000 4678b3ea9cSJorge Ramirez-Ortiz 47e2cf992dSJorge Ramirez-Ortiz #define IOMUXC_I2C1_SCL_CFG_OFF 0x47C 48e2cf992dSJorge Ramirez-Ortiz #define IOMUXC_I2C1_SDA_CFG_OFF 0x480 49e2cf992dSJorge Ramirez-Ortiz #define IOMUXC_I2C1_SCL_MUX_OFF 0x214 50e2cf992dSJorge Ramirez-Ortiz #define IOMUXC_I2C1_SDA_MUX_OFF 0x218 5178b3ea9cSJorge Ramirez-Ortiz #endif 5278b3ea9cSJorge Ramirez-Ortiz 53a9edcef3SVanessa Maegima #if defined(CFG_MX8MP) 54a9edcef3SVanessa Maegima #define I2C1_BASE 0x30a20000 55a9edcef3SVanessa Maegima #define I2C2_BASE 0x30a30000 56a9edcef3SVanessa Maegima #define I2C3_BASE 0x30a40000 57a9edcef3SVanessa Maegima #define I2C4_BASE 0x30a50000 58a9edcef3SVanessa Maegima #define I2C5_BASE 0x30ad0000 59a9edcef3SVanessa Maegima #define I2C6_BASE 0x30ae0000 60a9edcef3SVanessa Maegima 61a9edcef3SVanessa Maegima #define IOMUXC_I2C1_SCL_CFG_OFF 0x460 62a9edcef3SVanessa Maegima #define IOMUXC_I2C1_SDA_CFG_OFF 0x464 63a9edcef3SVanessa Maegima #define IOMUXC_I2C1_SCL_MUX_OFF 0x200 64a9edcef3SVanessa Maegima #define IOMUXC_I2C1_SDA_MUX_OFF 0x204 65a9edcef3SVanessa Maegima #endif 66a9edcef3SVanessa Maegima 672a128a33SClement Faure #endif /* __IMX8M_H__ */ 68