| /optee_os/core/arch/arm/plat-uniphier/ |
| H A D | main.c | 29 #ifdef DRAM0_BASE
30 register_ddr(DRAM0_BASE, DRAM0_SIZE);
|
| H A D | platform_config.h | 49 #define DRAM0_BASE (CFG_DRAM0_BASE + CFG_DRAM0_RSV_SIZE) macro
|
| /optee_os/core/arch/arm/plat-automotive_rd/ |
| H A D | platform_config.h | 18 #define DRAM0_BASE UL(0x80000000) macro
42 #define DRAM0_BASE UL(0x80000000) macro
|
| /optee_os/core/arch/arm/plat-zynqmp/ |
| H A D | main.c | 72 register_ddr(DRAM0_BASE, 0x80000000);
75 register_ddr(DRAM0_BASE, CFG_DDR_SIZE);
|
| H A D | platform_config.h | 43 #define DRAM0_BASE 0 macro
|
| /optee_os/core/arch/arm/plat-hikey/ |
| H A D | platform_config.h | 107 #define DRAM0_BASE 0x00000000 macro
109 #define DRAM0_SIZE (CFG_TZDRAM_START - DRAM0_BASE)
|
| /optee_os/core/arch/arm/plat-stm/ |
| H A D | platform_config.h | 202 #define DRAM0_BASE (CFG_DDR_START + CFG_STM_RSV_DRAM_STARTBYTES) macro
203 #define DRAM0_SIZE (STM_SECDDR_BASE - DRAM0_BASE)
|
| H A D | main.c | 28 #ifdef DRAM0_BASE
29 register_ddr(DRAM0_BASE, DRAM0_SIZE);
|
| /optee_os/core/arch/arm/plat-vexpress/ |
| H A D | platform_config.h | 100 #define DRAM0_BASE 0x80000000 macro
121 #define DRAM0_BASE 0x80000000 macro
|
| /optee_os/core/arch/arm/plat-telechips/ |
| H A D | plat_tzc.c | 19 .base = CFG_TZDRAM_START - DRAM0_BASE, in tzc_protect_teeos()
20 .top = (CFG_TZDRAM_START + CFG_TZDRAM_SIZE - 1) - DRAM0_BASE, in tzc_protect_teeos()
|
| /optee_os/core/arch/arm/plat-rpi5/ |
| H A D | platform_config.h | 19 #define DRAM0_BASE 0x00000000 macro
|
| /optee_os/core/arch/arm/plat-rpi3/ |
| H A D | platform_config.h | 68 #define DRAM0_BASE 0x00000000 macro
|
| /optee_os/core/arch/arm/plat-synquacer/ |
| H A D | platform_config.h | 26 #define DRAM0_BASE 0x80000000 macro
|
| /optee_os/core/arch/arm/plat-d02/ |
| H A D | platform_config.h | 67 #define DRAM0_BASE 0x00000000 macro
|
| /optee_os/core/arch/arm/plat-nuvoton/ |
| H A D | platform_config.h | 14 #define DRAM0_BASE 0x00000000 macro
|
| /optee_os/core/arch/arm/plat-qcom/ |
| H A D | platform_config.h | 16 #define DRAM0_BASE UL(0x80000000) macro
|
| H A D | main.c | 24 register_ddr(DRAM0_BASE, DRAM0_SIZE);
|
| /optee_os/core/arch/arm/plat-totalcompute/ |
| H A D | platform_config.h | 28 #define DRAM0_BASE 0x80000000 macro
|
| H A D | main.c | 25 register_ddr(DRAM0_BASE, DRAM0_SIZE);
|
| /optee_os/core/arch/arm/plat-versal2/ |
| H A D | main.c | 32 register_ddr(DRAM0_BASE, DRAM0_SIZE);
|
| H A D | platform_config.h | 44 #define DRAM0_BASE 0 macro
|
| /optee_os/core/arch/arm/plat-corstone1000/ |
| H A D | platform_config.h | 20 #define DRAM0_BASE 0x80000000 macro
|
| H A D | main.c | 17 register_ddr(DRAM0_BASE, DRAM0_SIZE);
|
| /optee_os/core/arch/arm/plat-versal/ |
| H A D | platform_config.h | 33 #define DRAM0_BASE 0 macro
|
| /optee_os/core/arch/arm/plat-sprd/ |
| H A D | platform_config.h | 51 #define DRAM0_BASE 0x80000000 macro
|