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Searched refs:ddrc (Results 1 – 25 of 36) sorted by relevance

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/OK3568_Linux_fs/u-boot/board/atmel/sama5d2_ptc/
H A Dsama5d2_ptc.c208 static void ddrc_conf(struct atmel_mpddrc_config *ddrc) in ddrc_conf() argument
210 ddrc->md = (ATMEL_MPDDRC_MD_DBW_32_BITS | ATMEL_MPDDRC_MD_DDR3_SDRAM); in ddrc_conf()
212 ddrc->cr = (ATMEL_MPDDRC_CR_NC_COL_10 | in ddrc_conf()
221 ddrc->rtr = 0x511; in ddrc_conf()
223 ddrc->tpr0 = ((6 << ATMEL_MPDDRC_TPR0_TRAS_OFFSET) | in ddrc_conf()
232 ddrc->tpr1 = ((27 << ATMEL_MPDDRC_TPR1_TRFC_OFFSET) | in ddrc_conf()
237 ddrc->tpr2 = ((0 << ATMEL_MPDDRC_TPR2_TXARD_OFFSET) | in ddrc_conf()
/OK3568_Linux_fs/u-boot/board/atmel/sama5d2_xplained/
H A Dsama5d2_xplained.c219 static void ddrc_conf(struct atmel_mpddrc_config *ddrc) in ddrc_conf() argument
221 ddrc->md = (ATMEL_MPDDRC_MD_DBW_32_BITS | ATMEL_MPDDRC_MD_DDR3_SDRAM); in ddrc_conf()
223 ddrc->cr = (ATMEL_MPDDRC_CR_NC_COL_10 | in ddrc_conf()
232 ddrc->rtr = 0x511; in ddrc_conf()
234 ddrc->tpr0 = (6 << ATMEL_MPDDRC_TPR0_TRAS_OFFSET | in ddrc_conf()
243 ddrc->tpr1 = (27 << ATMEL_MPDDRC_TPR1_TRFC_OFFSET | in ddrc_conf()
248 ddrc->tpr2 = (0 << ATMEL_MPDDRC_TPR2_TXARD_OFFSET | in ddrc_conf()
/OK3568_Linux_fs/kernel/Documentation/devicetree/bindings/memory-controllers/
H A Dsynopsys.txt14 - 'xlnx,zynq-ddrc-a05' : Zynq DDR ECC controller
15 - 'xlnx,zynqmp-ddrc-2.40a' : ZynqMP DDR ECC controller
18 Required properties for "xlnx,zynqmp-ddrc-2.40a":
23 compatible = "xlnx,zynq-ddrc-a05";
28 compatible = "xlnx,zynqmp-ddrc-2.40a";
/OK3568_Linux_fs/kernel/Documentation/admin-guide/perf/
H A Dhisi-pmu.rst23 /sys/devices/hisi_sccl{X}_<l3c{Y}/hha{Y}/ddrc{Y}>/, or
24 /sys/bus/event_source/devices/hisi_sccl{X}_<l3c{Y}/hha{Y}/ddrc{Y}>.
/OK3568_Linux_fs/u-boot/arch/arm/mach-zynq/
H A DMakefile13 obj-y += ddrc.o
/OK3568_Linux_fs/kernel/drivers/devfreq/
H A DMakefile13 obj-$(CONFIG_ARM_IMX8M_DDRC_DEVFREQ) += imx8m-ddrc.o
/OK3568_Linux_fs/kernel/arch/mips/include/asm/mach-rc32434/
H A Dddr.h40 u32 ddrc; member
/OK3568_Linux_fs/u-boot/drivers/ddr/fsl/
H A Dctrl_regs.c2319 struct ccsr_ddr __iomem *ddrc; in compute_fsl_memctl_config_regs() local
2323 ddrc = (void *)CONFIG_SYS_FSL_DDR_ADDR; in compute_fsl_memctl_config_regs()
2327 ddrc = (void *)CONFIG_SYS_FSL_DDR2_ADDR; in compute_fsl_memctl_config_regs()
2332 ddrc = (void *)CONFIG_SYS_FSL_DDR3_ADDR; in compute_fsl_memctl_config_regs()
2337 ddrc = (void *)CONFIG_SYS_FSL_DDR4_ADDR; in compute_fsl_memctl_config_regs()
2572 ddr->debug[28] = ddr_in32(&ddrc->debug[28]); in compute_fsl_memctl_config_regs()
2580 ddr->debug[28] |= ddr_in32(&ddrc->debug[28]); in compute_fsl_memctl_config_regs()
/OK3568_Linux_fs/kernel/arch/arm64/boot/dts/freescale/
H A Dimx8mm-evk.dts20 &ddrc {
H A Dimx8mn-ddr4-evk.dts32 &ddrc {
H A Dimx8mn.dtsi834 ddrc: memory-controller@3d400000 { label
835 compatible = "fsl,imx8mn-ddrc", "fsl,imx8m-ddrc";
H A Dimx8mm.dtsi967 ddrc: memory-controller@3d400000 { label
968 compatible = "fsl,imx8mm-ddrc", "fsl,imx8m-ddrc";
H A Dimx8mm-beacon-som.dtsi27 &ddrc {
H A Dimx8mq-librem5.dtsi210 &ddrc {
213 ddrc_opp_table: ddrc-opp-table {
H A Dimx8mq.dtsi1322 ddrc: memory-controller@3d400000 { label
1323 compatible = "fsl,imx8mq-ddrc", "fsl,imx8m-ddrc";
H A Dimx8mq-evk.dts108 &ddrc {
H A Dimx8mm-var-som.dtsi50 &ddrc {
/OK3568_Linux_fs/u-boot/board/hisilicon/hikey/
H A DREADME123 INFO: lpddr3_freq_init, set ddrc 533mhz
126 INFO: lpddr3_freq_init, set ddrc 800mhz
/OK3568_Linux_fs/kernel/Documentation/devicetree/bindings/pinctrl/
H A Dnvidia,tegra20-pinmux.txt89 ck32, ddrc, pmca, pmcb, pmcc, pmcd, pmce, xm2c, xm2d, ls, lc, ld17_0,
/OK3568_Linux_fs/u-boot/arch/arm/dts/
H A Dzynq-7000.dtsi158 compatible = "xlnx,zynq-ddrc-a05";
H A Dtegra20-tamonten.dtsi183 nvidia,pins = "ck32", "ddrc", "pmca", "pmcb",
H A Dtegra20-paz00.dts227 nvidia,pins = "ck32", "ddrc", "pmca", "pmcb",
/OK3568_Linux_fs/kernel/arch/arm/boot/dts/
H A Dtegra20-trimslice.dts218 nvidia,pins = "ck32", "ddrc", "pmca", "pmcb",
H A Dzynq-7000.dtsi187 compatible = "xlnx,zynq-ddrc-a05";
H A Dtegra20-tamonten.dtsi195 nvidia,pins = "ck32", "ddrc", "pmca", "pmcb",

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