1*4882a593Smuzhiyun====================================================== 2*4882a593SmuzhiyunHiSilicon SoC uncore Performance Monitoring Unit (PMU) 3*4882a593Smuzhiyun====================================================== 4*4882a593Smuzhiyun 5*4882a593SmuzhiyunThe HiSilicon SoC chip includes various independent system device PMUs 6*4882a593Smuzhiyunsuch as L3 cache (L3C), Hydra Home Agent (HHA) and DDRC. These PMUs are 7*4882a593Smuzhiyunindependent and have hardware logic to gather statistics and performance 8*4882a593Smuzhiyuninformation. 9*4882a593Smuzhiyun 10*4882a593SmuzhiyunThe HiSilicon SoC encapsulates multiple CPU and IO dies. Each CPU cluster 11*4882a593Smuzhiyun(CCL) is made up of 4 cpu cores sharing one L3 cache; each CPU die is 12*4882a593Smuzhiyuncalled Super CPU cluster (SCCL) and is made up of 6 CCLs. Each SCCL has 13*4882a593Smuzhiyuntwo HHAs (0 - 1) and four DDRCs (0 - 3), respectively. 14*4882a593Smuzhiyun 15*4882a593SmuzhiyunHiSilicon SoC uncore PMU driver 16*4882a593Smuzhiyun------------------------------- 17*4882a593Smuzhiyun 18*4882a593SmuzhiyunEach device PMU has separate registers for event counting, control and 19*4882a593Smuzhiyuninterrupt, and the PMU driver shall register perf PMU drivers like L3C, 20*4882a593SmuzhiyunHHA and DDRC etc. The available events and configuration options shall 21*4882a593Smuzhiyunbe described in the sysfs, see: 22*4882a593Smuzhiyun 23*4882a593Smuzhiyun/sys/devices/hisi_sccl{X}_<l3c{Y}/hha{Y}/ddrc{Y}>/, or 24*4882a593Smuzhiyun/sys/bus/event_source/devices/hisi_sccl{X}_<l3c{Y}/hha{Y}/ddrc{Y}>. 25*4882a593SmuzhiyunThe "perf list" command shall list the available events from sysfs. 26*4882a593Smuzhiyun 27*4882a593SmuzhiyunEach L3C, HHA and DDRC is registered as a separate PMU with perf. The PMU 28*4882a593Smuzhiyunname will appear in event listing as hisi_sccl<sccl-id>_module<index-id>. 29*4882a593Smuzhiyunwhere "sccl-id" is the identifier of the SCCL and "index-id" is the index of 30*4882a593Smuzhiyunmodule. 31*4882a593Smuzhiyun 32*4882a593Smuzhiyune.g. hisi_sccl3_l3c0/rd_hit_cpipe is READ_HIT_CPIPE event of L3C index #0 in 33*4882a593SmuzhiyunSCCL ID #3. 34*4882a593Smuzhiyun 35*4882a593Smuzhiyune.g. hisi_sccl1_hha0/rx_operations is RX_OPERATIONS event of HHA index #0 in 36*4882a593SmuzhiyunSCCL ID #1. 37*4882a593Smuzhiyun 38*4882a593SmuzhiyunThe driver also provides a "cpumask" sysfs attribute, which shows the CPU core 39*4882a593SmuzhiyunID used to count the uncore PMU event. 40*4882a593Smuzhiyun 41*4882a593SmuzhiyunExample usage of perf:: 42*4882a593Smuzhiyun 43*4882a593Smuzhiyun $# perf list 44*4882a593Smuzhiyun hisi_sccl3_l3c0/rd_hit_cpipe/ [kernel PMU event] 45*4882a593Smuzhiyun ------------------------------------------ 46*4882a593Smuzhiyun hisi_sccl3_l3c0/wr_hit_cpipe/ [kernel PMU event] 47*4882a593Smuzhiyun ------------------------------------------ 48*4882a593Smuzhiyun hisi_sccl1_l3c0/rd_hit_cpipe/ [kernel PMU event] 49*4882a593Smuzhiyun ------------------------------------------ 50*4882a593Smuzhiyun hisi_sccl1_l3c0/wr_hit_cpipe/ [kernel PMU event] 51*4882a593Smuzhiyun ------------------------------------------ 52*4882a593Smuzhiyun 53*4882a593Smuzhiyun $# perf stat -a -e hisi_sccl3_l3c0/rd_hit_cpipe/ sleep 5 54*4882a593Smuzhiyun $# perf stat -a -e hisi_sccl3_l3c0/config=0x02/ sleep 5 55*4882a593Smuzhiyun 56*4882a593SmuzhiyunThe current driver does not support sampling. So "perf record" is unsupported. 57*4882a593SmuzhiyunAlso attach to a task is unsupported as the events are all uncore. 58*4882a593Smuzhiyun 59*4882a593SmuzhiyunNote: Please contact the maintainer for a complete list of events supported for 60*4882a593Smuzhiyunthe PMU devices in the SoC and its information if needed. 61