1*4882a593Smuzhiyun/dts-v1/; 2*4882a593Smuzhiyun 3*4882a593Smuzhiyun#include <dt-bindings/input/input.h> 4*4882a593Smuzhiyun#include "tegra20.dtsi" 5*4882a593Smuzhiyun 6*4882a593Smuzhiyun/ { 7*4882a593Smuzhiyun model = "Toshiba AC100 / Dynabook AZ"; 8*4882a593Smuzhiyun compatible = "compal,paz00", "nvidia,tegra20"; 9*4882a593Smuzhiyun 10*4882a593Smuzhiyun chosen { 11*4882a593Smuzhiyun stdout-path = &uarta; 12*4882a593Smuzhiyun }; 13*4882a593Smuzhiyun 14*4882a593Smuzhiyun aliases { 15*4882a593Smuzhiyun rtc0 = "/i2c@7000d000/tps6586x@34"; 16*4882a593Smuzhiyun rtc1 = "/rtc@7000e000"; 17*4882a593Smuzhiyun serial0 = &uarta; 18*4882a593Smuzhiyun serial1 = &uartc; 19*4882a593Smuzhiyun usb0 = "/usb@c5000000"; 20*4882a593Smuzhiyun usb1 = "/usb@c5004000"; 21*4882a593Smuzhiyun usb2 = "/usb@c5008000"; 22*4882a593Smuzhiyun mmc0 = "/sdhci@c8000600"; 23*4882a593Smuzhiyun mmc1 = "/sdhci@c8000000"; 24*4882a593Smuzhiyun }; 25*4882a593Smuzhiyun 26*4882a593Smuzhiyun memory { 27*4882a593Smuzhiyun reg = <0x00000000 0x20000000>; 28*4882a593Smuzhiyun }; 29*4882a593Smuzhiyun 30*4882a593Smuzhiyun host1x@50000000 { 31*4882a593Smuzhiyun status = "okay"; 32*4882a593Smuzhiyun dc@54200000 { 33*4882a593Smuzhiyun status = "okay"; 34*4882a593Smuzhiyun rgb { 35*4882a593Smuzhiyun status = "okay"; 36*4882a593Smuzhiyun 37*4882a593Smuzhiyun nvidia,panel = <&panel>; 38*4882a593Smuzhiyun 39*4882a593Smuzhiyun display-timings { 40*4882a593Smuzhiyun timing@0 { 41*4882a593Smuzhiyun /* PAZ00 has 1024x600 */ 42*4882a593Smuzhiyun clock-frequency = <54030000>; 43*4882a593Smuzhiyun hactive = <1024>; 44*4882a593Smuzhiyun vactive = <600>; 45*4882a593Smuzhiyun hback-porch = <160>; 46*4882a593Smuzhiyun hfront-porch = <24>; 47*4882a593Smuzhiyun hsync-len = <136>; 48*4882a593Smuzhiyun vback-porch = <3>; 49*4882a593Smuzhiyun vfront-porch = <61>; 50*4882a593Smuzhiyun vsync-len = <6>; 51*4882a593Smuzhiyun hsync-active = <1>; 52*4882a593Smuzhiyun }; 53*4882a593Smuzhiyun }; 54*4882a593Smuzhiyun }; 55*4882a593Smuzhiyun }; 56*4882a593Smuzhiyun 57*4882a593Smuzhiyun hdmi@54280000 { 58*4882a593Smuzhiyun status = "okay"; 59*4882a593Smuzhiyun 60*4882a593Smuzhiyun vdd-supply = <&hdmi_vdd_reg>; 61*4882a593Smuzhiyun pll-supply = <&hdmi_pll_reg>; 62*4882a593Smuzhiyun 63*4882a593Smuzhiyun nvidia,ddc-i2c-bus = <&hdmi_ddc>; 64*4882a593Smuzhiyun nvidia,hpd-gpio = <&gpio TEGRA_GPIO(N, 7) 65*4882a593Smuzhiyun GPIO_ACTIVE_HIGH>; 66*4882a593Smuzhiyun }; 67*4882a593Smuzhiyun }; 68*4882a593Smuzhiyun 69*4882a593Smuzhiyun pinmux@70000014 { 70*4882a593Smuzhiyun pinctrl-names = "default"; 71*4882a593Smuzhiyun pinctrl-0 = <&state_default>; 72*4882a593Smuzhiyun 73*4882a593Smuzhiyun state_default: pinmux { 74*4882a593Smuzhiyun ata { 75*4882a593Smuzhiyun nvidia,pins = "ata", "atc", "atd", "ate", 76*4882a593Smuzhiyun "dap2", "gmb", "gmc", "gmd", "spia", 77*4882a593Smuzhiyun "spib", "spic", "spid", "spie"; 78*4882a593Smuzhiyun nvidia,function = "gmi"; 79*4882a593Smuzhiyun }; 80*4882a593Smuzhiyun atb { 81*4882a593Smuzhiyun nvidia,pins = "atb", "gma", "gme"; 82*4882a593Smuzhiyun nvidia,function = "sdio4"; 83*4882a593Smuzhiyun }; 84*4882a593Smuzhiyun cdev1 { 85*4882a593Smuzhiyun nvidia,pins = "cdev1"; 86*4882a593Smuzhiyun nvidia,function = "plla_out"; 87*4882a593Smuzhiyun }; 88*4882a593Smuzhiyun cdev2 { 89*4882a593Smuzhiyun nvidia,pins = "cdev2"; 90*4882a593Smuzhiyun nvidia,function = "pllp_out4"; 91*4882a593Smuzhiyun }; 92*4882a593Smuzhiyun crtp { 93*4882a593Smuzhiyun nvidia,pins = "crtp"; 94*4882a593Smuzhiyun nvidia,function = "crt"; 95*4882a593Smuzhiyun }; 96*4882a593Smuzhiyun csus { 97*4882a593Smuzhiyun nvidia,pins = "csus"; 98*4882a593Smuzhiyun nvidia,function = "pllc_out1"; 99*4882a593Smuzhiyun }; 100*4882a593Smuzhiyun dap1 { 101*4882a593Smuzhiyun nvidia,pins = "dap1"; 102*4882a593Smuzhiyun nvidia,function = "dap1"; 103*4882a593Smuzhiyun }; 104*4882a593Smuzhiyun dap3 { 105*4882a593Smuzhiyun nvidia,pins = "dap3"; 106*4882a593Smuzhiyun nvidia,function = "dap3"; 107*4882a593Smuzhiyun }; 108*4882a593Smuzhiyun dap4 { 109*4882a593Smuzhiyun nvidia,pins = "dap4"; 110*4882a593Smuzhiyun nvidia,function = "dap4"; 111*4882a593Smuzhiyun }; 112*4882a593Smuzhiyun ddc { 113*4882a593Smuzhiyun nvidia,pins = "ddc"; 114*4882a593Smuzhiyun nvidia,function = "i2c2"; 115*4882a593Smuzhiyun }; 116*4882a593Smuzhiyun dta { 117*4882a593Smuzhiyun nvidia,pins = "dta", "dtb", "dtc", "dtd", "dte"; 118*4882a593Smuzhiyun nvidia,function = "rsvd1"; 119*4882a593Smuzhiyun }; 120*4882a593Smuzhiyun dtf { 121*4882a593Smuzhiyun nvidia,pins = "dtf"; 122*4882a593Smuzhiyun nvidia,function = "i2c3"; 123*4882a593Smuzhiyun }; 124*4882a593Smuzhiyun gpu { 125*4882a593Smuzhiyun nvidia,pins = "gpu", "sdb", "sdd"; 126*4882a593Smuzhiyun nvidia,function = "pwm"; 127*4882a593Smuzhiyun }; 128*4882a593Smuzhiyun gpu7 { 129*4882a593Smuzhiyun nvidia,pins = "gpu7"; 130*4882a593Smuzhiyun nvidia,function = "rtck"; 131*4882a593Smuzhiyun }; 132*4882a593Smuzhiyun gpv { 133*4882a593Smuzhiyun nvidia,pins = "gpv", "slxa", "slxk"; 134*4882a593Smuzhiyun nvidia,function = "pcie"; 135*4882a593Smuzhiyun }; 136*4882a593Smuzhiyun hdint { 137*4882a593Smuzhiyun nvidia,pins = "hdint", "pta"; 138*4882a593Smuzhiyun nvidia,function = "hdmi"; 139*4882a593Smuzhiyun }; 140*4882a593Smuzhiyun i2cp { 141*4882a593Smuzhiyun nvidia,pins = "i2cp"; 142*4882a593Smuzhiyun nvidia,function = "i2cp"; 143*4882a593Smuzhiyun }; 144*4882a593Smuzhiyun irrx { 145*4882a593Smuzhiyun nvidia,pins = "irrx", "irtx"; 146*4882a593Smuzhiyun nvidia,function = "uarta"; 147*4882a593Smuzhiyun }; 148*4882a593Smuzhiyun kbca { 149*4882a593Smuzhiyun nvidia,pins = "kbca", "kbcc", "kbce", "kbcf"; 150*4882a593Smuzhiyun nvidia,function = "kbc"; 151*4882a593Smuzhiyun }; 152*4882a593Smuzhiyun kbcb { 153*4882a593Smuzhiyun nvidia,pins = "kbcb", "kbcd"; 154*4882a593Smuzhiyun nvidia,function = "sdio2"; 155*4882a593Smuzhiyun }; 156*4882a593Smuzhiyun lcsn { 157*4882a593Smuzhiyun nvidia,pins = "lcsn", "ld0", "ld1", "ld2", 158*4882a593Smuzhiyun "ld3", "ld4", "ld5", "ld6", "ld7", 159*4882a593Smuzhiyun "ld8", "ld9", "ld10", "ld11", "ld12", 160*4882a593Smuzhiyun "ld13", "ld14", "ld15", "ld16", "ld17", 161*4882a593Smuzhiyun "ldc", "ldi", "lhp0", "lhp1", "lhp2", 162*4882a593Smuzhiyun "lhs", "lm0", "lm1", "lpp", "lpw0", 163*4882a593Smuzhiyun "lpw1", "lpw2", "lsc0", "lsc1", "lsck", 164*4882a593Smuzhiyun "lsda", "lsdi", "lspi", "lvp0", "lvp1", 165*4882a593Smuzhiyun "lvs"; 166*4882a593Smuzhiyun nvidia,function = "displaya"; 167*4882a593Smuzhiyun }; 168*4882a593Smuzhiyun owc { 169*4882a593Smuzhiyun nvidia,pins = "owc"; 170*4882a593Smuzhiyun nvidia,function = "owr"; 171*4882a593Smuzhiyun }; 172*4882a593Smuzhiyun pmc { 173*4882a593Smuzhiyun nvidia,pins = "pmc"; 174*4882a593Smuzhiyun nvidia,function = "pwr_on"; 175*4882a593Smuzhiyun }; 176*4882a593Smuzhiyun rm { 177*4882a593Smuzhiyun nvidia,pins = "rm"; 178*4882a593Smuzhiyun nvidia,function = "i2c1"; 179*4882a593Smuzhiyun }; 180*4882a593Smuzhiyun sdc { 181*4882a593Smuzhiyun nvidia,pins = "sdc"; 182*4882a593Smuzhiyun nvidia,function = "twc"; 183*4882a593Smuzhiyun }; 184*4882a593Smuzhiyun sdio1 { 185*4882a593Smuzhiyun nvidia,pins = "sdio1"; 186*4882a593Smuzhiyun nvidia,function = "sdio1"; 187*4882a593Smuzhiyun }; 188*4882a593Smuzhiyun slxc { 189*4882a593Smuzhiyun nvidia,pins = "slxc", "slxd"; 190*4882a593Smuzhiyun nvidia,function = "spi4"; 191*4882a593Smuzhiyun }; 192*4882a593Smuzhiyun spdi { 193*4882a593Smuzhiyun nvidia,pins = "spdi", "spdo"; 194*4882a593Smuzhiyun nvidia,function = "rsvd2"; 195*4882a593Smuzhiyun }; 196*4882a593Smuzhiyun spif { 197*4882a593Smuzhiyun nvidia,pins = "spif", "uac"; 198*4882a593Smuzhiyun nvidia,function = "rsvd4"; 199*4882a593Smuzhiyun }; 200*4882a593Smuzhiyun spig { 201*4882a593Smuzhiyun nvidia,pins = "spig", "spih"; 202*4882a593Smuzhiyun nvidia,function = "spi2_alt"; 203*4882a593Smuzhiyun }; 204*4882a593Smuzhiyun uaa { 205*4882a593Smuzhiyun nvidia,pins = "uaa", "uab", "uda"; 206*4882a593Smuzhiyun nvidia,function = "ulpi"; 207*4882a593Smuzhiyun }; 208*4882a593Smuzhiyun uad { 209*4882a593Smuzhiyun nvidia,pins = "uad"; 210*4882a593Smuzhiyun nvidia,function = "spdif"; 211*4882a593Smuzhiyun }; 212*4882a593Smuzhiyun uca { 213*4882a593Smuzhiyun nvidia,pins = "uca", "ucb"; 214*4882a593Smuzhiyun nvidia,function = "uartc"; 215*4882a593Smuzhiyun }; 216*4882a593Smuzhiyun conf_ata { 217*4882a593Smuzhiyun nvidia,pins = "ata", "atb", "atc", "atd", "ate", 218*4882a593Smuzhiyun "cdev1", "cdev2", "dap1", "dap2", "dtf", 219*4882a593Smuzhiyun "gma", "gmb", "gmc", "gmd", "gme", 220*4882a593Smuzhiyun "gpu", "gpu7", "gpv", "i2cp", "pta", 221*4882a593Smuzhiyun "rm", "sdio1", "slxk", "spdo", "uac", 222*4882a593Smuzhiyun "uda"; 223*4882a593Smuzhiyun nvidia,pull = <TEGRA_PIN_PULL_NONE>; 224*4882a593Smuzhiyun nvidia,tristate = <TEGRA_PIN_DISABLE>; 225*4882a593Smuzhiyun }; 226*4882a593Smuzhiyun conf_ck32 { 227*4882a593Smuzhiyun nvidia,pins = "ck32", "ddrc", "pmca", "pmcb", 228*4882a593Smuzhiyun "pmcc", "pmcd", "pmce", "xm2c", "xm2d"; 229*4882a593Smuzhiyun nvidia,pull = <TEGRA_PIN_PULL_NONE>; 230*4882a593Smuzhiyun }; 231*4882a593Smuzhiyun conf_crtp { 232*4882a593Smuzhiyun nvidia,pins = "crtp", "dap3", "dap4", "dtb", 233*4882a593Smuzhiyun "dtc", "dte", "slxa", "slxc", "slxd", 234*4882a593Smuzhiyun "spdi"; 235*4882a593Smuzhiyun nvidia,pull = <TEGRA_PIN_PULL_NONE>; 236*4882a593Smuzhiyun nvidia,tristate = <TEGRA_PIN_ENABLE>; 237*4882a593Smuzhiyun }; 238*4882a593Smuzhiyun conf_csus { 239*4882a593Smuzhiyun nvidia,pins = "csus", "spia", "spib", "spid", 240*4882a593Smuzhiyun "spif"; 241*4882a593Smuzhiyun nvidia,pull = <TEGRA_PIN_PULL_DOWN>; 242*4882a593Smuzhiyun nvidia,tristate = <TEGRA_PIN_ENABLE>; 243*4882a593Smuzhiyun }; 244*4882a593Smuzhiyun conf_ddc { 245*4882a593Smuzhiyun nvidia,pins = "ddc", "irrx", "irtx", "kbca", 246*4882a593Smuzhiyun "kbcb", "kbcc", "kbcd", "kbce", "kbcf", 247*4882a593Smuzhiyun "spic", "spig", "uaa", "uab"; 248*4882a593Smuzhiyun nvidia,pull = <TEGRA_PIN_PULL_UP>; 249*4882a593Smuzhiyun nvidia,tristate = <TEGRA_PIN_DISABLE>; 250*4882a593Smuzhiyun }; 251*4882a593Smuzhiyun conf_dta { 252*4882a593Smuzhiyun nvidia,pins = "dta", "dtd", "owc", "sdc", "sdd", 253*4882a593Smuzhiyun "spie", "spih", "uad", "uca", "ucb"; 254*4882a593Smuzhiyun nvidia,pull = <TEGRA_PIN_PULL_UP>; 255*4882a593Smuzhiyun nvidia,tristate = <TEGRA_PIN_ENABLE>; 256*4882a593Smuzhiyun }; 257*4882a593Smuzhiyun conf_hdint { 258*4882a593Smuzhiyun nvidia,pins = "hdint", "ld0", "ld1", "ld2", 259*4882a593Smuzhiyun "ld3", "ld4", "ld5", "ld6", "ld7", 260*4882a593Smuzhiyun "ld8", "ld9", "ld10", "ld11", "ld12", 261*4882a593Smuzhiyun "ld13", "ld14", "ld15", "ld16", "ld17", 262*4882a593Smuzhiyun "ldc", "ldi", "lhs", "lsc0", "lspi", 263*4882a593Smuzhiyun "lvs", "pmc"; 264*4882a593Smuzhiyun nvidia,tristate = <TEGRA_PIN_DISABLE>; 265*4882a593Smuzhiyun }; 266*4882a593Smuzhiyun conf_lc { 267*4882a593Smuzhiyun nvidia,pins = "lc", "ls"; 268*4882a593Smuzhiyun nvidia,pull = <TEGRA_PIN_PULL_UP>; 269*4882a593Smuzhiyun }; 270*4882a593Smuzhiyun conf_lcsn { 271*4882a593Smuzhiyun nvidia,pins = "lcsn", "lhp0", "lhp1", "lhp2", 272*4882a593Smuzhiyun "lm0", "lm1", "lpp", "lpw0", "lpw1", 273*4882a593Smuzhiyun "lpw2", "lsc1", "lsck", "lsda", "lsdi", 274*4882a593Smuzhiyun "lvp0", "lvp1", "sdb"; 275*4882a593Smuzhiyun nvidia,tristate = <TEGRA_PIN_ENABLE>; 276*4882a593Smuzhiyun }; 277*4882a593Smuzhiyun conf_ld17_0 { 278*4882a593Smuzhiyun nvidia,pins = "ld17_0", "ld19_18", "ld21_20", 279*4882a593Smuzhiyun "ld23_22"; 280*4882a593Smuzhiyun nvidia,pull = <TEGRA_PIN_PULL_DOWN>; 281*4882a593Smuzhiyun }; 282*4882a593Smuzhiyun }; 283*4882a593Smuzhiyun }; 284*4882a593Smuzhiyun 285*4882a593Smuzhiyun i2s@70002800 { 286*4882a593Smuzhiyun status = "okay"; 287*4882a593Smuzhiyun }; 288*4882a593Smuzhiyun 289*4882a593Smuzhiyun serial@70006000 { 290*4882a593Smuzhiyun status = "okay"; 291*4882a593Smuzhiyun }; 292*4882a593Smuzhiyun 293*4882a593Smuzhiyun serial@70006200 { 294*4882a593Smuzhiyun status = "okay"; 295*4882a593Smuzhiyun }; 296*4882a593Smuzhiyun 297*4882a593Smuzhiyun pwm: pwm@7000a000 { 298*4882a593Smuzhiyun status = "okay"; 299*4882a593Smuzhiyun }; 300*4882a593Smuzhiyun 301*4882a593Smuzhiyun lvds_ddc: i2c@7000c000 { 302*4882a593Smuzhiyun status = "okay"; 303*4882a593Smuzhiyun clock-frequency = <400000>; 304*4882a593Smuzhiyun 305*4882a593Smuzhiyun alc5632: alc5632@1e { 306*4882a593Smuzhiyun compatible = "realtek,alc5632"; 307*4882a593Smuzhiyun reg = <0x1e>; 308*4882a593Smuzhiyun gpio-controller; 309*4882a593Smuzhiyun #gpio-cells = <2>; 310*4882a593Smuzhiyun }; 311*4882a593Smuzhiyun }; 312*4882a593Smuzhiyun 313*4882a593Smuzhiyun hdmi_ddc: i2c@7000c400 { 314*4882a593Smuzhiyun status = "okay"; 315*4882a593Smuzhiyun clock-frequency = <100000>; 316*4882a593Smuzhiyun }; 317*4882a593Smuzhiyun 318*4882a593Smuzhiyun nvec@7000c500 { 319*4882a593Smuzhiyun compatible = "nvidia,nvec"; 320*4882a593Smuzhiyun reg = <0x7000c500 0x100>; 321*4882a593Smuzhiyun interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>; 322*4882a593Smuzhiyun #address-cells = <1>; 323*4882a593Smuzhiyun #size-cells = <0>; 324*4882a593Smuzhiyun clock-frequency = <80000>; 325*4882a593Smuzhiyun request-gpios = <&gpio TEGRA_GPIO(V, 2) GPIO_ACTIVE_HIGH>; 326*4882a593Smuzhiyun slave-addr = <138>; 327*4882a593Smuzhiyun clocks = <&tegra_car TEGRA20_CLK_I2C3>, 328*4882a593Smuzhiyun <&tegra_car TEGRA20_CLK_PLL_P_OUT3>; 329*4882a593Smuzhiyun clock-names = "div-clk", "fast-clk"; 330*4882a593Smuzhiyun resets = <&tegra_car 67>; 331*4882a593Smuzhiyun reset-names = "i2c"; 332*4882a593Smuzhiyun }; 333*4882a593Smuzhiyun 334*4882a593Smuzhiyun i2c@7000d000 { 335*4882a593Smuzhiyun status = "okay"; 336*4882a593Smuzhiyun clock-frequency = <400000>; 337*4882a593Smuzhiyun 338*4882a593Smuzhiyun pmic: tps6586x@34 { 339*4882a593Smuzhiyun compatible = "ti,tps6586x"; 340*4882a593Smuzhiyun reg = <0x34>; 341*4882a593Smuzhiyun interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>; 342*4882a593Smuzhiyun 343*4882a593Smuzhiyun #gpio-cells = <2>; 344*4882a593Smuzhiyun gpio-controller; 345*4882a593Smuzhiyun 346*4882a593Smuzhiyun sys-supply = <&p5valw_reg>; 347*4882a593Smuzhiyun vin-sm0-supply = <&sys_reg>; 348*4882a593Smuzhiyun vin-sm1-supply = <&sys_reg>; 349*4882a593Smuzhiyun vin-sm2-supply = <&sys_reg>; 350*4882a593Smuzhiyun vinldo01-supply = <&sm2_reg>; 351*4882a593Smuzhiyun vinldo23-supply = <&sm2_reg>; 352*4882a593Smuzhiyun vinldo4-supply = <&sm2_reg>; 353*4882a593Smuzhiyun vinldo678-supply = <&sm2_reg>; 354*4882a593Smuzhiyun vinldo9-supply = <&sm2_reg>; 355*4882a593Smuzhiyun 356*4882a593Smuzhiyun regulators { 357*4882a593Smuzhiyun sys_reg: sys { 358*4882a593Smuzhiyun regulator-name = "vdd_sys"; 359*4882a593Smuzhiyun regulator-always-on; 360*4882a593Smuzhiyun }; 361*4882a593Smuzhiyun 362*4882a593Smuzhiyun sm0 { 363*4882a593Smuzhiyun regulator-name = "+1.2vs_sm0,vdd_core"; 364*4882a593Smuzhiyun regulator-min-microvolt = <1200000>; 365*4882a593Smuzhiyun regulator-max-microvolt = <1200000>; 366*4882a593Smuzhiyun regulator-always-on; 367*4882a593Smuzhiyun }; 368*4882a593Smuzhiyun 369*4882a593Smuzhiyun sm1 { 370*4882a593Smuzhiyun regulator-name = "+1.0vs_sm1,vdd_cpu"; 371*4882a593Smuzhiyun regulator-min-microvolt = <1000000>; 372*4882a593Smuzhiyun regulator-max-microvolt = <1000000>; 373*4882a593Smuzhiyun regulator-always-on; 374*4882a593Smuzhiyun }; 375*4882a593Smuzhiyun 376*4882a593Smuzhiyun sm2_reg: sm2 { 377*4882a593Smuzhiyun regulator-name = "+3.7vs_sm2,vin_ldo*"; 378*4882a593Smuzhiyun regulator-min-microvolt = <3700000>; 379*4882a593Smuzhiyun regulator-max-microvolt = <3700000>; 380*4882a593Smuzhiyun regulator-always-on; 381*4882a593Smuzhiyun }; 382*4882a593Smuzhiyun 383*4882a593Smuzhiyun /* LDO0 is not connected to anything */ 384*4882a593Smuzhiyun 385*4882a593Smuzhiyun ldo1 { 386*4882a593Smuzhiyun regulator-name = "+1.1vs_ldo1,avdd_pll*"; 387*4882a593Smuzhiyun regulator-min-microvolt = <1100000>; 388*4882a593Smuzhiyun regulator-max-microvolt = <1100000>; 389*4882a593Smuzhiyun regulator-always-on; 390*4882a593Smuzhiyun }; 391*4882a593Smuzhiyun 392*4882a593Smuzhiyun ldo2 { 393*4882a593Smuzhiyun regulator-name = "+1.2vs_ldo2,vdd_rtc"; 394*4882a593Smuzhiyun regulator-min-microvolt = <1200000>; 395*4882a593Smuzhiyun regulator-max-microvolt = <1200000>; 396*4882a593Smuzhiyun }; 397*4882a593Smuzhiyun 398*4882a593Smuzhiyun ldo3 { 399*4882a593Smuzhiyun regulator-name = "+3.3vs_ldo3,avdd_usb*"; 400*4882a593Smuzhiyun regulator-min-microvolt = <3300000>; 401*4882a593Smuzhiyun regulator-max-microvolt = <3300000>; 402*4882a593Smuzhiyun regulator-always-on; 403*4882a593Smuzhiyun }; 404*4882a593Smuzhiyun 405*4882a593Smuzhiyun ldo4 { 406*4882a593Smuzhiyun regulator-name = "+1.8vs_ldo4,avdd_osc,vddio_sys"; 407*4882a593Smuzhiyun regulator-min-microvolt = <1800000>; 408*4882a593Smuzhiyun regulator-max-microvolt = <1800000>; 409*4882a593Smuzhiyun regulator-always-on; 410*4882a593Smuzhiyun }; 411*4882a593Smuzhiyun 412*4882a593Smuzhiyun ldo5 { 413*4882a593Smuzhiyun regulator-name = "+2.85vs_ldo5,vcore_mmc"; 414*4882a593Smuzhiyun regulator-min-microvolt = <2850000>; 415*4882a593Smuzhiyun regulator-max-microvolt = <2850000>; 416*4882a593Smuzhiyun regulator-always-on; 417*4882a593Smuzhiyun }; 418*4882a593Smuzhiyun 419*4882a593Smuzhiyun ldo6 { 420*4882a593Smuzhiyun /* 421*4882a593Smuzhiyun * Research indicates this should be 422*4882a593Smuzhiyun * 1.8v; other boards that use this 423*4882a593Smuzhiyun * rail for the same purpose need it 424*4882a593Smuzhiyun * set to 1.8v. The schematic signal 425*4882a593Smuzhiyun * name is incorrect; perhaps copied 426*4882a593Smuzhiyun * from an incorrect NVIDIA reference. 427*4882a593Smuzhiyun */ 428*4882a593Smuzhiyun regulator-name = "+2.85vs_ldo6,avdd_vdac"; 429*4882a593Smuzhiyun regulator-min-microvolt = <1800000>; 430*4882a593Smuzhiyun regulator-max-microvolt = <1800000>; 431*4882a593Smuzhiyun }; 432*4882a593Smuzhiyun 433*4882a593Smuzhiyun hdmi_vdd_reg: ldo7 { 434*4882a593Smuzhiyun regulator-name = "+3.3vs_ldo7,avdd_hdmi"; 435*4882a593Smuzhiyun regulator-min-microvolt = <3300000>; 436*4882a593Smuzhiyun regulator-max-microvolt = <3300000>; 437*4882a593Smuzhiyun }; 438*4882a593Smuzhiyun 439*4882a593Smuzhiyun hdmi_pll_reg: ldo8 { 440*4882a593Smuzhiyun regulator-name = "+1.8vs_ldo8,avdd_hdmi_pll"; 441*4882a593Smuzhiyun regulator-min-microvolt = <1800000>; 442*4882a593Smuzhiyun regulator-max-microvolt = <1800000>; 443*4882a593Smuzhiyun }; 444*4882a593Smuzhiyun 445*4882a593Smuzhiyun ldo9 { 446*4882a593Smuzhiyun regulator-name = "+2.85vs_ldo9,vdd_ddr_rx"; 447*4882a593Smuzhiyun regulator-min-microvolt = <2850000>; 448*4882a593Smuzhiyun regulator-max-microvolt = <2850000>; 449*4882a593Smuzhiyun regulator-always-on; 450*4882a593Smuzhiyun }; 451*4882a593Smuzhiyun 452*4882a593Smuzhiyun ldo_rtc { 453*4882a593Smuzhiyun regulator-name = "+3.3vs_rtc"; 454*4882a593Smuzhiyun regulator-min-microvolt = <3300000>; 455*4882a593Smuzhiyun regulator-max-microvolt = <3300000>; 456*4882a593Smuzhiyun regulator-always-on; 457*4882a593Smuzhiyun }; 458*4882a593Smuzhiyun }; 459*4882a593Smuzhiyun }; 460*4882a593Smuzhiyun 461*4882a593Smuzhiyun adt7461@4c { 462*4882a593Smuzhiyun compatible = "adi,adt7461"; 463*4882a593Smuzhiyun reg = <0x4c>; 464*4882a593Smuzhiyun }; 465*4882a593Smuzhiyun }; 466*4882a593Smuzhiyun 467*4882a593Smuzhiyun pmc@7000e400 { 468*4882a593Smuzhiyun nvidia,invert-interrupt; 469*4882a593Smuzhiyun nvidia,suspend-mode = <1>; 470*4882a593Smuzhiyun nvidia,cpu-pwr-good-time = <2000>; 471*4882a593Smuzhiyun nvidia,cpu-pwr-off-time = <0>; 472*4882a593Smuzhiyun nvidia,core-pwr-good-time = <3845 3845>; 473*4882a593Smuzhiyun nvidia,core-pwr-off-time = <0>; 474*4882a593Smuzhiyun nvidia,sys-clock-req-active-high; 475*4882a593Smuzhiyun }; 476*4882a593Smuzhiyun 477*4882a593Smuzhiyun usb@c5000000 { 478*4882a593Smuzhiyun status = "okay"; 479*4882a593Smuzhiyun }; 480*4882a593Smuzhiyun 481*4882a593Smuzhiyun usb-phy@c5000000 { 482*4882a593Smuzhiyun status = "okay"; 483*4882a593Smuzhiyun }; 484*4882a593Smuzhiyun 485*4882a593Smuzhiyun usb@c5004000 { 486*4882a593Smuzhiyun status = "okay"; 487*4882a593Smuzhiyun nvidia,phy-reset-gpio = <&gpio TEGRA_GPIO(V, 0) 488*4882a593Smuzhiyun GPIO_ACTIVE_LOW>; 489*4882a593Smuzhiyun }; 490*4882a593Smuzhiyun 491*4882a593Smuzhiyun usb-phy@c5004000 { 492*4882a593Smuzhiyun status = "okay"; 493*4882a593Smuzhiyun nvidia,phy-reset-gpio = <&gpio TEGRA_GPIO(V, 0) 494*4882a593Smuzhiyun GPIO_ACTIVE_LOW>; 495*4882a593Smuzhiyun }; 496*4882a593Smuzhiyun 497*4882a593Smuzhiyun usb@c5008000 { 498*4882a593Smuzhiyun status = "okay"; 499*4882a593Smuzhiyun }; 500*4882a593Smuzhiyun 501*4882a593Smuzhiyun usb-phy@c5008000 { 502*4882a593Smuzhiyun status = "okay"; 503*4882a593Smuzhiyun }; 504*4882a593Smuzhiyun 505*4882a593Smuzhiyun sdhci@c8000000 { 506*4882a593Smuzhiyun status = "okay"; 507*4882a593Smuzhiyun cd-gpios = <&gpio TEGRA_GPIO(V, 5) GPIO_ACTIVE_LOW>; 508*4882a593Smuzhiyun wp-gpios = <&gpio TEGRA_GPIO(H, 1) GPIO_ACTIVE_HIGH>; 509*4882a593Smuzhiyun power-gpios = <&gpio TEGRA_GPIO(V, 1) GPIO_ACTIVE_HIGH>; 510*4882a593Smuzhiyun bus-width = <4>; 511*4882a593Smuzhiyun }; 512*4882a593Smuzhiyun 513*4882a593Smuzhiyun sdhci@c8000600 { 514*4882a593Smuzhiyun status = "okay"; 515*4882a593Smuzhiyun bus-width = <8>; 516*4882a593Smuzhiyun non-removable; 517*4882a593Smuzhiyun }; 518*4882a593Smuzhiyun 519*4882a593Smuzhiyun backlight: backlight { 520*4882a593Smuzhiyun compatible = "pwm-backlight"; 521*4882a593Smuzhiyun 522*4882a593Smuzhiyun enable-gpios = <&gpio TEGRA_GPIO(U, 4) GPIO_ACTIVE_HIGH>; 523*4882a593Smuzhiyun power-supply = <&vdd_bl_reg>; 524*4882a593Smuzhiyun pwms = <&pwm 0 5000000>; 525*4882a593Smuzhiyun 526*4882a593Smuzhiyun brightness-levels = <0 16 32 48 64 80 96 112 128 144 160 176 192 208 224 240 255>; 527*4882a593Smuzhiyun default-brightness-level = <10>; 528*4882a593Smuzhiyun 529*4882a593Smuzhiyun backlight-boot-off; 530*4882a593Smuzhiyun }; 531*4882a593Smuzhiyun 532*4882a593Smuzhiyun clocks { 533*4882a593Smuzhiyun compatible = "simple-bus"; 534*4882a593Smuzhiyun #address-cells = <1>; 535*4882a593Smuzhiyun #size-cells = <0>; 536*4882a593Smuzhiyun 537*4882a593Smuzhiyun clk32k_in: clock@0 { 538*4882a593Smuzhiyun compatible = "fixed-clock"; 539*4882a593Smuzhiyun reg = <0>; 540*4882a593Smuzhiyun #clock-cells = <0>; 541*4882a593Smuzhiyun clock-frequency = <32768>; 542*4882a593Smuzhiyun }; 543*4882a593Smuzhiyun }; 544*4882a593Smuzhiyun 545*4882a593Smuzhiyun gpio-keys { 546*4882a593Smuzhiyun compatible = "gpio-keys"; 547*4882a593Smuzhiyun 548*4882a593Smuzhiyun power { 549*4882a593Smuzhiyun label = "Power"; 550*4882a593Smuzhiyun gpios = <&gpio TEGRA_GPIO(J, 7) GPIO_ACTIVE_LOW>; 551*4882a593Smuzhiyun linux,code = <KEY_POWER>; 552*4882a593Smuzhiyun wakeup-source; 553*4882a593Smuzhiyun }; 554*4882a593Smuzhiyun }; 555*4882a593Smuzhiyun 556*4882a593Smuzhiyun gpio-leds { 557*4882a593Smuzhiyun compatible = "gpio-leds"; 558*4882a593Smuzhiyun 559*4882a593Smuzhiyun wifi { 560*4882a593Smuzhiyun label = "wifi-led"; 561*4882a593Smuzhiyun gpios = <&gpio TEGRA_GPIO(D, 0) GPIO_ACTIVE_HIGH>; 562*4882a593Smuzhiyun linux,default-trigger = "rfkill0"; 563*4882a593Smuzhiyun }; 564*4882a593Smuzhiyun }; 565*4882a593Smuzhiyun 566*4882a593Smuzhiyun panel: panel { 567*4882a593Smuzhiyun compatible = "samsung,ltn101nt05", "simple-panel"; 568*4882a593Smuzhiyun 569*4882a593Smuzhiyun ddc-i2c-bus = <&lvds_ddc>; 570*4882a593Smuzhiyun power-supply = <&vdd_pnl_reg>; 571*4882a593Smuzhiyun enable-gpios = <&gpio TEGRA_GPIO(M, 6) GPIO_ACTIVE_HIGH>; 572*4882a593Smuzhiyun 573*4882a593Smuzhiyun backlight = <&backlight>; 574*4882a593Smuzhiyun }; 575*4882a593Smuzhiyun 576*4882a593Smuzhiyun regulators { 577*4882a593Smuzhiyun compatible = "simple-bus"; 578*4882a593Smuzhiyun #address-cells = <1>; 579*4882a593Smuzhiyun #size-cells = <0>; 580*4882a593Smuzhiyun 581*4882a593Smuzhiyun p5valw_reg: regulator@0 { 582*4882a593Smuzhiyun compatible = "regulator-fixed"; 583*4882a593Smuzhiyun reg = <0>; 584*4882a593Smuzhiyun regulator-name = "+5valw"; 585*4882a593Smuzhiyun regulator-min-microvolt = <5000000>; 586*4882a593Smuzhiyun regulator-max-microvolt = <5000000>; 587*4882a593Smuzhiyun regulator-always-on; 588*4882a593Smuzhiyun }; 589*4882a593Smuzhiyun 590*4882a593Smuzhiyun vdd_pnl_reg: regulator@1 { 591*4882a593Smuzhiyun compatible = "regulator-fixed"; 592*4882a593Smuzhiyun reg = <1>; 593*4882a593Smuzhiyun regulator-name = "+3VS,vdd_pnl"; 594*4882a593Smuzhiyun regulator-min-microvolt = <3300000>; 595*4882a593Smuzhiyun regulator-max-microvolt = <3300000>; 596*4882a593Smuzhiyun gpio = <&gpio TEGRA_GPIO(A, 4) GPIO_ACTIVE_HIGH>; 597*4882a593Smuzhiyun enable-active-high; 598*4882a593Smuzhiyun }; 599*4882a593Smuzhiyun 600*4882a593Smuzhiyun vdd_bl_reg: regulator@2 { 601*4882a593Smuzhiyun compatible = "regulator-fixed"; 602*4882a593Smuzhiyun reg = <2>; 603*4882a593Smuzhiyun regulator-name = "vdd_bl"; 604*4882a593Smuzhiyun regulator-min-microvolt = <2800000>; 605*4882a593Smuzhiyun regulator-max-microvolt = <2800000>; 606*4882a593Smuzhiyun gpio = <&gpio TEGRA_GPIO(W, 0) GPIO_ACTIVE_HIGH>; 607*4882a593Smuzhiyun enable-active-high; 608*4882a593Smuzhiyun }; 609*4882a593Smuzhiyun }; 610*4882a593Smuzhiyun 611*4882a593Smuzhiyun sound { 612*4882a593Smuzhiyun compatible = "nvidia,tegra-audio-alc5632-paz00", 613*4882a593Smuzhiyun "nvidia,tegra-audio-alc5632"; 614*4882a593Smuzhiyun 615*4882a593Smuzhiyun nvidia,model = "Compal PAZ00"; 616*4882a593Smuzhiyun 617*4882a593Smuzhiyun nvidia,audio-routing = 618*4882a593Smuzhiyun "Int Spk", "SPKOUT", 619*4882a593Smuzhiyun "Int Spk", "SPKOUTN", 620*4882a593Smuzhiyun "Headset Mic", "MICBIAS1", 621*4882a593Smuzhiyun "MIC1", "Headset Mic", 622*4882a593Smuzhiyun "Headset Stereophone", "HPR", 623*4882a593Smuzhiyun "Headset Stereophone", "HPL", 624*4882a593Smuzhiyun "DMICDAT", "Digital Mic"; 625*4882a593Smuzhiyun 626*4882a593Smuzhiyun nvidia,audio-codec = <&alc5632>; 627*4882a593Smuzhiyun nvidia,i2s-controller = <&tegra_i2s1>; 628*4882a593Smuzhiyun nvidia,hp-det-gpios = <&gpio TEGRA_GPIO(W, 2) 629*4882a593Smuzhiyun GPIO_ACTIVE_HIGH>; 630*4882a593Smuzhiyun 631*4882a593Smuzhiyun clocks = <&tegra_car TEGRA20_CLK_PLL_A>, 632*4882a593Smuzhiyun <&tegra_car TEGRA20_CLK_PLL_A_OUT0>, 633*4882a593Smuzhiyun <&tegra_car TEGRA20_CLK_CDEV1>; 634*4882a593Smuzhiyun clock-names = "pll_a", "pll_a_out0", "mclk"; 635*4882a593Smuzhiyun }; 636*4882a593Smuzhiyun}; 637