1*4882a593SmuzhiyunBinding for Synopsys IntelliDDR Multi Protocol Memory Controller 2*4882a593Smuzhiyun 3*4882a593SmuzhiyunThe ZynqMP DDR ECC controller has an optional ECC support in 64-bit and 32-bit 4*4882a593Smuzhiyunbus width configurations. 5*4882a593Smuzhiyun 6*4882a593SmuzhiyunThe Zynq DDR ECC controller has an optional ECC support in half-bus width 7*4882a593Smuzhiyun(16-bit) configuration. 8*4882a593Smuzhiyun 9*4882a593SmuzhiyunThese both ECC controllers correct single bit ECC errors and detect double bit 10*4882a593SmuzhiyunECC errors. 11*4882a593Smuzhiyun 12*4882a593SmuzhiyunRequired properties: 13*4882a593Smuzhiyun - compatible: One of: 14*4882a593Smuzhiyun - 'xlnx,zynq-ddrc-a05' : Zynq DDR ECC controller 15*4882a593Smuzhiyun - 'xlnx,zynqmp-ddrc-2.40a' : ZynqMP DDR ECC controller 16*4882a593Smuzhiyun - reg: Should contain DDR controller registers location and length. 17*4882a593Smuzhiyun 18*4882a593SmuzhiyunRequired properties for "xlnx,zynqmp-ddrc-2.40a": 19*4882a593Smuzhiyun - interrupts: Property with a value describing the interrupt number. 20*4882a593Smuzhiyun 21*4882a593SmuzhiyunExample: 22*4882a593Smuzhiyun memory-controller@f8006000 { 23*4882a593Smuzhiyun compatible = "xlnx,zynq-ddrc-a05"; 24*4882a593Smuzhiyun reg = <0xf8006000 0x1000>; 25*4882a593Smuzhiyun }; 26*4882a593Smuzhiyun 27*4882a593Smuzhiyun mc: memory-controller@fd070000 { 28*4882a593Smuzhiyun compatible = "xlnx,zynqmp-ddrc-2.40a"; 29*4882a593Smuzhiyun reg = <0x0 0xfd070000 0x0 0x30000>; 30*4882a593Smuzhiyun interrupt-parent = <&gic>; 31*4882a593Smuzhiyun interrupts = <0 112 4>; 32*4882a593Smuzhiyun }; 33