xref: /OK3568_Linux_fs/u-boot/arch/arm/dts/tegra20-tamonten.dtsi (revision 4882a59341e53eb6f0b4789bf948001014eff981)
1*4882a593Smuzhiyun#include "tegra20.dtsi"
2*4882a593Smuzhiyun
3*4882a593Smuzhiyun/ {
4*4882a593Smuzhiyun	model = "Avionic Design Tamonten SOM";
5*4882a593Smuzhiyun	compatible = "ad,tamonten", "nvidia,tegra20";
6*4882a593Smuzhiyun
7*4882a593Smuzhiyun	memory {
8*4882a593Smuzhiyun		reg = <0x00000000 0x20000000>;
9*4882a593Smuzhiyun	};
10*4882a593Smuzhiyun
11*4882a593Smuzhiyun	host1x@50000000 {
12*4882a593Smuzhiyun		hdmi {
13*4882a593Smuzhiyun			vdd-supply = <&hdmi_vdd_reg>;
14*4882a593Smuzhiyun			pll-supply = <&hdmi_pll_reg>;
15*4882a593Smuzhiyun
16*4882a593Smuzhiyun			nvidia,ddc-i2c-bus = <&hdmi_ddc>;
17*4882a593Smuzhiyun			nvidia,hpd-gpio = <&gpio TEGRA_GPIO(N, 7)
18*4882a593Smuzhiyun				GPIO_ACTIVE_HIGH>;
19*4882a593Smuzhiyun		};
20*4882a593Smuzhiyun	};
21*4882a593Smuzhiyun
22*4882a593Smuzhiyun	pinmux {
23*4882a593Smuzhiyun		pinctrl-names = "default";
24*4882a593Smuzhiyun		pinctrl-0 = <&state_default>;
25*4882a593Smuzhiyun
26*4882a593Smuzhiyun		state_default: pinmux {
27*4882a593Smuzhiyun			ata {
28*4882a593Smuzhiyun				nvidia,pins = "ata";
29*4882a593Smuzhiyun				nvidia,function = "ide";
30*4882a593Smuzhiyun			};
31*4882a593Smuzhiyun			atb {
32*4882a593Smuzhiyun				nvidia,pins = "atb", "gma", "gme";
33*4882a593Smuzhiyun				nvidia,function = "sdio4";
34*4882a593Smuzhiyun			};
35*4882a593Smuzhiyun			atc {
36*4882a593Smuzhiyun				nvidia,pins = "atc";
37*4882a593Smuzhiyun				nvidia,function = "nand";
38*4882a593Smuzhiyun			};
39*4882a593Smuzhiyun			atd {
40*4882a593Smuzhiyun				nvidia,pins = "atd", "ate", "gmb", "gmd", "gpu",
41*4882a593Smuzhiyun					"spia", "spib", "spic";
42*4882a593Smuzhiyun				nvidia,function = "gmi";
43*4882a593Smuzhiyun			};
44*4882a593Smuzhiyun			cdev1 {
45*4882a593Smuzhiyun				nvidia,pins = "cdev1";
46*4882a593Smuzhiyun				nvidia,function = "plla_out";
47*4882a593Smuzhiyun			};
48*4882a593Smuzhiyun			cdev2 {
49*4882a593Smuzhiyun				nvidia,pins = "cdev2";
50*4882a593Smuzhiyun				nvidia,function = "pllp_out4";
51*4882a593Smuzhiyun			};
52*4882a593Smuzhiyun			crtp {
53*4882a593Smuzhiyun				nvidia,pins = "crtp";
54*4882a593Smuzhiyun				nvidia,function = "crt";
55*4882a593Smuzhiyun			};
56*4882a593Smuzhiyun			csus {
57*4882a593Smuzhiyun				nvidia,pins = "csus";
58*4882a593Smuzhiyun				nvidia,function = "vi_sensor_clk";
59*4882a593Smuzhiyun			};
60*4882a593Smuzhiyun			dap1 {
61*4882a593Smuzhiyun				nvidia,pins = "dap1";
62*4882a593Smuzhiyun				nvidia,function = "dap1";
63*4882a593Smuzhiyun			};
64*4882a593Smuzhiyun			dap2 {
65*4882a593Smuzhiyun				nvidia,pins = "dap2";
66*4882a593Smuzhiyun				nvidia,function = "dap2";
67*4882a593Smuzhiyun			};
68*4882a593Smuzhiyun			dap3 {
69*4882a593Smuzhiyun				nvidia,pins = "dap3";
70*4882a593Smuzhiyun				nvidia,function = "dap3";
71*4882a593Smuzhiyun			};
72*4882a593Smuzhiyun			dap4 {
73*4882a593Smuzhiyun				nvidia,pins = "dap4";
74*4882a593Smuzhiyun				nvidia,function = "dap4";
75*4882a593Smuzhiyun			};
76*4882a593Smuzhiyun			dta {
77*4882a593Smuzhiyun				nvidia,pins = "dta", "dtd";
78*4882a593Smuzhiyun				nvidia,function = "sdio2";
79*4882a593Smuzhiyun			};
80*4882a593Smuzhiyun			dtb {
81*4882a593Smuzhiyun				nvidia,pins = "dtb", "dtc", "dte";
82*4882a593Smuzhiyun				nvidia,function = "rsvd1";
83*4882a593Smuzhiyun			};
84*4882a593Smuzhiyun			dtf {
85*4882a593Smuzhiyun				nvidia,pins = "dtf";
86*4882a593Smuzhiyun				nvidia,function = "i2c3";
87*4882a593Smuzhiyun			};
88*4882a593Smuzhiyun			gmc {
89*4882a593Smuzhiyun				nvidia,pins = "gmc";
90*4882a593Smuzhiyun				nvidia,function = "uartd";
91*4882a593Smuzhiyun			};
92*4882a593Smuzhiyun			gpu7 {
93*4882a593Smuzhiyun				nvidia,pins = "gpu7";
94*4882a593Smuzhiyun				nvidia,function = "rtck";
95*4882a593Smuzhiyun			};
96*4882a593Smuzhiyun			gpv {
97*4882a593Smuzhiyun				nvidia,pins = "gpv", "slxa", "slxk";
98*4882a593Smuzhiyun				nvidia,function = "pcie";
99*4882a593Smuzhiyun			};
100*4882a593Smuzhiyun			hdint {
101*4882a593Smuzhiyun				nvidia,pins = "hdint";
102*4882a593Smuzhiyun				nvidia,function = "hdmi";
103*4882a593Smuzhiyun			};
104*4882a593Smuzhiyun			i2cp {
105*4882a593Smuzhiyun				nvidia,pins = "i2cp";
106*4882a593Smuzhiyun				nvidia,function = "i2cp";
107*4882a593Smuzhiyun			};
108*4882a593Smuzhiyun			irrx {
109*4882a593Smuzhiyun				nvidia,pins = "irrx", "irtx";
110*4882a593Smuzhiyun				nvidia,function = "uarta";
111*4882a593Smuzhiyun			};
112*4882a593Smuzhiyun			kbca {
113*4882a593Smuzhiyun				nvidia,pins = "kbca", "kbcb", "kbcc", "kbcd",
114*4882a593Smuzhiyun					"kbce", "kbcf";
115*4882a593Smuzhiyun				nvidia,function = "kbc";
116*4882a593Smuzhiyun			};
117*4882a593Smuzhiyun			lcsn {
118*4882a593Smuzhiyun				nvidia,pins = "lcsn", "ld0", "ld1", "ld2",
119*4882a593Smuzhiyun					"ld3", "ld4", "ld5", "ld6", "ld7",
120*4882a593Smuzhiyun					"ld8", "ld9", "ld10", "ld11", "ld12",
121*4882a593Smuzhiyun					"ld13", "ld14", "ld15", "ld16", "ld17",
122*4882a593Smuzhiyun					"ldc", "ldi", "lhp0", "lhp1", "lhp2",
123*4882a593Smuzhiyun					"lhs", "lm0", "lm1", "lpp", "lpw0",
124*4882a593Smuzhiyun					"lpw1", "lpw2", "lsc0", "lsc1", "lsck",
125*4882a593Smuzhiyun					"lsda", "lsdi", "lspi", "lvp0", "lvp1",
126*4882a593Smuzhiyun					"lvs";
127*4882a593Smuzhiyun				nvidia,function = "displaya";
128*4882a593Smuzhiyun			};
129*4882a593Smuzhiyun			owc {
130*4882a593Smuzhiyun				nvidia,pins = "owc", "spdi", "spdo", "uac";
131*4882a593Smuzhiyun				nvidia,function = "rsvd2";
132*4882a593Smuzhiyun			};
133*4882a593Smuzhiyun			pmc {
134*4882a593Smuzhiyun				nvidia,pins = "pmc";
135*4882a593Smuzhiyun				nvidia,function = "pwr_on";
136*4882a593Smuzhiyun			};
137*4882a593Smuzhiyun			rm {
138*4882a593Smuzhiyun				nvidia,pins = "rm";
139*4882a593Smuzhiyun				nvidia,function = "i2c1";
140*4882a593Smuzhiyun			};
141*4882a593Smuzhiyun			sdb {
142*4882a593Smuzhiyun				nvidia,pins = "sdb", "sdc", "sdd";
143*4882a593Smuzhiyun				nvidia,function = "pwm";
144*4882a593Smuzhiyun			};
145*4882a593Smuzhiyun			sdio1 {
146*4882a593Smuzhiyun				nvidia,pins = "sdio1";
147*4882a593Smuzhiyun				nvidia,function = "sdio1";
148*4882a593Smuzhiyun			};
149*4882a593Smuzhiyun			slxc {
150*4882a593Smuzhiyun				nvidia,pins = "slxc", "slxd";
151*4882a593Smuzhiyun				nvidia,function = "spdif";
152*4882a593Smuzhiyun			};
153*4882a593Smuzhiyun			spid {
154*4882a593Smuzhiyun				nvidia,pins = "spid", "spie", "spif";
155*4882a593Smuzhiyun				nvidia,function = "spi1";
156*4882a593Smuzhiyun			};
157*4882a593Smuzhiyun			spig {
158*4882a593Smuzhiyun				nvidia,pins = "spig", "spih";
159*4882a593Smuzhiyun				nvidia,function = "spi2_alt";
160*4882a593Smuzhiyun			};
161*4882a593Smuzhiyun			uaa {
162*4882a593Smuzhiyun				nvidia,pins = "uaa", "uab", "uda";
163*4882a593Smuzhiyun				nvidia,function = "ulpi";
164*4882a593Smuzhiyun			};
165*4882a593Smuzhiyun			uad {
166*4882a593Smuzhiyun				nvidia,pins = "uad";
167*4882a593Smuzhiyun				nvidia,function = "irda";
168*4882a593Smuzhiyun			};
169*4882a593Smuzhiyun			uca {
170*4882a593Smuzhiyun				nvidia,pins = "uca", "ucb";
171*4882a593Smuzhiyun				nvidia,function = "uartc";
172*4882a593Smuzhiyun			};
173*4882a593Smuzhiyun			conf_ata {
174*4882a593Smuzhiyun				nvidia,pins = "ata", "atb", "atc", "atd", "ate",
175*4882a593Smuzhiyun					"cdev1", "cdev2", "dap1", "dtb", "gma",
176*4882a593Smuzhiyun					"gmb", "gmc", "gmd", "gme", "gpu7",
177*4882a593Smuzhiyun					"gpv", "i2cp", "pta", "rm", "slxa",
178*4882a593Smuzhiyun					"slxk", "spia", "spib", "uac";
179*4882a593Smuzhiyun				nvidia,pull = <0>;
180*4882a593Smuzhiyun				nvidia,tristate = <0>;
181*4882a593Smuzhiyun			};
182*4882a593Smuzhiyun			conf_ck32 {
183*4882a593Smuzhiyun				nvidia,pins = "ck32", "ddrc", "pmca", "pmcb",
184*4882a593Smuzhiyun					"pmcc", "pmcd", "pmce", "xm2c", "xm2d";
185*4882a593Smuzhiyun				nvidia,pull = <0>;
186*4882a593Smuzhiyun			};
187*4882a593Smuzhiyun			conf_csus {
188*4882a593Smuzhiyun				nvidia,pins = "csus", "spid", "spif";
189*4882a593Smuzhiyun				nvidia,pull = <1>;
190*4882a593Smuzhiyun				nvidia,tristate = <1>;
191*4882a593Smuzhiyun			};
192*4882a593Smuzhiyun			conf_crtp {
193*4882a593Smuzhiyun				nvidia,pins = "crtp", "dap2", "dap3", "dap4",
194*4882a593Smuzhiyun					"dtc", "dte", "dtf", "gpu", "sdio1",
195*4882a593Smuzhiyun					"slxc", "slxd", "spdi", "spdo", "spig",
196*4882a593Smuzhiyun					"uda";
197*4882a593Smuzhiyun				nvidia,pull = <0>;
198*4882a593Smuzhiyun				nvidia,tristate = <1>;
199*4882a593Smuzhiyun			};
200*4882a593Smuzhiyun			conf_ddc {
201*4882a593Smuzhiyun				nvidia,pins = "ddc", "dta", "dtd", "kbca",
202*4882a593Smuzhiyun					"kbcb", "kbcc", "kbcd", "kbce", "kbcf",
203*4882a593Smuzhiyun					"sdc";
204*4882a593Smuzhiyun				nvidia,pull = <2>;
205*4882a593Smuzhiyun				nvidia,tristate = <0>;
206*4882a593Smuzhiyun			};
207*4882a593Smuzhiyun			conf_hdint {
208*4882a593Smuzhiyun				nvidia,pins = "hdint", "lcsn", "ldc", "lm1",
209*4882a593Smuzhiyun					"lpw1", "lsc1", "lsck", "lsda", "lsdi",
210*4882a593Smuzhiyun					"lvp0", "owc", "sdb";
211*4882a593Smuzhiyun				nvidia,tristate = <1>;
212*4882a593Smuzhiyun			};
213*4882a593Smuzhiyun			conf_irrx {
214*4882a593Smuzhiyun				nvidia,pins = "irrx", "irtx", "sdd", "spic",
215*4882a593Smuzhiyun					"spie", "spih", "uaa", "uab", "uad",
216*4882a593Smuzhiyun					"uca", "ucb";
217*4882a593Smuzhiyun				nvidia,pull = <2>;
218*4882a593Smuzhiyun				nvidia,tristate = <1>;
219*4882a593Smuzhiyun			};
220*4882a593Smuzhiyun			conf_lc {
221*4882a593Smuzhiyun				nvidia,pins = "lc", "ls";
222*4882a593Smuzhiyun				nvidia,pull = <2>;
223*4882a593Smuzhiyun			};
224*4882a593Smuzhiyun			conf_ld0 {
225*4882a593Smuzhiyun				nvidia,pins = "ld0", "ld1", "ld2", "ld3", "ld4",
226*4882a593Smuzhiyun					"ld5", "ld6", "ld7", "ld8", "ld9",
227*4882a593Smuzhiyun					"ld10", "ld11", "ld12", "ld13", "ld14",
228*4882a593Smuzhiyun					"ld15", "ld16", "ld17", "ldi", "lhp0",
229*4882a593Smuzhiyun					"lhp1", "lhp2", "lhs", "lm0", "lpp",
230*4882a593Smuzhiyun					"lpw0", "lpw2", "lsc0", "lspi", "lvp1",
231*4882a593Smuzhiyun					"lvs", "pmc";
232*4882a593Smuzhiyun				nvidia,tristate = <0>;
233*4882a593Smuzhiyun			};
234*4882a593Smuzhiyun			conf_ld17_0 {
235*4882a593Smuzhiyun				nvidia,pins = "ld17_0", "ld19_18", "ld21_20",
236*4882a593Smuzhiyun					"ld23_22";
237*4882a593Smuzhiyun				nvidia,pull = <1>;
238*4882a593Smuzhiyun			};
239*4882a593Smuzhiyun		};
240*4882a593Smuzhiyun
241*4882a593Smuzhiyun		state_i2cmux_ddc: pinmux_i2cmux_ddc {
242*4882a593Smuzhiyun			ddc {
243*4882a593Smuzhiyun				nvidia,pins = "ddc";
244*4882a593Smuzhiyun				nvidia,function = "i2c2";
245*4882a593Smuzhiyun			};
246*4882a593Smuzhiyun			pta {
247*4882a593Smuzhiyun				nvidia,pins = "pta";
248*4882a593Smuzhiyun				nvidia,function = "rsvd4";
249*4882a593Smuzhiyun			};
250*4882a593Smuzhiyun		};
251*4882a593Smuzhiyun
252*4882a593Smuzhiyun		state_i2cmux_pta: pinmux_i2cmux_pta {
253*4882a593Smuzhiyun			ddc {
254*4882a593Smuzhiyun				nvidia,pins = "ddc";
255*4882a593Smuzhiyun				nvidia,function = "rsvd4";
256*4882a593Smuzhiyun			};
257*4882a593Smuzhiyun			pta {
258*4882a593Smuzhiyun				nvidia,pins = "pta";
259*4882a593Smuzhiyun				nvidia,function = "i2c2";
260*4882a593Smuzhiyun			};
261*4882a593Smuzhiyun		};
262*4882a593Smuzhiyun
263*4882a593Smuzhiyun		state_i2cmux_idle: pinmux_i2cmux_idle {
264*4882a593Smuzhiyun			ddc {
265*4882a593Smuzhiyun				nvidia,pins = "ddc";
266*4882a593Smuzhiyun				nvidia,function = "rsvd4";
267*4882a593Smuzhiyun			};
268*4882a593Smuzhiyun			pta {
269*4882a593Smuzhiyun				nvidia,pins = "pta";
270*4882a593Smuzhiyun				nvidia,function = "rsvd4";
271*4882a593Smuzhiyun			};
272*4882a593Smuzhiyun		};
273*4882a593Smuzhiyun	};
274*4882a593Smuzhiyun
275*4882a593Smuzhiyun	i2s@70002800 {
276*4882a593Smuzhiyun		status = "okay";
277*4882a593Smuzhiyun	};
278*4882a593Smuzhiyun
279*4882a593Smuzhiyun	serial@70006300 {
280*4882a593Smuzhiyun		status = "okay";
281*4882a593Smuzhiyun	};
282*4882a593Smuzhiyun
283*4882a593Smuzhiyun	nand-controller@70008000 {
284*4882a593Smuzhiyun		nvidia,wp-gpios = <&gpio TEGRA_GPIO(C, 7) GPIO_ACTIVE_HIGH>;
285*4882a593Smuzhiyun		nvidia,width = <8>;
286*4882a593Smuzhiyun		nvidia,timing = <26 100 20 80 20 10 12 10 70>;
287*4882a593Smuzhiyun
288*4882a593Smuzhiyun		nand@0 {
289*4882a593Smuzhiyun			reg = <0>;
290*4882a593Smuzhiyun			compatible = "hynix,hy27uf4g2b", "nand-flash";
291*4882a593Smuzhiyun		};
292*4882a593Smuzhiyun	};
293*4882a593Smuzhiyun
294*4882a593Smuzhiyun	i2c@7000c000 {
295*4882a593Smuzhiyun		clock-frequency = <400000>;
296*4882a593Smuzhiyun		status = "okay";
297*4882a593Smuzhiyun	};
298*4882a593Smuzhiyun
299*4882a593Smuzhiyun	i2c@7000c400 {
300*4882a593Smuzhiyun		clock-frequency = <100000>;
301*4882a593Smuzhiyun		status = "okay";
302*4882a593Smuzhiyun	};
303*4882a593Smuzhiyun
304*4882a593Smuzhiyun	i2cmux {
305*4882a593Smuzhiyun		compatible = "i2c-mux-pinctrl";
306*4882a593Smuzhiyun		#address-cells = <1>;
307*4882a593Smuzhiyun		#size-cells = <0>;
308*4882a593Smuzhiyun
309*4882a593Smuzhiyun		i2c-parent = <&{/i2c@7000c400}>;
310*4882a593Smuzhiyun
311*4882a593Smuzhiyun		pinctrl-names = "ddc", "pta", "idle";
312*4882a593Smuzhiyun		pinctrl-0 = <&state_i2cmux_ddc>;
313*4882a593Smuzhiyun		pinctrl-1 = <&state_i2cmux_pta>;
314*4882a593Smuzhiyun		pinctrl-2 = <&state_i2cmux_idle>;
315*4882a593Smuzhiyun
316*4882a593Smuzhiyun		hdmi_ddc: i2c@0 {
317*4882a593Smuzhiyun			reg = <0>;
318*4882a593Smuzhiyun			#address-cells = <1>;
319*4882a593Smuzhiyun			#size-cells = <0>;
320*4882a593Smuzhiyun		};
321*4882a593Smuzhiyun
322*4882a593Smuzhiyun		i2c@1 {
323*4882a593Smuzhiyun			reg = <1>;
324*4882a593Smuzhiyun			#address-cells = <1>;
325*4882a593Smuzhiyun			#size-cells = <0>;
326*4882a593Smuzhiyun		};
327*4882a593Smuzhiyun	};
328*4882a593Smuzhiyun
329*4882a593Smuzhiyun	i2c@7000d000 {
330*4882a593Smuzhiyun		clock-frequency = <400000>;
331*4882a593Smuzhiyun		status = "okay";
332*4882a593Smuzhiyun
333*4882a593Smuzhiyun		pmic: tps6586x@34 {
334*4882a593Smuzhiyun			compatible = "ti,tps6586x";
335*4882a593Smuzhiyun			reg = <0x34>;
336*4882a593Smuzhiyun			interrupts = <0 86 0x4>;
337*4882a593Smuzhiyun
338*4882a593Smuzhiyun			ti,system-power-controller;
339*4882a593Smuzhiyun
340*4882a593Smuzhiyun			#gpio-cells = <2>;
341*4882a593Smuzhiyun			gpio-controller;
342*4882a593Smuzhiyun
343*4882a593Smuzhiyun			sys-supply = <&vdd_5v0_reg>;
344*4882a593Smuzhiyun			vin-sm0-supply = <&sys_reg>;
345*4882a593Smuzhiyun			vin-sm1-supply = <&sys_reg>;
346*4882a593Smuzhiyun			vin-sm2-supply = <&sys_reg>;
347*4882a593Smuzhiyun			vinldo01-supply = <&sm2_reg>;
348*4882a593Smuzhiyun			vinldo23-supply = <&sm2_reg>;
349*4882a593Smuzhiyun			vinldo4-supply = <&sm2_reg>;
350*4882a593Smuzhiyun			vinldo678-supply = <&sm2_reg>;
351*4882a593Smuzhiyun			vinldo9-supply = <&sm2_reg>;
352*4882a593Smuzhiyun
353*4882a593Smuzhiyun			regulators {
354*4882a593Smuzhiyun				sys_reg: sys {
355*4882a593Smuzhiyun					regulator-name = "vdd_sys";
356*4882a593Smuzhiyun					regulator-always-on;
357*4882a593Smuzhiyun				};
358*4882a593Smuzhiyun
359*4882a593Smuzhiyun				sm0 {
360*4882a593Smuzhiyun					regulator-name = "vdd_sys_sm0,vdd_core";
361*4882a593Smuzhiyun					regulator-min-microvolt = <1200000>;
362*4882a593Smuzhiyun					regulator-max-microvolt = <1200000>;
363*4882a593Smuzhiyun					regulator-always-on;
364*4882a593Smuzhiyun				};
365*4882a593Smuzhiyun
366*4882a593Smuzhiyun				sm1 {
367*4882a593Smuzhiyun					regulator-name = "vdd_sys_sm1,vdd_cpu";
368*4882a593Smuzhiyun					regulator-min-microvolt = <1000000>;
369*4882a593Smuzhiyun					regulator-max-microvolt = <1000000>;
370*4882a593Smuzhiyun					regulator-always-on;
371*4882a593Smuzhiyun				};
372*4882a593Smuzhiyun
373*4882a593Smuzhiyun				sm2_reg: sm2 {
374*4882a593Smuzhiyun					regulator-name = "vdd_sys_sm2,vin_ldo*";
375*4882a593Smuzhiyun					regulator-min-microvolt = <3700000>;
376*4882a593Smuzhiyun					regulator-max-microvolt = <3700000>;
377*4882a593Smuzhiyun					regulator-always-on;
378*4882a593Smuzhiyun				};
379*4882a593Smuzhiyun
380*4882a593Smuzhiyun				ldo0 {
381*4882a593Smuzhiyun					regulator-name = "vdd_ldo0,vddio_pex_clk";
382*4882a593Smuzhiyun					regulator-min-microvolt = <3300000>;
383*4882a593Smuzhiyun					regulator-max-microvolt = <3300000>;
384*4882a593Smuzhiyun				};
385*4882a593Smuzhiyun
386*4882a593Smuzhiyun				ldo1 {
387*4882a593Smuzhiyun					regulator-name = "vdd_ldo1,avdd_pll*";
388*4882a593Smuzhiyun					regulator-min-microvolt = <1100000>;
389*4882a593Smuzhiyun					regulator-max-microvolt = <1100000>;
390*4882a593Smuzhiyun					regulator-always-on;
391*4882a593Smuzhiyun				};
392*4882a593Smuzhiyun
393*4882a593Smuzhiyun				ldo2 {
394*4882a593Smuzhiyun					regulator-name = "vdd_ldo2,vdd_rtc";
395*4882a593Smuzhiyun					regulator-min-microvolt = <1200000>;
396*4882a593Smuzhiyun					regulator-max-microvolt = <1200000>;
397*4882a593Smuzhiyun				};
398*4882a593Smuzhiyun
399*4882a593Smuzhiyun				ldo3 {
400*4882a593Smuzhiyun					regulator-name = "vdd_ldo3,avdd_usb*";
401*4882a593Smuzhiyun					regulator-min-microvolt = <3300000>;
402*4882a593Smuzhiyun					regulator-max-microvolt = <3300000>;
403*4882a593Smuzhiyun					regulator-always-on;
404*4882a593Smuzhiyun				};
405*4882a593Smuzhiyun
406*4882a593Smuzhiyun				ldo4 {
407*4882a593Smuzhiyun					regulator-name = "vdd_ldo4,avdd_osc,vddio_sys";
408*4882a593Smuzhiyun					regulator-min-microvolt = <1800000>;
409*4882a593Smuzhiyun					regulator-max-microvolt = <1800000>;
410*4882a593Smuzhiyun					regulator-always-on;
411*4882a593Smuzhiyun				};
412*4882a593Smuzhiyun
413*4882a593Smuzhiyun				ldo5 {
414*4882a593Smuzhiyun					regulator-name = "vdd_ldo5,vcore_mmc";
415*4882a593Smuzhiyun					regulator-min-microvolt = <2850000>;
416*4882a593Smuzhiyun					regulator-max-microvolt = <2850000>;
417*4882a593Smuzhiyun				};
418*4882a593Smuzhiyun
419*4882a593Smuzhiyun				ldo6 {
420*4882a593Smuzhiyun					regulator-name = "vdd_ldo6,avdd_vdac";
421*4882a593Smuzhiyun					/*
422*4882a593Smuzhiyun					 * According to the Tegra 2 Automotive
423*4882a593Smuzhiyun					 * DataSheet, a typical value for this
424*4882a593Smuzhiyun					 * would be 2.8V, but the PMIC only
425*4882a593Smuzhiyun					 * supports 2.85V.
426*4882a593Smuzhiyun					 */
427*4882a593Smuzhiyun					regulator-min-microvolt = <2850000>;
428*4882a593Smuzhiyun					regulator-max-microvolt = <2850000>;
429*4882a593Smuzhiyun				};
430*4882a593Smuzhiyun
431*4882a593Smuzhiyun				hdmi_vdd_reg: ldo7 {
432*4882a593Smuzhiyun					regulator-name = "vdd_ldo7,avdd_hdmi";
433*4882a593Smuzhiyun					regulator-min-microvolt = <3300000>;
434*4882a593Smuzhiyun					regulator-max-microvolt = <3300000>;
435*4882a593Smuzhiyun				};
436*4882a593Smuzhiyun
437*4882a593Smuzhiyun				hdmi_pll_reg: ldo8 {
438*4882a593Smuzhiyun					regulator-name = "vdd_ldo8,avdd_hdmi_pll";
439*4882a593Smuzhiyun					regulator-min-microvolt = <1800000>;
440*4882a593Smuzhiyun					regulator-max-microvolt = <1800000>;
441*4882a593Smuzhiyun				};
442*4882a593Smuzhiyun
443*4882a593Smuzhiyun				ldo9 {
444*4882a593Smuzhiyun					regulator-name = "vdd_ldo9,vdd_ddr_rx,avdd_cam";
445*4882a593Smuzhiyun					/*
446*4882a593Smuzhiyun					 * According to the Tegra 2 Automotive
447*4882a593Smuzhiyun					 * DataSheet, a typical value for this
448*4882a593Smuzhiyun					 * would be 2.8V, but the PMIC only
449*4882a593Smuzhiyun					 * supports 2.85V.
450*4882a593Smuzhiyun					 */
451*4882a593Smuzhiyun					regulator-min-microvolt = <2850000>;
452*4882a593Smuzhiyun					regulator-max-microvolt = <2850000>;
453*4882a593Smuzhiyun					regulator-always-on;
454*4882a593Smuzhiyun				};
455*4882a593Smuzhiyun
456*4882a593Smuzhiyun				ldo_rtc {
457*4882a593Smuzhiyun					regulator-name = "vdd_rtc_out";
458*4882a593Smuzhiyun					regulator-min-microvolt = <3300000>;
459*4882a593Smuzhiyun					regulator-max-microvolt = <3300000>;
460*4882a593Smuzhiyun					regulator-always-on;
461*4882a593Smuzhiyun				};
462*4882a593Smuzhiyun			};
463*4882a593Smuzhiyun		};
464*4882a593Smuzhiyun
465*4882a593Smuzhiyun		temperature-sensor@4c {
466*4882a593Smuzhiyun			compatible = "onnn,nct1008";
467*4882a593Smuzhiyun			reg = <0x4c>;
468*4882a593Smuzhiyun		};
469*4882a593Smuzhiyun	};
470*4882a593Smuzhiyun
471*4882a593Smuzhiyun	pmc {
472*4882a593Smuzhiyun		nvidia,invert-interrupt;
473*4882a593Smuzhiyun	};
474*4882a593Smuzhiyun
475*4882a593Smuzhiyun	usb@c5008000 {
476*4882a593Smuzhiyun		status = "okay";
477*4882a593Smuzhiyun	};
478*4882a593Smuzhiyun
479*4882a593Smuzhiyun	sdhci@c8000600 {
480*4882a593Smuzhiyun		cd-gpios = <&gpio TEGRA_GPIO(H, 2) GPIO_ACTIVE_LOW>;
481*4882a593Smuzhiyun		wp-gpios = <&gpio TEGRA_GPIO(H, 3) GPIO_ACTIVE_HIGH>;
482*4882a593Smuzhiyun		bus-width = <4>;
483*4882a593Smuzhiyun		status = "okay";
484*4882a593Smuzhiyun	};
485*4882a593Smuzhiyun
486*4882a593Smuzhiyun	clocks {
487*4882a593Smuzhiyun		compatible = "simple-bus";
488*4882a593Smuzhiyun		#address-cells = <1>;
489*4882a593Smuzhiyun		#size-cells = <0>;
490*4882a593Smuzhiyun
491*4882a593Smuzhiyun		clk32k_in: clock@0 {
492*4882a593Smuzhiyun			compatible = "fixed-clock";
493*4882a593Smuzhiyun			reg=<0>;
494*4882a593Smuzhiyun			#clock-cells = <0>;
495*4882a593Smuzhiyun			clock-frequency = <32768>;
496*4882a593Smuzhiyun		};
497*4882a593Smuzhiyun	};
498*4882a593Smuzhiyun
499*4882a593Smuzhiyun	regulators {
500*4882a593Smuzhiyun		compatible = "simple-bus";
501*4882a593Smuzhiyun
502*4882a593Smuzhiyun		#address-cells = <1>;
503*4882a593Smuzhiyun		#size-cells = <0>;
504*4882a593Smuzhiyun
505*4882a593Smuzhiyun		vdd_5v0_reg: regulator@0 {
506*4882a593Smuzhiyun			compatible = "regulator-fixed";
507*4882a593Smuzhiyun			reg = <0>;
508*4882a593Smuzhiyun			regulator-name = "vdd_5v0";
509*4882a593Smuzhiyun			regulator-min-microvolt = <5000000>;
510*4882a593Smuzhiyun			regulator-max-microvolt = <5000000>;
511*4882a593Smuzhiyun			regulator-always-on;
512*4882a593Smuzhiyun		};
513*4882a593Smuzhiyun	};
514*4882a593Smuzhiyun};
515