1*4882a593Smuzhiyun// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2*4882a593Smuzhiyun/* 3*4882a593Smuzhiyun * Copyright 2019-2020 NXP 4*4882a593Smuzhiyun */ 5*4882a593Smuzhiyun 6*4882a593Smuzhiyun/dts-v1/; 7*4882a593Smuzhiyun 8*4882a593Smuzhiyun#include <dt-bindings/usb/pd.h> 9*4882a593Smuzhiyun#include "imx8mm-evk.dtsi" 10*4882a593Smuzhiyun 11*4882a593Smuzhiyun/ { 12*4882a593Smuzhiyun model = "FSL i.MX8MM EVK board"; 13*4882a593Smuzhiyun compatible = "fsl,imx8mm-evk", "fsl,imx8mm"; 14*4882a593Smuzhiyun 15*4882a593Smuzhiyun aliases { 16*4882a593Smuzhiyun spi0 = &flexspi; 17*4882a593Smuzhiyun }; 18*4882a593Smuzhiyun}; 19*4882a593Smuzhiyun 20*4882a593Smuzhiyun&ddrc { 21*4882a593Smuzhiyun operating-points-v2 = <&ddrc_opp_table>; 22*4882a593Smuzhiyun 23*4882a593Smuzhiyun ddrc_opp_table: opp-table { 24*4882a593Smuzhiyun compatible = "operating-points-v2"; 25*4882a593Smuzhiyun 26*4882a593Smuzhiyun opp-25M { 27*4882a593Smuzhiyun opp-hz = /bits/ 64 <25000000>; 28*4882a593Smuzhiyun }; 29*4882a593Smuzhiyun 30*4882a593Smuzhiyun opp-100M { 31*4882a593Smuzhiyun opp-hz = /bits/ 64 <100000000>; 32*4882a593Smuzhiyun }; 33*4882a593Smuzhiyun 34*4882a593Smuzhiyun opp-750M { 35*4882a593Smuzhiyun opp-hz = /bits/ 64 <750000000>; 36*4882a593Smuzhiyun }; 37*4882a593Smuzhiyun }; 38*4882a593Smuzhiyun}; 39*4882a593Smuzhiyun 40*4882a593Smuzhiyun&flexspi { 41*4882a593Smuzhiyun pinctrl-names = "default"; 42*4882a593Smuzhiyun pinctrl-0 = <&pinctrl_flexspi>; 43*4882a593Smuzhiyun status = "okay"; 44*4882a593Smuzhiyun 45*4882a593Smuzhiyun flash@0 { 46*4882a593Smuzhiyun reg = <0>; 47*4882a593Smuzhiyun #address-cells = <1>; 48*4882a593Smuzhiyun #size-cells = <1>; 49*4882a593Smuzhiyun compatible = "jedec,spi-nor"; 50*4882a593Smuzhiyun spi-max-frequency = <80000000>; 51*4882a593Smuzhiyun spi-tx-bus-width = <4>; 52*4882a593Smuzhiyun spi-rx-bus-width = <4>; 53*4882a593Smuzhiyun }; 54*4882a593Smuzhiyun}; 55*4882a593Smuzhiyun 56*4882a593Smuzhiyun&usdhc3 { 57*4882a593Smuzhiyun assigned-clocks = <&clk IMX8MM_CLK_USDHC3_ROOT>; 58*4882a593Smuzhiyun assigned-clock-rates = <400000000>; 59*4882a593Smuzhiyun pinctrl-names = "default", "state_100mhz", "state_200mhz"; 60*4882a593Smuzhiyun pinctrl-0 = <&pinctrl_usdhc3>; 61*4882a593Smuzhiyun pinctrl-1 = <&pinctrl_usdhc3_100mhz>; 62*4882a593Smuzhiyun pinctrl-2 = <&pinctrl_usdhc3_200mhz>; 63*4882a593Smuzhiyun bus-width = <8>; 64*4882a593Smuzhiyun non-removable; 65*4882a593Smuzhiyun status = "okay"; 66*4882a593Smuzhiyun}; 67*4882a593Smuzhiyun 68*4882a593Smuzhiyun&iomuxc { 69*4882a593Smuzhiyun pinctrl_flexspi: flexspigrp { 70*4882a593Smuzhiyun fsl,pins = < 71*4882a593Smuzhiyun MX8MM_IOMUXC_NAND_ALE_QSPI_A_SCLK 0x1c2 72*4882a593Smuzhiyun MX8MM_IOMUXC_NAND_CE0_B_QSPI_A_SS0_B 0x82 73*4882a593Smuzhiyun MX8MM_IOMUXC_NAND_DATA00_QSPI_A_DATA0 0x82 74*4882a593Smuzhiyun MX8MM_IOMUXC_NAND_DATA01_QSPI_A_DATA1 0x82 75*4882a593Smuzhiyun MX8MM_IOMUXC_NAND_DATA02_QSPI_A_DATA2 0x82 76*4882a593Smuzhiyun MX8MM_IOMUXC_NAND_DATA03_QSPI_A_DATA3 0x82 77*4882a593Smuzhiyun >; 78*4882a593Smuzhiyun }; 79*4882a593Smuzhiyun 80*4882a593Smuzhiyun pinctrl_usdhc3: usdhc3grp { 81*4882a593Smuzhiyun fsl,pins = < 82*4882a593Smuzhiyun MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x190 83*4882a593Smuzhiyun MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d0 84*4882a593Smuzhiyun MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d0 85*4882a593Smuzhiyun MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d0 86*4882a593Smuzhiyun MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d0 87*4882a593Smuzhiyun MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d0 88*4882a593Smuzhiyun MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d0 89*4882a593Smuzhiyun MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d0 90*4882a593Smuzhiyun MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d0 91*4882a593Smuzhiyun MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d0 92*4882a593Smuzhiyun MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d0 93*4882a593Smuzhiyun MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x190 94*4882a593Smuzhiyun >; 95*4882a593Smuzhiyun }; 96*4882a593Smuzhiyun 97*4882a593Smuzhiyun pinctrl_usdhc3_100mhz: usdhc3-100mhzgrp { 98*4882a593Smuzhiyun fsl,pins = < 99*4882a593Smuzhiyun MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x194 100*4882a593Smuzhiyun MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d4 101*4882a593Smuzhiyun MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d4 102*4882a593Smuzhiyun MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d4 103*4882a593Smuzhiyun MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d4 104*4882a593Smuzhiyun MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d4 105*4882a593Smuzhiyun MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d4 106*4882a593Smuzhiyun MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d4 107*4882a593Smuzhiyun MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d4 108*4882a593Smuzhiyun MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d4 109*4882a593Smuzhiyun MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x194 110*4882a593Smuzhiyun >; 111*4882a593Smuzhiyun }; 112*4882a593Smuzhiyun 113*4882a593Smuzhiyun pinctrl_usdhc3_200mhz: usdhc3-200mhzgrp { 114*4882a593Smuzhiyun fsl,pins = < 115*4882a593Smuzhiyun MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x196 116*4882a593Smuzhiyun MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d6 117*4882a593Smuzhiyun MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d6 118*4882a593Smuzhiyun MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d6 119*4882a593Smuzhiyun MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d6 120*4882a593Smuzhiyun MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d6 121*4882a593Smuzhiyun MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d6 122*4882a593Smuzhiyun MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d6 123*4882a593Smuzhiyun MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d6 124*4882a593Smuzhiyun MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d6 125*4882a593Smuzhiyun MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x196 126*4882a593Smuzhiyun >; 127*4882a593Smuzhiyun }; 128*4882a593Smuzhiyun}; 129