xref: /OK3568_Linux_fs/kernel/arch/arm/boot/dts/tegra20-tamonten.dtsi (revision 4882a59341e53eb6f0b4789bf948001014eff981)
1*4882a593Smuzhiyun// SPDX-License-Identifier: GPL-2.0
2*4882a593Smuzhiyun#include "tegra20.dtsi"
3*4882a593Smuzhiyun
4*4882a593Smuzhiyun/ {
5*4882a593Smuzhiyun	model = "Avionic Design Tamonten SOM";
6*4882a593Smuzhiyun	compatible = "ad,tamonten", "nvidia,tegra20";
7*4882a593Smuzhiyun
8*4882a593Smuzhiyun	aliases {
9*4882a593Smuzhiyun		rtc0 = "/i2c@7000d000/tps6586x@34";
10*4882a593Smuzhiyun		rtc1 = "/rtc@7000e000";
11*4882a593Smuzhiyun		serial0 = &uartd;
12*4882a593Smuzhiyun	};
13*4882a593Smuzhiyun
14*4882a593Smuzhiyun	chosen {
15*4882a593Smuzhiyun		stdout-path = "serial0:115200n8";
16*4882a593Smuzhiyun	};
17*4882a593Smuzhiyun
18*4882a593Smuzhiyun	memory@0 {
19*4882a593Smuzhiyun		reg = <0x00000000 0x20000000>;
20*4882a593Smuzhiyun	};
21*4882a593Smuzhiyun
22*4882a593Smuzhiyun	host1x@50000000 {
23*4882a593Smuzhiyun		hdmi@54280000 {
24*4882a593Smuzhiyun			vdd-supply = <&hdmi_vdd_reg>;
25*4882a593Smuzhiyun			pll-supply = <&hdmi_pll_reg>;
26*4882a593Smuzhiyun
27*4882a593Smuzhiyun			nvidia,ddc-i2c-bus = <&hdmi_ddc>;
28*4882a593Smuzhiyun			nvidia,hpd-gpio = <&gpio TEGRA_GPIO(N, 7)
29*4882a593Smuzhiyun				GPIO_ACTIVE_HIGH>;
30*4882a593Smuzhiyun		};
31*4882a593Smuzhiyun	};
32*4882a593Smuzhiyun
33*4882a593Smuzhiyun	pinmux@70000014 {
34*4882a593Smuzhiyun		pinctrl-names = "default";
35*4882a593Smuzhiyun		pinctrl-0 = <&state_default>;
36*4882a593Smuzhiyun
37*4882a593Smuzhiyun		state_default: pinmux {
38*4882a593Smuzhiyun			ata {
39*4882a593Smuzhiyun				nvidia,pins = "ata";
40*4882a593Smuzhiyun				nvidia,function = "ide";
41*4882a593Smuzhiyun			};
42*4882a593Smuzhiyun			atb {
43*4882a593Smuzhiyun				nvidia,pins = "atb", "gma", "gme";
44*4882a593Smuzhiyun				nvidia,function = "sdio4";
45*4882a593Smuzhiyun			};
46*4882a593Smuzhiyun			atc {
47*4882a593Smuzhiyun				nvidia,pins = "atc";
48*4882a593Smuzhiyun				nvidia,function = "nand";
49*4882a593Smuzhiyun			};
50*4882a593Smuzhiyun			atd {
51*4882a593Smuzhiyun				nvidia,pins = "atd", "ate", "gmb", "gmd", "gpu",
52*4882a593Smuzhiyun					"spia", "spib", "spic";
53*4882a593Smuzhiyun				nvidia,function = "gmi";
54*4882a593Smuzhiyun			};
55*4882a593Smuzhiyun			cdev1 {
56*4882a593Smuzhiyun				nvidia,pins = "cdev1";
57*4882a593Smuzhiyun				nvidia,function = "plla_out";
58*4882a593Smuzhiyun			};
59*4882a593Smuzhiyun			cdev2 {
60*4882a593Smuzhiyun				nvidia,pins = "cdev2";
61*4882a593Smuzhiyun				nvidia,function = "pllp_out4";
62*4882a593Smuzhiyun			};
63*4882a593Smuzhiyun			crtp {
64*4882a593Smuzhiyun				nvidia,pins = "crtp";
65*4882a593Smuzhiyun				nvidia,function = "crt";
66*4882a593Smuzhiyun			};
67*4882a593Smuzhiyun			csus {
68*4882a593Smuzhiyun				nvidia,pins = "csus";
69*4882a593Smuzhiyun				nvidia,function = "vi_sensor_clk";
70*4882a593Smuzhiyun			};
71*4882a593Smuzhiyun			dap1 {
72*4882a593Smuzhiyun				nvidia,pins = "dap1";
73*4882a593Smuzhiyun				nvidia,function = "dap1";
74*4882a593Smuzhiyun			};
75*4882a593Smuzhiyun			dap2 {
76*4882a593Smuzhiyun				nvidia,pins = "dap2";
77*4882a593Smuzhiyun				nvidia,function = "dap2";
78*4882a593Smuzhiyun			};
79*4882a593Smuzhiyun			dap3 {
80*4882a593Smuzhiyun				nvidia,pins = "dap3";
81*4882a593Smuzhiyun				nvidia,function = "dap3";
82*4882a593Smuzhiyun			};
83*4882a593Smuzhiyun			dap4 {
84*4882a593Smuzhiyun				nvidia,pins = "dap4";
85*4882a593Smuzhiyun				nvidia,function = "dap4";
86*4882a593Smuzhiyun			};
87*4882a593Smuzhiyun			dta {
88*4882a593Smuzhiyun				nvidia,pins = "dta", "dtd";
89*4882a593Smuzhiyun				nvidia,function = "sdio2";
90*4882a593Smuzhiyun			};
91*4882a593Smuzhiyun			dtb {
92*4882a593Smuzhiyun				nvidia,pins = "dtb", "dtc", "dte";
93*4882a593Smuzhiyun				nvidia,function = "rsvd1";
94*4882a593Smuzhiyun			};
95*4882a593Smuzhiyun			dtf {
96*4882a593Smuzhiyun				nvidia,pins = "dtf";
97*4882a593Smuzhiyun				nvidia,function = "i2c3";
98*4882a593Smuzhiyun			};
99*4882a593Smuzhiyun			gmc {
100*4882a593Smuzhiyun				nvidia,pins = "gmc";
101*4882a593Smuzhiyun				nvidia,function = "uartd";
102*4882a593Smuzhiyun			};
103*4882a593Smuzhiyun			gpu7 {
104*4882a593Smuzhiyun				nvidia,pins = "gpu7";
105*4882a593Smuzhiyun				nvidia,function = "rtck";
106*4882a593Smuzhiyun			};
107*4882a593Smuzhiyun			gpv {
108*4882a593Smuzhiyun				nvidia,pins = "gpv", "slxa", "slxk";
109*4882a593Smuzhiyun				nvidia,function = "pcie";
110*4882a593Smuzhiyun			};
111*4882a593Smuzhiyun			hdint {
112*4882a593Smuzhiyun				nvidia,pins = "hdint";
113*4882a593Smuzhiyun				nvidia,function = "hdmi";
114*4882a593Smuzhiyun			};
115*4882a593Smuzhiyun			i2cp {
116*4882a593Smuzhiyun				nvidia,pins = "i2cp";
117*4882a593Smuzhiyun				nvidia,function = "i2cp";
118*4882a593Smuzhiyun			};
119*4882a593Smuzhiyun			irrx {
120*4882a593Smuzhiyun				nvidia,pins = "irrx", "irtx";
121*4882a593Smuzhiyun				nvidia,function = "uarta";
122*4882a593Smuzhiyun			};
123*4882a593Smuzhiyun			kbca {
124*4882a593Smuzhiyun				nvidia,pins = "kbca", "kbcb", "kbcc", "kbcd",
125*4882a593Smuzhiyun					"kbce", "kbcf";
126*4882a593Smuzhiyun				nvidia,function = "kbc";
127*4882a593Smuzhiyun			};
128*4882a593Smuzhiyun			lcsn {
129*4882a593Smuzhiyun				nvidia,pins = "lcsn", "ld0", "ld1", "ld2",
130*4882a593Smuzhiyun					"ld3", "ld4", "ld5", "ld6", "ld7",
131*4882a593Smuzhiyun					"ld8", "ld9", "ld10", "ld11", "ld12",
132*4882a593Smuzhiyun					"ld13", "ld14", "ld15", "ld16", "ld17",
133*4882a593Smuzhiyun					"ldc", "ldi", "lhp0", "lhp1", "lhp2",
134*4882a593Smuzhiyun					"lhs", "lm0", "lm1", "lpp", "lpw0",
135*4882a593Smuzhiyun					"lpw1", "lpw2", "lsc0", "lsc1", "lsck",
136*4882a593Smuzhiyun					"lsda", "lsdi", "lspi", "lvp0", "lvp1",
137*4882a593Smuzhiyun					"lvs";
138*4882a593Smuzhiyun				nvidia,function = "displaya";
139*4882a593Smuzhiyun			};
140*4882a593Smuzhiyun			owc {
141*4882a593Smuzhiyun				nvidia,pins = "owc", "spdi", "spdo", "uac";
142*4882a593Smuzhiyun				nvidia,function = "rsvd2";
143*4882a593Smuzhiyun			};
144*4882a593Smuzhiyun			pmc {
145*4882a593Smuzhiyun				nvidia,pins = "pmc";
146*4882a593Smuzhiyun				nvidia,function = "pwr_on";
147*4882a593Smuzhiyun			};
148*4882a593Smuzhiyun			rm {
149*4882a593Smuzhiyun				nvidia,pins = "rm";
150*4882a593Smuzhiyun				nvidia,function = "i2c1";
151*4882a593Smuzhiyun			};
152*4882a593Smuzhiyun			sdb {
153*4882a593Smuzhiyun				nvidia,pins = "sdb", "sdc", "sdd";
154*4882a593Smuzhiyun				nvidia,function = "pwm";
155*4882a593Smuzhiyun			};
156*4882a593Smuzhiyun			sdio1 {
157*4882a593Smuzhiyun				nvidia,pins = "sdio1";
158*4882a593Smuzhiyun				nvidia,function = "sdio1";
159*4882a593Smuzhiyun			};
160*4882a593Smuzhiyun			slxc {
161*4882a593Smuzhiyun				nvidia,pins = "slxc", "slxd";
162*4882a593Smuzhiyun				nvidia,function = "spdif";
163*4882a593Smuzhiyun			};
164*4882a593Smuzhiyun			spid {
165*4882a593Smuzhiyun				nvidia,pins = "spid", "spie", "spif";
166*4882a593Smuzhiyun				nvidia,function = "spi1";
167*4882a593Smuzhiyun			};
168*4882a593Smuzhiyun			spig {
169*4882a593Smuzhiyun				nvidia,pins = "spig", "spih";
170*4882a593Smuzhiyun				nvidia,function = "spi2_alt";
171*4882a593Smuzhiyun			};
172*4882a593Smuzhiyun			uaa {
173*4882a593Smuzhiyun				nvidia,pins = "uaa", "uab", "uda";
174*4882a593Smuzhiyun				nvidia,function = "ulpi";
175*4882a593Smuzhiyun			};
176*4882a593Smuzhiyun			uad {
177*4882a593Smuzhiyun				nvidia,pins = "uad";
178*4882a593Smuzhiyun				nvidia,function = "irda";
179*4882a593Smuzhiyun			};
180*4882a593Smuzhiyun			uca {
181*4882a593Smuzhiyun				nvidia,pins = "uca", "ucb";
182*4882a593Smuzhiyun				nvidia,function = "uartc";
183*4882a593Smuzhiyun			};
184*4882a593Smuzhiyun			conf_ata {
185*4882a593Smuzhiyun				nvidia,pins = "ata", "atb", "atc", "atd", "ate",
186*4882a593Smuzhiyun					"cdev1", "cdev2", "dap1", "dtb", "dtf",
187*4882a593Smuzhiyun					"gma", "gmb", "gmc", "gmd", "gme", "gpu7",
188*4882a593Smuzhiyun					"gpv", "i2cp", "irrx", "irtx", "pta",
189*4882a593Smuzhiyun					"rm", "slxa", "slxk", "spia", "spib",
190*4882a593Smuzhiyun					"uac";
191*4882a593Smuzhiyun				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
192*4882a593Smuzhiyun				nvidia,tristate = <TEGRA_PIN_DISABLE>;
193*4882a593Smuzhiyun			};
194*4882a593Smuzhiyun			conf_ck32 {
195*4882a593Smuzhiyun				nvidia,pins = "ck32", "ddrc", "pmca", "pmcb",
196*4882a593Smuzhiyun					"pmcc", "pmcd", "pmce", "xm2c", "xm2d";
197*4882a593Smuzhiyun				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
198*4882a593Smuzhiyun			};
199*4882a593Smuzhiyun			conf_csus {
200*4882a593Smuzhiyun				nvidia,pins = "csus", "spid", "spif";
201*4882a593Smuzhiyun				nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
202*4882a593Smuzhiyun				nvidia,tristate = <TEGRA_PIN_ENABLE>;
203*4882a593Smuzhiyun			};
204*4882a593Smuzhiyun			conf_crtp {
205*4882a593Smuzhiyun				nvidia,pins = "crtp", "dap2", "dap3", "dap4",
206*4882a593Smuzhiyun					"dtc", "dte", "gpu", "sdio1",
207*4882a593Smuzhiyun					"slxc", "slxd", "spdi", "spdo", "spig",
208*4882a593Smuzhiyun					"uda";
209*4882a593Smuzhiyun				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
210*4882a593Smuzhiyun				nvidia,tristate = <TEGRA_PIN_ENABLE>;
211*4882a593Smuzhiyun			};
212*4882a593Smuzhiyun			conf_ddc {
213*4882a593Smuzhiyun				nvidia,pins = "ddc", "dta", "dtd", "kbca",
214*4882a593Smuzhiyun					"kbcb", "kbcc", "kbcd", "kbce", "kbcf",
215*4882a593Smuzhiyun					"sdc", "uad", "uca";
216*4882a593Smuzhiyun				nvidia,pull = <TEGRA_PIN_PULL_UP>;
217*4882a593Smuzhiyun				nvidia,tristate = <TEGRA_PIN_DISABLE>;
218*4882a593Smuzhiyun			};
219*4882a593Smuzhiyun			conf_hdint {
220*4882a593Smuzhiyun				nvidia,pins = "hdint", "lcsn", "ldc", "lm1",
221*4882a593Smuzhiyun					"lpw1", "lsc1", "lsck", "lsda", "lsdi",
222*4882a593Smuzhiyun					"lvp0", "owc", "sdb";
223*4882a593Smuzhiyun				nvidia,tristate = <TEGRA_PIN_ENABLE>;
224*4882a593Smuzhiyun			};
225*4882a593Smuzhiyun			conf_sdd {
226*4882a593Smuzhiyun				nvidia,pins = "sdd", "spic", "spie", "spih",
227*4882a593Smuzhiyun					"uaa", "uab", "ucb";
228*4882a593Smuzhiyun				nvidia,pull = <TEGRA_PIN_PULL_UP>;
229*4882a593Smuzhiyun				nvidia,tristate = <TEGRA_PIN_ENABLE>;
230*4882a593Smuzhiyun			};
231*4882a593Smuzhiyun			conf_lc {
232*4882a593Smuzhiyun				nvidia,pins = "lc", "ls";
233*4882a593Smuzhiyun				nvidia,pull = <TEGRA_PIN_PULL_UP>;
234*4882a593Smuzhiyun			};
235*4882a593Smuzhiyun			conf_ld0 {
236*4882a593Smuzhiyun				nvidia,pins = "ld0", "ld1", "ld2", "ld3", "ld4",
237*4882a593Smuzhiyun					"ld5", "ld6", "ld7", "ld8", "ld9",
238*4882a593Smuzhiyun					"ld10", "ld11", "ld12", "ld13", "ld14",
239*4882a593Smuzhiyun					"ld15", "ld16", "ld17", "ldi", "lhp0",
240*4882a593Smuzhiyun					"lhp1", "lhp2", "lhs", "lm0", "lpp",
241*4882a593Smuzhiyun					"lpw0", "lpw2", "lsc0", "lspi", "lvp1",
242*4882a593Smuzhiyun					"lvs", "pmc";
243*4882a593Smuzhiyun				nvidia,tristate = <TEGRA_PIN_DISABLE>;
244*4882a593Smuzhiyun			};
245*4882a593Smuzhiyun			conf_ld17_0 {
246*4882a593Smuzhiyun				nvidia,pins = "ld17_0", "ld19_18", "ld21_20",
247*4882a593Smuzhiyun					"ld23_22";
248*4882a593Smuzhiyun				nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
249*4882a593Smuzhiyun			};
250*4882a593Smuzhiyun		};
251*4882a593Smuzhiyun
252*4882a593Smuzhiyun		state_i2cmux_ddc: pinmux_i2cmux_ddc {
253*4882a593Smuzhiyun			ddc {
254*4882a593Smuzhiyun				nvidia,pins = "ddc";
255*4882a593Smuzhiyun				nvidia,function = "i2c2";
256*4882a593Smuzhiyun			};
257*4882a593Smuzhiyun			pta {
258*4882a593Smuzhiyun				nvidia,pins = "pta";
259*4882a593Smuzhiyun				nvidia,function = "rsvd4";
260*4882a593Smuzhiyun			};
261*4882a593Smuzhiyun		};
262*4882a593Smuzhiyun
263*4882a593Smuzhiyun		state_i2cmux_pta: pinmux_i2cmux_pta {
264*4882a593Smuzhiyun			ddc {
265*4882a593Smuzhiyun				nvidia,pins = "ddc";
266*4882a593Smuzhiyun				nvidia,function = "rsvd4";
267*4882a593Smuzhiyun			};
268*4882a593Smuzhiyun			pta {
269*4882a593Smuzhiyun				nvidia,pins = "pta";
270*4882a593Smuzhiyun				nvidia,function = "i2c2";
271*4882a593Smuzhiyun			};
272*4882a593Smuzhiyun		};
273*4882a593Smuzhiyun
274*4882a593Smuzhiyun		state_i2cmux_idle: pinmux_i2cmux_idle {
275*4882a593Smuzhiyun			ddc {
276*4882a593Smuzhiyun				nvidia,pins = "ddc";
277*4882a593Smuzhiyun				nvidia,function = "rsvd4";
278*4882a593Smuzhiyun			};
279*4882a593Smuzhiyun			pta {
280*4882a593Smuzhiyun				nvidia,pins = "pta";
281*4882a593Smuzhiyun				nvidia,function = "rsvd4";
282*4882a593Smuzhiyun			};
283*4882a593Smuzhiyun		};
284*4882a593Smuzhiyun	};
285*4882a593Smuzhiyun
286*4882a593Smuzhiyun	i2s@70002800 {
287*4882a593Smuzhiyun		status = "okay";
288*4882a593Smuzhiyun	};
289*4882a593Smuzhiyun
290*4882a593Smuzhiyun	serial@70006300 {
291*4882a593Smuzhiyun		status = "okay";
292*4882a593Smuzhiyun	};
293*4882a593Smuzhiyun
294*4882a593Smuzhiyun	i2c@7000c000 {
295*4882a593Smuzhiyun		clock-frequency = <400000>;
296*4882a593Smuzhiyun		status = "okay";
297*4882a593Smuzhiyun	};
298*4882a593Smuzhiyun
299*4882a593Smuzhiyun	i2c@7000c400 {
300*4882a593Smuzhiyun		clock-frequency = <100000>;
301*4882a593Smuzhiyun		status = "okay";
302*4882a593Smuzhiyun	};
303*4882a593Smuzhiyun
304*4882a593Smuzhiyun	i2cmux {
305*4882a593Smuzhiyun		compatible = "i2c-mux-pinctrl";
306*4882a593Smuzhiyun		#address-cells = <1>;
307*4882a593Smuzhiyun		#size-cells = <0>;
308*4882a593Smuzhiyun
309*4882a593Smuzhiyun		i2c-parent = <&{/i2c@7000c400}>;
310*4882a593Smuzhiyun
311*4882a593Smuzhiyun		pinctrl-names = "ddc", "pta", "idle";
312*4882a593Smuzhiyun		pinctrl-0 = <&state_i2cmux_ddc>;
313*4882a593Smuzhiyun		pinctrl-1 = <&state_i2cmux_pta>;
314*4882a593Smuzhiyun		pinctrl-2 = <&state_i2cmux_idle>;
315*4882a593Smuzhiyun
316*4882a593Smuzhiyun		hdmi_ddc: i2c@0 {
317*4882a593Smuzhiyun			reg = <0>;
318*4882a593Smuzhiyun			#address-cells = <1>;
319*4882a593Smuzhiyun			#size-cells = <0>;
320*4882a593Smuzhiyun		};
321*4882a593Smuzhiyun
322*4882a593Smuzhiyun		i2c@1 {
323*4882a593Smuzhiyun			reg = <1>;
324*4882a593Smuzhiyun			#address-cells = <1>;
325*4882a593Smuzhiyun			#size-cells = <0>;
326*4882a593Smuzhiyun		};
327*4882a593Smuzhiyun	};
328*4882a593Smuzhiyun
329*4882a593Smuzhiyun	i2c@7000d000 {
330*4882a593Smuzhiyun		clock-frequency = <400000>;
331*4882a593Smuzhiyun		status = "okay";
332*4882a593Smuzhiyun
333*4882a593Smuzhiyun		pmic: tps6586x@34 {
334*4882a593Smuzhiyun			compatible = "ti,tps6586x";
335*4882a593Smuzhiyun			reg = <0x34>;
336*4882a593Smuzhiyun			interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
337*4882a593Smuzhiyun
338*4882a593Smuzhiyun			ti,system-power-controller;
339*4882a593Smuzhiyun
340*4882a593Smuzhiyun			#gpio-cells = <2>;
341*4882a593Smuzhiyun			gpio-controller;
342*4882a593Smuzhiyun
343*4882a593Smuzhiyun			/* vdd_5v0_reg must be provided by the base board */
344*4882a593Smuzhiyun			sys-supply = <&vdd_5v0_reg>;
345*4882a593Smuzhiyun			vin-sm0-supply = <&sys_reg>;
346*4882a593Smuzhiyun			vin-sm1-supply = <&sys_reg>;
347*4882a593Smuzhiyun			vin-sm2-supply = <&sys_reg>;
348*4882a593Smuzhiyun			vinldo01-supply = <&sm2_reg>;
349*4882a593Smuzhiyun			vinldo23-supply = <&sm2_reg>;
350*4882a593Smuzhiyun			vinldo4-supply = <&sm2_reg>;
351*4882a593Smuzhiyun			vinldo678-supply = <&sm2_reg>;
352*4882a593Smuzhiyun			vinldo9-supply = <&sm2_reg>;
353*4882a593Smuzhiyun
354*4882a593Smuzhiyun			regulators {
355*4882a593Smuzhiyun				sys_reg: sys {
356*4882a593Smuzhiyun					regulator-name = "vdd_sys";
357*4882a593Smuzhiyun					regulator-always-on;
358*4882a593Smuzhiyun				};
359*4882a593Smuzhiyun
360*4882a593Smuzhiyun				sm0 {
361*4882a593Smuzhiyun					regulator-name = "vdd_sys_sm0,vdd_core";
362*4882a593Smuzhiyun					regulator-min-microvolt = <1200000>;
363*4882a593Smuzhiyun					regulator-max-microvolt = <1200000>;
364*4882a593Smuzhiyun					regulator-always-on;
365*4882a593Smuzhiyun				};
366*4882a593Smuzhiyun
367*4882a593Smuzhiyun				sm1 {
368*4882a593Smuzhiyun					regulator-name = "vdd_sys_sm1,vdd_cpu";
369*4882a593Smuzhiyun					regulator-min-microvolt = <1000000>;
370*4882a593Smuzhiyun					regulator-max-microvolt = <1000000>;
371*4882a593Smuzhiyun					regulator-always-on;
372*4882a593Smuzhiyun				};
373*4882a593Smuzhiyun
374*4882a593Smuzhiyun				sm2_reg: sm2 {
375*4882a593Smuzhiyun					regulator-name = "vdd_sys_sm2,vin_ldo*";
376*4882a593Smuzhiyun					regulator-min-microvolt = <3700000>;
377*4882a593Smuzhiyun					regulator-max-microvolt = <3700000>;
378*4882a593Smuzhiyun					regulator-always-on;
379*4882a593Smuzhiyun				};
380*4882a593Smuzhiyun
381*4882a593Smuzhiyun				pci_clk_reg: ldo0 {
382*4882a593Smuzhiyun					regulator-name = "vdd_ldo0,vddio_pex_clk";
383*4882a593Smuzhiyun					regulator-min-microvolt = <3300000>;
384*4882a593Smuzhiyun					regulator-max-microvolt = <3300000>;
385*4882a593Smuzhiyun				};
386*4882a593Smuzhiyun
387*4882a593Smuzhiyun				ldo1 {
388*4882a593Smuzhiyun					regulator-name = "vdd_ldo1,avdd_pll*";
389*4882a593Smuzhiyun					regulator-min-microvolt = <1100000>;
390*4882a593Smuzhiyun					regulator-max-microvolt = <1100000>;
391*4882a593Smuzhiyun					regulator-always-on;
392*4882a593Smuzhiyun				};
393*4882a593Smuzhiyun
394*4882a593Smuzhiyun				ldo2 {
395*4882a593Smuzhiyun					regulator-name = "vdd_ldo2,vdd_rtc";
396*4882a593Smuzhiyun					regulator-min-microvolt = <1200000>;
397*4882a593Smuzhiyun					regulator-max-microvolt = <1200000>;
398*4882a593Smuzhiyun				};
399*4882a593Smuzhiyun
400*4882a593Smuzhiyun				ldo3 {
401*4882a593Smuzhiyun					regulator-name = "vdd_ldo3,avdd_usb*";
402*4882a593Smuzhiyun					regulator-min-microvolt = <3300000>;
403*4882a593Smuzhiyun					regulator-max-microvolt = <3300000>;
404*4882a593Smuzhiyun					regulator-always-on;
405*4882a593Smuzhiyun				};
406*4882a593Smuzhiyun
407*4882a593Smuzhiyun				ldo4 {
408*4882a593Smuzhiyun					regulator-name = "vdd_ldo4,avdd_osc,vddio_sys";
409*4882a593Smuzhiyun					regulator-min-microvolt = <1800000>;
410*4882a593Smuzhiyun					regulator-max-microvolt = <1800000>;
411*4882a593Smuzhiyun					regulator-always-on;
412*4882a593Smuzhiyun				};
413*4882a593Smuzhiyun
414*4882a593Smuzhiyun				ldo5 {
415*4882a593Smuzhiyun					regulator-name = "vdd_ldo5,vcore_mmc";
416*4882a593Smuzhiyun					regulator-min-microvolt = <2850000>;
417*4882a593Smuzhiyun					regulator-max-microvolt = <2850000>;
418*4882a593Smuzhiyun				};
419*4882a593Smuzhiyun
420*4882a593Smuzhiyun				ldo6 {
421*4882a593Smuzhiyun					regulator-name = "vdd_ldo6,avdd_vdac";
422*4882a593Smuzhiyun					/*
423*4882a593Smuzhiyun					 * According to the Tegra 2 Automotive
424*4882a593Smuzhiyun					 * DataSheet, a typical value for this
425*4882a593Smuzhiyun					 * would be 2.8V, but the PMIC only
426*4882a593Smuzhiyun					 * supports 2.85V.
427*4882a593Smuzhiyun					 */
428*4882a593Smuzhiyun					regulator-min-microvolt = <2850000>;
429*4882a593Smuzhiyun					regulator-max-microvolt = <2850000>;
430*4882a593Smuzhiyun				};
431*4882a593Smuzhiyun
432*4882a593Smuzhiyun				hdmi_vdd_reg: ldo7 {
433*4882a593Smuzhiyun					regulator-name = "vdd_ldo7,avdd_hdmi";
434*4882a593Smuzhiyun					regulator-min-microvolt = <3300000>;
435*4882a593Smuzhiyun					regulator-max-microvolt = <3300000>;
436*4882a593Smuzhiyun				};
437*4882a593Smuzhiyun
438*4882a593Smuzhiyun				hdmi_pll_reg: ldo8 {
439*4882a593Smuzhiyun					regulator-name = "vdd_ldo8,avdd_hdmi_pll";
440*4882a593Smuzhiyun					regulator-min-microvolt = <1800000>;
441*4882a593Smuzhiyun					regulator-max-microvolt = <1800000>;
442*4882a593Smuzhiyun				};
443*4882a593Smuzhiyun
444*4882a593Smuzhiyun				ldo9 {
445*4882a593Smuzhiyun					regulator-name = "vdd_ldo9,vdd_ddr_rx,avdd_cam";
446*4882a593Smuzhiyun					/*
447*4882a593Smuzhiyun					 * According to the Tegra 2 Automotive
448*4882a593Smuzhiyun					 * DataSheet, a typical value for this
449*4882a593Smuzhiyun					 * would be 2.8V, but the PMIC only
450*4882a593Smuzhiyun					 * supports 2.85V.
451*4882a593Smuzhiyun					 */
452*4882a593Smuzhiyun					regulator-min-microvolt = <2850000>;
453*4882a593Smuzhiyun					regulator-max-microvolt = <2850000>;
454*4882a593Smuzhiyun					regulator-always-on;
455*4882a593Smuzhiyun				};
456*4882a593Smuzhiyun
457*4882a593Smuzhiyun				ldo_rtc {
458*4882a593Smuzhiyun					regulator-name = "vdd_rtc_out";
459*4882a593Smuzhiyun					regulator-min-microvolt = <3300000>;
460*4882a593Smuzhiyun					regulator-max-microvolt = <3300000>;
461*4882a593Smuzhiyun					regulator-always-on;
462*4882a593Smuzhiyun				};
463*4882a593Smuzhiyun			};
464*4882a593Smuzhiyun		};
465*4882a593Smuzhiyun
466*4882a593Smuzhiyun		temperature-sensor@4c {
467*4882a593Smuzhiyun			compatible = "onnn,nct1008";
468*4882a593Smuzhiyun			reg = <0x4c>;
469*4882a593Smuzhiyun		};
470*4882a593Smuzhiyun	};
471*4882a593Smuzhiyun
472*4882a593Smuzhiyun	pmc@7000e400 {
473*4882a593Smuzhiyun		nvidia,invert-interrupt;
474*4882a593Smuzhiyun		nvidia,suspend-mode = <1>;
475*4882a593Smuzhiyun		nvidia,cpu-pwr-good-time = <5000>;
476*4882a593Smuzhiyun		nvidia,cpu-pwr-off-time = <5000>;
477*4882a593Smuzhiyun		nvidia,core-pwr-good-time = <3845 3845>;
478*4882a593Smuzhiyun		nvidia,core-pwr-off-time = <3875>;
479*4882a593Smuzhiyun		nvidia,sys-clock-req-active-high;
480*4882a593Smuzhiyun	};
481*4882a593Smuzhiyun
482*4882a593Smuzhiyun	pcie@80003000 {
483*4882a593Smuzhiyun		avdd-pex-supply = <&pci_vdd_reg>;
484*4882a593Smuzhiyun		vdd-pex-supply = <&pci_vdd_reg>;
485*4882a593Smuzhiyun		avdd-pex-pll-supply = <&pci_vdd_reg>;
486*4882a593Smuzhiyun		avdd-plle-supply = <&pci_vdd_reg>;
487*4882a593Smuzhiyun		vddio-pex-clk-supply = <&pci_clk_reg>;
488*4882a593Smuzhiyun	};
489*4882a593Smuzhiyun
490*4882a593Smuzhiyun	usb@c5008000 {
491*4882a593Smuzhiyun		status = "okay";
492*4882a593Smuzhiyun	};
493*4882a593Smuzhiyun
494*4882a593Smuzhiyun	usb-phy@c5008000 {
495*4882a593Smuzhiyun		status = "okay";
496*4882a593Smuzhiyun	};
497*4882a593Smuzhiyun
498*4882a593Smuzhiyun	mmc@c8000600 {
499*4882a593Smuzhiyun		cd-gpios = <&gpio TEGRA_GPIO(H, 2) GPIO_ACTIVE_LOW>;
500*4882a593Smuzhiyun		wp-gpios = <&gpio TEGRA_GPIO(H, 3) GPIO_ACTIVE_HIGH>;
501*4882a593Smuzhiyun		bus-width = <4>;
502*4882a593Smuzhiyun		status = "okay";
503*4882a593Smuzhiyun	};
504*4882a593Smuzhiyun
505*4882a593Smuzhiyun	clk32k_in: clock@0 {
506*4882a593Smuzhiyun		compatible = "fixed-clock";
507*4882a593Smuzhiyun		clock-frequency = <32768>;
508*4882a593Smuzhiyun		#clock-cells = <0>;
509*4882a593Smuzhiyun	};
510*4882a593Smuzhiyun
511*4882a593Smuzhiyun	pci_vdd_reg: regulator@1 {
512*4882a593Smuzhiyun		compatible = "regulator-fixed";
513*4882a593Smuzhiyun		regulator-name = "vdd_1v05";
514*4882a593Smuzhiyun		regulator-min-microvolt = <1050000>;
515*4882a593Smuzhiyun		regulator-max-microvolt = <1050000>;
516*4882a593Smuzhiyun		gpio = <&pmic 2 0>;
517*4882a593Smuzhiyun		enable-active-high;
518*4882a593Smuzhiyun	};
519*4882a593Smuzhiyun};
520