1*4882a593Smuzhiyun// SPDX-License-Identifier: GPL-2.0+ 2*4882a593Smuzhiyun/* 3*4882a593Smuzhiyun * Copyright 2018-2020 Purism SPC 4*4882a593Smuzhiyun */ 5*4882a593Smuzhiyun 6*4882a593Smuzhiyun/dts-v1/; 7*4882a593Smuzhiyun 8*4882a593Smuzhiyun#include "dt-bindings/input/input.h" 9*4882a593Smuzhiyun#include <dt-bindings/interrupt-controller/irq.h> 10*4882a593Smuzhiyun#include "dt-bindings/pwm/pwm.h" 11*4882a593Smuzhiyun#include "dt-bindings/usb/pd.h" 12*4882a593Smuzhiyun#include "imx8mq.dtsi" 13*4882a593Smuzhiyun 14*4882a593Smuzhiyun/ { 15*4882a593Smuzhiyun model = "Purism Librem 5"; 16*4882a593Smuzhiyun compatible = "purism,librem5", "fsl,imx8mq"; 17*4882a593Smuzhiyun 18*4882a593Smuzhiyun backlight_dsi: backlight-dsi { 19*4882a593Smuzhiyun compatible = "led-backlight"; 20*4882a593Smuzhiyun leds = <&led_backlight>; 21*4882a593Smuzhiyun }; 22*4882a593Smuzhiyun 23*4882a593Smuzhiyun pmic_osc: clock-pmic { 24*4882a593Smuzhiyun compatible = "fixed-clock"; 25*4882a593Smuzhiyun #clock-cells = <0>; 26*4882a593Smuzhiyun clock-frequency = <32768>; 27*4882a593Smuzhiyun clock-output-names = "pmic_osc"; 28*4882a593Smuzhiyun }; 29*4882a593Smuzhiyun 30*4882a593Smuzhiyun chosen { 31*4882a593Smuzhiyun stdout-path = &uart1; 32*4882a593Smuzhiyun }; 33*4882a593Smuzhiyun 34*4882a593Smuzhiyun gpio-keys { 35*4882a593Smuzhiyun compatible = "gpio-keys"; 36*4882a593Smuzhiyun pinctrl-names = "default"; 37*4882a593Smuzhiyun pinctrl-0 = <&pinctrl_keys>; 38*4882a593Smuzhiyun 39*4882a593Smuzhiyun vol-down { 40*4882a593Smuzhiyun label = "VOL_DOWN"; 41*4882a593Smuzhiyun gpios = <&gpio1 17 GPIO_ACTIVE_LOW>; 42*4882a593Smuzhiyun linux,code = <KEY_VOLUMEDOWN>; 43*4882a593Smuzhiyun }; 44*4882a593Smuzhiyun 45*4882a593Smuzhiyun vol-up { 46*4882a593Smuzhiyun label = "VOL_UP"; 47*4882a593Smuzhiyun gpios = <&gpio1 16 GPIO_ACTIVE_LOW>; 48*4882a593Smuzhiyun linux,code = <KEY_VOLUMEUP>; 49*4882a593Smuzhiyun }; 50*4882a593Smuzhiyun }; 51*4882a593Smuzhiyun 52*4882a593Smuzhiyun reg_aud_1v8: regulator-audio-1v8 { 53*4882a593Smuzhiyun compatible = "regulator-fixed"; 54*4882a593Smuzhiyun pinctrl-names = "default"; 55*4882a593Smuzhiyun pinctrl-0 = <&pinctrl_audiopwr>; 56*4882a593Smuzhiyun regulator-name = "AUDIO_PWR_EN"; 57*4882a593Smuzhiyun regulator-min-microvolt = <1800000>; 58*4882a593Smuzhiyun regulator-max-microvolt = <1800000>; 59*4882a593Smuzhiyun gpio = <&gpio1 4 GPIO_ACTIVE_HIGH>; 60*4882a593Smuzhiyun enable-active-high; 61*4882a593Smuzhiyun }; 62*4882a593Smuzhiyun 63*4882a593Smuzhiyun reg_gnss: regulator-gnss { 64*4882a593Smuzhiyun compatible = "regulator-fixed"; 65*4882a593Smuzhiyun pinctrl-names = "default"; 66*4882a593Smuzhiyun pinctrl-0 = <&pinctrl_gnsspwr>; 67*4882a593Smuzhiyun regulator-name = "GNSS"; 68*4882a593Smuzhiyun regulator-min-microvolt = <3300000>; 69*4882a593Smuzhiyun regulator-max-microvolt = <3300000>; 70*4882a593Smuzhiyun gpio = <&gpio3 12 GPIO_ACTIVE_HIGH>; 71*4882a593Smuzhiyun enable-active-high; 72*4882a593Smuzhiyun }; 73*4882a593Smuzhiyun 74*4882a593Smuzhiyun reg_hub: regulator-hub { 75*4882a593Smuzhiyun compatible = "regulator-fixed"; 76*4882a593Smuzhiyun pinctrl-names = "default"; 77*4882a593Smuzhiyun pinctrl-0 = <&pinctrl_hub_pwr>; 78*4882a593Smuzhiyun regulator-name = "HUB"; 79*4882a593Smuzhiyun regulator-min-microvolt = <3300000>; 80*4882a593Smuzhiyun regulator-max-microvolt = <3300000>; 81*4882a593Smuzhiyun gpio = <&gpio1 14 GPIO_ACTIVE_HIGH>; 82*4882a593Smuzhiyun enable-active-high; 83*4882a593Smuzhiyun }; 84*4882a593Smuzhiyun 85*4882a593Smuzhiyun reg_lcd_3v4: regulator-lcd-3v4 { 86*4882a593Smuzhiyun compatible = "regulator-fixed"; 87*4882a593Smuzhiyun regulator-name = "LCD_3V4"; 88*4882a593Smuzhiyun pinctrl-names = "default"; 89*4882a593Smuzhiyun pinctrl-0 = <&pinctrl_dsibiasen>; 90*4882a593Smuzhiyun vin-supply = <®_vsys_3v4>; 91*4882a593Smuzhiyun gpio = <&gpio1 20 GPIO_ACTIVE_HIGH>; 92*4882a593Smuzhiyun enable-active-high; 93*4882a593Smuzhiyun }; 94*4882a593Smuzhiyun 95*4882a593Smuzhiyun reg_vdd_sen: regulator-vdd-sen { 96*4882a593Smuzhiyun compatible = "regulator-fixed"; 97*4882a593Smuzhiyun regulator-name = "VDD_SEN"; 98*4882a593Smuzhiyun regulator-min-microvolt = <3300000>; 99*4882a593Smuzhiyun regulator-max-microvolt = <3300000>; 100*4882a593Smuzhiyun }; 101*4882a593Smuzhiyun 102*4882a593Smuzhiyun reg_vdd_3v3: regulator-vdd-3v3 { 103*4882a593Smuzhiyun compatible = "regulator-fixed"; 104*4882a593Smuzhiyun regulator-name = "VDD_3V3"; 105*4882a593Smuzhiyun regulator-min-microvolt = <3300000>; 106*4882a593Smuzhiyun regulator-max-microvolt = <3300000>; 107*4882a593Smuzhiyun }; 108*4882a593Smuzhiyun 109*4882a593Smuzhiyun reg_vdd_1v8: regulator-vdd-1v8 { 110*4882a593Smuzhiyun compatible = "regulator-fixed"; 111*4882a593Smuzhiyun regulator-name = "VCC_1V8"; 112*4882a593Smuzhiyun regulator-min-microvolt = <1800000>; 113*4882a593Smuzhiyun regulator-max-microvolt = <1800000>; 114*4882a593Smuzhiyun }; 115*4882a593Smuzhiyun 116*4882a593Smuzhiyun reg_vsys_3v4: regulator-vsys-3v4 { 117*4882a593Smuzhiyun compatible = "regulator-fixed"; 118*4882a593Smuzhiyun regulator-name = "VSYS_3V4"; 119*4882a593Smuzhiyun regulator-min-microvolt = <3400000>; 120*4882a593Smuzhiyun regulator-max-microvolt = <3400000>; 121*4882a593Smuzhiyun regulator-always-on; 122*4882a593Smuzhiyun }; 123*4882a593Smuzhiyun 124*4882a593Smuzhiyun reg_wifi_3v3: regulator-wifi-3v3 { 125*4882a593Smuzhiyun compatible = "regulator-fixed"; 126*4882a593Smuzhiyun regulator-name = "3V3_WIFI"; 127*4882a593Smuzhiyun regulator-min-microvolt = <3300000>; 128*4882a593Smuzhiyun regulator-max-microvolt = <3300000>; 129*4882a593Smuzhiyun }; 130*4882a593Smuzhiyun 131*4882a593Smuzhiyun sound { 132*4882a593Smuzhiyun compatible = "simple-audio-card"; 133*4882a593Smuzhiyun pinctrl-names = "default"; 134*4882a593Smuzhiyun pinctrl-0 = <&pinctrl_hp>; 135*4882a593Smuzhiyun simple-audio-card,name = "Librem 5"; 136*4882a593Smuzhiyun simple-audio-card,format = "i2s"; 137*4882a593Smuzhiyun simple-audio-card,widgets = 138*4882a593Smuzhiyun "Headphone", "Headphones", 139*4882a593Smuzhiyun "Microphone", "Headset Mic", 140*4882a593Smuzhiyun "Microphone", "Digital Mic", 141*4882a593Smuzhiyun "Speaker", "Speaker"; 142*4882a593Smuzhiyun simple-audio-card,routing = 143*4882a593Smuzhiyun "Headphones", "HPOUTL", 144*4882a593Smuzhiyun "Headphones", "HPOUTR", 145*4882a593Smuzhiyun "Speaker", "SPKOUTL", 146*4882a593Smuzhiyun "Speaker", "SPKOUTR", 147*4882a593Smuzhiyun "Headset Mic", "MICBIAS", 148*4882a593Smuzhiyun "IN3R", "Headset Mic", 149*4882a593Smuzhiyun "DMICDAT", "Digital Mic"; 150*4882a593Smuzhiyun simple-audio-card,hp-det-gpio = <&gpio3 9 GPIO_ACTIVE_HIGH>; 151*4882a593Smuzhiyun 152*4882a593Smuzhiyun simple-audio-card,cpu { 153*4882a593Smuzhiyun sound-dai = <&sai2>; 154*4882a593Smuzhiyun }; 155*4882a593Smuzhiyun 156*4882a593Smuzhiyun simple-audio-card,codec { 157*4882a593Smuzhiyun sound-dai = <&codec>; 158*4882a593Smuzhiyun clocks = <&clk IMX8MQ_CLK_SAI2_ROOT>; 159*4882a593Smuzhiyun frame-master; 160*4882a593Smuzhiyun bitclock-master; 161*4882a593Smuzhiyun }; 162*4882a593Smuzhiyun }; 163*4882a593Smuzhiyun 164*4882a593Smuzhiyun sound-wwan { 165*4882a593Smuzhiyun compatible = "simple-audio-card"; 166*4882a593Smuzhiyun simple-audio-card,name = "Modem"; 167*4882a593Smuzhiyun simple-audio-card,format = "i2s"; 168*4882a593Smuzhiyun 169*4882a593Smuzhiyun simple-audio-card,cpu { 170*4882a593Smuzhiyun sound-dai = <&sai6>; 171*4882a593Smuzhiyun frame-inversion; 172*4882a593Smuzhiyun }; 173*4882a593Smuzhiyun 174*4882a593Smuzhiyun simple-audio-card,codec { 175*4882a593Smuzhiyun sound-dai = <&bm818_codec>; 176*4882a593Smuzhiyun frame-master; 177*4882a593Smuzhiyun bitclock-master; 178*4882a593Smuzhiyun }; 179*4882a593Smuzhiyun }; 180*4882a593Smuzhiyun 181*4882a593Smuzhiyun bm818_codec: sound-wwan-codec { 182*4882a593Smuzhiyun compatible = "broadmobi,bm818", "option,gtm601"; 183*4882a593Smuzhiyun #sound-dai-cells = <0>; 184*4882a593Smuzhiyun }; 185*4882a593Smuzhiyun 186*4882a593Smuzhiyun vibrator { 187*4882a593Smuzhiyun compatible = "pwm-vibrator"; 188*4882a593Smuzhiyun pwms = <&pwm1 0 1000000000 0>; 189*4882a593Smuzhiyun pwm-names = "enable"; 190*4882a593Smuzhiyun vcc-supply = <®_vdd_3v3>; 191*4882a593Smuzhiyun }; 192*4882a593Smuzhiyun}; 193*4882a593Smuzhiyun 194*4882a593Smuzhiyun&A53_0 { 195*4882a593Smuzhiyun cpu-supply = <&buck2_reg>; 196*4882a593Smuzhiyun}; 197*4882a593Smuzhiyun 198*4882a593Smuzhiyun&A53_1 { 199*4882a593Smuzhiyun cpu-supply = <&buck2_reg>; 200*4882a593Smuzhiyun}; 201*4882a593Smuzhiyun 202*4882a593Smuzhiyun&A53_2 { 203*4882a593Smuzhiyun cpu-supply = <&buck2_reg>; 204*4882a593Smuzhiyun}; 205*4882a593Smuzhiyun 206*4882a593Smuzhiyun&A53_3 { 207*4882a593Smuzhiyun cpu-supply = <&buck2_reg>; 208*4882a593Smuzhiyun}; 209*4882a593Smuzhiyun 210*4882a593Smuzhiyun&ddrc { 211*4882a593Smuzhiyun operating-points-v2 = <&ddrc_opp_table>; 212*4882a593Smuzhiyun 213*4882a593Smuzhiyun ddrc_opp_table: ddrc-opp-table { 214*4882a593Smuzhiyun compatible = "operating-points-v2"; 215*4882a593Smuzhiyun 216*4882a593Smuzhiyun opp-25M { 217*4882a593Smuzhiyun opp-hz = /bits/ 64 <25000000>; 218*4882a593Smuzhiyun }; 219*4882a593Smuzhiyun 220*4882a593Smuzhiyun opp-100M { 221*4882a593Smuzhiyun opp-hz = /bits/ 64 <100000000>; 222*4882a593Smuzhiyun }; 223*4882a593Smuzhiyun 224*4882a593Smuzhiyun opp-800M { 225*4882a593Smuzhiyun opp-hz = /bits/ 64 <800000000>; 226*4882a593Smuzhiyun }; 227*4882a593Smuzhiyun }; 228*4882a593Smuzhiyun}; 229*4882a593Smuzhiyun 230*4882a593Smuzhiyun&dphy { 231*4882a593Smuzhiyun status = "okay"; 232*4882a593Smuzhiyun}; 233*4882a593Smuzhiyun 234*4882a593Smuzhiyun&ecspi1 { 235*4882a593Smuzhiyun pinctrl-names = "default"; 236*4882a593Smuzhiyun pinctrl-0 = <&pinctrl_ecspi1>; 237*4882a593Smuzhiyun cs-gpios = <&gpio5 9 GPIO_ACTIVE_LOW>; 238*4882a593Smuzhiyun #address-cells = <1>; 239*4882a593Smuzhiyun #size-cells = <0>; 240*4882a593Smuzhiyun status = "okay"; 241*4882a593Smuzhiyun 242*4882a593Smuzhiyun nor_flash: flash@0 { 243*4882a593Smuzhiyun compatible = "jedec,spi-nor"; 244*4882a593Smuzhiyun reg = <0>; 245*4882a593Smuzhiyun spi-max-frequency = <1000000>; 246*4882a593Smuzhiyun }; 247*4882a593Smuzhiyun}; 248*4882a593Smuzhiyun 249*4882a593Smuzhiyun&gpio1 { 250*4882a593Smuzhiyun pinctrl-names = "default"; 251*4882a593Smuzhiyun pinctrl-0 = <&pinctrl_pmic_5v>; 252*4882a593Smuzhiyun 253*4882a593Smuzhiyun pmic-5v { 254*4882a593Smuzhiyun gpio-hog; 255*4882a593Smuzhiyun gpios = <&gpio1 1 GPIO_ACTIVE_HIGH>; 256*4882a593Smuzhiyun input; 257*4882a593Smuzhiyun }; 258*4882a593Smuzhiyun}; 259*4882a593Smuzhiyun 260*4882a593Smuzhiyun&iomuxc { 261*4882a593Smuzhiyun pinctrl_audiopwr: audiopwrgrp { 262*4882a593Smuzhiyun fsl,pins = < 263*4882a593Smuzhiyun /* AUDIO_POWER_EN_3V3 */ 264*4882a593Smuzhiyun MX8MQ_IOMUXC_GPIO1_IO04_GPIO1_IO4 0x83 265*4882a593Smuzhiyun >; 266*4882a593Smuzhiyun }; 267*4882a593Smuzhiyun 268*4882a593Smuzhiyun pinctrl_bl: blgrp { 269*4882a593Smuzhiyun fsl,pins = < 270*4882a593Smuzhiyun /* BACKLINGE_EN */ 271*4882a593Smuzhiyun MX8MQ_IOMUXC_NAND_DQS_GPIO3_IO14 0x83 272*4882a593Smuzhiyun >; 273*4882a593Smuzhiyun }; 274*4882a593Smuzhiyun 275*4882a593Smuzhiyun pinctrl_charger_in: chargeringrp { 276*4882a593Smuzhiyun fsl,pins = < 277*4882a593Smuzhiyun /* CHRG_INT */ 278*4882a593Smuzhiyun MX8MQ_IOMUXC_NAND_CE2_B_GPIO3_IO3 0x00 279*4882a593Smuzhiyun /* CHG_STATUS_B */ 280*4882a593Smuzhiyun MX8MQ_IOMUXC_NAND_ALE_GPIO3_IO0 0x80 281*4882a593Smuzhiyun >; 282*4882a593Smuzhiyun }; 283*4882a593Smuzhiyun 284*4882a593Smuzhiyun pinctrl_dsibiasen: dsibiasengrp { 285*4882a593Smuzhiyun fsl,pins = < 286*4882a593Smuzhiyun /* DSI_BIAS_EN */ 287*4882a593Smuzhiyun MX8MQ_IOMUXC_ENET_TD1_GPIO1_IO20 0x83 288*4882a593Smuzhiyun >; 289*4882a593Smuzhiyun }; 290*4882a593Smuzhiyun 291*4882a593Smuzhiyun pinctrl_dsien: dsiengrp { 292*4882a593Smuzhiyun fsl,pins = < 293*4882a593Smuzhiyun /* DSI_EN_3V3 */ 294*4882a593Smuzhiyun MX8MQ_IOMUXC_GPIO1_IO05_GPIO1_IO5 0x83 295*4882a593Smuzhiyun >; 296*4882a593Smuzhiyun }; 297*4882a593Smuzhiyun 298*4882a593Smuzhiyun pinctrl_ecspi1: ecspigrp { 299*4882a593Smuzhiyun fsl,pins = < 300*4882a593Smuzhiyun MX8MQ_IOMUXC_ECSPI1_MOSI_ECSPI1_MOSI 0x83 301*4882a593Smuzhiyun MX8MQ_IOMUXC_ECSPI1_MISO_ECSPI1_MISO 0x83 302*4882a593Smuzhiyun MX8MQ_IOMUXC_ECSPI1_SS0_GPIO5_IO9 0x19 303*4882a593Smuzhiyun MX8MQ_IOMUXC_ECSPI1_SCLK_ECSPI1_SCLK 0x83 304*4882a593Smuzhiyun >; 305*4882a593Smuzhiyun }; 306*4882a593Smuzhiyun 307*4882a593Smuzhiyun pinctrl_gauge: gaugegrp { 308*4882a593Smuzhiyun fsl,pins = < 309*4882a593Smuzhiyun /* BAT_LOW */ 310*4882a593Smuzhiyun MX8MQ_IOMUXC_SAI5_RXC_GPIO3_IO20 0x80 311*4882a593Smuzhiyun >; 312*4882a593Smuzhiyun }; 313*4882a593Smuzhiyun 314*4882a593Smuzhiyun pinctrl_gnsspwr: gnsspwrgrp { 315*4882a593Smuzhiyun fsl,pins = < 316*4882a593Smuzhiyun /* GPS3V3_EN */ 317*4882a593Smuzhiyun MX8MQ_IOMUXC_NAND_DATA06_GPIO3_IO12 0x83 318*4882a593Smuzhiyun >; 319*4882a593Smuzhiyun }; 320*4882a593Smuzhiyun 321*4882a593Smuzhiyun pinctrl_haptic: hapticgrp { 322*4882a593Smuzhiyun fsl,pins = < 323*4882a593Smuzhiyun /* MOTO */ 324*4882a593Smuzhiyun MX8MQ_IOMUXC_SPDIF_EXT_CLK_PWM1_OUT 0x83 325*4882a593Smuzhiyun >; 326*4882a593Smuzhiyun }; 327*4882a593Smuzhiyun 328*4882a593Smuzhiyun pinctrl_hp: hpgrp { 329*4882a593Smuzhiyun fsl,pins = < 330*4882a593Smuzhiyun /* HEADPHONE_DET_1V8 */ 331*4882a593Smuzhiyun MX8MQ_IOMUXC_NAND_DATA03_GPIO3_IO9 0x180 332*4882a593Smuzhiyun >; 333*4882a593Smuzhiyun }; 334*4882a593Smuzhiyun 335*4882a593Smuzhiyun pinctrl_hub_pwr: hubpwrgrp { 336*4882a593Smuzhiyun fsl,pins = < 337*4882a593Smuzhiyun /* HUB_PWR_3V3_EN */ 338*4882a593Smuzhiyun MX8MQ_IOMUXC_GPIO1_IO14_GPIO1_IO14 0x83 339*4882a593Smuzhiyun >; 340*4882a593Smuzhiyun }; 341*4882a593Smuzhiyun 342*4882a593Smuzhiyun pinctrl_i2c1: i2c1grp { 343*4882a593Smuzhiyun fsl,pins = < 344*4882a593Smuzhiyun MX8MQ_IOMUXC_I2C1_SCL_I2C1_SCL 0x40000026 345*4882a593Smuzhiyun MX8MQ_IOMUXC_I2C1_SDA_I2C1_SDA 0x40000026 346*4882a593Smuzhiyun >; 347*4882a593Smuzhiyun }; 348*4882a593Smuzhiyun 349*4882a593Smuzhiyun pinctrl_i2c2: i2c2grp { 350*4882a593Smuzhiyun fsl,pins = < 351*4882a593Smuzhiyun MX8MQ_IOMUXC_I2C2_SCL_I2C2_SCL 0x40000026 352*4882a593Smuzhiyun MX8MQ_IOMUXC_I2C2_SDA_I2C2_SDA 0x40000026 353*4882a593Smuzhiyun >; 354*4882a593Smuzhiyun }; 355*4882a593Smuzhiyun 356*4882a593Smuzhiyun pinctrl_i2c3: i2c3grp { 357*4882a593Smuzhiyun fsl,pins = < 358*4882a593Smuzhiyun MX8MQ_IOMUXC_I2C3_SCL_I2C3_SCL 0x40000026 359*4882a593Smuzhiyun MX8MQ_IOMUXC_I2C3_SDA_I2C3_SDA 0x40000026 360*4882a593Smuzhiyun >; 361*4882a593Smuzhiyun }; 362*4882a593Smuzhiyun 363*4882a593Smuzhiyun pinctrl_i2c4: i2c4grp { 364*4882a593Smuzhiyun fsl,pins = < 365*4882a593Smuzhiyun MX8MQ_IOMUXC_I2C4_SCL_I2C4_SCL 0x40000026 366*4882a593Smuzhiyun MX8MQ_IOMUXC_I2C4_SDA_I2C4_SDA 0x40000026 367*4882a593Smuzhiyun >; 368*4882a593Smuzhiyun }; 369*4882a593Smuzhiyun 370*4882a593Smuzhiyun pinctrl_keys: keysgrp { 371*4882a593Smuzhiyun fsl,pins = < 372*4882a593Smuzhiyun /* VOL- */ 373*4882a593Smuzhiyun MX8MQ_IOMUXC_ENET_MDIO_GPIO1_IO17 0x01C0 374*4882a593Smuzhiyun /* VOL+ */ 375*4882a593Smuzhiyun MX8MQ_IOMUXC_ENET_MDC_GPIO1_IO16 0x01C0 376*4882a593Smuzhiyun >; 377*4882a593Smuzhiyun }; 378*4882a593Smuzhiyun 379*4882a593Smuzhiyun pinctrl_led_b: ledbgrp { 380*4882a593Smuzhiyun fsl,pins = < 381*4882a593Smuzhiyun /* LED_B */ 382*4882a593Smuzhiyun MX8MQ_IOMUXC_GPIO1_IO13_PWM2_OUT 0x06 383*4882a593Smuzhiyun >; 384*4882a593Smuzhiyun }; 385*4882a593Smuzhiyun 386*4882a593Smuzhiyun pinctrl_led_g: ledggrp { 387*4882a593Smuzhiyun fsl,pins = < 388*4882a593Smuzhiyun /* LED_G */ 389*4882a593Smuzhiyun MX8MQ_IOMUXC_SAI3_MCLK_PWM4_OUT 0x06 390*4882a593Smuzhiyun >; 391*4882a593Smuzhiyun }; 392*4882a593Smuzhiyun 393*4882a593Smuzhiyun pinctrl_led_r: ledrgrp { 394*4882a593Smuzhiyun fsl,pins = < 395*4882a593Smuzhiyun /* LED_R */ 396*4882a593Smuzhiyun MX8MQ_IOMUXC_SPDIF_TX_PWM3_OUT 0x06 397*4882a593Smuzhiyun >; 398*4882a593Smuzhiyun }; 399*4882a593Smuzhiyun 400*4882a593Smuzhiyun pinctrl_mag: maggrp { 401*4882a593Smuzhiyun fsl,pins = < 402*4882a593Smuzhiyun /* INT_MAG */ 403*4882a593Smuzhiyun MX8MQ_IOMUXC_SAI5_RXD1_GPIO3_IO22 0x80 404*4882a593Smuzhiyun >; 405*4882a593Smuzhiyun }; 406*4882a593Smuzhiyun 407*4882a593Smuzhiyun pinctrl_pmic: pmicgrp { 408*4882a593Smuzhiyun fsl,pins = < 409*4882a593Smuzhiyun /* PMIC_NINT */ 410*4882a593Smuzhiyun MX8MQ_IOMUXC_GPIO1_IO07_GPIO1_IO7 0x80 411*4882a593Smuzhiyun >; 412*4882a593Smuzhiyun }; 413*4882a593Smuzhiyun 414*4882a593Smuzhiyun pinctrl_pmic_5v: pmic5vgrp { 415*4882a593Smuzhiyun fsl,pins = < 416*4882a593Smuzhiyun /* PMIC_5V */ 417*4882a593Smuzhiyun MX8MQ_IOMUXC_GPIO1_IO01_GPIO1_IO1 0x80 418*4882a593Smuzhiyun >; 419*4882a593Smuzhiyun }; 420*4882a593Smuzhiyun 421*4882a593Smuzhiyun pinctrl_prox: proxgrp { 422*4882a593Smuzhiyun fsl,pins = < 423*4882a593Smuzhiyun /* INT_LIGHT */ 424*4882a593Smuzhiyun MX8MQ_IOMUXC_NAND_DATA01_GPIO3_IO7 0x80 425*4882a593Smuzhiyun >; 426*4882a593Smuzhiyun }; 427*4882a593Smuzhiyun 428*4882a593Smuzhiyun pinctrl_rtc: rtcgrp { 429*4882a593Smuzhiyun fsl,pins = < 430*4882a593Smuzhiyun /* RTC_INT */ 431*4882a593Smuzhiyun MX8MQ_IOMUXC_GPIO1_IO09_GPIO1_IO9 0x80 432*4882a593Smuzhiyun >; 433*4882a593Smuzhiyun }; 434*4882a593Smuzhiyun 435*4882a593Smuzhiyun pinctrl_sai2: sai2grp { 436*4882a593Smuzhiyun fsl,pins = < 437*4882a593Smuzhiyun MX8MQ_IOMUXC_SAI2_TXD0_SAI2_TX_DATA0 0xd6 438*4882a593Smuzhiyun MX8MQ_IOMUXC_SAI2_TXFS_SAI2_TX_SYNC 0xd6 439*4882a593Smuzhiyun MX8MQ_IOMUXC_SAI2_MCLK_SAI2_MCLK 0xd6 440*4882a593Smuzhiyun MX8MQ_IOMUXC_SAI2_RXD0_SAI2_RX_DATA0 0xd6 441*4882a593Smuzhiyun MX8MQ_IOMUXC_SAI2_TXC_SAI2_TX_BCLK 0xd6 442*4882a593Smuzhiyun >; 443*4882a593Smuzhiyun }; 444*4882a593Smuzhiyun 445*4882a593Smuzhiyun pinctrl_sai6: sai6grp { 446*4882a593Smuzhiyun fsl,pins = < 447*4882a593Smuzhiyun MX8MQ_IOMUXC_SAI1_RXD5_SAI6_RX_DATA0 0xd6 448*4882a593Smuzhiyun MX8MQ_IOMUXC_SAI1_RXD6_SAI6_RX_SYNC 0xd6 449*4882a593Smuzhiyun MX8MQ_IOMUXC_SAI1_TXD4_SAI6_RX_BCLK 0xd6 450*4882a593Smuzhiyun MX8MQ_IOMUXC_SAI1_TXD5_SAI6_TX_DATA0 0xd6 451*4882a593Smuzhiyun >; 452*4882a593Smuzhiyun }; 453*4882a593Smuzhiyun 454*4882a593Smuzhiyun pinctrl_tcpc: tcpcgrp { 455*4882a593Smuzhiyun fsl,pins = < 456*4882a593Smuzhiyun /* TCPC_INT */ 457*4882a593Smuzhiyun MX8MQ_IOMUXC_GPIO1_IO10_GPIO1_IO10 0x01C0 458*4882a593Smuzhiyun >; 459*4882a593Smuzhiyun }; 460*4882a593Smuzhiyun 461*4882a593Smuzhiyun pinctrl_typec: typecgrp { 462*4882a593Smuzhiyun fsl,pins = < 463*4882a593Smuzhiyun /* TYPEC_MUX_EN */ 464*4882a593Smuzhiyun MX8MQ_IOMUXC_GPIO1_IO11_GPIO1_IO11 0x83 465*4882a593Smuzhiyun >; 466*4882a593Smuzhiyun }; 467*4882a593Smuzhiyun 468*4882a593Smuzhiyun pinctrl_uart1: uart1grp { 469*4882a593Smuzhiyun fsl,pins = < 470*4882a593Smuzhiyun MX8MQ_IOMUXC_UART1_RXD_UART1_DCE_RX 0x49 471*4882a593Smuzhiyun MX8MQ_IOMUXC_UART1_TXD_UART1_DCE_TX 0x49 472*4882a593Smuzhiyun >; 473*4882a593Smuzhiyun }; 474*4882a593Smuzhiyun 475*4882a593Smuzhiyun pinctrl_uart2: uart2grp { 476*4882a593Smuzhiyun fsl,pins = < 477*4882a593Smuzhiyun MX8MQ_IOMUXC_UART2_TXD_UART2_DCE_TX 0x49 478*4882a593Smuzhiyun MX8MQ_IOMUXC_UART2_RXD_UART2_DCE_RX 0x49 479*4882a593Smuzhiyun >; 480*4882a593Smuzhiyun }; 481*4882a593Smuzhiyun 482*4882a593Smuzhiyun pinctrl_uart3: uart3grp { 483*4882a593Smuzhiyun fsl,pins = < 484*4882a593Smuzhiyun MX8MQ_IOMUXC_UART3_RXD_UART3_DCE_RX 0x49 485*4882a593Smuzhiyun MX8MQ_IOMUXC_UART3_TXD_UART3_DCE_TX 0x49 486*4882a593Smuzhiyun >; 487*4882a593Smuzhiyun }; 488*4882a593Smuzhiyun 489*4882a593Smuzhiyun pinctrl_uart4: uart4grp { 490*4882a593Smuzhiyun fsl,pins = < 491*4882a593Smuzhiyun MX8MQ_IOMUXC_ECSPI2_SCLK_UART4_DCE_RX 0x49 492*4882a593Smuzhiyun MX8MQ_IOMUXC_ECSPI2_MOSI_UART4_DCE_TX 0x49 493*4882a593Smuzhiyun MX8MQ_IOMUXC_ECSPI2_MISO_UART4_DCE_CTS_B 0x49 494*4882a593Smuzhiyun MX8MQ_IOMUXC_ECSPI2_SS0_UART4_DCE_RTS_B 0x49 495*4882a593Smuzhiyun >; 496*4882a593Smuzhiyun }; 497*4882a593Smuzhiyun 498*4882a593Smuzhiyun pinctrl_usdhc1: usdhc1grp { 499*4882a593Smuzhiyun fsl,pins = < 500*4882a593Smuzhiyun MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK 0x83 501*4882a593Smuzhiyun MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD 0xc3 502*4882a593Smuzhiyun MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0 0xc3 503*4882a593Smuzhiyun MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1 0xc3 504*4882a593Smuzhiyun MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2 0xc3 505*4882a593Smuzhiyun MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3 0xc3 506*4882a593Smuzhiyun MX8MQ_IOMUXC_SD1_DATA4_USDHC1_DATA4 0xc3 507*4882a593Smuzhiyun MX8MQ_IOMUXC_SD1_DATA5_USDHC1_DATA5 0xc3 508*4882a593Smuzhiyun MX8MQ_IOMUXC_SD1_DATA6_USDHC1_DATA6 0xc3 509*4882a593Smuzhiyun MX8MQ_IOMUXC_SD1_DATA7_USDHC1_DATA7 0xc3 510*4882a593Smuzhiyun MX8MQ_IOMUXC_SD1_STROBE_USDHC1_STROBE 0x83 511*4882a593Smuzhiyun MX8MQ_IOMUXC_SD1_RESET_B_USDHC1_RESET_B 0xc1 512*4882a593Smuzhiyun >; 513*4882a593Smuzhiyun }; 514*4882a593Smuzhiyun 515*4882a593Smuzhiyun pinctrl_usdhc1_100mhz: usdhc1grp100mhz { 516*4882a593Smuzhiyun fsl,pins = < 517*4882a593Smuzhiyun MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK 0x8d 518*4882a593Smuzhiyun MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD 0xcd 519*4882a593Smuzhiyun MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0 0xcd 520*4882a593Smuzhiyun MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1 0xcd 521*4882a593Smuzhiyun MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2 0xcd 522*4882a593Smuzhiyun MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3 0xcd 523*4882a593Smuzhiyun MX8MQ_IOMUXC_SD1_DATA4_USDHC1_DATA4 0xcd 524*4882a593Smuzhiyun MX8MQ_IOMUXC_SD1_DATA5_USDHC1_DATA5 0xcd 525*4882a593Smuzhiyun MX8MQ_IOMUXC_SD1_DATA6_USDHC1_DATA6 0xcd 526*4882a593Smuzhiyun MX8MQ_IOMUXC_SD1_DATA7_USDHC1_DATA7 0xcd 527*4882a593Smuzhiyun MX8MQ_IOMUXC_SD1_STROBE_USDHC1_STROBE 0x8d 528*4882a593Smuzhiyun MX8MQ_IOMUXC_SD1_RESET_B_USDHC1_RESET_B 0xc1 529*4882a593Smuzhiyun >; 530*4882a593Smuzhiyun }; 531*4882a593Smuzhiyun 532*4882a593Smuzhiyun pinctrl_usdhc1_200mhz: usdhc1grp200mhz { 533*4882a593Smuzhiyun fsl,pins = < 534*4882a593Smuzhiyun MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK 0x9f 535*4882a593Smuzhiyun MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD 0xdf 536*4882a593Smuzhiyun MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0 0xdf 537*4882a593Smuzhiyun MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1 0xdf 538*4882a593Smuzhiyun MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2 0xdf 539*4882a593Smuzhiyun MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3 0xdf 540*4882a593Smuzhiyun MX8MQ_IOMUXC_SD1_DATA4_USDHC1_DATA4 0xdf 541*4882a593Smuzhiyun MX8MQ_IOMUXC_SD1_DATA5_USDHC1_DATA5 0xdf 542*4882a593Smuzhiyun MX8MQ_IOMUXC_SD1_DATA6_USDHC1_DATA6 0xdf 543*4882a593Smuzhiyun MX8MQ_IOMUXC_SD1_DATA7_USDHC1_DATA7 0xdf 544*4882a593Smuzhiyun MX8MQ_IOMUXC_SD1_STROBE_USDHC1_STROBE 0x9f 545*4882a593Smuzhiyun MX8MQ_IOMUXC_SD1_RESET_B_USDHC1_RESET_B 0xc1 546*4882a593Smuzhiyun >; 547*4882a593Smuzhiyun }; 548*4882a593Smuzhiyun 549*4882a593Smuzhiyun pinctrl_usdhc2: usdhc2grp { 550*4882a593Smuzhiyun fsl,pins = < 551*4882a593Smuzhiyun MX8MQ_IOMUXC_SD2_CD_B_GPIO2_IO12 0x80 552*4882a593Smuzhiyun MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK 0x83 553*4882a593Smuzhiyun MX8MQ_IOMUXC_SD2_CMD_USDHC2_CMD 0xc3 554*4882a593Smuzhiyun MX8MQ_IOMUXC_SD2_DATA0_USDHC2_DATA0 0xc3 555*4882a593Smuzhiyun MX8MQ_IOMUXC_SD2_DATA1_USDHC2_DATA1 0xc3 556*4882a593Smuzhiyun MX8MQ_IOMUXC_SD2_DATA2_USDHC2_DATA2 0xc3 557*4882a593Smuzhiyun MX8MQ_IOMUXC_SD2_DATA3_USDHC2_DATA3 0xc3 558*4882a593Smuzhiyun MX8MQ_IOMUXC_SD2_RESET_B_USDHC2_RESET_B 0xc1 559*4882a593Smuzhiyun >; 560*4882a593Smuzhiyun }; 561*4882a593Smuzhiyun 562*4882a593Smuzhiyun pinctrl_usdhc2_100mhz: usdhc2grp100mhz { 563*4882a593Smuzhiyun fsl,pins = < 564*4882a593Smuzhiyun MX8MQ_IOMUXC_SD2_CD_B_GPIO2_IO12 0x80 565*4882a593Smuzhiyun MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK 0x8d 566*4882a593Smuzhiyun MX8MQ_IOMUXC_SD2_CMD_USDHC2_CMD 0xcd 567*4882a593Smuzhiyun MX8MQ_IOMUXC_SD2_DATA0_USDHC2_DATA0 0xcd 568*4882a593Smuzhiyun MX8MQ_IOMUXC_SD2_DATA1_USDHC2_DATA1 0xcd 569*4882a593Smuzhiyun MX8MQ_IOMUXC_SD2_DATA2_USDHC2_DATA2 0xcd 570*4882a593Smuzhiyun MX8MQ_IOMUXC_SD2_DATA3_USDHC2_DATA3 0xcd 571*4882a593Smuzhiyun MX8MQ_IOMUXC_SD2_RESET_B_USDHC2_RESET_B 0xc1 572*4882a593Smuzhiyun >; 573*4882a593Smuzhiyun }; 574*4882a593Smuzhiyun 575*4882a593Smuzhiyun pinctrl_usdhc2_200mhz: usdhc2grp200mhz { 576*4882a593Smuzhiyun fsl,pins = < 577*4882a593Smuzhiyun MX8MQ_IOMUXC_SD2_CD_B_GPIO2_IO12 0x80 578*4882a593Smuzhiyun MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK 0x9f 579*4882a593Smuzhiyun MX8MQ_IOMUXC_SD2_CMD_USDHC2_CMD 0xcf 580*4882a593Smuzhiyun MX8MQ_IOMUXC_SD2_DATA0_USDHC2_DATA0 0xcf 581*4882a593Smuzhiyun MX8MQ_IOMUXC_SD2_DATA1_USDHC2_DATA1 0xcf 582*4882a593Smuzhiyun MX8MQ_IOMUXC_SD2_DATA2_USDHC2_DATA2 0xcf 583*4882a593Smuzhiyun MX8MQ_IOMUXC_SD2_DATA3_USDHC2_DATA3 0xcf 584*4882a593Smuzhiyun MX8MQ_IOMUXC_SD2_RESET_B_USDHC2_RESET_B 0xc1 585*4882a593Smuzhiyun >; 586*4882a593Smuzhiyun }; 587*4882a593Smuzhiyun 588*4882a593Smuzhiyun pinctrl_wdog: wdoggrp { 589*4882a593Smuzhiyun fsl,pins = < 590*4882a593Smuzhiyun /* nWDOG */ 591*4882a593Smuzhiyun MX8MQ_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B 0x1f 592*4882a593Smuzhiyun >; 593*4882a593Smuzhiyun }; 594*4882a593Smuzhiyun}; 595*4882a593Smuzhiyun 596*4882a593Smuzhiyun&i2c1 { 597*4882a593Smuzhiyun clock-frequency = <387000>; 598*4882a593Smuzhiyun pinctrl-names = "default"; 599*4882a593Smuzhiyun pinctrl-0 = <&pinctrl_i2c1>; 600*4882a593Smuzhiyun status = "okay"; 601*4882a593Smuzhiyun 602*4882a593Smuzhiyun typec_pd: usb-pd@3f { 603*4882a593Smuzhiyun compatible = "ti,tps6598x"; 604*4882a593Smuzhiyun reg = <0x3f>; 605*4882a593Smuzhiyun pinctrl-names = "default"; 606*4882a593Smuzhiyun pinctrl-0 = <&pinctrl_typec>, <&pinctrl_tcpc>; 607*4882a593Smuzhiyun interrupt-parent = <&gpio1>; 608*4882a593Smuzhiyun interrupts = <10 IRQ_TYPE_LEVEL_LOW>; 609*4882a593Smuzhiyun interrupt-names = "irq"; 610*4882a593Smuzhiyun 611*4882a593Smuzhiyun connector { 612*4882a593Smuzhiyun ports { 613*4882a593Smuzhiyun #address-cells = <1>; 614*4882a593Smuzhiyun #size-cells = <0>; 615*4882a593Smuzhiyun 616*4882a593Smuzhiyun port@0 { 617*4882a593Smuzhiyun reg = <0>; 618*4882a593Smuzhiyun 619*4882a593Smuzhiyun usb_con_hs: endpoint { 620*4882a593Smuzhiyun remote-endpoint = <&typec_hs>; 621*4882a593Smuzhiyun }; 622*4882a593Smuzhiyun }; 623*4882a593Smuzhiyun 624*4882a593Smuzhiyun port@1 { 625*4882a593Smuzhiyun reg = <1>; 626*4882a593Smuzhiyun 627*4882a593Smuzhiyun usb_con_ss: endpoint { 628*4882a593Smuzhiyun remote-endpoint = <&typec_ss>; 629*4882a593Smuzhiyun }; 630*4882a593Smuzhiyun }; 631*4882a593Smuzhiyun }; 632*4882a593Smuzhiyun }; 633*4882a593Smuzhiyun }; 634*4882a593Smuzhiyun 635*4882a593Smuzhiyun pmic: pmic@4b { 636*4882a593Smuzhiyun compatible = "rohm,bd71837"; 637*4882a593Smuzhiyun reg = <0x4b>; 638*4882a593Smuzhiyun pinctrl-names = "default"; 639*4882a593Smuzhiyun pinctrl-0 = <&pinctrl_pmic>; 640*4882a593Smuzhiyun clocks = <&pmic_osc>; 641*4882a593Smuzhiyun clock-names = "osc"; 642*4882a593Smuzhiyun clock-output-names = "pmic_clk"; 643*4882a593Smuzhiyun interrupt-parent = <&gpio1>; 644*4882a593Smuzhiyun interrupts = <7 IRQ_TYPE_LEVEL_LOW>; 645*4882a593Smuzhiyun rohm,reset-snvs-powered; 646*4882a593Smuzhiyun 647*4882a593Smuzhiyun regulators { 648*4882a593Smuzhiyun buck1_reg: BUCK1 { 649*4882a593Smuzhiyun regulator-name = "buck1"; 650*4882a593Smuzhiyun regulator-min-microvolt = <700000>; 651*4882a593Smuzhiyun regulator-max-microvolt = <1300000>; 652*4882a593Smuzhiyun regulator-ramp-delay = <1250>; 653*4882a593Smuzhiyun rohm,dvs-run-voltage = <900000>; 654*4882a593Smuzhiyun rohm,dvs-idle-voltage = <850000>; 655*4882a593Smuzhiyun rohm,dvs-suspend-voltage = <800000>; 656*4882a593Smuzhiyun regulator-always-on; 657*4882a593Smuzhiyun }; 658*4882a593Smuzhiyun 659*4882a593Smuzhiyun buck2_reg: BUCK2 { 660*4882a593Smuzhiyun regulator-name = "buck2"; 661*4882a593Smuzhiyun regulator-min-microvolt = <700000>; 662*4882a593Smuzhiyun regulator-max-microvolt = <1300000>; 663*4882a593Smuzhiyun regulator-ramp-delay = <1250>; 664*4882a593Smuzhiyun rohm,dvs-run-voltage = <1000000>; 665*4882a593Smuzhiyun rohm,dvs-idle-voltage = <900000>; 666*4882a593Smuzhiyun regulator-always-on; 667*4882a593Smuzhiyun }; 668*4882a593Smuzhiyun 669*4882a593Smuzhiyun buck3_reg: BUCK3 { 670*4882a593Smuzhiyun regulator-name = "buck3"; 671*4882a593Smuzhiyun regulator-min-microvolt = <700000>; 672*4882a593Smuzhiyun regulator-max-microvolt = <1300000>; 673*4882a593Smuzhiyun rohm,dvs-run-voltage = <900000>; 674*4882a593Smuzhiyun regulator-always-on; 675*4882a593Smuzhiyun }; 676*4882a593Smuzhiyun 677*4882a593Smuzhiyun buck4_reg: BUCK4 { 678*4882a593Smuzhiyun regulator-name = "buck4"; 679*4882a593Smuzhiyun regulator-min-microvolt = <700000>; 680*4882a593Smuzhiyun regulator-max-microvolt = <1300000>; 681*4882a593Smuzhiyun rohm,dvs-run-voltage = <1000000>; 682*4882a593Smuzhiyun }; 683*4882a593Smuzhiyun 684*4882a593Smuzhiyun buck5_reg: BUCK5 { 685*4882a593Smuzhiyun regulator-name = "buck5"; 686*4882a593Smuzhiyun regulator-min-microvolt = <700000>; 687*4882a593Smuzhiyun regulator-max-microvolt = <1350000>; 688*4882a593Smuzhiyun regulator-always-on; 689*4882a593Smuzhiyun }; 690*4882a593Smuzhiyun 691*4882a593Smuzhiyun buck6_reg: BUCK6 { 692*4882a593Smuzhiyun regulator-name = "buck6"; 693*4882a593Smuzhiyun regulator-min-microvolt = <3000000>; 694*4882a593Smuzhiyun regulator-max-microvolt = <3300000>; 695*4882a593Smuzhiyun regulator-always-on; 696*4882a593Smuzhiyun }; 697*4882a593Smuzhiyun 698*4882a593Smuzhiyun buck7_reg: BUCK7 { 699*4882a593Smuzhiyun regulator-name = "buck7"; 700*4882a593Smuzhiyun regulator-min-microvolt = <1605000>; 701*4882a593Smuzhiyun regulator-max-microvolt = <1995000>; 702*4882a593Smuzhiyun regulator-always-on; 703*4882a593Smuzhiyun }; 704*4882a593Smuzhiyun 705*4882a593Smuzhiyun buck8_reg: BUCK8 { 706*4882a593Smuzhiyun regulator-name = "buck8"; 707*4882a593Smuzhiyun regulator-min-microvolt = <800000>; 708*4882a593Smuzhiyun regulator-max-microvolt = <1400000>; 709*4882a593Smuzhiyun regulator-always-on; 710*4882a593Smuzhiyun }; 711*4882a593Smuzhiyun 712*4882a593Smuzhiyun ldo1_reg: LDO1 { 713*4882a593Smuzhiyun regulator-name = "ldo1"; 714*4882a593Smuzhiyun regulator-min-microvolt = <3000000>; 715*4882a593Smuzhiyun regulator-max-microvolt = <3300000>; 716*4882a593Smuzhiyun /* leave on for snvs power button */ 717*4882a593Smuzhiyun regulator-always-on; 718*4882a593Smuzhiyun }; 719*4882a593Smuzhiyun 720*4882a593Smuzhiyun ldo2_reg: LDO2 { 721*4882a593Smuzhiyun regulator-name = "ldo2"; 722*4882a593Smuzhiyun regulator-min-microvolt = <900000>; 723*4882a593Smuzhiyun regulator-max-microvolt = <900000>; 724*4882a593Smuzhiyun /* leave on for snvs power button */ 725*4882a593Smuzhiyun regulator-always-on; 726*4882a593Smuzhiyun }; 727*4882a593Smuzhiyun 728*4882a593Smuzhiyun ldo3_reg: LDO3 { 729*4882a593Smuzhiyun regulator-name = "ldo3"; 730*4882a593Smuzhiyun regulator-min-microvolt = <1800000>; 731*4882a593Smuzhiyun regulator-max-microvolt = <3300000>; 732*4882a593Smuzhiyun regulator-always-on; 733*4882a593Smuzhiyun }; 734*4882a593Smuzhiyun 735*4882a593Smuzhiyun ldo4_reg: LDO4 { 736*4882a593Smuzhiyun regulator-name = "ldo4"; 737*4882a593Smuzhiyun regulator-min-microvolt = <900000>; 738*4882a593Smuzhiyun regulator-max-microvolt = <1800000>; 739*4882a593Smuzhiyun regulator-always-on; 740*4882a593Smuzhiyun }; 741*4882a593Smuzhiyun 742*4882a593Smuzhiyun ldo5_reg: LDO5 { 743*4882a593Smuzhiyun /* VDD_PHY_0V9 - MIPI and HDMI domains */ 744*4882a593Smuzhiyun regulator-name = "ldo5"; 745*4882a593Smuzhiyun regulator-min-microvolt = <1800000>; 746*4882a593Smuzhiyun regulator-max-microvolt = <3300000>; 747*4882a593Smuzhiyun regulator-always-on; 748*4882a593Smuzhiyun }; 749*4882a593Smuzhiyun 750*4882a593Smuzhiyun ldo6_reg: LDO6 { 751*4882a593Smuzhiyun /* VDD_PHY_0V9 - MIPI, HDMI and USB domains */ 752*4882a593Smuzhiyun regulator-name = "ldo6"; 753*4882a593Smuzhiyun regulator-min-microvolt = <900000>; 754*4882a593Smuzhiyun regulator-max-microvolt = <1800000>; 755*4882a593Smuzhiyun regulator-always-on; 756*4882a593Smuzhiyun }; 757*4882a593Smuzhiyun 758*4882a593Smuzhiyun ldo7_reg: LDO7 { 759*4882a593Smuzhiyun /* VDD_PHY_3V3 - USB domain */ 760*4882a593Smuzhiyun regulator-name = "ldo7"; 761*4882a593Smuzhiyun regulator-min-microvolt = <1800000>; 762*4882a593Smuzhiyun regulator-max-microvolt = <3300000>; 763*4882a593Smuzhiyun regulator-always-on; 764*4882a593Smuzhiyun }; 765*4882a593Smuzhiyun }; 766*4882a593Smuzhiyun }; 767*4882a593Smuzhiyun 768*4882a593Smuzhiyun rtc@68 { 769*4882a593Smuzhiyun compatible = "microcrystal,rv4162"; 770*4882a593Smuzhiyun reg = <0x68>; 771*4882a593Smuzhiyun pinctrl-names = "default"; 772*4882a593Smuzhiyun pinctrl-0 = <&pinctrl_rtc>; 773*4882a593Smuzhiyun interrupt-parent = <&gpio1>; 774*4882a593Smuzhiyun interrupts = <9 IRQ_TYPE_LEVEL_LOW>; 775*4882a593Smuzhiyun }; 776*4882a593Smuzhiyun}; 777*4882a593Smuzhiyun 778*4882a593Smuzhiyun&i2c2 { 779*4882a593Smuzhiyun clock-frequency = <387000>; 780*4882a593Smuzhiyun pinctrl-names = "default"; 781*4882a593Smuzhiyun pinctrl-0 = <&pinctrl_i2c2>; 782*4882a593Smuzhiyun status = "okay"; 783*4882a593Smuzhiyun 784*4882a593Smuzhiyun magnetometer@1e { 785*4882a593Smuzhiyun compatible = "st,lsm9ds1-magn"; 786*4882a593Smuzhiyun reg = <0x1e>; 787*4882a593Smuzhiyun pinctrl-names = "default"; 788*4882a593Smuzhiyun pinctrl-0 = <&pinctrl_mag>; 789*4882a593Smuzhiyun interrupt-parent = <&gpio3>; 790*4882a593Smuzhiyun interrupts = <22 IRQ_TYPE_LEVEL_HIGH>; 791*4882a593Smuzhiyun vdd-supply = <®_vdd_sen>; 792*4882a593Smuzhiyun vddio-supply = <®_vdd_1v8>; 793*4882a593Smuzhiyun }; 794*4882a593Smuzhiyun 795*4882a593Smuzhiyun regulator@3e { 796*4882a593Smuzhiyun compatible = "tps65132"; 797*4882a593Smuzhiyun reg = <0x3e>; 798*4882a593Smuzhiyun 799*4882a593Smuzhiyun outp { 800*4882a593Smuzhiyun regulator-name = "LCD_AVDD"; 801*4882a593Smuzhiyun vin-supply = <®_lcd_3v4>; 802*4882a593Smuzhiyun }; 803*4882a593Smuzhiyun 804*4882a593Smuzhiyun outn { 805*4882a593Smuzhiyun regulator-name = "LCD_AVEE"; 806*4882a593Smuzhiyun vin-supply = <®_lcd_3v4>; 807*4882a593Smuzhiyun }; 808*4882a593Smuzhiyun }; 809*4882a593Smuzhiyun 810*4882a593Smuzhiyun proximity: prox@60 { 811*4882a593Smuzhiyun compatible = "vishay,vcnl4040"; 812*4882a593Smuzhiyun reg = <0x60>; 813*4882a593Smuzhiyun pinctrl-names = "default"; 814*4882a593Smuzhiyun pinctrl-0 = <&pinctrl_prox>; 815*4882a593Smuzhiyun interrupt-parent = <&gpio3>; 816*4882a593Smuzhiyun interrupts = <7 IRQ_TYPE_LEVEL_LOW>; 817*4882a593Smuzhiyun }; 818*4882a593Smuzhiyun 819*4882a593Smuzhiyun accel_gyro: accel-gyro@6a { 820*4882a593Smuzhiyun compatible = "st,lsm9ds1-imu"; 821*4882a593Smuzhiyun reg = <0x6a>; 822*4882a593Smuzhiyun vdd-supply = <®_vdd_sen>; 823*4882a593Smuzhiyun vddio-supply = <®_vdd_1v8>; 824*4882a593Smuzhiyun }; 825*4882a593Smuzhiyun}; 826*4882a593Smuzhiyun 827*4882a593Smuzhiyun&i2c3 { 828*4882a593Smuzhiyun clock-frequency = <387000>; 829*4882a593Smuzhiyun pinctrl-names = "default"; 830*4882a593Smuzhiyun pinctrl-0 = <&pinctrl_i2c3>; 831*4882a593Smuzhiyun status = "okay"; 832*4882a593Smuzhiyun 833*4882a593Smuzhiyun codec: audio-codec@1a { 834*4882a593Smuzhiyun compatible = "wlf,wm8962"; 835*4882a593Smuzhiyun reg = <0x1a>; 836*4882a593Smuzhiyun clocks = <&clk IMX8MQ_CLK_SAI2_ROOT>; 837*4882a593Smuzhiyun assigned-clocks = <&clk IMX8MQ_CLK_SAI2>; 838*4882a593Smuzhiyun assigned-clock-parents = <&clk IMX8MQ_AUDIO_PLL1_OUT>; 839*4882a593Smuzhiyun assigned-clock-rates = <24576000>; 840*4882a593Smuzhiyun #sound-dai-cells = <0>; 841*4882a593Smuzhiyun mic-cfg = <0x200>; 842*4882a593Smuzhiyun DCVDD-supply = <®_aud_1v8>; 843*4882a593Smuzhiyun DBVDD-supply = <®_aud_1v8>; 844*4882a593Smuzhiyun AVDD-supply = <®_aud_1v8>; 845*4882a593Smuzhiyun CPVDD-supply = <®_aud_1v8>; 846*4882a593Smuzhiyun MICVDD-supply = <®_aud_1v8>; 847*4882a593Smuzhiyun PLLVDD-supply = <®_aud_1v8>; 848*4882a593Smuzhiyun SPKVDD1-supply = <®_vsys_3v4>; 849*4882a593Smuzhiyun SPKVDD2-supply = <®_vsys_3v4>; 850*4882a593Smuzhiyun gpio-cfg = < 851*4882a593Smuzhiyun 0x0000 /* n/c */ 852*4882a593Smuzhiyun 0x0001 /* gpio2, 1: default */ 853*4882a593Smuzhiyun 0x0013 /* gpio3, 2: dmicclk */ 854*4882a593Smuzhiyun 0x0000 /* n/c, 3: default */ 855*4882a593Smuzhiyun 0x8014 /* gpio5, 4: dmic_dat */ 856*4882a593Smuzhiyun 0x0000 /* gpio6, 5: default */ 857*4882a593Smuzhiyun >; 858*4882a593Smuzhiyun }; 859*4882a593Smuzhiyun 860*4882a593Smuzhiyun backlight@36 { 861*4882a593Smuzhiyun compatible = "ti,lm36922"; 862*4882a593Smuzhiyun reg = <0x36>; 863*4882a593Smuzhiyun pinctrl-names = "default"; 864*4882a593Smuzhiyun pinctrl-0 = <&pinctrl_bl>; 865*4882a593Smuzhiyun #address-cells = <1>; 866*4882a593Smuzhiyun #size-cells = <0>; 867*4882a593Smuzhiyun enable-gpios = <&gpio3 14 GPIO_ACTIVE_HIGH>; 868*4882a593Smuzhiyun vled-supply = <®_vsys_3v4>; 869*4882a593Smuzhiyun ti,ovp-microvolt = <25000000>; 870*4882a593Smuzhiyun 871*4882a593Smuzhiyun led_backlight: led@0 { 872*4882a593Smuzhiyun reg = <0>; 873*4882a593Smuzhiyun label = ":backlight"; 874*4882a593Smuzhiyun linux,default-trigger = "backlight"; 875*4882a593Smuzhiyun led-max-microamp = <20000>; 876*4882a593Smuzhiyun }; 877*4882a593Smuzhiyun }; 878*4882a593Smuzhiyun 879*4882a593Smuzhiyun touchscreen@38 { 880*4882a593Smuzhiyun compatible = "edt,edt-ft5506"; 881*4882a593Smuzhiyun reg = <0x38>; 882*4882a593Smuzhiyun interrupt-parent = <&gpio1>; 883*4882a593Smuzhiyun interrupts = <27 IRQ_TYPE_EDGE_FALLING>; 884*4882a593Smuzhiyun touchscreen-size-x = <720>; 885*4882a593Smuzhiyun touchscreen-size-y = <1440>; 886*4882a593Smuzhiyun }; 887*4882a593Smuzhiyun}; 888*4882a593Smuzhiyun 889*4882a593Smuzhiyun&i2c4 { 890*4882a593Smuzhiyun clock-frequency = <387000>; 891*4882a593Smuzhiyun pinctrl-names = "default"; 892*4882a593Smuzhiyun pinctrl-0 = <&pinctrl_i2c4>; 893*4882a593Smuzhiyun status = "okay"; 894*4882a593Smuzhiyun 895*4882a593Smuzhiyun bat: fuel-gauge@36 { 896*4882a593Smuzhiyun compatible = "maxim,max17055"; 897*4882a593Smuzhiyun reg = <0x36>; 898*4882a593Smuzhiyun interrupt-parent = <&gpio3>; 899*4882a593Smuzhiyun interrupts = <20 IRQ_TYPE_LEVEL_LOW>; 900*4882a593Smuzhiyun pinctrl-names = "default"; 901*4882a593Smuzhiyun pinctrl-0 = <&pinctrl_gauge>; 902*4882a593Smuzhiyun power-supplies = <&bq25895>; 903*4882a593Smuzhiyun maxim,over-heat-temp = <700>; 904*4882a593Smuzhiyun maxim,over-volt = <4500>; 905*4882a593Smuzhiyun maxim,rsns-microohm = <5000>; 906*4882a593Smuzhiyun }; 907*4882a593Smuzhiyun 908*4882a593Smuzhiyun bq25895: charger@6a { 909*4882a593Smuzhiyun compatible = "ti,bq25895", "ti,bq25890"; 910*4882a593Smuzhiyun reg = <0x6a>; 911*4882a593Smuzhiyun pinctrl-names = "default"; 912*4882a593Smuzhiyun pinctrl-0 = <&pinctrl_charger_in>; 913*4882a593Smuzhiyun interrupt-parent = <&gpio3>; 914*4882a593Smuzhiyun interrupts = <3 IRQ_TYPE_EDGE_FALLING>; 915*4882a593Smuzhiyun phys = <&usb3_phy0>; 916*4882a593Smuzhiyun ti,precharge-current = <130000>; /* uA */ 917*4882a593Smuzhiyun ti,minimum-sys-voltage = <3700000>; /* uV */ 918*4882a593Smuzhiyun ti,boost-voltage = <5000000>; /* uV */ 919*4882a593Smuzhiyun ti,boost-max-current = <500000>; /* uA */ 920*4882a593Smuzhiyun ti,use-vinmin-threshold = <1>; /* enable VINDPM */ 921*4882a593Smuzhiyun ti,vinmin-threshold = <3900000>; /* uV */ 922*4882a593Smuzhiyun monitored-battery = <&bat>; 923*4882a593Smuzhiyun }; 924*4882a593Smuzhiyun}; 925*4882a593Smuzhiyun 926*4882a593Smuzhiyun&pgc_gpu { 927*4882a593Smuzhiyun power-supply = <&buck3_reg>; 928*4882a593Smuzhiyun}; 929*4882a593Smuzhiyun 930*4882a593Smuzhiyun&pgc_mipi { 931*4882a593Smuzhiyun power-supply = <&ldo5_reg>; 932*4882a593Smuzhiyun}; 933*4882a593Smuzhiyun 934*4882a593Smuzhiyun&pgc_vpu { 935*4882a593Smuzhiyun power-supply = <&buck4_reg>; 936*4882a593Smuzhiyun}; 937*4882a593Smuzhiyun 938*4882a593Smuzhiyun&pwm1 { 939*4882a593Smuzhiyun pinctrl-names = "default"; 940*4882a593Smuzhiyun pinctrl-0 = <&pinctrl_haptic>; 941*4882a593Smuzhiyun status = "okay"; 942*4882a593Smuzhiyun}; 943*4882a593Smuzhiyun 944*4882a593Smuzhiyun&pwm2 { 945*4882a593Smuzhiyun pinctrl-names = "default"; 946*4882a593Smuzhiyun pinctrl-0 = <&pinctrl_led_b>; 947*4882a593Smuzhiyun status = "okay"; 948*4882a593Smuzhiyun}; 949*4882a593Smuzhiyun 950*4882a593Smuzhiyun&pwm3 { 951*4882a593Smuzhiyun pinctrl-names = "default"; 952*4882a593Smuzhiyun pinctrl-0 = <&pinctrl_led_g>; 953*4882a593Smuzhiyun status = "okay"; 954*4882a593Smuzhiyun}; 955*4882a593Smuzhiyun 956*4882a593Smuzhiyun&pwm4 { 957*4882a593Smuzhiyun pinctrl-names = "default"; 958*4882a593Smuzhiyun pinctrl-0 = <&pinctrl_led_r>; 959*4882a593Smuzhiyun status = "okay"; 960*4882a593Smuzhiyun}; 961*4882a593Smuzhiyun 962*4882a593Smuzhiyun&sai2 { 963*4882a593Smuzhiyun pinctrl-names = "default"; 964*4882a593Smuzhiyun pinctrl-0 = <&pinctrl_sai2>; 965*4882a593Smuzhiyun assigned-clocks = <&clk IMX8MQ_CLK_SAI2>; 966*4882a593Smuzhiyun assigned-clock-parents = <&clk IMX8MQ_AUDIO_PLL1_OUT>; 967*4882a593Smuzhiyun assigned-clock-rates = <24576000>; 968*4882a593Smuzhiyun assigned-clocks = <&clk IMX8MQ_AUDIO_PLL1>, <&clk IMX8MQ_AUDIO_PLL2>; 969*4882a593Smuzhiyun assigned-clock-rates = <786432000>, <722534400>; 970*4882a593Smuzhiyun status = "okay"; 971*4882a593Smuzhiyun}; 972*4882a593Smuzhiyun 973*4882a593Smuzhiyun&sai6 { 974*4882a593Smuzhiyun pinctrl-names = "default"; 975*4882a593Smuzhiyun pinctrl-0 = <&pinctrl_sai6>; 976*4882a593Smuzhiyun assigned-clocks = <&clk IMX8MQ_CLK_SAI6>; 977*4882a593Smuzhiyun assigned-clock-parents = <&clk IMX8MQ_AUDIO_PLL1_OUT>; 978*4882a593Smuzhiyun assigned-clock-rates = <24576000>; 979*4882a593Smuzhiyun fsl,sai-synchronous-rx; 980*4882a593Smuzhiyun status = "okay"; 981*4882a593Smuzhiyun}; 982*4882a593Smuzhiyun 983*4882a593Smuzhiyun&snvs_pwrkey { 984*4882a593Smuzhiyun status = "okay"; 985*4882a593Smuzhiyun}; 986*4882a593Smuzhiyun 987*4882a593Smuzhiyun&snvs_rtc { 988*4882a593Smuzhiyun status = "disabled"; 989*4882a593Smuzhiyun}; 990*4882a593Smuzhiyun 991*4882a593Smuzhiyun&uart1 { /* console */ 992*4882a593Smuzhiyun pinctrl-names = "default"; 993*4882a593Smuzhiyun pinctrl-0 = <&pinctrl_uart1>; 994*4882a593Smuzhiyun status = "okay"; 995*4882a593Smuzhiyun}; 996*4882a593Smuzhiyun 997*4882a593Smuzhiyun&uart2 { /* TPS - GPS - DEBUG */ 998*4882a593Smuzhiyun pinctrl-names = "default"; 999*4882a593Smuzhiyun pinctrl-0 = <&pinctrl_uart2>; 1000*4882a593Smuzhiyun status = "okay"; 1001*4882a593Smuzhiyun 1002*4882a593Smuzhiyun gnss { 1003*4882a593Smuzhiyun compatible = "globaltop,pa6h"; 1004*4882a593Smuzhiyun vcc-supply = <®_gnss>; 1005*4882a593Smuzhiyun current-speed = <9600>; 1006*4882a593Smuzhiyun }; 1007*4882a593Smuzhiyun}; 1008*4882a593Smuzhiyun 1009*4882a593Smuzhiyun&uart3 { /* SMC */ 1010*4882a593Smuzhiyun pinctrl-names = "default"; 1011*4882a593Smuzhiyun pinctrl-0 = <&pinctrl_uart3>; 1012*4882a593Smuzhiyun status = "okay"; 1013*4882a593Smuzhiyun}; 1014*4882a593Smuzhiyun 1015*4882a593Smuzhiyun&uart4 { /* BT */ 1016*4882a593Smuzhiyun pinctrl-names = "default"; 1017*4882a593Smuzhiyun pinctrl-0 = <&pinctrl_uart4>; 1018*4882a593Smuzhiyun uart-has-rtscts; 1019*4882a593Smuzhiyun status = "okay"; 1020*4882a593Smuzhiyun}; 1021*4882a593Smuzhiyun 1022*4882a593Smuzhiyun&usb3_phy0 { 1023*4882a593Smuzhiyun status = "okay"; 1024*4882a593Smuzhiyun}; 1025*4882a593Smuzhiyun 1026*4882a593Smuzhiyun&usb3_phy1 { 1027*4882a593Smuzhiyun vbus-supply = <®_hub>; 1028*4882a593Smuzhiyun status = "okay"; 1029*4882a593Smuzhiyun}; 1030*4882a593Smuzhiyun 1031*4882a593Smuzhiyun&usb_dwc3_0 { 1032*4882a593Smuzhiyun #address-cells = <1>; 1033*4882a593Smuzhiyun #size-cells = <0>; 1034*4882a593Smuzhiyun dr_mode = "otg"; 1035*4882a593Smuzhiyun snps,dis_u3_susphy_quirk; 1036*4882a593Smuzhiyun status = "okay"; 1037*4882a593Smuzhiyun 1038*4882a593Smuzhiyun port@0 { 1039*4882a593Smuzhiyun reg = <0>; 1040*4882a593Smuzhiyun 1041*4882a593Smuzhiyun typec_hs: endpoint { 1042*4882a593Smuzhiyun remote-endpoint = <&usb_con_hs>; 1043*4882a593Smuzhiyun }; 1044*4882a593Smuzhiyun }; 1045*4882a593Smuzhiyun 1046*4882a593Smuzhiyun port@1 { 1047*4882a593Smuzhiyun reg = <1>; 1048*4882a593Smuzhiyun 1049*4882a593Smuzhiyun typec_ss: endpoint { 1050*4882a593Smuzhiyun remote-endpoint = <&usb_con_ss>; 1051*4882a593Smuzhiyun }; 1052*4882a593Smuzhiyun }; 1053*4882a593Smuzhiyun}; 1054*4882a593Smuzhiyun 1055*4882a593Smuzhiyun&usb_dwc3_1 { 1056*4882a593Smuzhiyun dr_mode = "host"; 1057*4882a593Smuzhiyun status = "okay"; 1058*4882a593Smuzhiyun #address-cells = <1>; 1059*4882a593Smuzhiyun #size-cells = <0>; 1060*4882a593Smuzhiyun 1061*4882a593Smuzhiyun /* Microchip USB2642 */ 1062*4882a593Smuzhiyun hub@1 { 1063*4882a593Smuzhiyun compatible = "usb424,2640"; 1064*4882a593Smuzhiyun reg = <1>; 1065*4882a593Smuzhiyun #address-cells = <1>; 1066*4882a593Smuzhiyun #size-cells = <0>; 1067*4882a593Smuzhiyun 1068*4882a593Smuzhiyun mass-storage@1 { 1069*4882a593Smuzhiyun compatible = "usb424,4041"; 1070*4882a593Smuzhiyun reg = <1>; 1071*4882a593Smuzhiyun }; 1072*4882a593Smuzhiyun }; 1073*4882a593Smuzhiyun}; 1074*4882a593Smuzhiyun 1075*4882a593Smuzhiyun&usdhc1 { 1076*4882a593Smuzhiyun pinctrl-names = "default", "state_100mhz", "state_200mhz"; 1077*4882a593Smuzhiyun pinctrl-0 = <&pinctrl_usdhc1>; 1078*4882a593Smuzhiyun pinctrl-1 = <&pinctrl_usdhc1_100mhz>; 1079*4882a593Smuzhiyun pinctrl-2 = <&pinctrl_usdhc1_200mhz>; 1080*4882a593Smuzhiyun bus-width = <8>; 1081*4882a593Smuzhiyun vmmc-supply = <®_vdd_3v3>; 1082*4882a593Smuzhiyun power-supply = <®_vdd_1v8>; 1083*4882a593Smuzhiyun non-removable; 1084*4882a593Smuzhiyun status = "okay"; 1085*4882a593Smuzhiyun}; 1086*4882a593Smuzhiyun 1087*4882a593Smuzhiyun&usdhc2 { 1088*4882a593Smuzhiyun pinctrl-names = "default", "state_100mhz", "state_200mhz"; 1089*4882a593Smuzhiyun pinctrl-0 = <&pinctrl_usdhc2>; 1090*4882a593Smuzhiyun pinctrl-1 = <&pinctrl_usdhc2_100mhz>; 1091*4882a593Smuzhiyun pinctrl-2 = <&pinctrl_usdhc2_200mhz>; 1092*4882a593Smuzhiyun bus-width = <4>; 1093*4882a593Smuzhiyun vmmc-supply = <®_wifi_3v3>; 1094*4882a593Smuzhiyun cd-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>; 1095*4882a593Smuzhiyun disable-wp; 1096*4882a593Smuzhiyun cap-sdio-irq; 1097*4882a593Smuzhiyun keep-power-in-suspend; 1098*4882a593Smuzhiyun wakeup-source; 1099*4882a593Smuzhiyun status = "okay"; 1100*4882a593Smuzhiyun}; 1101*4882a593Smuzhiyun 1102*4882a593Smuzhiyun&wdog1 { 1103*4882a593Smuzhiyun pinctrl-names = "default"; 1104*4882a593Smuzhiyun pinctrl-0 = <&pinctrl_wdog>; 1105*4882a593Smuzhiyun fsl,ext-reset-output; 1106*4882a593Smuzhiyun status = "okay"; 1107*4882a593Smuzhiyun}; 1108