| /OK3568_Linux_fs/kernel/drivers/clk/meson/ |
| H A D | sclk-div.c | 23 #include "sclk-div.h"
31 static int sclk_div_maxval(struct meson_sclk_div_data *sclk) in sclk_div_maxval() argument
33 return (1 << sclk->div.width) - 1; in sclk_div_maxval()
36 static int sclk_div_maxdiv(struct meson_sclk_div_data *sclk) in sclk_div_maxdiv() argument
38 return sclk_div_maxval(sclk) + 1; in sclk_div_maxdiv()
51 struct meson_sclk_div_data *sclk) in sclk_div_bestdiv() argument
61 maxdiv = sclk_div_maxdiv(sclk); in sclk_div_bestdiv()
92 bestdiv = sclk_div_maxdiv(sclk); in sclk_div_bestdiv()
103 struct meson_sclk_div_data *sclk = meson_sclk_div_data(clk); in sclk_div_round_rate() local
106 div = sclk_div_bestdiv(hw, rate, prate, sclk); in sclk_div_round_rate()
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| /OK3568_Linux_fs/kernel/drivers/clk/hisilicon/ |
| H A D | clkgate-separated.c | 34 struct clkgate_separated *sclk; in clkgate_separated_enable() local
38 sclk = container_of(hw, struct clkgate_separated, hw); in clkgate_separated_enable()
39 if (sclk->lock) in clkgate_separated_enable()
40 spin_lock_irqsave(sclk->lock, flags); in clkgate_separated_enable()
41 reg = BIT(sclk->bit_idx); in clkgate_separated_enable()
42 writel_relaxed(reg, sclk->enable); in clkgate_separated_enable()
43 readl_relaxed(sclk->enable + CLKGATE_SEPERATED_STATUS); in clkgate_separated_enable()
44 if (sclk->lock) in clkgate_separated_enable()
45 spin_unlock_irqrestore(sclk->lock, flags); in clkgate_separated_enable()
51 struct clkgate_separated *sclk; in clkgate_separated_disable() local
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| /OK3568_Linux_fs/kernel/drivers/clk/ |
| H A D | clk-scmi.c | 105 static int scmi_clk_ops_init(struct device *dev, struct scmi_clk *sclk) in scmi_clk_ops_init() argument
114 .name = sclk->info->name, in scmi_clk_ops_init()
117 sclk->hw.init = &init; in scmi_clk_ops_init()
118 ret = devm_clk_hw_register(dev, &sclk->hw); in scmi_clk_ops_init()
122 if (sclk->info->rate_discrete) { in scmi_clk_ops_init()
123 int num_rates = sclk->info->list.num_rates; in scmi_clk_ops_init()
128 min_rate = sclk->info->list.rates[0]; in scmi_clk_ops_init()
129 max_rate = sclk->info->list.rates[num_rates - 1]; in scmi_clk_ops_init()
131 min_rate = sclk->info->range.min_rate; in scmi_clk_ops_init()
132 max_rate = sclk->info->range.max_rate; in scmi_clk_ops_init()
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| H A D | clk-scpi.c | 140 struct scpi_clk *sclk, const char *name) in scpi_clk_ops_init() argument
150 sclk->hw.init = &init; in scpi_clk_ops_init()
151 sclk->scpi_ops = get_scpi_ops(); in scpi_clk_ops_init()
154 sclk->info = sclk->scpi_ops->dvfs_get_info(sclk->id); in scpi_clk_ops_init()
155 if (IS_ERR(sclk->info)) in scpi_clk_ops_init()
156 return PTR_ERR(sclk->info); in scpi_clk_ops_init()
158 if (sclk->scpi_ops->clk_get_range(sclk->id, &min, &max) || !max) in scpi_clk_ops_init()
164 ret = devm_clk_hw_register(dev, &sclk->hw); in scpi_clk_ops_init()
166 clk_hw_set_rate_range(&sclk->hw, min, max); in scpi_clk_ops_init()
178 struct scpi_clk *sclk; in scpi_of_clk_src_get() local
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| H A D | clk-u300.c | 455 static void syscon_block_reset_enable(struct clk_syscon *sclk) in syscon_block_reset_enable() argument
461 if (!sclk->res_reg) in syscon_block_reset_enable()
464 val = readw(sclk->res_reg); in syscon_block_reset_enable()
465 val |= BIT(sclk->res_bit); in syscon_block_reset_enable()
466 writew(val, sclk->res_reg); in syscon_block_reset_enable()
468 sclk->reset = true; in syscon_block_reset_enable()
471 static void syscon_block_reset_disable(struct clk_syscon *sclk) in syscon_block_reset_disable() argument
477 if (!sclk->res_reg) in syscon_block_reset_disable()
480 val = readw(sclk->res_reg); in syscon_block_reset_disable()
481 val &= ~BIT(sclk->res_bit); in syscon_block_reset_disable()
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| H A D | clk-nomadik.c | 302 struct clk_src *sclk = to_src(hw); in src_clk_enable() local
303 u32 enreg = sclk->group1 ? SRC_PCKEN1 : SRC_PCKEN0; in src_clk_enable()
304 u32 sreg = sclk->group1 ? SRC_PCKSR1 : SRC_PCKSR0; in src_clk_enable()
306 writel(sclk->clkbit, src_base + enreg); in src_clk_enable()
308 while (!(readl(src_base + sreg) & sclk->clkbit)) in src_clk_enable()
315 struct clk_src *sclk = to_src(hw); in src_clk_disable() local
316 u32 disreg = sclk->group1 ? SRC_PCKDIS1 : SRC_PCKDIS0; in src_clk_disable()
317 u32 sreg = sclk->group1 ? SRC_PCKSR1 : SRC_PCKSR0; in src_clk_disable()
319 writel(sclk->clkbit, src_base + disreg); in src_clk_disable()
321 while (readl(src_base + sreg) & sclk->clkbit) in src_clk_disable()
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| /OK3568_Linux_fs/u-boot/board/renesas/stout/ |
| H A D | cpld.c | 16 #define SCLK GPIO_GP_3_24 macro
35 gpio_set_value(SCLK, 1); in cpld_read()
37 gpio_set_value(SCLK, 0); in cpld_read()
42 gpio_set_value(SCLK, 1); in cpld_read()
43 gpio_set_value(SCLK, 0); in cpld_read()
47 gpio_set_value(SCLK, 1); in cpld_read()
50 gpio_set_value(SCLK, 0); in cpld_read()
62 gpio_set_value(SCLK, 1); in cpld_write()
64 gpio_set_value(SCLK, 0); in cpld_write()
69 gpio_set_value(SCLK, 1); in cpld_write()
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| /OK3568_Linux_fs/kernel/drivers/clk/microchip/ |
| H A D | clk-core.c | 759 /* System mux clock(aka SCLK) */
774 struct pic32_sys_clk *sclk = clkhw_to_sys_clk(hw); in sclk_get_rate() local
777 div = (readl(sclk->slew_reg) >> SLEW_SYSDIV_SHIFT) & SLEW_SYSDIV; in sclk_get_rate()
792 struct pic32_sys_clk *sclk = clkhw_to_sys_clk(hw); in sclk_set_rate() local
799 spin_lock_irqsave(&sclk->core->reg_lock, flags); in sclk_set_rate()
802 v = readl(sclk->slew_reg); in sclk_set_rate()
808 writel(v, sclk->slew_reg); in sclk_set_rate()
811 err = readl_poll_timeout_atomic(sclk->slew_reg, v, in sclk_set_rate()
814 spin_unlock_irqrestore(&sclk->core->reg_lock, flags); in sclk_set_rate()
821 struct pic32_sys_clk *sclk = clkhw_to_sys_clk(hw); in sclk_get_parent() local
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| /OK3568_Linux_fs/kernel/drivers/gpu/drm/radeon/ |
| H A D | rv730_dpm.c | 41 RV770_SMC_SCLK_VALUE *sclk) in rv730_populate_sclk_value() argument
108 sclk->sclk_value = cpu_to_be32(engine_clock); in rv730_populate_sclk_value()
109 sclk->vCG_SPLL_FUNC_CNTL = cpu_to_be32(spll_func_cntl); in rv730_populate_sclk_value()
110 sclk->vCG_SPLL_FUNC_CNTL_2 = cpu_to_be32(spll_func_cntl_2); in rv730_populate_sclk_value()
111 sclk->vCG_SPLL_FUNC_CNTL_3 = cpu_to_be32(spll_func_cntl_3); in rv730_populate_sclk_value()
112 sclk->vCG_SPLL_SPREAD_SPECTRUM = cpu_to_be32(cg_spll_spread_spectrum); in rv730_populate_sclk_value()
113 sclk->vCG_SPLL_SPREAD_SPECTRUM_2 = cpu_to_be32(cg_spll_spread_spectrum_2); in rv730_populate_sclk_value()
304 table->ACPIState.levels[0].sclk.vCG_SPLL_FUNC_CNTL = cpu_to_be32(spll_func_cntl); in rv730_populate_smc_acpi_state()
305 table->ACPIState.levels[0].sclk.vCG_SPLL_FUNC_CNTL_2 = cpu_to_be32(spll_func_cntl_2); in rv730_populate_smc_acpi_state()
306 table->ACPIState.levels[0].sclk.vCG_SPLL_FUNC_CNTL_3 = cpu_to_be32(spll_func_cntl_3); in rv730_populate_smc_acpi_state()
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| H A D | rv770_dpm.c | 271 a_n = (int)state->medium.sclk * pi->lmp + in rv770_populate_smc_t()
272 (int)state->low.sclk * (R600_AH_DFLT - pi->rlp); in rv770_populate_smc_t()
273 a_d = (int)state->low.sclk * (100 - (int)pi->rlp) + in rv770_populate_smc_t()
274 (int)state->medium.sclk * pi->lmp; in rv770_populate_smc_t()
279 a_n = (int)state->high.sclk * pi->lhp + (int)state->medium.sclk * in rv770_populate_smc_t()
281 a_d = (int)state->medium.sclk * (100 - (int)pi->rmp) + in rv770_populate_smc_t()
282 (int)state->high.sclk * pi->lhp; in rv770_populate_smc_t()
485 RV770_SMC_SCLK_VALUE *sclk) in rv770_populate_sclk_value() argument
555 sclk->sclk_value = cpu_to_be32(engine_clock); in rv770_populate_sclk_value()
556 sclk->vCG_SPLL_FUNC_CNTL = cpu_to_be32(spll_func_cntl); in rv770_populate_sclk_value()
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| H A D | trinity_dpm.c | 584 u32 index, u32 sclk) in trinity_set_divider_value() argument
592 sclk, false, ÷rs); in trinity_set_divider_value()
602 sclk/2, false, ÷rs); in trinity_set_divider_value()
722 trinity_set_divider_value(rdev, index, pl->sclk); in trinity_program_power_level()
969 if (new_ps->levels[new_ps->num_levels - 1].sclk >= in trinity_set_uvd_clock_before_set_eng_clock()
970 current_ps->levels[current_ps->num_levels - 1].sclk) in trinity_set_uvd_clock_before_set_eng_clock()
983 if (new_ps->levels[new_ps->num_levels - 1].sclk < in trinity_set_uvd_clock_after_set_eng_clock()
984 current_ps->levels[current_ps->num_levels - 1].sclk) in trinity_set_uvd_clock_after_set_eng_clock()
1334 static u8 trinity_calculate_vce_wm(struct radeon_device *rdev, u32 sclk) in trinity_calculate_vce_wm() argument
1336 if (sclk < 20000) in trinity_calculate_vce_wm()
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| H A D | sumo_dpm.c | 347 u32 highest_engine_clock = ps->levels[ps->num_levels - 1].sclk; in sumo_program_bsp()
350 highest_engine_clock = pi->boost_pl.sclk; in sumo_program_bsp()
411 m_a = asi * ps->levels[i].sclk / 100; in sumo_program_at()
421 m_a = asi * pi->boost_pl.sclk / 100; in sumo_program_at()
555 pl->sclk, false, ÷rs); in sumo_program_power_level()
671 pi->boost_pl.sclk = pi->sys_info.boost_sclk; in sumo_patch_boost_state()
790 pi->acpi_pl.sclk, in sumo_program_acpi_power_level()
844 if (new_ps->levels[new_ps->num_levels - 1].sclk >= in sumo_set_uvd_clock_before_set_eng_clock()
845 current_ps->levels[current_ps->num_levels - 1].sclk) in sumo_set_uvd_clock_before_set_eng_clock()
862 if (new_ps->levels[new_ps->num_levels - 1].sclk < in sumo_set_uvd_clock_after_set_eng_clock()
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| H A D | btc_dpm.c | 1244 u32 *sclk, u32 *mclk) in btc_skip_blacklist_clocks() argument
1248 if ((sclk == NULL) || (mclk == NULL)) in btc_skip_blacklist_clocks()
1254 if ((btc_blacklist_clocks[i].sclk == *sclk) && in btc_skip_blacklist_clocks()
1261 *sclk = btc_get_valid_sclk(rdev, max_sclk, *sclk + 1); in btc_skip_blacklist_clocks()
1263 if (*sclk < max_sclk) in btc_skip_blacklist_clocks()
1264 btc_skip_blacklist_clocks(rdev, max_sclk, max_mclk, sclk, mclk); in btc_skip_blacklist_clocks()
1274 if ((pl->mclk == 0) || (pl->sclk == 0)) in btc_adjust_clock_combinations()
1277 if (pl->mclk == pl->sclk) in btc_adjust_clock_combinations()
1280 if (pl->mclk > pl->sclk) { in btc_adjust_clock_combinations()
1281 if (((pl->mclk + (pl->sclk - 1)) / pl->sclk) > rdev->pm.dpm.dyn_state.mclk_sclk_ratio) in btc_adjust_clock_combinations()
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| H A D | kv_dpm.c | 535 u32 index, u32 sclk) in kv_set_divider_value() argument
542 sclk, false, ÷rs); in kv_set_divider_value()
547 pi->graphics_level[index].SclkFrequency = cpu_to_be32(sclk); in kv_set_divider_value()
724 if (table->entries[i].clk == pi->boot_pl.sclk) in kv_program_bootup_state()
738 if (table->entries[i].sclk_frequency == pi->boot_pl.sclk) in kv_program_bootup_state()
1717 if ((table->entries[i].clk >= new_ps->levels[0].sclk) || in kv_set_valid_clock_range()
1725 if (table->entries[i].clk <= new_ps->levels[new_ps->num_levels - 1].sclk) in kv_set_valid_clock_range()
1731 if ((new_ps->levels[0].sclk - table->entries[pi->highest_valid].clk) > in kv_set_valid_clock_range()
1732 (table->entries[pi->lowest_valid].clk - new_ps->levels[new_ps->num_levels - 1].sclk)) in kv_set_valid_clock_range()
1742 if (table->entries[i].sclk_frequency >= new_ps->levels[0].sclk || in kv_set_valid_clock_range()
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| H A D | rv6xx_dpm.c | 439 state->low.sclk; in rv6xx_calculate_engine_speed_stepping_parameters()
441 state->medium.sclk; in rv6xx_calculate_engine_speed_stepping_parameters()
443 state->high.sclk; in rv6xx_calculate_engine_speed_stepping_parameters()
1027 rv6xx_calculate_t(state->low.sclk, in rv6xx_calculate_ap()
1028 state->medium.sclk, in rv6xx_calculate_ap()
1035 rv6xx_calculate_t(state->medium.sclk, in rv6xx_calculate_ap()
1036 state->high.sclk, in rv6xx_calculate_ap()
1426 old_state->low.sclk, in rv6xx_generate_transition_stepping()
1427 new_state->low.sclk, in rv6xx_generate_transition_stepping()
1439 new_state->low.sclk, in rv6xx_generate_low_step()
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| H A D | ni_dpm.c | 811 if (ps->performance_levels[i].sclk > max_limits->sclk) in ni_apply_state_adjust_rules()
812 ps->performance_levels[i].sclk = max_limits->sclk; in ni_apply_state_adjust_rules()
830 btc_skip_blacklist_clocks(rdev, max_limits->sclk, max_limits->mclk, in ni_apply_state_adjust_rules()
831 &ps->performance_levels[0].sclk, in ni_apply_state_adjust_rules()
835 if (ps->performance_levels[i].sclk < ps->performance_levels[i - 1].sclk) in ni_apply_state_adjust_rules()
836 ps->performance_levels[i].sclk = ps->performance_levels[i - 1].sclk; in ni_apply_state_adjust_rules()
865 btc_skip_blacklist_clocks(rdev, max_limits->sclk, max_limits->mclk, in ni_apply_state_adjust_rules()
866 &ps->performance_levels[i].sclk, in ni_apply_state_adjust_rules()
875 ps->performance_levels[i].sclk, in ni_apply_state_adjust_rules()
1622 (u8)rv770_calculate_memory_refresh_rate(rdev, pl->sclk); in ni_populate_memory_timing_parameters()
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| H A D | rv740_dpm.c | 121 RV770_SMC_SCLK_VALUE *sclk) in rv740_populate_sclk_value() argument
176 sclk->sclk_value = cpu_to_be32(engine_clock); in rv740_populate_sclk_value()
177 sclk->vCG_SPLL_FUNC_CNTL = cpu_to_be32(spll_func_cntl); in rv740_populate_sclk_value()
178 sclk->vCG_SPLL_FUNC_CNTL_2 = cpu_to_be32(spll_func_cntl_2); in rv740_populate_sclk_value()
179 sclk->vCG_SPLL_FUNC_CNTL_3 = cpu_to_be32(spll_func_cntl_3); in rv740_populate_sclk_value()
180 sclk->vCG_SPLL_SPREAD_SPECTRUM = cpu_to_be32(cg_spll_spread_spectrum); in rv740_populate_sclk_value()
181 sclk->vCG_SPLL_SPREAD_SPECTRUM_2 = cpu_to_be32(cg_spll_spread_spectrum_2); in rv740_populate_sclk_value()
382 table->ACPIState.levels[0].sclk.vCG_SPLL_FUNC_CNTL = cpu_to_be32(spll_func_cntl); in rv740_populate_smc_acpi_state()
383 table->ACPIState.levels[0].sclk.vCG_SPLL_FUNC_CNTL_2 = cpu_to_be32(spll_func_cntl_2); in rv740_populate_smc_acpi_state()
384 table->ACPIState.levels[0].sclk.vCG_SPLL_FUNC_CNTL_3 = cpu_to_be32(spll_func_cntl_3); in rv740_populate_smc_acpi_state()
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| /OK3568_Linux_fs/kernel/drivers/gpu/drm/nouveau/nvkm/subdev/clk/ |
| H A D | gk104.c | 68 u32 sclk; in read_pll() local
77 sclk = device->crystal; in read_pll()
81 sclk = read_pll(clk, 0x132020); in read_pll()
85 sclk = read_div(clk, 0, 0x137320, 0x137330); in read_pll()
92 sclk = read_div(clk, (pll & 0xff) / 0x20, 0x137120, 0x137140); in read_pll()
101 sclk = (sclk * N) + (((u16)(fN + 4096) * sclk) >> 13); in read_pll()
102 return sclk / (M * P); in read_pll()
121 u32 sclk = read_vco(clk, dsrc + (doff * 4)); in read_div() local
123 return (sclk * 2) / sdiv; in read_div()
149 u32 sclk, sdiv; in read_clk() local
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| H A D | gf100.c | 67 u32 sclk; in read_pll() local
75 sclk = device->crystal; in read_pll()
79 sclk = nvkm_clk_read(&clk->base, nv_clk_src_mpllsrc); in read_pll()
82 sclk = nvkm_clk_read(&clk->base, nv_clk_src_mpllsrcref); in read_pll()
88 sclk = read_div(clk, (pll & 0xff) / 0x20, 0x137120, 0x137140); in read_pll()
94 return sclk * N / M / P; in read_pll()
102 u32 sclk, sctl, sdiv = 2; in read_div() local
112 sclk = read_vco(clk, dsrc + (doff * 4)); in read_div()
126 return (sclk * 2) / sdiv; in read_div()
138 u32 sclk, sdiv; in read_clk() local
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| /OK3568_Linux_fs/u-boot/arch/arm/mach-exynos/ |
| H A D | clock.c | 368 unsigned long sclk = 0; in exynos5_get_periph_rate() local
438 sclk = exynos5_get_pll_clk(MPLL); in exynos5_get_periph_rate()
441 sclk = exynos5_get_pll_clk(EPLL); in exynos5_get_periph_rate()
444 sclk = exynos5_get_pll_clk(VPLL); in exynos5_get_periph_rate()
461 return (sclk / (div + 1)) / (sub_div + 1); in exynos5_get_periph_rate()
467 unsigned long sclk = 0; in exynos542x_get_periph_rate() local
529 sclk = exynos542x_get_pll_clk(MPLL); in exynos542x_get_periph_rate()
532 sclk = exynos542x_get_pll_clk(SPLL); in exynos542x_get_periph_rate()
535 sclk = exynos542x_get_pll_clk(EPLL); in exynos542x_get_periph_rate()
538 sclk = exynos542x_get_pll_clk(RPLL); in exynos542x_get_periph_rate()
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| /OK3568_Linux_fs/kernel/drivers/tty/serial/8250/ |
| H A D | 8250_em.c | 24 struct clk *sclk; member
100 priv->sclk = devm_clk_get(&pdev->dev, "sclk"); in serial8250_em_probe()
101 if (IS_ERR(priv->sclk)) { in serial8250_em_probe()
103 return PTR_ERR(priv->sclk); in serial8250_em_probe()
114 clk_prepare_enable(priv->sclk); in serial8250_em_probe()
115 up.port.uartclk = clk_get_rate(priv->sclk); in serial8250_em_probe()
126 clk_disable_unprepare(priv->sclk); in serial8250_em_probe()
140 clk_disable_unprepare(priv->sclk); in serial8250_em_remove()
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| /OK3568_Linux_fs/kernel/sound/soc/cirrus/ |
| H A D | ep93xx-i2s.c | 75 struct clk *sclk; member
115 clk_enable(info->sclk); in ep93xx_i2s_enable()
160 clk_disable(info->sclk); in ep93xx_i2s_disable()
326 * EP93xx I2S module can be setup so SCLK / LRCLK value can be in ep93xx_i2s_hw_params()
327 * 32, 64, 128. MCLK / SCLK value can be 2 and 4. in ep93xx_i2s_hw_params()
328 * We set LRCLK equal to `rate' and minimum SCLK / LRCLK in ep93xx_i2s_hw_params()
343 err = clk_set_rate(info->sclk, clk_get_rate(info->mclk) / sdiv); in ep93xx_i2s_hw_params()
347 err = clk_set_rate(info->lrclk, clk_get_rate(info->sclk) / lrdiv); in ep93xx_i2s_hw_params()
460 info->sclk = clk_get(&pdev->dev, "sclk"); in ep93xx_i2s_probe()
461 if (IS_ERR(info->sclk)) { in ep93xx_i2s_probe()
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| /OK3568_Linux_fs/kernel/sound/soc/meson/ |
| H A D | axg-tdm-formatter.c | 20 struct clk *sclk; member
99 * If sclk is inverted, it means the bit should latched on the in axg_tdm_formatter_enable()
104 ret = clk_set_phase(formatter->sclk, invert ? 0 : 180); in axg_tdm_formatter_enable()
116 ret = clk_prepare_enable(formatter->sclk); in axg_tdm_formatter_enable()
122 clk_disable_unprepare(formatter->sclk); in axg_tdm_formatter_enable()
141 clk_disable_unprepare(formatter->sclk); in axg_tdm_formatter_disable()
198 ret = clk_set_parent(formatter->sclk_sel, ts->iface->sclk); in axg_tdm_formatter_power_up()
293 formatter->sclk = devm_clk_get(dev, "sclk"); in axg_tdm_formatter_probe()
294 if (IS_ERR(formatter->sclk)) { in axg_tdm_formatter_probe()
295 ret = PTR_ERR(formatter->sclk); in axg_tdm_formatter_probe()
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| /OK3568_Linux_fs/u-boot/board/renesas/ulcb/ |
| H A D | cpld.c | 15 #define SCLK GPIO_GP_6_8 macro
51 gpio_set_value(SCLK, set); in ulcb_softspi_scl()
63 gpio_set_value(SCLK, 1); in cpld_rw()
64 gpio_set_value(SCLK, 0); in cpld_rw()
100 gpio_request(SCLK, NULL); in cpld_init()
105 gpio_direction_output(SCLK, 0); in cpld_init()
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| /OK3568_Linux_fs/kernel/sound/soc/intel/skylake/ |
| H A D | skl-nhlt.c | 192 * sclk/sclkfs.
200 struct skl_ssp_clk *sclk, *sclkfs; in skl_get_ssp_clks() local
210 sclk = &ssp_clks[SKL_SCLK_OFS]; in skl_get_ssp_clks()
231 * But the sclk rate will be generated for the total in skl_get_ssp_clks()
255 /* check if the rate is added already to the given SSP's sclk */ in skl_get_ssp_clks()
257 (sclk[id].rate_cfg[j].rate != 0); j++) { in skl_get_ssp_clks()
258 if (sclk[id].rate_cfg[j].rate == rate) { in skl_get_ssp_clks()
264 /* Fill rate and parent for sclk/sclkfs */ in skl_get_ssp_clks()
294 sclk[id].rate_cfg[rate_index].rate = rate; in skl_get_ssp_clks()
295 sclk[id].rate_cfg[rate_index].config = saved_fmt_cfg; in skl_get_ssp_clks()
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