1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0-or-later
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun * Hisilicon clock separated gate driver
4*4882a593Smuzhiyun *
5*4882a593Smuzhiyun * Copyright (c) 2012-2013 Hisilicon Limited.
6*4882a593Smuzhiyun * Copyright (c) 2012-2013 Linaro Limited.
7*4882a593Smuzhiyun *
8*4882a593Smuzhiyun * Author: Haojian Zhuang <haojian.zhuang@linaro.org>
9*4882a593Smuzhiyun * Xin Li <li.xin@linaro.org>
10*4882a593Smuzhiyun */
11*4882a593Smuzhiyun
12*4882a593Smuzhiyun #include <linux/kernel.h>
13*4882a593Smuzhiyun #include <linux/clk-provider.h>
14*4882a593Smuzhiyun #include <linux/io.h>
15*4882a593Smuzhiyun #include <linux/slab.h>
16*4882a593Smuzhiyun
17*4882a593Smuzhiyun #include "clk.h"
18*4882a593Smuzhiyun
19*4882a593Smuzhiyun /* clock separated gate register offset */
20*4882a593Smuzhiyun #define CLKGATE_SEPERATED_ENABLE 0x0
21*4882a593Smuzhiyun #define CLKGATE_SEPERATED_DISABLE 0x4
22*4882a593Smuzhiyun #define CLKGATE_SEPERATED_STATUS 0x8
23*4882a593Smuzhiyun
24*4882a593Smuzhiyun struct clkgate_separated {
25*4882a593Smuzhiyun struct clk_hw hw;
26*4882a593Smuzhiyun void __iomem *enable; /* enable register */
27*4882a593Smuzhiyun u8 bit_idx; /* bits in enable/disable register */
28*4882a593Smuzhiyun u8 flags;
29*4882a593Smuzhiyun spinlock_t *lock;
30*4882a593Smuzhiyun };
31*4882a593Smuzhiyun
clkgate_separated_enable(struct clk_hw * hw)32*4882a593Smuzhiyun static int clkgate_separated_enable(struct clk_hw *hw)
33*4882a593Smuzhiyun {
34*4882a593Smuzhiyun struct clkgate_separated *sclk;
35*4882a593Smuzhiyun unsigned long flags = 0;
36*4882a593Smuzhiyun u32 reg;
37*4882a593Smuzhiyun
38*4882a593Smuzhiyun sclk = container_of(hw, struct clkgate_separated, hw);
39*4882a593Smuzhiyun if (sclk->lock)
40*4882a593Smuzhiyun spin_lock_irqsave(sclk->lock, flags);
41*4882a593Smuzhiyun reg = BIT(sclk->bit_idx);
42*4882a593Smuzhiyun writel_relaxed(reg, sclk->enable);
43*4882a593Smuzhiyun readl_relaxed(sclk->enable + CLKGATE_SEPERATED_STATUS);
44*4882a593Smuzhiyun if (sclk->lock)
45*4882a593Smuzhiyun spin_unlock_irqrestore(sclk->lock, flags);
46*4882a593Smuzhiyun return 0;
47*4882a593Smuzhiyun }
48*4882a593Smuzhiyun
clkgate_separated_disable(struct clk_hw * hw)49*4882a593Smuzhiyun static void clkgate_separated_disable(struct clk_hw *hw)
50*4882a593Smuzhiyun {
51*4882a593Smuzhiyun struct clkgate_separated *sclk;
52*4882a593Smuzhiyun unsigned long flags = 0;
53*4882a593Smuzhiyun u32 reg;
54*4882a593Smuzhiyun
55*4882a593Smuzhiyun sclk = container_of(hw, struct clkgate_separated, hw);
56*4882a593Smuzhiyun if (sclk->lock)
57*4882a593Smuzhiyun spin_lock_irqsave(sclk->lock, flags);
58*4882a593Smuzhiyun reg = BIT(sclk->bit_idx);
59*4882a593Smuzhiyun writel_relaxed(reg, sclk->enable + CLKGATE_SEPERATED_DISABLE);
60*4882a593Smuzhiyun readl_relaxed(sclk->enable + CLKGATE_SEPERATED_STATUS);
61*4882a593Smuzhiyun if (sclk->lock)
62*4882a593Smuzhiyun spin_unlock_irqrestore(sclk->lock, flags);
63*4882a593Smuzhiyun }
64*4882a593Smuzhiyun
clkgate_separated_is_enabled(struct clk_hw * hw)65*4882a593Smuzhiyun static int clkgate_separated_is_enabled(struct clk_hw *hw)
66*4882a593Smuzhiyun {
67*4882a593Smuzhiyun struct clkgate_separated *sclk;
68*4882a593Smuzhiyun u32 reg;
69*4882a593Smuzhiyun
70*4882a593Smuzhiyun sclk = container_of(hw, struct clkgate_separated, hw);
71*4882a593Smuzhiyun reg = readl_relaxed(sclk->enable + CLKGATE_SEPERATED_STATUS);
72*4882a593Smuzhiyun reg &= BIT(sclk->bit_idx);
73*4882a593Smuzhiyun
74*4882a593Smuzhiyun return reg ? 1 : 0;
75*4882a593Smuzhiyun }
76*4882a593Smuzhiyun
77*4882a593Smuzhiyun static const struct clk_ops clkgate_separated_ops = {
78*4882a593Smuzhiyun .enable = clkgate_separated_enable,
79*4882a593Smuzhiyun .disable = clkgate_separated_disable,
80*4882a593Smuzhiyun .is_enabled = clkgate_separated_is_enabled,
81*4882a593Smuzhiyun };
82*4882a593Smuzhiyun
hisi_register_clkgate_sep(struct device * dev,const char * name,const char * parent_name,unsigned long flags,void __iomem * reg,u8 bit_idx,u8 clk_gate_flags,spinlock_t * lock)83*4882a593Smuzhiyun struct clk *hisi_register_clkgate_sep(struct device *dev, const char *name,
84*4882a593Smuzhiyun const char *parent_name,
85*4882a593Smuzhiyun unsigned long flags,
86*4882a593Smuzhiyun void __iomem *reg, u8 bit_idx,
87*4882a593Smuzhiyun u8 clk_gate_flags, spinlock_t *lock)
88*4882a593Smuzhiyun {
89*4882a593Smuzhiyun struct clkgate_separated *sclk;
90*4882a593Smuzhiyun struct clk *clk;
91*4882a593Smuzhiyun struct clk_init_data init;
92*4882a593Smuzhiyun
93*4882a593Smuzhiyun sclk = kzalloc(sizeof(*sclk), GFP_KERNEL);
94*4882a593Smuzhiyun if (!sclk)
95*4882a593Smuzhiyun return ERR_PTR(-ENOMEM);
96*4882a593Smuzhiyun
97*4882a593Smuzhiyun init.name = name;
98*4882a593Smuzhiyun init.ops = &clkgate_separated_ops;
99*4882a593Smuzhiyun init.flags = flags;
100*4882a593Smuzhiyun init.parent_names = (parent_name ? &parent_name : NULL);
101*4882a593Smuzhiyun init.num_parents = (parent_name ? 1 : 0);
102*4882a593Smuzhiyun
103*4882a593Smuzhiyun sclk->enable = reg + CLKGATE_SEPERATED_ENABLE;
104*4882a593Smuzhiyun sclk->bit_idx = bit_idx;
105*4882a593Smuzhiyun sclk->flags = clk_gate_flags;
106*4882a593Smuzhiyun sclk->hw.init = &init;
107*4882a593Smuzhiyun sclk->lock = lock;
108*4882a593Smuzhiyun
109*4882a593Smuzhiyun clk = clk_register(dev, &sclk->hw);
110*4882a593Smuzhiyun if (IS_ERR(clk))
111*4882a593Smuzhiyun kfree(sclk);
112*4882a593Smuzhiyun return clk;
113*4882a593Smuzhiyun }
114