xref: /OK3568_Linux_fs/kernel/drivers/clk/clk-scpi.c (revision 4882a59341e53eb6f0b4789bf948001014eff981)
1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0-only
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun  * System Control and Power Interface (SCPI) Protocol based clock driver
4*4882a593Smuzhiyun  *
5*4882a593Smuzhiyun  * Copyright (C) 2015 ARM Ltd.
6*4882a593Smuzhiyun  */
7*4882a593Smuzhiyun 
8*4882a593Smuzhiyun #include <linux/clk-provider.h>
9*4882a593Smuzhiyun #include <linux/device.h>
10*4882a593Smuzhiyun #include <linux/err.h>
11*4882a593Smuzhiyun #include <linux/of.h>
12*4882a593Smuzhiyun #include <linux/module.h>
13*4882a593Smuzhiyun #include <linux/of_platform.h>
14*4882a593Smuzhiyun #include <linux/platform_device.h>
15*4882a593Smuzhiyun #include <linux/scpi_protocol.h>
16*4882a593Smuzhiyun 
17*4882a593Smuzhiyun struct scpi_clk {
18*4882a593Smuzhiyun 	u32 id;
19*4882a593Smuzhiyun 	struct clk_hw hw;
20*4882a593Smuzhiyun 	struct scpi_dvfs_info *info;
21*4882a593Smuzhiyun 	struct scpi_ops *scpi_ops;
22*4882a593Smuzhiyun };
23*4882a593Smuzhiyun 
24*4882a593Smuzhiyun #define to_scpi_clk(clk) container_of(clk, struct scpi_clk, hw)
25*4882a593Smuzhiyun 
26*4882a593Smuzhiyun static struct platform_device *cpufreq_dev;
27*4882a593Smuzhiyun 
scpi_clk_recalc_rate(struct clk_hw * hw,unsigned long parent_rate)28*4882a593Smuzhiyun static unsigned long scpi_clk_recalc_rate(struct clk_hw *hw,
29*4882a593Smuzhiyun 					  unsigned long parent_rate)
30*4882a593Smuzhiyun {
31*4882a593Smuzhiyun 	struct scpi_clk *clk = to_scpi_clk(hw);
32*4882a593Smuzhiyun 
33*4882a593Smuzhiyun 	return clk->scpi_ops->clk_get_val(clk->id);
34*4882a593Smuzhiyun }
35*4882a593Smuzhiyun 
scpi_clk_round_rate(struct clk_hw * hw,unsigned long rate,unsigned long * parent_rate)36*4882a593Smuzhiyun static long scpi_clk_round_rate(struct clk_hw *hw, unsigned long rate,
37*4882a593Smuzhiyun 				unsigned long *parent_rate)
38*4882a593Smuzhiyun {
39*4882a593Smuzhiyun 	/*
40*4882a593Smuzhiyun 	 * We can't figure out what rate it will be, so just return the
41*4882a593Smuzhiyun 	 * rate back to the caller. scpi_clk_recalc_rate() will be called
42*4882a593Smuzhiyun 	 * after the rate is set and we'll know what rate the clock is
43*4882a593Smuzhiyun 	 * running at then.
44*4882a593Smuzhiyun 	 */
45*4882a593Smuzhiyun 	return rate;
46*4882a593Smuzhiyun }
47*4882a593Smuzhiyun 
scpi_clk_set_rate(struct clk_hw * hw,unsigned long rate,unsigned long parent_rate)48*4882a593Smuzhiyun static int scpi_clk_set_rate(struct clk_hw *hw, unsigned long rate,
49*4882a593Smuzhiyun 			     unsigned long parent_rate)
50*4882a593Smuzhiyun {
51*4882a593Smuzhiyun 	struct scpi_clk *clk = to_scpi_clk(hw);
52*4882a593Smuzhiyun 
53*4882a593Smuzhiyun 	return clk->scpi_ops->clk_set_val(clk->id, rate);
54*4882a593Smuzhiyun }
55*4882a593Smuzhiyun 
56*4882a593Smuzhiyun static const struct clk_ops scpi_clk_ops = {
57*4882a593Smuzhiyun 	.recalc_rate = scpi_clk_recalc_rate,
58*4882a593Smuzhiyun 	.round_rate = scpi_clk_round_rate,
59*4882a593Smuzhiyun 	.set_rate = scpi_clk_set_rate,
60*4882a593Smuzhiyun };
61*4882a593Smuzhiyun 
62*4882a593Smuzhiyun /* find closest match to given frequency in OPP table */
__scpi_dvfs_round_rate(struct scpi_clk * clk,unsigned long rate)63*4882a593Smuzhiyun static long __scpi_dvfs_round_rate(struct scpi_clk *clk, unsigned long rate)
64*4882a593Smuzhiyun {
65*4882a593Smuzhiyun 	int idx;
66*4882a593Smuzhiyun 	unsigned long fmin = 0, fmax = ~0, ftmp;
67*4882a593Smuzhiyun 	const struct scpi_opp *opp = clk->info->opps;
68*4882a593Smuzhiyun 
69*4882a593Smuzhiyun 	for (idx = 0; idx < clk->info->count; idx++, opp++) {
70*4882a593Smuzhiyun 		ftmp = opp->freq;
71*4882a593Smuzhiyun 		if (ftmp >= rate) {
72*4882a593Smuzhiyun 			if (ftmp <= fmax)
73*4882a593Smuzhiyun 				fmax = ftmp;
74*4882a593Smuzhiyun 			break;
75*4882a593Smuzhiyun 		} else if (ftmp >= fmin) {
76*4882a593Smuzhiyun 			fmin = ftmp;
77*4882a593Smuzhiyun 		}
78*4882a593Smuzhiyun 	}
79*4882a593Smuzhiyun 	return fmax != ~0 ? fmax : fmin;
80*4882a593Smuzhiyun }
81*4882a593Smuzhiyun 
scpi_dvfs_recalc_rate(struct clk_hw * hw,unsigned long parent_rate)82*4882a593Smuzhiyun static unsigned long scpi_dvfs_recalc_rate(struct clk_hw *hw,
83*4882a593Smuzhiyun 					   unsigned long parent_rate)
84*4882a593Smuzhiyun {
85*4882a593Smuzhiyun 	struct scpi_clk *clk = to_scpi_clk(hw);
86*4882a593Smuzhiyun 	int idx = clk->scpi_ops->dvfs_get_idx(clk->id);
87*4882a593Smuzhiyun 	const struct scpi_opp *opp;
88*4882a593Smuzhiyun 
89*4882a593Smuzhiyun 	if (idx < 0)
90*4882a593Smuzhiyun 		return 0;
91*4882a593Smuzhiyun 
92*4882a593Smuzhiyun 	opp = clk->info->opps + idx;
93*4882a593Smuzhiyun 	return opp->freq;
94*4882a593Smuzhiyun }
95*4882a593Smuzhiyun 
scpi_dvfs_round_rate(struct clk_hw * hw,unsigned long rate,unsigned long * parent_rate)96*4882a593Smuzhiyun static long scpi_dvfs_round_rate(struct clk_hw *hw, unsigned long rate,
97*4882a593Smuzhiyun 				 unsigned long *parent_rate)
98*4882a593Smuzhiyun {
99*4882a593Smuzhiyun 	struct scpi_clk *clk = to_scpi_clk(hw);
100*4882a593Smuzhiyun 
101*4882a593Smuzhiyun 	return __scpi_dvfs_round_rate(clk, rate);
102*4882a593Smuzhiyun }
103*4882a593Smuzhiyun 
__scpi_find_dvfs_index(struct scpi_clk * clk,unsigned long rate)104*4882a593Smuzhiyun static int __scpi_find_dvfs_index(struct scpi_clk *clk, unsigned long rate)
105*4882a593Smuzhiyun {
106*4882a593Smuzhiyun 	int idx, max_opp = clk->info->count;
107*4882a593Smuzhiyun 	const struct scpi_opp *opp = clk->info->opps;
108*4882a593Smuzhiyun 
109*4882a593Smuzhiyun 	for (idx = 0; idx < max_opp; idx++, opp++)
110*4882a593Smuzhiyun 		if (opp->freq == rate)
111*4882a593Smuzhiyun 			return idx;
112*4882a593Smuzhiyun 	return -EINVAL;
113*4882a593Smuzhiyun }
114*4882a593Smuzhiyun 
scpi_dvfs_set_rate(struct clk_hw * hw,unsigned long rate,unsigned long parent_rate)115*4882a593Smuzhiyun static int scpi_dvfs_set_rate(struct clk_hw *hw, unsigned long rate,
116*4882a593Smuzhiyun 			      unsigned long parent_rate)
117*4882a593Smuzhiyun {
118*4882a593Smuzhiyun 	struct scpi_clk *clk = to_scpi_clk(hw);
119*4882a593Smuzhiyun 	int ret = __scpi_find_dvfs_index(clk, rate);
120*4882a593Smuzhiyun 
121*4882a593Smuzhiyun 	if (ret < 0)
122*4882a593Smuzhiyun 		return ret;
123*4882a593Smuzhiyun 	return clk->scpi_ops->dvfs_set_idx(clk->id, (u8)ret);
124*4882a593Smuzhiyun }
125*4882a593Smuzhiyun 
126*4882a593Smuzhiyun static const struct clk_ops scpi_dvfs_ops = {
127*4882a593Smuzhiyun 	.recalc_rate = scpi_dvfs_recalc_rate,
128*4882a593Smuzhiyun 	.round_rate = scpi_dvfs_round_rate,
129*4882a593Smuzhiyun 	.set_rate = scpi_dvfs_set_rate,
130*4882a593Smuzhiyun };
131*4882a593Smuzhiyun 
132*4882a593Smuzhiyun static const struct of_device_id scpi_clk_match[] = {
133*4882a593Smuzhiyun 	{ .compatible = "arm,scpi-dvfs-clocks", .data = &scpi_dvfs_ops, },
134*4882a593Smuzhiyun 	{ .compatible = "arm,scpi-variable-clocks", .data = &scpi_clk_ops, },
135*4882a593Smuzhiyun 	{}
136*4882a593Smuzhiyun };
137*4882a593Smuzhiyun 
138*4882a593Smuzhiyun static int
scpi_clk_ops_init(struct device * dev,const struct of_device_id * match,struct scpi_clk * sclk,const char * name)139*4882a593Smuzhiyun scpi_clk_ops_init(struct device *dev, const struct of_device_id *match,
140*4882a593Smuzhiyun 		  struct scpi_clk *sclk, const char *name)
141*4882a593Smuzhiyun {
142*4882a593Smuzhiyun 	struct clk_init_data init;
143*4882a593Smuzhiyun 	unsigned long min = 0, max = 0;
144*4882a593Smuzhiyun 	int ret;
145*4882a593Smuzhiyun 
146*4882a593Smuzhiyun 	init.name = name;
147*4882a593Smuzhiyun 	init.flags = 0;
148*4882a593Smuzhiyun 	init.num_parents = 0;
149*4882a593Smuzhiyun 	init.ops = match->data;
150*4882a593Smuzhiyun 	sclk->hw.init = &init;
151*4882a593Smuzhiyun 	sclk->scpi_ops = get_scpi_ops();
152*4882a593Smuzhiyun 
153*4882a593Smuzhiyun 	if (init.ops == &scpi_dvfs_ops) {
154*4882a593Smuzhiyun 		sclk->info = sclk->scpi_ops->dvfs_get_info(sclk->id);
155*4882a593Smuzhiyun 		if (IS_ERR(sclk->info))
156*4882a593Smuzhiyun 			return PTR_ERR(sclk->info);
157*4882a593Smuzhiyun 	} else if (init.ops == &scpi_clk_ops) {
158*4882a593Smuzhiyun 		if (sclk->scpi_ops->clk_get_range(sclk->id, &min, &max) || !max)
159*4882a593Smuzhiyun 			return -EINVAL;
160*4882a593Smuzhiyun 	} else {
161*4882a593Smuzhiyun 		return -EINVAL;
162*4882a593Smuzhiyun 	}
163*4882a593Smuzhiyun 
164*4882a593Smuzhiyun 	ret = devm_clk_hw_register(dev, &sclk->hw);
165*4882a593Smuzhiyun 	if (!ret && max)
166*4882a593Smuzhiyun 		clk_hw_set_rate_range(&sclk->hw, min, max);
167*4882a593Smuzhiyun 	return ret;
168*4882a593Smuzhiyun }
169*4882a593Smuzhiyun 
170*4882a593Smuzhiyun struct scpi_clk_data {
171*4882a593Smuzhiyun 	struct scpi_clk **clk;
172*4882a593Smuzhiyun 	unsigned int clk_num;
173*4882a593Smuzhiyun };
174*4882a593Smuzhiyun 
175*4882a593Smuzhiyun static struct clk_hw *
scpi_of_clk_src_get(struct of_phandle_args * clkspec,void * data)176*4882a593Smuzhiyun scpi_of_clk_src_get(struct of_phandle_args *clkspec, void *data)
177*4882a593Smuzhiyun {
178*4882a593Smuzhiyun 	struct scpi_clk *sclk;
179*4882a593Smuzhiyun 	struct scpi_clk_data *clk_data = data;
180*4882a593Smuzhiyun 	unsigned int idx = clkspec->args[0], count;
181*4882a593Smuzhiyun 
182*4882a593Smuzhiyun 	for (count = 0; count < clk_data->clk_num; count++) {
183*4882a593Smuzhiyun 		sclk = clk_data->clk[count];
184*4882a593Smuzhiyun 		if (idx == sclk->id)
185*4882a593Smuzhiyun 			return &sclk->hw;
186*4882a593Smuzhiyun 	}
187*4882a593Smuzhiyun 
188*4882a593Smuzhiyun 	return ERR_PTR(-EINVAL);
189*4882a593Smuzhiyun }
190*4882a593Smuzhiyun 
scpi_clk_add(struct device * dev,struct device_node * np,const struct of_device_id * match)191*4882a593Smuzhiyun static int scpi_clk_add(struct device *dev, struct device_node *np,
192*4882a593Smuzhiyun 			const struct of_device_id *match)
193*4882a593Smuzhiyun {
194*4882a593Smuzhiyun 	int idx, count, err;
195*4882a593Smuzhiyun 	struct scpi_clk_data *clk_data;
196*4882a593Smuzhiyun 
197*4882a593Smuzhiyun 	count = of_property_count_strings(np, "clock-output-names");
198*4882a593Smuzhiyun 	if (count < 0) {
199*4882a593Smuzhiyun 		dev_err(dev, "%pOFn: invalid clock output count\n", np);
200*4882a593Smuzhiyun 		return -EINVAL;
201*4882a593Smuzhiyun 	}
202*4882a593Smuzhiyun 
203*4882a593Smuzhiyun 	clk_data = devm_kmalloc(dev, sizeof(*clk_data), GFP_KERNEL);
204*4882a593Smuzhiyun 	if (!clk_data)
205*4882a593Smuzhiyun 		return -ENOMEM;
206*4882a593Smuzhiyun 
207*4882a593Smuzhiyun 	clk_data->clk_num = count;
208*4882a593Smuzhiyun 	clk_data->clk = devm_kcalloc(dev, count, sizeof(*clk_data->clk),
209*4882a593Smuzhiyun 				     GFP_KERNEL);
210*4882a593Smuzhiyun 	if (!clk_data->clk)
211*4882a593Smuzhiyun 		return -ENOMEM;
212*4882a593Smuzhiyun 
213*4882a593Smuzhiyun 	for (idx = 0; idx < count; idx++) {
214*4882a593Smuzhiyun 		struct scpi_clk *sclk;
215*4882a593Smuzhiyun 		const char *name;
216*4882a593Smuzhiyun 		u32 val;
217*4882a593Smuzhiyun 
218*4882a593Smuzhiyun 		sclk = devm_kzalloc(dev, sizeof(*sclk), GFP_KERNEL);
219*4882a593Smuzhiyun 		if (!sclk)
220*4882a593Smuzhiyun 			return -ENOMEM;
221*4882a593Smuzhiyun 
222*4882a593Smuzhiyun 		if (of_property_read_string_index(np, "clock-output-names",
223*4882a593Smuzhiyun 						  idx, &name)) {
224*4882a593Smuzhiyun 			dev_err(dev, "invalid clock name @ %pOFn\n", np);
225*4882a593Smuzhiyun 			return -EINVAL;
226*4882a593Smuzhiyun 		}
227*4882a593Smuzhiyun 
228*4882a593Smuzhiyun 		if (of_property_read_u32_index(np, "clock-indices",
229*4882a593Smuzhiyun 					       idx, &val)) {
230*4882a593Smuzhiyun 			dev_err(dev, "invalid clock index @ %pOFn\n", np);
231*4882a593Smuzhiyun 			return -EINVAL;
232*4882a593Smuzhiyun 		}
233*4882a593Smuzhiyun 
234*4882a593Smuzhiyun 		sclk->id = val;
235*4882a593Smuzhiyun 
236*4882a593Smuzhiyun 		err = scpi_clk_ops_init(dev, match, sclk, name);
237*4882a593Smuzhiyun 		if (err) {
238*4882a593Smuzhiyun 			dev_err(dev, "failed to register clock '%s'\n", name);
239*4882a593Smuzhiyun 			return err;
240*4882a593Smuzhiyun 		}
241*4882a593Smuzhiyun 
242*4882a593Smuzhiyun 		dev_dbg(dev, "Registered clock '%s'\n", name);
243*4882a593Smuzhiyun 		clk_data->clk[idx] = sclk;
244*4882a593Smuzhiyun 	}
245*4882a593Smuzhiyun 
246*4882a593Smuzhiyun 	return of_clk_add_hw_provider(np, scpi_of_clk_src_get, clk_data);
247*4882a593Smuzhiyun }
248*4882a593Smuzhiyun 
scpi_clocks_remove(struct platform_device * pdev)249*4882a593Smuzhiyun static int scpi_clocks_remove(struct platform_device *pdev)
250*4882a593Smuzhiyun {
251*4882a593Smuzhiyun 	struct device *dev = &pdev->dev;
252*4882a593Smuzhiyun 	struct device_node *child, *np = dev->of_node;
253*4882a593Smuzhiyun 
254*4882a593Smuzhiyun 	if (cpufreq_dev) {
255*4882a593Smuzhiyun 		platform_device_unregister(cpufreq_dev);
256*4882a593Smuzhiyun 		cpufreq_dev = NULL;
257*4882a593Smuzhiyun 	}
258*4882a593Smuzhiyun 
259*4882a593Smuzhiyun 	for_each_available_child_of_node(np, child)
260*4882a593Smuzhiyun 		of_clk_del_provider(np);
261*4882a593Smuzhiyun 	return 0;
262*4882a593Smuzhiyun }
263*4882a593Smuzhiyun 
scpi_clocks_probe(struct platform_device * pdev)264*4882a593Smuzhiyun static int scpi_clocks_probe(struct platform_device *pdev)
265*4882a593Smuzhiyun {
266*4882a593Smuzhiyun 	int ret;
267*4882a593Smuzhiyun 	struct device *dev = &pdev->dev;
268*4882a593Smuzhiyun 	struct device_node *child, *np = dev->of_node;
269*4882a593Smuzhiyun 	const struct of_device_id *match;
270*4882a593Smuzhiyun 
271*4882a593Smuzhiyun 	if (!get_scpi_ops())
272*4882a593Smuzhiyun 		return -ENXIO;
273*4882a593Smuzhiyun 
274*4882a593Smuzhiyun 	for_each_available_child_of_node(np, child) {
275*4882a593Smuzhiyun 		match = of_match_node(scpi_clk_match, child);
276*4882a593Smuzhiyun 		if (!match)
277*4882a593Smuzhiyun 			continue;
278*4882a593Smuzhiyun 		ret = scpi_clk_add(dev, child, match);
279*4882a593Smuzhiyun 		if (ret) {
280*4882a593Smuzhiyun 			scpi_clocks_remove(pdev);
281*4882a593Smuzhiyun 			of_node_put(child);
282*4882a593Smuzhiyun 			return ret;
283*4882a593Smuzhiyun 		}
284*4882a593Smuzhiyun 
285*4882a593Smuzhiyun 		if (match->data != &scpi_dvfs_ops)
286*4882a593Smuzhiyun 			continue;
287*4882a593Smuzhiyun 		/* Add the virtual cpufreq device if it's DVFS clock provider */
288*4882a593Smuzhiyun 		cpufreq_dev = platform_device_register_simple("scpi-cpufreq",
289*4882a593Smuzhiyun 							      -1, NULL, 0);
290*4882a593Smuzhiyun 		if (IS_ERR(cpufreq_dev))
291*4882a593Smuzhiyun 			pr_warn("unable to register cpufreq device");
292*4882a593Smuzhiyun 	}
293*4882a593Smuzhiyun 	return 0;
294*4882a593Smuzhiyun }
295*4882a593Smuzhiyun 
296*4882a593Smuzhiyun static const struct of_device_id scpi_clocks_ids[] = {
297*4882a593Smuzhiyun 	{ .compatible = "arm,scpi-clocks", },
298*4882a593Smuzhiyun 	{}
299*4882a593Smuzhiyun };
300*4882a593Smuzhiyun MODULE_DEVICE_TABLE(of, scpi_clocks_ids);
301*4882a593Smuzhiyun 
302*4882a593Smuzhiyun static struct platform_driver scpi_clocks_driver = {
303*4882a593Smuzhiyun 	.driver	= {
304*4882a593Smuzhiyun 		.name = "scpi_clocks",
305*4882a593Smuzhiyun 		.of_match_table = scpi_clocks_ids,
306*4882a593Smuzhiyun 	},
307*4882a593Smuzhiyun 	.probe = scpi_clocks_probe,
308*4882a593Smuzhiyun 	.remove = scpi_clocks_remove,
309*4882a593Smuzhiyun };
310*4882a593Smuzhiyun module_platform_driver(scpi_clocks_driver);
311*4882a593Smuzhiyun 
312*4882a593Smuzhiyun MODULE_AUTHOR("Sudeep Holla <sudeep.holla@arm.com>");
313*4882a593Smuzhiyun MODULE_DESCRIPTION("ARM SCPI clock driver");
314*4882a593Smuzhiyun MODULE_LICENSE("GPL v2");
315