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/OK3568_Linux_fs/kernel/Documentation/devicetree/bindings/perf/
H A Dfsl-imx-ddr.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/perf/fsl-imx-ddr.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Freescale(NXP) IMX8 DDR performance monitor
10 - Frank Li <frank.li@nxp.com>
15 - enum:
16 - fsl,imx8-ddr-pmu
17 - fsl,imx8m-ddr-pmu
18 - fsl,imx8mp-ddr-pmu
[all …]
/OK3568_Linux_fs/kernel/drivers/perf/
H A Dfsl_imx8_ddr_perf.c1 // SPDX-License-Identifier: GPL-2.0
40 #define to_ddr_pmu(p) container_of(p, struct ddr_pmu, pmu)
47 /* DDR Perf hardware feature */
52 unsigned int quirks; /* quirks needed for different DDR Perf core */
66 { .compatible = "fsl,imx8-ddr-pmu", .data = &imx8_devtype_data},
67 { .compatible = "fsl,imx8m-ddr-pmu", .data = &imx8m_devtype_data},
68 { .compatible = "fsl,imx8mp-ddr-pmu", .data = &imx8mp_devtype_data},
74 struct pmu pmu; member
93 static u32 ddr_perf_filter_cap_get(struct ddr_pmu *pmu, int cap) in ddr_perf_filter_cap_get() argument
95 u32 quirks = pmu->devtype_data->quirks; in ddr_perf_filter_cap_get()
[all …]
H A DKconfig1 # SPDX-License-Identifier: GPL-2.0-only
10 tristate "ARM CCI PMU driver"
14 Support for PMU events monitoring on the ARM CCI (Cache Coherent
17 If compiled as a module, it will be called arm-cci.
20 bool "support CCI-400"
25 CCI-400 provides 4 independent event counters counting events related
29 bool "support CCI-500/CCI-550"
33 CCI-500/CCI-550 both provide 8 independent event counters, which can
41 PMU (perf) driver supporting the ARM CCN (Cache Coherent Network)
45 tristate "Arm CMN-600 PMU support"
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/OK3568_Linux_fs/u-boot/doc/device-tree-bindings/clock/
H A Drockchip,rk3288-dmc.txt3 - compatible: "rockchip,rk3288-dmc", "syscon"
4 - rockchip,cru: this driver should access cru regs, so need get cru here
5 - rockchip,grf: this driver should access grf regs, so need get grf here
6 - rockchip,pmu: this driver should access pmu regs, so need get pmu here
7 - rockchip,sgrf: this driver should access sgrf regs, so need get sgrf here
8 - rockchip,noc: this driver should access noc regs, so need get noc here
9 - reg: dynamic ram protocol controller(PCTL) address and phy controller(PHYCTL) address
10 - clock: must include clock specifiers corresponding to entries in the clock-names property.
11 - clock-output-names: from common clock binding to override the default output clock name
18 -logic-supply: this driver should adjust VDD_LOGIC according to dmc frequency, so need get logic-su…
[all …]
/OK3568_Linux_fs/kernel/Documentation/admin-guide/perf/
H A Dimx-ddr.rst2 Freescale i.MX8 DDR Performance Monitoring Unit (PMU)
21 in DDR PMU, see /sys/bus/events_source/devices/imx8_ddr0/caps/.
23 .. code-block:: bash
25 perf stat -a -e imx8_ddr0/cycles/ cmd
26 perf stat -a -e imx8_ddr0/read/,imx8_ddr0/write/ cmd
28 AXI filtering is only used by CSV modes 0x41 (axid-read) and 0x42 (axid-write)
32 indicates whether PMU supports AXI ID filter or not; enhanced_filter indicates
33 whether PMU supports enhanced AXI ID filter or not. Value 0 for un-supported, and
38 --AXI_ID defines AxID matching value.
39 --AXI_MASKING defines which bits of AxID are meaningful for the matching.
[all …]
H A Dindex.rst1 .. SPDX-License-Identifier: GPL-2.0
10 hisi-pmu
11 imx-ddr
14 arm-ccn
15 arm-cmn
16 xgene-pmu
18 thunderx2-pmu
/OK3568_Linux_fs/buildroot/boot/uboot/
H A DConfig.in2 bool "U-Boot"
4 Build "Das U-Boot" Boot Monitor
6 https://www.denx.de/wiki/U-Boot
17 Select this option if you use a recent U-Boot version (2015.04
23 Select this option if you use an old U-Boot (older than
30 string "U-Boot board name"
32 One of U-Boot supported boards to be built.
33 This will be suffixed with _config to meet U-Boot standard
34 naming. See boards.cfg in U-Boot source code for the list of
39 prompt "U-Boot Version"
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/OK3568_Linux_fs/kernel/include/dt-bindings/suspend/
H A Drockchip-rk3308.h33 * rockchip_suspend: rockchip-suspend {
34 * rockchip,sleep-mode-config = <...>;
35 * rockchip,wakeup-config = <...>;
36 * rockchip,apios-suspend = <...>;
37 * rockchip,pwm-regulator-config = <...>;
43 * rockchip,sleep-mode-config = <...>;
47 #define RKPM_PMU_HW_PLLS_PD BIT(3) /* disable PLLs by PMU hardware, recommend */
51 #define RKPM_DDR_SREF_HARDWARE BIT(7) /* ddr enter self-refresh by PMU hardware, not recommend */
52 #define RKPM_DDR_EXIT_SRPD_IDLE BIT(8) /* ddr exit sr/pd idle by ddr controller, not recommend */
59 * rockchip,pwm-regulator-config = <...>;
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/OK3568_Linux_fs/kernel/Documentation/devicetree/bindings/devfreq/
H A Drk3399_dmc.txt4 - compatible: Must be "rockchip,rk3399-dmc".
5 - devfreq-events: Node to get DDR loading, Refer to
7 rockchip-dfi.txt
8 - clocks: Phandles for clock specified in "clock-names" property
9 - clock-names : The name of clock used by the DFI, must be
11 - operating-points-v2: Refer to Documentation/devicetree/bindings/opp/opp.txt
13 - center-supply: DMC supply node.
14 - status: Marks the node enabled/disabled.
17 - interrupts: The CPU interrupt number. The interrupt specifier
19 It should be a DCF interrupt. When DDR DVFS finishes
[all …]
/OK3568_Linux_fs/u-boot/doc/
H A DREADME.440-DDR-performance1 AMCC suggested to set the PMU bit to 0 for best performace on the
2 PPC440 DDR controller. The 440er common DDR setup files (sdram.c &
11 ----------------------------------------
12 SDRAM0_CFG0[PMU] = 1 (U-Boot default for Bamboo, Yosemite and Yellowstone)
13 ----------------------------------------
15 -------------------------------------------------------------
17 -------------------------------------------------------------
22 -------------------------------------------------------------
28 -------------------------------------------------------------
29 WARNING -- The above is only a rough guideline.
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/OK3568_Linux_fs/kernel/arch/arm/boot/dts/
H A Decx-2000.dts1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright 2011-2012 Calxeda, Inc.
6 /dts-v1/;
12 model = "Calxeda ECX-2000";
13 compatible = "calxeda,ecx-2000";
14 #address-cells = <2>;
15 #size-cells = <2>;
18 #address-cells = <1>;
19 #size-cells = <0>;
22 compatible = "arm,cortex-a15";
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H A Dmeson8b.dtsi1 // SPDX-License-Identifier: GPL-2.0 OR MIT
7 #include <dt-bindings/clock/meson8-ddr-clkc.h>
8 #include <dt-bindings/clock/meson8b-clkc.h>
9 #include <dt-bindings/gpio/meson8b-gpio.h>
10 #include <dt-bindings/power/meson8-power.h>
11 #include <dt-bindings/reset/amlogic,meson8b-reset.h>
12 #include <dt-bindings/reset/amlogic,meson8b-clkc-reset.h>
17 #address-cells = <1>;
18 #size-cells = <0>;
22 compatible = "arm,cortex-a5";
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H A Dmeson8.dtsi1 // SPDX-License-Identifier: GPL-2.0 OR MIT
6 #include <dt-bindings/clock/meson8-ddr-clkc.h>
7 #include <dt-bindings/clock/meson8b-clkc.h>
8 #include <dt-bindings/gpio/meson8-gpio.h>
9 #include <dt-bindings/power/meson8-power.h>
10 #include <dt-bindings/reset/amlogic,meson8b-clkc-reset.h>
11 #include <dt-bindings/reset/amlogic,meson8b-reset.h>
19 #address-cells = <1>;
20 #size-cells = <0>;
24 compatible = "arm,cortex-a9";
[all …]
H A Dhighbank.dts1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright 2011-2012 Calxeda, Inc.
6 /dts-v1/;
14 #address-cells = <1>;
15 #size-cells = <1>;
18 #address-cells = <1>;
19 #size-cells = <0>;
22 compatible = "arm,cortex-a9";
25 next-level-cache = <&L2>;
27 clock-names = "cpu";
[all …]
/OK3568_Linux_fs/kernel/drivers/perf/hisilicon/
H A DKconfig1 # SPDX-License-Identifier: GPL-2.0-only
3 tristate "HiSilicon SoC PMU drivers"
7 Agent performance monitor and DDR Controller performance monitor.
/OK3568_Linux_fs/kernel/arch/arm/mach-imx/
H A Dmmdc.c1 // SPDX-License-Identifier: GPL-2.0-or-later
59 #define to_mmdc_pmu(p) container_of(p, struct mmdc_pmu, pmu)
75 { .compatible = "fsl,imx6q-mmdc", .data = (void *)&imx6q_data},
76 { .compatible = "fsl,imx6qp-mmdc", .data = (void *)&imx6qp_data},
85 PMU_EVENT_ATTR_STRING(total-cycles, mmdc_pmu_total_cycles, "event=0x00")
86 PMU_EVENT_ATTR_STRING(busy-cycles, mmdc_pmu_busy_cycles, "event=0x01")
87 PMU_EVENT_ATTR_STRING(read-accesses, mmdc_pmu_read_accesses, "event=0x02")
88 PMU_EVENT_ATTR_STRING(write-accesses, mmdc_pmu_write_accesses, "event=0x03")
89 PMU_EVENT_ATTR_STRING(read-bytes, mmdc_pmu_read_bytes, "event=0x04")
90 PMU_EVENT_ATTR_STRING(read-bytes.unit, mmdc_pmu_read_bytes_unit, "MB");
[all …]
/OK3568_Linux_fs/rkbin/doc/release/
H A DRK3588_EN.md6 | ---------- | :-------------------- | ------------ | --------- |
7 | 2023-07-13 | rk3588_bl31_v1.40.elf | dc1125f48 | important |
13 ------
18 | ---------- | :------------------------------------------- | ------------ | --------- |
19 | 2023-07-06 | rk3588_ddr_lp4_2112MHz_lp5_2736MHz_v1.12.bin | 52218f4949 | important |
28 …----- | --------- | ------------------------------------------------------------ | ---------------…
29 …fail issue that max freq between 1066-1600MHz | Panic in ddrbin when max DDR freq between 1066…
30 …DDR | When the first SPL firmware failed to load, reloading the second firmware would result in re…
32 ------
37 | ---------- | :-------------------- | ------------ | --------- |
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/OK3568_Linux_fs/kernel/drivers/devfreq/event/
H A Drockchip-dfi.c1 // SPDX-License-Identifier: GPL-2.0-only
4 * Author: Lin Huang <hl@rock-chips.com>
8 #include <linux/devfreq-event.h>
84 /* pmu grf */
105 * The dfi controller can monitor DDR load. It has an upper and lower threshold
107 * generated to indicate the DDR frequency should be changed.
138 regmap_write(info->regmap_grf, in rk3128_dfi_start_hardware_counter()
147 regmap_write(info->regmap_grf, in rk3128_dfi_stop_hardware_counter()
182 regmap_read(info->regmap_grf, RK3128_GRF_DFI_WRNUM, &dfi_wr); in rk3128_dfi_get_event()
183 regmap_read(info->regmap_grf, RK3128_GRF_DFI_RDNUM, &dfi_rd); in rk3128_dfi_get_event()
[all …]
/OK3568_Linux_fs/kernel/arch/arm/mach-rockchip/
H A Drv1106_sleep.S1 /* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
101 /* clear pmu reset hold */
156 /* ddr resume data */
161 /* ddr resume function (physical address) */
167 .word . - rockchip_slp_cpu_resume
H A Drv1106_pm.c1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
286 while (delay-- >= 0) { in pm_pll_wait_lock()
406 rkpm_bootdata_cpusp = RV1106_PMUSRAM_BASE + (SZ_8K - 8); in rv1106_config_bootdata()
540 pvtm_div = (pvtm_freq_khz + 16) / 32 - 1; in pvtm_32k_config()
579 /* disable ddr auto gt */ in ddr_sleep_config()
584 /* ddr low power request by pmu */ in ddr_sleep_config()
597 /* ddr io ret by pmu */ in ddr_sleep_config()
700 /* pmu count */ in pmu_sleep_config()
705 /* Pmu's clk has switched to 24M back When pmu FSM counts in pmu_sleep_config()
713 /* pmu reset hold */ in pmu_sleep_config()
[all …]
/OK3568_Linux_fs/u-boot/drivers/ram/rockchip/
H A Dsdram_rk3188.c5 * SPDX-License-Identifier: GPL-2.0
7 * Adapted from the very similar rk3288 ddr init.
13 #include <dt-structs.h>
43 struct rk3188_pmu *pmu; member
106 rk_clrsetreg(&cru->cru_softrst_con[5], in ddr_reset()
119 rk_clrsetreg(&cru->cru_softrst_con[5], in ddr_phy_ctl_reset()
131 clrbits_le32(&publ->acdllcr, ACDLLCR_DLLSRST); in phy_pctrl_reset()
133 clrbits_le32(&publ->datx8[i].dxdllcr, DXDLLCR_DLLSRST); in phy_pctrl_reset()
136 setbits_le32(&publ->acdllcr, ACDLLCR_DLLSRST); in phy_pctrl_reset()
138 setbits_le32(&publ->datx8[i].dxdllcr, DXDLLCR_DLLSRST); in phy_pctrl_reset()
[all …]
/OK3568_Linux_fs/docs/cn/RK3566_RK3568/
H A DRK3566_RK3568_Linux5.10_SDK_Note.md3 ---
9 ---
14 - Filtering Mali DDK does not support GBM_FORMAT_R8 error issue
15 - Fix the issue of the menu bar sliding and getting stuck on the top left side of the Xfce desktop
16 - Fix the issue of abnormal rotation function after sretting FlipFB to always
17 - Add support for Cheese H264 encoding and default to using H264 encoding
18 - Update rkaiq to release v5.0x1.3
19 - Update mpp/gstreamer rockchip
23 - Update lvgl
24 - Update weston to suppor some issues
[all …]
/OK3568_Linux_fs/docs/en/RK3566_RK3568/
H A DRK3566_RK3568_Linux5.10_SDK_Note.md3 ---
9 ---
14 - Filtering Mali DDK does not support GBM_FORMAT_R8 error issue
15 - Fix the issue of the menu bar sliding and getting stuck on the top left side of the Xfce desktop
16 - Fix the issue of abnormal rotation function after sretting FlipFB to always
17 - Add support for Cheese H264 encoding and default to using H264 encoding
18 - Update rkaiq to release v5.0x1.3
19 - Update mpp/gstreamer rockchip
23 - Update lvgl
24 - Update weston to suppor some issues
[all …]
/OK3568_Linux_fs/u-boot/arch/arm/include/asm/arch-rockchip/
H A Dsdram_rk3308.h1 /* SPDX-License-Identifier: GPL-2.0+ */
36 /* ddr standby */
77 struct rk3308_pmu *pmu; member
/OK3568_Linux_fs/u-boot/arch/arm/mach-rockchip/rk3066/
H A Dsdram_rk3066.c5 * SPDX-License-Identifier: GPL-2.0
7 * Adapted from the very similar rk3188 ddr init.
13 #include <dt-structs.h>
43 struct rk3188_pmu *pmu; member
106 rk_clrsetreg(&cru->cru_softrst_con[5], in ddr_reset()
119 rk_clrsetreg(&cru->cru_softrst_con[5], in ddr_phy_ctl_reset()
131 clrbits_le32(&publ->acdllcr, ACDLLCR_DLLSRST); in phy_pctrl_reset()
133 clrbits_le32(&publ->datx8[i].dxdllcr, DXDLLCR_DLLSRST); in phy_pctrl_reset()
136 setbits_le32(&publ->acdllcr, ACDLLCR_DLLSRST); in phy_pctrl_reset()
138 setbits_le32(&publ->datx8[i].dxdllcr, DXDLLCR_DLLSRST); in phy_pctrl_reset()
[all …]

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