1 /*
2 * (C) Copyright 2015 Google, Inc
3 * Copyright 2014 Rockchip Inc.
4 *
5 * SPDX-License-Identifier: GPL-2.0
6 *
7 * Adapted from the very similar rk3188 ddr init.
8 */
9
10 #include <common.h>
11 #include <clk.h>
12 #include <dm.h>
13 #include <dt-structs.h>
14 #include <errno.h>
15 #include <ram.h>
16 #include <regmap.h>
17 #include <syscon.h>
18 #include <asm/io.h>
19 #include <asm/arch/clock.h>
20 #include <asm/arch/cru_rk3066.h>
21 #include <asm/arch/ddr_rk3188.h>
22 #include <asm/arch/grf_rk3066.h>
23 #include <asm/arch/pmu_rk3188.h>
24 #include <asm/arch/sdram_rk3288.h>
25 #include <asm/arch/sdram.h>
26 #include <linux/err.h>
27
28 DECLARE_GLOBAL_DATA_PTR;
29
30 struct chan_info {
31 struct rk3288_ddr_pctl *pctl;
32 struct rk3288_ddr_publ *publ;
33 struct rk3188_msch *msch;
34 };
35
36 struct dram_info {
37 struct chan_info chan[1];
38 struct ram_info info;
39 struct clk ddr_clk;
40 struct rk3066_cru *cru;
41 struct rk3066_grf *grf;
42 struct rk3066_sgrf *sgrf;
43 struct rk3188_pmu *pmu;
44 };
45
46 struct rk3066_sdram_params {
47 #if CONFIG_IS_ENABLED(OF_PLATDATA)
48 struct dtd_rockchip_rk3066_dmc of_plat;
49 #endif
50 struct rk3288_sdram_channel ch[2];
51 struct rk3288_sdram_pctl_timing pctl_timing;
52 struct rk3288_sdram_phy_timing phy_timing;
53 struct rk3288_base_params base;
54 int num_channels;
55 struct regmap *map;
56 };
57
58 const int ddrconf_table[] = {
59 /*
60 * [5:4] row(13+n)
61 * [1:0] col(9+n), assume bw=2
62 * row col,bw
63 */
64 0,
65 (2 << DDRCONF_ROW_SHIFT) | 1 << DDRCONF_COL_SHIFT,
66 (1 << DDRCONF_ROW_SHIFT) | 1 << DDRCONF_COL_SHIFT,
67 (0 << DDRCONF_ROW_SHIFT) | 1 << DDRCONF_COL_SHIFT,
68 (2 << DDRCONF_ROW_SHIFT) | 2 << DDRCONF_COL_SHIFT,
69 (1 << DDRCONF_ROW_SHIFT) | 2 << DDRCONF_COL_SHIFT,
70 (0 << DDRCONF_ROW_SHIFT) | 2 << DDRCONF_COL_SHIFT,
71 (1 << DDRCONF_ROW_SHIFT) | 0 << DDRCONF_COL_SHIFT,
72 (0 << DDRCONF_ROW_SHIFT) | 0 << DDRCONF_COL_SHIFT,
73 0,
74 0,
75 0,
76 0,
77 0,
78 0,
79 0,
80 };
81
82 #define TEST_PATTEN 0x5aa5f00f
83 #define DQS_GATE_TRAINING_ERROR_RANK0 (1 << 4)
84 #define DQS_GATE_TRAINING_ERROR_RANK1 (2 << 4)
85
86 #ifdef CONFIG_TPL_BUILD
copy_to_reg(u32 * dest,const u32 * src,u32 n)87 static void copy_to_reg(u32 *dest, const u32 *src, u32 n)
88 {
89 int i;
90
91 for (i = 0; i < n / sizeof(u32); i++) {
92 writel(*src, dest);
93 src++;
94 dest++;
95 }
96 }
97
ddr_reset(struct rk3066_cru * cru,u32 ch,u32 ctl,u32 phy)98 static void ddr_reset(struct rk3066_cru *cru, u32 ch, u32 ctl, u32 phy)
99 {
100 u32 phy_ctl_srstn_shift = 13;
101 u32 ctl_psrstn_shift = 11;
102 u32 ctl_srstn_shift = 10;
103 u32 phy_psrstn_shift = 9;
104 u32 phy_srstn_shift = 8;
105
106 rk_clrsetreg(&cru->cru_softrst_con[5],
107 1 << phy_ctl_srstn_shift | 1 << ctl_psrstn_shift |
108 1 << ctl_srstn_shift | 1 << phy_psrstn_shift |
109 1 << phy_srstn_shift,
110 phy << phy_ctl_srstn_shift | ctl << ctl_psrstn_shift |
111 ctl << ctl_srstn_shift | phy << phy_psrstn_shift |
112 phy << phy_srstn_shift);
113 }
114
ddr_phy_ctl_reset(struct rk3066_cru * cru,u32 ch,u32 n)115 static void ddr_phy_ctl_reset(struct rk3066_cru *cru, u32 ch, u32 n)
116 {
117 u32 phy_ctl_srstn_shift = 13;
118
119 rk_clrsetreg(&cru->cru_softrst_con[5],
120 1 << phy_ctl_srstn_shift, n << phy_ctl_srstn_shift);
121 }
122
phy_pctrl_reset(struct rk3066_cru * cru,struct rk3288_ddr_publ * publ,int channel)123 static void phy_pctrl_reset(struct rk3066_cru *cru,
124 struct rk3288_ddr_publ *publ,
125 int channel)
126 {
127 int i;
128
129 ddr_reset(cru, channel, 1, 1);
130 udelay(1);
131 clrbits_le32(&publ->acdllcr, ACDLLCR_DLLSRST);
132 for (i = 0; i < 4; i++)
133 clrbits_le32(&publ->datx8[i].dxdllcr, DXDLLCR_DLLSRST);
134
135 udelay(10);
136 setbits_le32(&publ->acdllcr, ACDLLCR_DLLSRST);
137 for (i = 0; i < 4; i++)
138 setbits_le32(&publ->datx8[i].dxdllcr, DXDLLCR_DLLSRST);
139
140 udelay(10);
141 ddr_reset(cru, channel, 1, 0);
142 udelay(10);
143 ddr_reset(cru, channel, 0, 0);
144 udelay(10);
145 }
146
phy_dll_bypass_set(struct rk3288_ddr_publ * publ,u32 freq)147 static void phy_dll_bypass_set(struct rk3288_ddr_publ *publ,
148 u32 freq)
149 {
150 int i;
151
152 if (freq <= 250000000) {
153 if (freq <= 150000000)
154 clrbits_le32(&publ->dllgcr, SBIAS_BYPASS);
155 else
156 setbits_le32(&publ->dllgcr, SBIAS_BYPASS);
157 setbits_le32(&publ->acdllcr, ACDLLCR_DLLDIS);
158 for (i = 0; i < 4; i++)
159 setbits_le32(&publ->datx8[i].dxdllcr,
160 DXDLLCR_DLLDIS);
161
162 setbits_le32(&publ->pir, PIR_DLLBYP);
163 } else {
164 clrbits_le32(&publ->dllgcr, SBIAS_BYPASS);
165 clrbits_le32(&publ->acdllcr, ACDLLCR_DLLDIS);
166 for (i = 0; i < 4; i++) {
167 clrbits_le32(&publ->datx8[i].dxdllcr,
168 DXDLLCR_DLLDIS);
169 }
170
171 clrbits_le32(&publ->pir, PIR_DLLBYP);
172 }
173 }
174
dfi_cfg(struct rk3288_ddr_pctl * pctl,u32 dramtype)175 static void dfi_cfg(struct rk3288_ddr_pctl *pctl, u32 dramtype)
176 {
177 writel(DFI_INIT_START, &pctl->dfistcfg0);
178 writel(DFI_DRAM_CLK_SR_EN | DFI_DRAM_CLK_DPD_EN,
179 &pctl->dfistcfg1);
180 writel(DFI_PARITY_INTR_EN | DFI_PARITY_EN, &pctl->dfistcfg2);
181 writel(7 << TLP_RESP_TIME_SHIFT | LP_SR_EN | LP_PD_EN,
182 &pctl->dfilpcfg0);
183
184 writel(2 << TCTRL_DELAY_TIME_SHIFT, &pctl->dfitctrldelay);
185 writel(1 << TPHY_WRDATA_TIME_SHIFT, &pctl->dfitphywrdata);
186 writel(0xf << TPHY_RDLAT_TIME_SHIFT, &pctl->dfitphyrdlat);
187 writel(2 << TDRAM_CLK_DIS_TIME_SHIFT, &pctl->dfitdramclkdis);
188 writel(2 << TDRAM_CLK_EN_TIME_SHIFT, &pctl->dfitdramclken);
189 writel(1, &pctl->dfitphyupdtype0);
190
191 /* cs0 and cs1 write odt enable */
192 writel((RANK0_ODT_WRITE_SEL | RANK1_ODT_WRITE_SEL),
193 &pctl->dfiodtcfg);
194 /* odt write length */
195 writel(7 << ODT_LEN_BL8_W_SHIFT, &pctl->dfiodtcfg1);
196 /* phyupd and ctrlupd disabled */
197 writel(0, &pctl->dfiupdcfg);
198 }
199
ddr_set_ddr3_mode(struct rk3066_grf * grf,uint channel,bool ddr3_mode)200 static void ddr_set_ddr3_mode(struct rk3066_grf *grf, uint channel,
201 bool ddr3_mode)
202 {
203 uint mask, val;
204
205 mask = MSCH4_MAINDDR3_MASK << MSCH4_MAINDDR3_SHIFT;
206 val = ddr3_mode << MSCH4_MAINDDR3_SHIFT;
207 rk_clrsetreg(&grf->soc_con2, mask, val);
208 }
209
ddr_rank_2_row15en(struct rk3066_grf * grf,bool enable)210 static void ddr_rank_2_row15en(struct rk3066_grf *grf, bool enable)
211 {
212 uint mask, val;
213
214 mask = RANK_TO_ROW15_EN_MASK << RANK_TO_ROW15_EN_SHIFT;
215 val = enable << RANK_TO_ROW15_EN_SHIFT;
216 rk_clrsetreg(&grf->soc_con2, mask, val);
217 }
218
pctl_cfg(int channel,struct rk3288_ddr_pctl * pctl,struct rk3066_sdram_params * sdram_params,struct rk3066_grf * grf)219 static void pctl_cfg(int channel, struct rk3288_ddr_pctl *pctl,
220 struct rk3066_sdram_params *sdram_params,
221 struct rk3066_grf *grf)
222 {
223 copy_to_reg(&pctl->togcnt1u, &sdram_params->pctl_timing.togcnt1u,
224 sizeof(sdram_params->pctl_timing));
225 switch (sdram_params->base.dramtype) {
226 case DDR3:
227 if (sdram_params->phy_timing.mr[1] & DDR3_DLL_DISABLE) {
228 writel(sdram_params->pctl_timing.tcl - 3,
229 &pctl->dfitrddataen);
230 } else {
231 writel(sdram_params->pctl_timing.tcl - 2,
232 &pctl->dfitrddataen);
233 }
234 writel(sdram_params->pctl_timing.tcwl - 1,
235 &pctl->dfitphywrlat);
236 writel(0 << MDDR_LPDDR2_CLK_STOP_IDLE_SHIFT | DDR3_EN |
237 DDR2_DDR3_BL_8 | (6 - 4) << TFAW_SHIFT | PD_EXIT_SLOW |
238 1 << PD_TYPE_SHIFT | 0 << PD_IDLE_SHIFT,
239 &pctl->mcfg);
240 ddr_set_ddr3_mode(grf, channel, true);
241 break;
242 }
243
244 setbits_le32(&pctl->scfg, 1);
245 }
246
phy_cfg(const struct chan_info * chan,int channel,struct rk3066_sdram_params * sdram_params)247 static void phy_cfg(const struct chan_info *chan, int channel,
248 struct rk3066_sdram_params *sdram_params)
249 {
250 struct rk3288_ddr_publ *publ = chan->publ;
251 struct rk3188_msch *msch = chan->msch;
252 uint ddr_freq_mhz = sdram_params->base.ddr_freq / 1000000;
253 u32 dinit2;
254 int i;
255
256 dinit2 = DIV_ROUND_UP(ddr_freq_mhz * 200000, 1000);
257 /* DDR PHY Timing */
258 copy_to_reg(&publ->dtpr[0], &sdram_params->phy_timing.dtpr0,
259 sizeof(sdram_params->phy_timing));
260 writel(sdram_params->base.noc_timing, &msch->ddrtiming);
261 writel(0x3f, &msch->readlatency);
262 writel(DIV_ROUND_UP(ddr_freq_mhz * 5120, 1000) << PRT_DLLLOCK_SHIFT |
263 DIV_ROUND_UP(ddr_freq_mhz * 50, 1000) << PRT_DLLSRST_SHIFT |
264 8 << PRT_ITMSRST_SHIFT, &publ->ptr[0]);
265 writel(DIV_ROUND_UP(ddr_freq_mhz * 500000, 1000) << PRT_DINIT0_SHIFT |
266 DIV_ROUND_UP(ddr_freq_mhz * 400, 1000) << PRT_DINIT1_SHIFT,
267 &publ->ptr[1]);
268 writel(min(dinit2, 0x1ffffU) << PRT_DINIT2_SHIFT |
269 DIV_ROUND_UP(ddr_freq_mhz * 1000, 1000) << PRT_DINIT3_SHIFT,
270 &publ->ptr[2]);
271
272 switch (sdram_params->base.dramtype) {
273 case DDR3:
274 clrbits_le32(&publ->pgcr, 0x1f);
275 clrsetbits_le32(&publ->dcr, DDRMD_MASK << DDRMD_SHIFT,
276 DDRMD_DDR3 << DDRMD_SHIFT);
277 break;
278 }
279 if (sdram_params->base.odt) {
280 /*dynamic RTT enable */
281 for (i = 0; i < 4; i++)
282 setbits_le32(&publ->datx8[i].dxgcr, DQSRTT | DQRTT);
283 } else {
284 /*dynamic RTT disable */
285 for (i = 0; i < 4; i++)
286 clrbits_le32(&publ->datx8[i].dxgcr, DQSRTT | DQRTT);
287 }
288 }
289
phy_init(struct rk3288_ddr_publ * publ)290 static void phy_init(struct rk3288_ddr_publ *publ)
291 {
292 setbits_le32(&publ->pir, PIR_INIT | PIR_DLLSRST
293 | PIR_DLLLOCK | PIR_ZCAL | PIR_ITMSRST | PIR_CLRSR);
294 udelay(1);
295 while ((readl(&publ->pgsr) &
296 (PGSR_IDONE | PGSR_DLDONE | PGSR_ZCDONE)) !=
297 (PGSR_IDONE | PGSR_DLDONE | PGSR_ZCDONE))
298 ;
299 }
300
send_command(struct rk3288_ddr_pctl * pctl,u32 rank,u32 cmd,u32 arg)301 static void send_command(struct rk3288_ddr_pctl *pctl, u32 rank,
302 u32 cmd, u32 arg)
303 {
304 writel((START_CMD | (rank << 20) | arg | cmd), &pctl->mcmd);
305 udelay(1);
306 while (readl(&pctl->mcmd) & START_CMD)
307 ;
308 }
309
send_command_op(struct rk3288_ddr_pctl * pctl,u32 rank,u32 cmd,u32 ma,u32 op)310 static inline void send_command_op(struct rk3288_ddr_pctl *pctl,
311 u32 rank, u32 cmd, u32 ma, u32 op)
312 {
313 send_command(pctl, rank, cmd, (ma & LPDDR2_MA_MASK) << LPDDR2_MA_SHIFT |
314 (op & LPDDR2_OP_MASK) << LPDDR2_OP_SHIFT);
315 }
316
memory_init(struct rk3288_ddr_publ * publ,u32 dramtype)317 static void memory_init(struct rk3288_ddr_publ *publ,
318 u32 dramtype)
319 {
320 setbits_le32(&publ->pir,
321 (PIR_INIT | PIR_DRAMINIT | PIR_LOCKBYP
322 | PIR_ZCALBYP | PIR_CLRSR | PIR_ICPC
323 | (dramtype == DDR3 ? PIR_DRAMRST : 0)));
324 udelay(1);
325 while ((readl(&publ->pgsr) & (PGSR_IDONE | PGSR_DLDONE))
326 != (PGSR_IDONE | PGSR_DLDONE))
327 ;
328 }
329
move_to_config_state(struct rk3288_ddr_publ * publ,struct rk3288_ddr_pctl * pctl)330 static void move_to_config_state(struct rk3288_ddr_publ *publ,
331 struct rk3288_ddr_pctl *pctl)
332 {
333 unsigned int state;
334
335 while (1) {
336 state = readl(&pctl->stat) & PCTL_STAT_MSK;
337
338 switch (state) {
339 case LOW_POWER:
340 writel(WAKEUP_STATE, &pctl->sctl);
341 while ((readl(&pctl->stat) & PCTL_STAT_MSK)
342 != ACCESS)
343 ;
344 /* wait DLL lock */
345 while ((readl(&publ->pgsr) & PGSR_DLDONE)
346 != PGSR_DLDONE)
347 ;
348 /*
349 * if at low power state,need wakeup first,
350 * and then enter the config, so
351 * fallthrough
352 */
353 case ACCESS:
354 /* fallthrough */
355 case INIT_MEM:
356 writel(CFG_STATE, &pctl->sctl);
357 while ((readl(&pctl->stat) & PCTL_STAT_MSK) != CONFIG)
358 ;
359 break;
360 case CONFIG:
361 return;
362 default:
363 break;
364 }
365 }
366 }
367
set_bandwidth_ratio(const struct chan_info * chan,int channel,u32 n,struct rk3066_grf * grf)368 static void set_bandwidth_ratio(const struct chan_info *chan, int channel,
369 u32 n, struct rk3066_grf *grf)
370 {
371 struct rk3288_ddr_pctl *pctl = chan->pctl;
372 struct rk3288_ddr_publ *publ = chan->publ;
373 struct rk3188_msch *msch = chan->msch;
374
375 if (n == 1) {
376 setbits_le32(&pctl->ppcfg, 1);
377 setbits_le32(&msch->ddrtiming, 1 << 31);
378 /* Data Byte disable*/
379 clrbits_le32(&publ->datx8[2].dxgcr, 1);
380 clrbits_le32(&publ->datx8[3].dxgcr, 1);
381 /* disable DLL */
382 setbits_le32(&publ->datx8[2].dxdllcr, DXDLLCR_DLLDIS);
383 setbits_le32(&publ->datx8[3].dxdllcr, DXDLLCR_DLLDIS);
384 } else {
385 clrbits_le32(&pctl->ppcfg, 1);
386 clrbits_le32(&msch->ddrtiming, 1 << 31);
387 /* Data Byte enable*/
388 setbits_le32(&publ->datx8[2].dxgcr, 1);
389 setbits_le32(&publ->datx8[3].dxgcr, 1);
390
391 /* enable DLL */
392 clrbits_le32(&publ->datx8[2].dxdllcr, DXDLLCR_DLLDIS);
393 clrbits_le32(&publ->datx8[3].dxdllcr, DXDLLCR_DLLDIS);
394 /* reset DLL */
395 clrbits_le32(&publ->datx8[2].dxdllcr, DXDLLCR_DLLSRST);
396 clrbits_le32(&publ->datx8[3].dxdllcr, DXDLLCR_DLLSRST);
397 udelay(10);
398 setbits_le32(&publ->datx8[2].dxdllcr, DXDLLCR_DLLSRST);
399 setbits_le32(&publ->datx8[3].dxdllcr, DXDLLCR_DLLSRST);
400 }
401 setbits_le32(&pctl->dfistcfg0, 1 << 2);
402 }
403
data_training(const struct chan_info * chan,int channel,struct rk3066_sdram_params * sdram_params)404 static int data_training(const struct chan_info *chan, int channel,
405 struct rk3066_sdram_params *sdram_params)
406 {
407 unsigned int j;
408 int ret = 0;
409 u32 rank;
410 int i;
411 u32 step[2] = { PIR_QSTRN, PIR_RVTRN };
412 struct rk3288_ddr_publ *publ = chan->publ;
413 struct rk3288_ddr_pctl *pctl = chan->pctl;
414
415 /* disable auto refresh */
416 writel(0, &pctl->trefi);
417
418 if (sdram_params->base.dramtype != LPDDR3)
419 setbits_le32(&publ->pgcr, 1 << PGCR_DQSCFG_SHIFT);
420 rank = sdram_params->ch[channel].rank | 1;
421 for (j = 0; j < ARRAY_SIZE(step); j++) {
422 /*
423 * trigger QSTRN and RVTRN
424 * clear DTDONE status
425 */
426 setbits_le32(&publ->pir, PIR_CLRSR);
427
428 /* trigger DTT */
429 setbits_le32(&publ->pir,
430 PIR_INIT | step[j] | PIR_LOCKBYP | PIR_ZCALBYP |
431 PIR_CLRSR);
432 udelay(1);
433 /* wait echo byte DTDONE */
434 while ((readl(&publ->datx8[0].dxgsr[0]) & rank)
435 != rank)
436 ;
437 while ((readl(&publ->datx8[1].dxgsr[0]) & rank)
438 != rank)
439 ;
440 if (!(readl(&pctl->ppcfg) & 1)) {
441 while ((readl(&publ->datx8[2].dxgsr[0])
442 & rank) != rank)
443 ;
444 while ((readl(&publ->datx8[3].dxgsr[0])
445 & rank) != rank)
446 ;
447 }
448 if (readl(&publ->pgsr) &
449 (PGSR_DTERR | PGSR_RVERR | PGSR_RVEIRR)) {
450 ret = -1;
451 break;
452 }
453 }
454 /* send some auto refresh to complement the lost while DTT */
455 for (i = 0; i < (rank > 1 ? 8 : 4); i++)
456 send_command(pctl, rank, REF_CMD, 0);
457
458 if (sdram_params->base.dramtype != LPDDR3)
459 clrbits_le32(&publ->pgcr, 1 << PGCR_DQSCFG_SHIFT);
460
461 /* resume auto refresh */
462 writel(sdram_params->pctl_timing.trefi, &pctl->trefi);
463
464 return ret;
465 }
466
move_to_access_state(const struct chan_info * chan)467 static void move_to_access_state(const struct chan_info *chan)
468 {
469 struct rk3288_ddr_publ *publ = chan->publ;
470 struct rk3288_ddr_pctl *pctl = chan->pctl;
471 unsigned int state;
472
473 while (1) {
474 state = readl(&pctl->stat) & PCTL_STAT_MSK;
475
476 switch (state) {
477 case LOW_POWER:
478 if (((readl(&pctl->stat) >> LP_TRIG_SHIFT) &
479 LP_TRIG_MASK) == 1)
480 return;
481
482 writel(WAKEUP_STATE, &pctl->sctl);
483 while ((readl(&pctl->stat) & PCTL_STAT_MSK) != ACCESS)
484 ;
485 /* wait DLL lock */
486 while ((readl(&publ->pgsr) & PGSR_DLDONE)
487 != PGSR_DLDONE)
488 ;
489 break;
490 case INIT_MEM:
491 writel(CFG_STATE, &pctl->sctl);
492 while ((readl(&pctl->stat) & PCTL_STAT_MSK) != CONFIG)
493 ;
494 /* fallthrough */
495 case CONFIG:
496 writel(GO_STATE, &pctl->sctl);
497 while ((readl(&pctl->stat) & PCTL_STAT_MSK) == CONFIG)
498 ;
499 break;
500 case ACCESS:
501 return;
502 default:
503 break;
504 }
505 }
506 }
507
dram_cfg_rbc(const struct chan_info * chan,u32 chnum,struct rk3066_sdram_params * sdram_params)508 static void dram_cfg_rbc(const struct chan_info *chan, u32 chnum,
509 struct rk3066_sdram_params *sdram_params)
510 {
511 struct rk3288_ddr_publ *publ = chan->publ;
512
513 if (sdram_params->ch[chnum].bk == 3)
514 clrsetbits_le32(&publ->dcr, PDQ_MASK << PDQ_SHIFT,
515 1 << PDQ_SHIFT);
516 else
517 clrbits_le32(&publ->dcr, PDQ_MASK << PDQ_SHIFT);
518
519 writel(sdram_params->base.ddrconfig, &chan->msch->ddrconf);
520 }
521
dram_all_config(const struct dram_info * dram,struct rk3066_sdram_params * sdram_params)522 static void dram_all_config(const struct dram_info *dram,
523 struct rk3066_sdram_params *sdram_params)
524 {
525 unsigned int chan;
526 u32 sys_reg = 0;
527
528 sys_reg |= sdram_params->base.dramtype << SYS_REG_DDRTYPE_SHIFT;
529 sys_reg |= (sdram_params->num_channels - 1) << SYS_REG_NUM_CH_SHIFT;
530 for (chan = 0; chan < sdram_params->num_channels; chan++) {
531 const struct rk3288_sdram_channel *info =
532 &sdram_params->ch[chan];
533
534 sys_reg |= info->row_3_4 << SYS_REG_ROW_3_4_SHIFT(chan);
535 sys_reg |= 1 << SYS_REG_CHINFO_SHIFT(chan);
536 sys_reg |= (info->rank - 1) << SYS_REG_RANK_SHIFT(chan);
537 sys_reg |= (info->col - 9) << SYS_REG_COL_SHIFT(chan);
538 sys_reg |= info->bk == 3 ? 0 : 1 << SYS_REG_BK_SHIFT(chan);
539 sys_reg |= (info->cs0_row - 13) << SYS_REG_CS0_ROW_SHIFT(chan);
540 sys_reg |= (info->cs1_row - 13) << SYS_REG_CS1_ROW_SHIFT(chan);
541 sys_reg |= (2 >> info->bw) << SYS_REG_BW_SHIFT(chan);
542 sys_reg |= (2 >> info->dbw) << SYS_REG_DBW_SHIFT(chan);
543
544 dram_cfg_rbc(&dram->chan[chan], chan, sdram_params);
545 }
546 if (sdram_params->ch[0].rank == 2)
547 ddr_rank_2_row15en(dram->grf, 0);
548 else
549 ddr_rank_2_row15en(dram->grf, 1);
550
551 writel(sys_reg, &dram->pmu->sys_reg[2]);
552 }
553
sdram_rank_bw_detect(struct dram_info * dram,int channel,struct rk3066_sdram_params * sdram_params)554 static int sdram_rank_bw_detect(struct dram_info *dram, int channel,
555 struct rk3066_sdram_params *sdram_params)
556 {
557 int reg;
558 int need_trainig = 0;
559 const struct chan_info *chan = &dram->chan[channel];
560 struct rk3288_ddr_publ *publ = chan->publ;
561
562 ddr_rank_2_row15en(dram->grf, 0);
563
564 if (data_training(chan, channel, sdram_params) < 0) {
565 debug("first data training fail!\n");
566 reg = readl(&publ->datx8[0].dxgsr[0]);
567 /* Check the result for rank 0 */
568 if ((channel == 0) && (reg & DQS_GATE_TRAINING_ERROR_RANK0)) {
569 debug("data training fail!\n");
570 return -EIO;
571 }
572
573 /* Check the result for rank 1 */
574 if (reg & DQS_GATE_TRAINING_ERROR_RANK1) {
575 sdram_params->ch[channel].rank = 1;
576 clrsetbits_le32(&publ->pgcr, 0xF << 18,
577 sdram_params->ch[channel].rank << 18);
578 need_trainig = 1;
579 }
580 reg = readl(&publ->datx8[2].dxgsr[0]);
581 if (reg & (1 << 4)) {
582 sdram_params->ch[channel].bw = 1;
583 set_bandwidth_ratio(chan, channel,
584 sdram_params->ch[channel].bw,
585 dram->grf);
586 need_trainig = 1;
587 }
588 }
589 /* Assume the Die bit width are the same with the chip bit width */
590 sdram_params->ch[channel].dbw = sdram_params->ch[channel].bw;
591
592 if (need_trainig &&
593 (data_training(chan, channel, sdram_params) < 0)) {
594 if (sdram_params->base.dramtype == LPDDR3) {
595 ddr_phy_ctl_reset(dram->cru, channel, 1);
596 udelay(10);
597 ddr_phy_ctl_reset(dram->cru, channel, 0);
598 udelay(10);
599 }
600 debug("2nd data training failed!");
601 return -EIO;
602 }
603
604 return 0;
605 }
606
607 /*
608 * Detect ram columns and rows.
609 * @dram: dram info struct
610 * @channel: channel number to handle
611 * @sdram_params: sdram parameters, function will fill in col and row values
612 *
613 * Returns 0 or negative on error.
614 */
sdram_col_row_detect(struct dram_info * dram,int channel,struct rk3066_sdram_params * sdram_params)615 static int sdram_col_row_detect(struct dram_info *dram, int channel,
616 struct rk3066_sdram_params *sdram_params)
617 {
618 int row, col;
619 unsigned int addr;
620 const struct chan_info *chan = &dram->chan[channel];
621 struct rk3288_ddr_pctl *pctl = chan->pctl;
622 struct rk3288_ddr_publ *publ = chan->publ;
623 int ret = 0;
624
625 /* Detect col */
626 for (col = 11; col >= 9; col--) {
627 writel(0, CONFIG_SYS_SDRAM_BASE);
628 addr = CONFIG_SYS_SDRAM_BASE +
629 (1 << (col + sdram_params->ch[channel].bw - 1));
630 writel(TEST_PATTEN, addr);
631 if ((readl(addr) == TEST_PATTEN) &&
632 (readl(CONFIG_SYS_SDRAM_BASE) == 0))
633 break;
634 }
635 if (col == 8) {
636 debug("Col detect error\n");
637 ret = -EINVAL;
638 goto out;
639 } else {
640 sdram_params->ch[channel].col = col;
641 }
642
643 ddr_rank_2_row15en(dram->grf, 1);
644 move_to_config_state(publ, pctl);
645 writel(1, &chan->msch->ddrconf);
646 move_to_access_state(chan);
647 /* Detect row, max 15,min13 in rk3066*/
648 for (row = 16; row >= 13; row--) {
649 writel(0, CONFIG_SYS_SDRAM_BASE);
650 addr = CONFIG_SYS_SDRAM_BASE + (1 << (row + 15 - 1));
651 writel(TEST_PATTEN, addr);
652 if ((readl(addr) == TEST_PATTEN) &&
653 (readl(CONFIG_SYS_SDRAM_BASE) == 0))
654 break;
655 }
656 if (row == 12) {
657 debug("Row detect error\n");
658 ret = -EINVAL;
659 } else {
660 sdram_params->ch[channel].cs1_row = row;
661 sdram_params->ch[channel].row_3_4 = 0;
662 debug("chn %d col %d, row %d\n", channel, col, row);
663 sdram_params->ch[channel].cs0_row = row;
664 }
665
666 out:
667 return ret;
668 }
669
sdram_get_niu_config(struct rk3066_sdram_params * sdram_params)670 static int sdram_get_niu_config(struct rk3066_sdram_params *sdram_params)
671 {
672 int i, tmp, size, ret = 0;
673
674 tmp = sdram_params->ch[0].col - 9;
675 tmp -= (sdram_params->ch[0].bw == 2) ? 0 : 1;
676 tmp |= ((sdram_params->ch[0].cs0_row - 13) << 4);
677 size = sizeof(ddrconf_table)/sizeof(ddrconf_table[0]);
678 for (i = 0; i < size; i++)
679 if (tmp == ddrconf_table[i])
680 break;
681 if (i >= size) {
682 debug("niu config not found\n");
683 ret = -EINVAL;
684 } else {
685 debug("niu config %d\n", i);
686 sdram_params->base.ddrconfig = i;
687 }
688
689 return ret;
690 }
691
sdram_init(struct dram_info * dram,struct rk3066_sdram_params * sdram_params)692 static int sdram_init(struct dram_info *dram,
693 struct rk3066_sdram_params *sdram_params)
694 {
695 int channel;
696 int zqcr;
697 int ret;
698
699 if ((sdram_params->base.dramtype == DDR3 &&
700 sdram_params->base.ddr_freq > 800000000)) {
701 debug("SDRAM frequency is too high!");
702 return -E2BIG;
703 }
704
705 ret = clk_set_rate(&dram->ddr_clk, sdram_params->base.ddr_freq);
706 if (ret) {
707 debug("Could not set DDR clock\n");
708 return ret;
709 }
710
711 for (channel = 0; channel < 1; channel++) {
712 const struct chan_info *chan = &dram->chan[channel];
713 struct rk3288_ddr_pctl *pctl = chan->pctl;
714 struct rk3288_ddr_publ *publ = chan->publ;
715
716 phy_pctrl_reset(dram->cru, publ, channel);
717 phy_dll_bypass_set(publ, sdram_params->base.ddr_freq);
718
719 dfi_cfg(pctl, sdram_params->base.dramtype);
720
721 pctl_cfg(channel, pctl, sdram_params, dram->grf);
722
723 phy_cfg(chan, channel, sdram_params);
724
725 phy_init(publ);
726
727 writel(POWER_UP_START, &pctl->powctl);
728 while (!(readl(&pctl->powstat) & POWER_UP_DONE))
729 ;
730
731 memory_init(publ, sdram_params->base.dramtype);
732 move_to_config_state(publ, pctl);
733
734 /* Using 32bit bus width for detect */
735 sdram_params->ch[channel].bw = 2;
736 set_bandwidth_ratio(chan, channel,
737 sdram_params->ch[channel].bw, dram->grf);
738 /*
739 * set cs, using n=3 for detect
740 * CS0, n=1
741 * CS1, n=2
742 * CS0 & CS1, n = 3
743 */
744 sdram_params->ch[channel].rank = 2,
745 clrsetbits_le32(&publ->pgcr, 0xF << 18,
746 (sdram_params->ch[channel].rank | 1) << 18);
747
748 /* DS=40ohm,ODT=155ohm */
749 zqcr = 1 << ZDEN_SHIFT | 2 << PU_ONDIE_SHIFT |
750 2 << PD_ONDIE_SHIFT | 0x19 << PU_OUTPUT_SHIFT |
751 0x19 << PD_OUTPUT_SHIFT;
752 writel(zqcr, &publ->zq1cr[0]);
753 writel(zqcr, &publ->zq0cr[0]);
754
755 /* Detect the rank and bit-width with data-training */
756 writel(1, &chan->msch->ddrconf);
757 sdram_rank_bw_detect(dram, channel, sdram_params);
758
759 if (sdram_params->base.dramtype == LPDDR3) {
760 u32 i;
761 writel(0, &pctl->mrrcfg0);
762 for (i = 0; i < 17; i++)
763 send_command_op(pctl, 1, MRR_CMD, i, 0);
764 }
765 writel(4, &chan->msch->ddrconf);
766 move_to_access_state(chan);
767 /* DDR3 and LPDDR3 are always 8 bank, no need detect */
768 sdram_params->ch[channel].bk = 3;
769 /* Detect Col and Row number*/
770 ret = sdram_col_row_detect(dram, channel, sdram_params);
771 if (ret)
772 goto error;
773 }
774 /* Find NIU DDR configuration */
775 ret = sdram_get_niu_config(sdram_params);
776 if (ret)
777 goto error;
778
779 dram_all_config(dram, sdram_params);
780 debug("%s done\n", __func__);
781
782 return 0;
783 error:
784 debug("DRAM init failed!\n");
785 hang();
786 }
787 #endif /* CONFIG_TPL_BUILD */
788
789 #ifdef CONFIG_TPL_BUILD
setup_sdram(struct udevice * dev)790 static int setup_sdram(struct udevice *dev)
791 {
792 struct dram_info *priv = dev_get_priv(dev);
793 struct rk3066_sdram_params *params = dev_get_platdata(dev);
794
795 return sdram_init(priv, params);
796 }
797
rk3066_dmc_ofdata_to_platdata(struct udevice * dev)798 static int rk3066_dmc_ofdata_to_platdata(struct udevice *dev)
799 {
800 #if !CONFIG_IS_ENABLED(OF_PLATDATA)
801 struct rk3066_sdram_params *params = dev_get_platdata(dev);
802 const void *blob = gd->fdt_blob;
803 int node = dev_of_offset(dev);
804 int ret;
805
806 /* rk3066 supports only one-channel */
807 params->num_channels = 1;
808 ret = fdtdec_get_int_array(blob, node, "rockchip,pctl-timing",
809 (u32 *)¶ms->pctl_timing,
810 sizeof(params->pctl_timing) / sizeof(u32));
811 if (ret) {
812 debug("%s: Cannot read rockchip,pctl-timing\n", __func__);
813 return -EINVAL;
814 }
815 ret = fdtdec_get_int_array(blob, node, "rockchip,phy-timing",
816 (u32 *)¶ms->phy_timing,
817 sizeof(params->phy_timing) / sizeof(u32));
818 if (ret) {
819 debug("%s: Cannot read rockchip,phy-timing\n", __func__);
820 return -EINVAL;
821 }
822 ret = fdtdec_get_int_array(blob, node, "rockchip,sdram-params",
823 (u32 *)¶ms->base,
824 sizeof(params->base) / sizeof(u32));
825 if (ret) {
826 debug("%s: Cannot read rockchip,sdram-params\n", __func__);
827 return -EINVAL;
828 }
829 ret = regmap_init_mem(dev, ¶ms->map);
830 if (ret)
831 return ret;
832 #endif
833
834 return 0;
835 }
836 #endif /* CONFIG_TPL_BUILD */
837
838 #if CONFIG_IS_ENABLED(OF_PLATDATA)
conv_of_platdata(struct udevice * dev)839 static int conv_of_platdata(struct udevice *dev)
840 {
841 struct rk3066_sdram_params *plat = dev_get_platdata(dev);
842 struct dtd_rockchip_rk3066_dmc *of_plat = &plat->of_plat;
843 int ret;
844
845 memcpy(&plat->pctl_timing, of_plat->rockchip_pctl_timing,
846 sizeof(plat->pctl_timing));
847 memcpy(&plat->phy_timing, of_plat->rockchip_phy_timing,
848 sizeof(plat->phy_timing));
849 memcpy(&plat->base, of_plat->rockchip_sdram_params, sizeof(plat->base));
850 /* rk3066 supports dual-channel, set default channel num to 2 */
851 plat->num_channels = 1;
852 ret = regmap_init_mem_platdata(dev, of_plat->reg,
853 ARRAY_SIZE(of_plat->reg) / 2,
854 &plat->map);
855 if (ret)
856 return ret;
857 return 0;
858 }
859 #endif
860
rk3066_dmc_probe(struct udevice * dev)861 static int rk3066_dmc_probe(struct udevice *dev)
862 {
863 #ifdef CONFIG_TPL_BUILD
864 struct rk3066_sdram_params *plat = dev_get_platdata(dev);
865 #endif
866 struct dram_info *priv = dev_get_priv(dev);
867 struct regmap *map;
868 int ret;
869 struct udevice *dev_clk;
870
871 #if CONFIG_IS_ENABLED(OF_PLATDATA)
872 ret = conv_of_platdata(dev);
873 if (ret)
874 return ret;
875 #endif
876 map = syscon_get_regmap_by_driver_data(ROCKCHIP_SYSCON_NOC);
877 if (IS_ERR(map))
878 return PTR_ERR(map);
879 priv->chan[0].msch = regmap_get_range(map, 0);
880
881 priv->grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF);
882 priv->pmu = syscon_get_first_range(ROCKCHIP_SYSCON_PMU);
883
884 #ifdef CONFIG_TPL_BUILD
885 priv->chan[0].pctl = regmap_get_range(plat->map, 0);
886 priv->chan[0].publ = regmap_get_range(plat->map, 1);
887 #endif
888 ret = rockchip_get_clk(&dev_clk);
889 if (ret)
890 return ret;
891 priv->ddr_clk.id = CLK_DDR;
892
893 ret = clk_request(dev_clk, &priv->ddr_clk);
894 if (ret)
895 return ret;
896
897 priv->cru = rockchip_get_cru();
898 if (IS_ERR(priv->cru))
899 return PTR_ERR(priv->cru);
900 #ifdef CONFIG_TPL_BUILD
901 ret = setup_sdram(dev);
902 if (ret)
903 return ret;
904 #endif
905 priv->info.base = CONFIG_SYS_SDRAM_BASE;
906 priv->info.size = rockchip_sdram_size(
907 (phys_addr_t)&priv->pmu->sys_reg[2]);
908
909 return 0;
910 }
911
rk3066_dmc_get_info(struct udevice * dev,struct ram_info * info)912 static int rk3066_dmc_get_info(struct udevice *dev, struct ram_info *info)
913 {
914 struct dram_info *priv = dev_get_priv(dev);
915
916 *info = priv->info;
917
918 return 0;
919 }
920
921 static struct ram_ops rk3066_dmc_ops = {
922 .get_info = rk3066_dmc_get_info,
923 };
924
925 static const struct udevice_id rk3066_dmc_ids[] = {
926 { .compatible = "rockchip,rk3066-dmc" },
927 { }
928 };
929
930 U_BOOT_DRIVER(dmc_rk3066) = {
931 .name = "rockchip_rk3066_dmc",
932 .id = UCLASS_RAM,
933 .of_match = rk3066_dmc_ids,
934 .ops = &rk3066_dmc_ops,
935 #ifdef CONFIG_TPL_BUILD
936 .ofdata_to_platdata = rk3066_dmc_ofdata_to_platdata,
937 #endif
938 .probe = rk3066_dmc_probe,
939 .priv_auto_alloc_size = sizeof(struct dram_info),
940 #ifdef CONFIG_TPL_BUILD
941 .platdata_auto_alloc_size = sizeof(struct rk3066_sdram_params),
942 #endif
943 };
944