Lines Matching +full:ddr +full:- +full:pmu
5 * SPDX-License-Identifier: GPL-2.0
7 * Adapted from the very similar rk3288 ddr init.
13 #include <dt-structs.h>
43 struct rk3188_pmu *pmu; member
106 rk_clrsetreg(&cru->cru_softrst_con[5], in ddr_reset()
119 rk_clrsetreg(&cru->cru_softrst_con[5], in ddr_phy_ctl_reset()
131 clrbits_le32(&publ->acdllcr, ACDLLCR_DLLSRST); in phy_pctrl_reset()
133 clrbits_le32(&publ->datx8[i].dxdllcr, DXDLLCR_DLLSRST); in phy_pctrl_reset()
136 setbits_le32(&publ->acdllcr, ACDLLCR_DLLSRST); in phy_pctrl_reset()
138 setbits_le32(&publ->datx8[i].dxdllcr, DXDLLCR_DLLSRST); in phy_pctrl_reset()
154 clrbits_le32(&publ->dllgcr, SBIAS_BYPASS); in phy_dll_bypass_set()
156 setbits_le32(&publ->dllgcr, SBIAS_BYPASS); in phy_dll_bypass_set()
157 setbits_le32(&publ->acdllcr, ACDLLCR_DLLDIS); in phy_dll_bypass_set()
159 setbits_le32(&publ->datx8[i].dxdllcr, in phy_dll_bypass_set()
162 setbits_le32(&publ->pir, PIR_DLLBYP); in phy_dll_bypass_set()
164 clrbits_le32(&publ->dllgcr, SBIAS_BYPASS); in phy_dll_bypass_set()
165 clrbits_le32(&publ->acdllcr, ACDLLCR_DLLDIS); in phy_dll_bypass_set()
167 clrbits_le32(&publ->datx8[i].dxdllcr, in phy_dll_bypass_set()
171 clrbits_le32(&publ->pir, PIR_DLLBYP); in phy_dll_bypass_set()
177 writel(DFI_INIT_START, &pctl->dfistcfg0); in dfi_cfg()
179 &pctl->dfistcfg1); in dfi_cfg()
180 writel(DFI_PARITY_INTR_EN | DFI_PARITY_EN, &pctl->dfistcfg2); in dfi_cfg()
182 &pctl->dfilpcfg0); in dfi_cfg()
184 writel(2 << TCTRL_DELAY_TIME_SHIFT, &pctl->dfitctrldelay); in dfi_cfg()
185 writel(1 << TPHY_WRDATA_TIME_SHIFT, &pctl->dfitphywrdata); in dfi_cfg()
186 writel(0xf << TPHY_RDLAT_TIME_SHIFT, &pctl->dfitphyrdlat); in dfi_cfg()
187 writel(2 << TDRAM_CLK_DIS_TIME_SHIFT, &pctl->dfitdramclkdis); in dfi_cfg()
188 writel(2 << TDRAM_CLK_EN_TIME_SHIFT, &pctl->dfitdramclken); in dfi_cfg()
189 writel(1, &pctl->dfitphyupdtype0); in dfi_cfg()
193 &pctl->dfiodtcfg); in dfi_cfg()
195 writel(7 << ODT_LEN_BL8_W_SHIFT, &pctl->dfiodtcfg1); in dfi_cfg()
197 writel(0, &pctl->dfiupdcfg); in dfi_cfg()
207 rk_clrsetreg(&grf->ddrc_con0, 1 << DDR_16BIT_EN_SHIFT, val); in ddr_set_enable()
217 rk_clrsetreg(&grf->soc_con2, mask, val); in ddr_set_ddr3_mode()
226 rk_clrsetreg(&grf->soc_con2, mask, val); in ddr_rank_2_row15en()
233 copy_to_reg(&pctl->togcnt1u, &sdram_params->pctl_timing.togcnt1u, in pctl_cfg()
234 sizeof(sdram_params->pctl_timing)); in pctl_cfg()
235 switch (sdram_params->base.dramtype) { in pctl_cfg()
237 if (sdram_params->phy_timing.mr[1] & DDR3_DLL_DISABLE) { in pctl_cfg()
238 writel(sdram_params->pctl_timing.tcl - 3, in pctl_cfg()
239 &pctl->dfitrddataen); in pctl_cfg()
241 writel(sdram_params->pctl_timing.tcl - 2, in pctl_cfg()
242 &pctl->dfitrddataen); in pctl_cfg()
244 writel(sdram_params->pctl_timing.tcwl - 1, in pctl_cfg()
245 &pctl->dfitphywrlat); in pctl_cfg()
247 DDR2_DDR3_BL_8 | (6 - 4) << TFAW_SHIFT | PD_EXIT_SLOW | in pctl_cfg()
249 &pctl->mcfg); in pctl_cfg()
255 setbits_le32(&pctl->scfg, 1); in pctl_cfg()
261 struct rk3288_ddr_publ *publ = chan->publ; in phy_cfg()
262 struct rk3188_msch *msch = chan->msch; in phy_cfg()
263 uint ddr_freq_mhz = sdram_params->base.ddr_freq / 1000000; in phy_cfg()
268 /* DDR PHY Timing */ in phy_cfg()
269 copy_to_reg(&publ->dtpr[0], &sdram_params->phy_timing.dtpr0, in phy_cfg()
270 sizeof(sdram_params->phy_timing)); in phy_cfg()
271 writel(sdram_params->base.noc_timing, &msch->ddrtiming); in phy_cfg()
272 writel(0x3f, &msch->readlatency); in phy_cfg()
275 8 << PRT_ITMSRST_SHIFT, &publ->ptr[0]); in phy_cfg()
278 &publ->ptr[1]); in phy_cfg()
281 &publ->ptr[2]); in phy_cfg()
283 switch (sdram_params->base.dramtype) { in phy_cfg()
285 clrbits_le32(&publ->pgcr, 0x1f); in phy_cfg()
286 clrsetbits_le32(&publ->dcr, DDRMD_MASK << DDRMD_SHIFT, in phy_cfg()
290 if (sdram_params->base.odt) { in phy_cfg()
293 setbits_le32(&publ->datx8[i].dxgcr, DQSRTT | DQRTT); in phy_cfg()
297 clrbits_le32(&publ->datx8[i].dxgcr, DQSRTT | DQRTT); in phy_cfg()
303 setbits_le32(&publ->pir, PIR_INIT | PIR_DLLSRST in phy_init()
306 while ((readl(&publ->pgsr) & in phy_init()
315 writel((START_CMD | (rank << 20) | arg | cmd), &pctl->mcmd); in send_command()
317 while (readl(&pctl->mcmd) & START_CMD) in send_command()
331 setbits_le32(&publ->pir, in memory_init()
336 while ((readl(&publ->pgsr) & (PGSR_IDONE | PGSR_DLDONE)) in memory_init()
347 state = readl(&pctl->stat) & PCTL_STAT_MSK; in move_to_config_state()
351 writel(WAKEUP_STATE, &pctl->sctl); in move_to_config_state()
352 while ((readl(&pctl->stat) & PCTL_STAT_MSK) in move_to_config_state()
356 while ((readl(&publ->pgsr) & PGSR_DLDONE) in move_to_config_state()
367 writel(CFG_STATE, &pctl->sctl); in move_to_config_state()
368 while ((readl(&pctl->stat) & PCTL_STAT_MSK) != CONFIG) in move_to_config_state()
382 struct rk3288_ddr_pctl *pctl = chan->pctl; in set_bandwidth_ratio()
383 struct rk3288_ddr_publ *publ = chan->publ; in set_bandwidth_ratio()
384 struct rk3188_msch *msch = chan->msch; in set_bandwidth_ratio()
387 setbits_le32(&pctl->ppcfg, 1); in set_bandwidth_ratio()
389 setbits_le32(&msch->ddrtiming, 1 << 31); in set_bandwidth_ratio()
391 clrbits_le32(&publ->datx8[2].dxgcr, 1); in set_bandwidth_ratio()
392 clrbits_le32(&publ->datx8[3].dxgcr, 1); in set_bandwidth_ratio()
394 setbits_le32(&publ->datx8[2].dxdllcr, DXDLLCR_DLLDIS); in set_bandwidth_ratio()
395 setbits_le32(&publ->datx8[3].dxdllcr, DXDLLCR_DLLDIS); in set_bandwidth_ratio()
397 clrbits_le32(&pctl->ppcfg, 1); in set_bandwidth_ratio()
399 clrbits_le32(&msch->ddrtiming, 1 << 31); in set_bandwidth_ratio()
401 setbits_le32(&publ->datx8[2].dxgcr, 1); in set_bandwidth_ratio()
402 setbits_le32(&publ->datx8[3].dxgcr, 1); in set_bandwidth_ratio()
405 clrbits_le32(&publ->datx8[2].dxdllcr, DXDLLCR_DLLDIS); in set_bandwidth_ratio()
406 clrbits_le32(&publ->datx8[3].dxdllcr, DXDLLCR_DLLDIS); in set_bandwidth_ratio()
408 clrbits_le32(&publ->datx8[2].dxdllcr, DXDLLCR_DLLSRST); in set_bandwidth_ratio()
409 clrbits_le32(&publ->datx8[3].dxdllcr, DXDLLCR_DLLSRST); in set_bandwidth_ratio()
411 setbits_le32(&publ->datx8[2].dxdllcr, DXDLLCR_DLLSRST); in set_bandwidth_ratio()
412 setbits_le32(&publ->datx8[3].dxdllcr, DXDLLCR_DLLSRST); in set_bandwidth_ratio()
414 setbits_le32(&pctl->dfistcfg0, 1 << 2); in set_bandwidth_ratio()
425 struct rk3288_ddr_publ *publ = chan->publ; in data_training()
426 struct rk3288_ddr_pctl *pctl = chan->pctl; in data_training()
429 writel(0, &pctl->trefi); in data_training()
431 if (sdram_params->base.dramtype != LPDDR3) in data_training()
432 setbits_le32(&publ->pgcr, 1 << PGCR_DQSCFG_SHIFT); in data_training()
433 rank = sdram_params->ch[channel].rank | 1; in data_training()
439 setbits_le32(&publ->pir, PIR_CLRSR); in data_training()
442 setbits_le32(&publ->pir, in data_training()
447 while ((readl(&publ->datx8[0].dxgsr[0]) & rank) in data_training()
450 while ((readl(&publ->datx8[1].dxgsr[0]) & rank) in data_training()
453 if (!(readl(&pctl->ppcfg) & 1)) { in data_training()
454 while ((readl(&publ->datx8[2].dxgsr[0]) in data_training()
457 while ((readl(&publ->datx8[3].dxgsr[0]) in data_training()
461 if (readl(&publ->pgsr) & in data_training()
463 ret = -1; in data_training()
471 if (sdram_params->base.dramtype != LPDDR3) in data_training()
472 clrbits_le32(&publ->pgcr, 1 << PGCR_DQSCFG_SHIFT); in data_training()
475 writel(sdram_params->pctl_timing.trefi, &pctl->trefi); in data_training()
482 struct rk3288_ddr_publ *publ = chan->publ; in move_to_access_state()
483 struct rk3288_ddr_pctl *pctl = chan->pctl; in move_to_access_state()
487 state = readl(&pctl->stat) & PCTL_STAT_MSK; in move_to_access_state()
491 if (((readl(&pctl->stat) >> LP_TRIG_SHIFT) & in move_to_access_state()
495 writel(WAKEUP_STATE, &pctl->sctl); in move_to_access_state()
496 while ((readl(&pctl->stat) & PCTL_STAT_MSK) != ACCESS) in move_to_access_state()
499 while ((readl(&publ->pgsr) & PGSR_DLDONE) in move_to_access_state()
504 writel(CFG_STATE, &pctl->sctl); in move_to_access_state()
505 while ((readl(&pctl->stat) & PCTL_STAT_MSK) != CONFIG) in move_to_access_state()
509 writel(GO_STATE, &pctl->sctl); in move_to_access_state()
510 while ((readl(&pctl->stat) & PCTL_STAT_MSK) == CONFIG) in move_to_access_state()
524 struct rk3288_ddr_publ *publ = chan->publ; in dram_cfg_rbc()
526 if (sdram_params->ch[chnum].bk == 3) in dram_cfg_rbc()
527 clrsetbits_le32(&publ->dcr, PDQ_MASK << PDQ_SHIFT, in dram_cfg_rbc()
530 clrbits_le32(&publ->dcr, PDQ_MASK << PDQ_SHIFT); in dram_cfg_rbc()
532 writel(sdram_params->base.ddrconfig, &chan->msch->ddrconf); in dram_cfg_rbc()
541 sys_reg |= sdram_params->base.dramtype << SYS_REG_DDRTYPE_SHIFT; in dram_all_config()
542 sys_reg |= (sdram_params->num_channels - 1) << SYS_REG_NUM_CH_SHIFT; in dram_all_config()
543 for (chan = 0; chan < sdram_params->num_channels; chan++) { in dram_all_config()
545 &sdram_params->ch[chan]; in dram_all_config()
547 sys_reg |= info->row_3_4 << SYS_REG_ROW_3_4_SHIFT(chan); in dram_all_config()
549 sys_reg |= (info->rank - 1) << SYS_REG_RANK_SHIFT(chan); in dram_all_config()
550 sys_reg |= (info->col - 9) << SYS_REG_COL_SHIFT(chan); in dram_all_config()
551 sys_reg |= info->bk == 3 ? 0 : 1 << SYS_REG_BK_SHIFT(chan); in dram_all_config()
552 sys_reg |= (info->cs0_row - 13) << SYS_REG_CS0_ROW_SHIFT(chan); in dram_all_config()
553 sys_reg |= (info->cs1_row - 13) << SYS_REG_CS1_ROW_SHIFT(chan); in dram_all_config()
554 sys_reg |= (2 >> info->bw) << SYS_REG_BW_SHIFT(chan); in dram_all_config()
555 sys_reg |= (2 >> info->dbw) << SYS_REG_DBW_SHIFT(chan); in dram_all_config()
557 dram_cfg_rbc(&dram->chan[chan], chan, sdram_params); in dram_all_config()
559 if (sdram_params->ch[0].rank == 2) in dram_all_config()
560 ddr_rank_2_row15en(dram->grf, 0); in dram_all_config()
562 ddr_rank_2_row15en(dram->grf, 1); in dram_all_config()
564 writel(sys_reg, &dram->pmu->sys_reg[2]); in dram_all_config()
572 const struct chan_info *chan = &dram->chan[channel]; in sdram_rank_bw_detect()
573 struct rk3288_ddr_publ *publ = chan->publ; in sdram_rank_bw_detect()
575 ddr_rank_2_row15en(dram->grf, 0); in sdram_rank_bw_detect()
579 reg = readl(&publ->datx8[0].dxgsr[0]); in sdram_rank_bw_detect()
583 return -EIO; in sdram_rank_bw_detect()
588 sdram_params->ch[channel].rank = 1; in sdram_rank_bw_detect()
589 clrsetbits_le32(&publ->pgcr, 0xF << 18, in sdram_rank_bw_detect()
590 sdram_params->ch[channel].rank << 18); in sdram_rank_bw_detect()
593 reg = readl(&publ->datx8[2].dxgsr[0]); in sdram_rank_bw_detect()
595 sdram_params->ch[channel].bw = 1; in sdram_rank_bw_detect()
597 sdram_params->ch[channel].bw, in sdram_rank_bw_detect()
598 dram->grf); in sdram_rank_bw_detect()
603 sdram_params->ch[channel].dbw = sdram_params->ch[channel].bw; in sdram_rank_bw_detect()
607 if (sdram_params->base.dramtype == LPDDR3) { in sdram_rank_bw_detect()
608 ddr_phy_ctl_reset(dram->cru, channel, 1); in sdram_rank_bw_detect()
610 ddr_phy_ctl_reset(dram->cru, channel, 0); in sdram_rank_bw_detect()
614 return -EIO; in sdram_rank_bw_detect()
633 const struct chan_info *chan = &dram->chan[channel]; in sdram_col_row_detect()
634 struct rk3288_ddr_pctl *pctl = chan->pctl; in sdram_col_row_detect()
635 struct rk3288_ddr_publ *publ = chan->publ; in sdram_col_row_detect()
639 for (col = 11; col >= 9; col--) { in sdram_col_row_detect()
642 (1 << (col + sdram_params->ch[channel].bw - 1)); in sdram_col_row_detect()
650 ret = -EINVAL; in sdram_col_row_detect()
653 sdram_params->ch[channel].col = col; in sdram_col_row_detect()
656 ddr_rank_2_row15en(dram->grf, 1); in sdram_col_row_detect()
658 writel(1, &chan->msch->ddrconf); in sdram_col_row_detect()
661 for (row = 16; row >= 13; row--) { in sdram_col_row_detect()
663 addr = CONFIG_SYS_SDRAM_BASE + (1 << (row + 15 - 1)); in sdram_col_row_detect()
671 ret = -EINVAL; in sdram_col_row_detect()
673 sdram_params->ch[channel].cs1_row = row; in sdram_col_row_detect()
674 sdram_params->ch[channel].row_3_4 = 0; in sdram_col_row_detect()
676 sdram_params->ch[channel].cs0_row = row; in sdram_col_row_detect()
687 row = sdram_params->ch[0].cs0_row; in sdram_get_niu_config()
689 * RK3188 share the rank and row bit15, we use same ddr config for 15bit in sdram_get_niu_config()
694 tmp = sdram_params->ch[0].col - 9; in sdram_get_niu_config()
695 tmp -= (sdram_params->ch[0].bw == 2) ? 0 : 1; in sdram_get_niu_config()
696 tmp |= ((row - 13) << 4); in sdram_get_niu_config()
703 ret = -EINVAL; in sdram_get_niu_config()
706 sdram_params->base.ddrconfig = i; in sdram_get_niu_config()
719 if ((sdram_params->base.dramtype == DDR3 && in sdram_init()
720 sdram_params->base.ddr_freq > 800000000)) { in sdram_init()
722 return -E2BIG; in sdram_init()
725 ret = clk_set_rate(&dram->ddr_clk, sdram_params->base.ddr_freq); in sdram_init()
727 printf("Could not set DDR clock\n"); in sdram_init()
732 const struct chan_info *chan = &dram->chan[channel]; in sdram_init()
733 struct rk3288_ddr_pctl *pctl = chan->pctl; in sdram_init()
734 struct rk3288_ddr_publ *publ = chan->publ; in sdram_init()
736 phy_pctrl_reset(dram->cru, publ, channel); in sdram_init()
737 phy_dll_bypass_set(publ, sdram_params->base.ddr_freq); in sdram_init()
739 dfi_cfg(pctl, sdram_params->base.dramtype); in sdram_init()
741 pctl_cfg(channel, pctl, sdram_params, dram->grf); in sdram_init()
747 writel(POWER_UP_START, &pctl->powctl); in sdram_init()
748 while (!(readl(&pctl->powstat) & POWER_UP_DONE)) in sdram_init()
751 memory_init(publ, sdram_params->base.dramtype); in sdram_init()
755 sdram_params->ch[channel].bw = 2; in sdram_init()
757 sdram_params->ch[channel].bw, dram->grf); in sdram_init()
764 sdram_params->ch[channel].rank = 2, in sdram_init()
765 clrsetbits_le32(&publ->pgcr, 0xF << 18, in sdram_init()
766 (sdram_params->ch[channel].rank | 1) << 18); in sdram_init()
772 writel(zqcr, &publ->zq1cr[0]); in sdram_init()
773 writel(zqcr, &publ->zq0cr[0]); in sdram_init()
775 /* Detect the rank and bit-width with data-training */ in sdram_init()
776 writel(1, &chan->msch->ddrconf); in sdram_init()
779 if (sdram_params->base.dramtype == LPDDR3) { in sdram_init()
781 writel(0, &pctl->mrrcfg0); in sdram_init()
785 writel(4, &chan->msch->ddrconf); in sdram_init()
788 sdram_params->ch[channel].bk = 3; in sdram_init()
794 /* Find NIU DDR configuration */ in sdram_init()
822 /* rk3188 supports only one-channel */ in rk3188_dmc_ofdata_to_platdata()
823 params->num_channels = 1; in rk3188_dmc_ofdata_to_platdata()
824 ret = dev_read_u32_array(dev, "rockchip,pctl-timing", in rk3188_dmc_ofdata_to_platdata()
825 (u32 *)¶ms->pctl_timing, in rk3188_dmc_ofdata_to_platdata()
826 sizeof(params->pctl_timing) / sizeof(u32)); in rk3188_dmc_ofdata_to_platdata()
828 printf("%s: Cannot read rockchip,pctl-timing\n", __func__); in rk3188_dmc_ofdata_to_platdata()
829 return -EINVAL; in rk3188_dmc_ofdata_to_platdata()
831 ret = dev_read_u32_array(dev, "rockchip,phy-timing", in rk3188_dmc_ofdata_to_platdata()
832 (u32 *)¶ms->phy_timing, in rk3188_dmc_ofdata_to_platdata()
833 sizeof(params->phy_timing) / sizeof(u32)); in rk3188_dmc_ofdata_to_platdata()
835 printf("%s: Cannot read rockchip,phy-timing\n", __func__); in rk3188_dmc_ofdata_to_platdata()
836 return -EINVAL; in rk3188_dmc_ofdata_to_platdata()
838 ret = dev_read_u32_array(dev, "rockchip,sdram-params", in rk3188_dmc_ofdata_to_platdata()
839 (u32 *)¶ms->base, in rk3188_dmc_ofdata_to_platdata()
840 sizeof(params->base) / sizeof(u32)); in rk3188_dmc_ofdata_to_platdata()
842 printf("%s: Cannot read rockchip,sdram-params\n", __func__); in rk3188_dmc_ofdata_to_platdata()
843 return -EINVAL; in rk3188_dmc_ofdata_to_platdata()
845 ret = regmap_init_mem(dev, ¶ms->map); in rk3188_dmc_ofdata_to_platdata()
858 struct dtd_rockchip_rk3188_dmc *of_plat = &plat->of_plat; in conv_of_platdata()
861 memcpy(&plat->pctl_timing, of_plat->rockchip_pctl_timing, in conv_of_platdata()
862 sizeof(plat->pctl_timing)); in conv_of_platdata()
863 memcpy(&plat->phy_timing, of_plat->rockchip_phy_timing, in conv_of_platdata()
864 sizeof(plat->phy_timing)); in conv_of_platdata()
865 memcpy(&plat->base, of_plat->rockchip_sdram_params, sizeof(plat->base)); in conv_of_platdata()
866 /* rk3188 supports dual-channel, set default channel num to 2 */ in conv_of_platdata()
867 plat->num_channels = 1; in conv_of_platdata()
868 ret = regmap_init_mem_platdata(dev, of_plat->reg, in conv_of_platdata()
869 ARRAY_SIZE(of_plat->reg) / 2, in conv_of_platdata()
870 &plat->map); in conv_of_platdata()
888 priv->pmu = syscon_get_first_range(ROCKCHIP_SYSCON_PMU); in rk3188_dmc_probe()
899 priv->chan[0].msch = regmap_get_range(map, 0); in rk3188_dmc_probe()
901 priv->grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF); in rk3188_dmc_probe()
903 priv->chan[0].pctl = regmap_get_range(plat->map, 0); in rk3188_dmc_probe()
904 priv->chan[0].publ = regmap_get_range(plat->map, 1); in rk3188_dmc_probe()
909 priv->ddr_clk.id = CLK_DDR; in rk3188_dmc_probe()
910 ret = clk_request(dev_clk, &priv->ddr_clk); in rk3188_dmc_probe()
914 priv->cru = rockchip_get_cru(); in rk3188_dmc_probe()
915 if (IS_ERR(priv->cru)) in rk3188_dmc_probe()
916 return PTR_ERR(priv->cru); in rk3188_dmc_probe()
921 priv->info.base = CONFIG_SYS_SDRAM_BASE; in rk3188_dmc_probe()
922 priv->info.size = rockchip_sdram_size( in rk3188_dmc_probe()
923 (phys_addr_t)&priv->pmu->sys_reg[2]); in rk3188_dmc_probe()
933 *info = priv->info; in rk3188_dmc_get_info()
943 { .compatible = "rockchip,rk3188-dmc" },