1/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */ 2/* 3 * Copyright (c) 2023 Rockchip Electronics Co., Ltd. 4 */ 5 6#include <linux/linkage.h> 7#include <asm/assembler.h> 8 9#include "rv1106_pm.h" 10 11#define RV1106_GPIO0_INT_ST 0xff380050 12#define RV1106_PMUGRF_OS_REG10 0xff020228 13#define RV1106_PMUGRF_SOC_CON4 0xff020010 14#define RV1106_CRU_GLB_SRST_FST 0xff3b0c08 15 16#if RV1106_SLEEP_DEBUG 17/********************* console used for sleep.S ******************************/ 18#define UART_REG_DLL (0x00) 19#define UART_REG_DLH (0x04) 20#define UART_REG_IER (0x04) 21#define UART_REG_FCR (0x08) 22#define UART_REG_LCR (0x0c) 23#define UART_REG_MCR (0x10) 24 25#define UARTLCR_DLAB (1 << 7) 26#define UARTFCR_DMAEN (1 << 3) 27#define UARTFCR_FIFOEN (1 << 0) 28 29#define CONSOLE_UART_BASE 0xff4c0000 30#define CONSOLE_CLKRATE 24000000 31#define CONSOLE_BAUDRATE 115200 32 33#define GPIO1_B_IOMUX 0xff538008 34#define GRF_GPIO1D_VAL 0xff002200 35 36.macro early_console_init 37 ldr r0, =GPIO1_B_IOMUX 38 ldr r1, =GRF_GPIO1D_VAL 39 str r1, [r0] 40 41 ldr r0, =CONSOLE_UART_BASE 42 ldr r1, =CONSOLE_CLKRATE 43 ldr r2, =CONSOLE_BAUDRATE 44 /* Program the baudrate */ 45 /* Divisor = Uart clock / (16 * baudrate) */ 46 mov r1, #0xd 47 mov r2, #0x0 48 ldr r3, [r0, #UART_REG_LCR] 49 orr r3, r3, #UARTLCR_DLAB 50 str r3, [r0, #UART_REG_LCR] /* enable DLL, DLH programming */ 51 str r1, [r0, #UART_REG_DLL] /* program DLL */ 52 str r2, [r0, #UART_REG_DLH] /* program DLH */ 53 mov r2, #~UARTLCR_DLAB 54 and r3, r3, r2 55 str r3, [r0, #UART_REG_LCR] /* disable DLL, DLH programming */ 56 57 /* 8n1 */ 58 mov r3, #3 59 str r3, [r0, #UART_REG_LCR] 60 /* no interrupt */ 61 mov r3, #0 62 str r3, [r0, #UART_REG_IER] 63 /* enable fifo, DMA */ 64 mov r3, #(UARTFCR_FIFOEN | UARTFCR_DMAEN) 65 str r3, [r0, #UART_REG_FCR] 66 /* DTR + RTS */ 67 mov r3, #3 68 str r3, [r0, #UART_REG_MCR] 69 mov r0, #1 70 dsb sy 71.endm 72 73.macro early_console_putc ch 74 ldr r0, =CONSOLE_UART_BASE 75 mov r1, #\ch 76 str r1, [r0] 77.endm 78/********************* console used for sleep.S ******************************/ 79#endif 80 81.align 2 82.arm 83 84 85ENTRY(rockchip_slp_cpu_resume) 86#if RV1106_SLEEP_DEBUG 87 early_console_init 88 /* print 'A' */ 89 early_console_putc 0x41 90#endif 91 92 setmode PSR_I_BIT | PSR_F_BIT | SVC_MODE, r1 @ set svc, irqs off 93 94#if RV1106_WAKEUP_TO_SYSTEM_RESET 95 /* save gpio wakeup src */ 96 ldr r0, =RV1106_PMUGRF_OS_REG10 97 ldr r1, =RV1106_GPIO0_INT_ST 98 ldr r1, [r1] 99 str r1, [r0] 100 101 /* clear pmu reset hold */ 102 ldr r0, =RV1106_PMUGRF_SOC_CON4 103 ldr r1, =0xffff0000 104 str r1, [r0] 105 add r0, r0, #4 106 str r1, [r0] 107 108 /* first reset */ 109 ldr r0, =RV1106_CRU_GLB_SRST_FST 110 mov r1, #0xfdb9 111 str r1, [r0] 112 b . 113#endif 114 115 ldr r3, rkpm_bootdata_l2ctlr_f 116 cmp r3, #0 117 beq sp_set 118 ldr r3, rkpm_bootdata_l2ctlr 119 mcr p15, 1, r3, c9, c0, 2 120sp_set: 121 ldr sp, rkpm_bootdata_cpusp 122 123 ldr r0, rkpm_ddr_data 124 ldr r1, rkpm_ddr_func 125 cmp r1, #0 126 beq boot 127 blx r1 128 129boot: 130 ldr r1, rkpm_bootdata_cpu_code 131 bx r1 132ENDPROC(rockchip_slp_cpu_resume) 133 134/* Parameters filled in by the kernel */ 135 136/* Flag for whether to restore L2CTLR on resume */ 137 .global rkpm_bootdata_l2ctlr_f 138rkpm_bootdata_l2ctlr_f: 139 .long 0 140 141/* Saved L2CTLR to restore on resume */ 142 .global rkpm_bootdata_l2ctlr 143rkpm_bootdata_l2ctlr: 144 .long 0 145 146/* CPU resume SP addr */ 147 .globl rkpm_bootdata_cpusp 148rkpm_bootdata_cpusp: 149 .long 0 150 151/* CPU resume function (physical address) */ 152 .globl rkpm_bootdata_cpu_code 153rkpm_bootdata_cpu_code: 154 .long 0 155 156/* ddr resume data */ 157 .globl rkpm_ddr_data 158rkpm_ddr_data: 159 .long 0 160 161/* ddr resume function (physical address) */ 162 .globl rkpm_ddr_func 163rkpm_ddr_func: 164 .long 0 165 166ENTRY(rv1106_bootram_sz) 167 .word . - rockchip_slp_cpu_resume 168