1 /* 2 * Header providing constants for Rockchip suspend bindings. 3 * 4 * Copyright (C) 2018, Fuzhou Rockchip Electronics Co., Ltd 5 * Author: Joseph Chen 6 * 7 * This program is free software; you can redistribute it and/or modify 8 * it under the terms of the GNU General Public License as published by 9 * the Free Software Foundation; either version 2 of the License, or 10 * (at your option) any later version. 11 * 12 * This program is distributed in the hope that it will be useful, 13 * but WITHOUT ANY WARRANTY; without even the implied warranty of 14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 15 * GNU General Public License for more details. 16 */ 17 #ifndef __DT_BINDINGS_RK3308_PM_H__ 18 #define __DT_BINDINGS_RK3308_PM_H__ 19 /******************************bits ops************************************/ 20 21 #ifndef BIT 22 #define BIT(nr) (1 << (nr)) 23 #endif 24 25 /* 26 * RK3308 system suspend mode configure definitions. 27 * 28 * Driver: 29 * These configures are pass to ATF by SMC in: 30 * drivers/soc/rockchip/rockchip_pm_config.c 31 * 32 * DTS: 33 * rockchip_suspend: rockchip-suspend { 34 * rockchip,sleep-mode-config = <...>; 35 * rockchip,wakeup-config = <...>; 36 * rockchip,apios-suspend = <...>; 37 * rockchip,pwm-regulator-config = <...>; 38 * }; 39 */ 40 41 /* 42 * Suspend mode: 43 * rockchip,sleep-mode-config = <...>; 44 */ 45 #define RKPM_ARMOFF BIT(0) /* vdd_arm off */ 46 #define RKPM_VADOFF BIT(1) /* assume vad off, enter lowest system suspend */ 47 #define RKPM_PMU_HW_PLLS_PD BIT(3) /* disable PLLs by PMU hardware, recommend */ 48 #define RKPM_PMU_DIS_OSC BIT(4) /* disable 24M osc */ 49 #define RKPM_PMU_PMUALIVE_32K BIT(5) /* pvtm 32khz */ 50 #define RKPM_PMU_EXT_32K BIT(6) /* ext 32khz osc */ 51 #define RKPM_DDR_SREF_HARDWARE BIT(7) /* ddr enter self-refresh by PMU hardware, not recommend */ 52 #define RKPM_DDR_EXIT_SRPD_IDLE BIT(8) /* ddr exit sr/pd idle by ddr controller, not recommend */ 53 #define RKPM_PDM_CLK_OFF BIT(9) /* armoff with pdm clk off, not recommend */ 54 #define RKPM_PWM_VOLTAGE_DEFAULT BIT(10) /* pwm regulator default voltage (same with maskrom) */ 55 #define RKPM_PWM_VOLTAGE_DEFAULT_BS BIT(20) /* pwm regulator default voltage on 0.895v for RK3308BS chip */ 56 57 /* 58 * Regulator mode: 59 * rockchip,pwm-regulator-config = <...>; 60 */ 61 #define RKPM_PWM_REGULATOR BIT(2) /* support pwm regulator */ 62 63 /* 64 * Wakeup source: 65 * rockchip,wakeup-config = <...>; 66 */ 67 #define RKPM_ARM_PRE_WAKEUP_EN BIT(11) /* all interrupts can wakeup(gic doesn't filter these) */ 68 #define RKPM_ARM_GIC_WAKEUP_EN BIT(12) /* all interrupts can wakeup(gic filter these) */ 69 #define RKPM_SDMMC_WAKEUP_EN BIT(13) /* sdmmc can wakeup */ 70 #define RKPM_SDMMC_GRF_IRQ_WAKEUP_EN BIT(14) /* sdmmc grf irq can wakeup */ 71 #define RKPM_TIMER_WAKEUP_EN BIT(15) /* rk timers can wakeup */ 72 #define RKPM_USBDEV_WAKEUP_EN BIT(16) /* usbdev can wakeup */ 73 #define RKPM_TIMEOUT_WAKEUP_EN BIT(17) /* PMU timeout can wakeup, for self test */ 74 #define RKPM_GPIO0_WAKEUP_EN BIT(18) /* gpio0(only) can wakeup */ 75 #define RKPM_VAD_WAKEUP_EN BIT(19) /* vad can wakeup */ 76 77 /* 78 * Debug control in system suspend: 79 * rockchip,sleep-mode-config = <...>; 80 */ 81 #define RKPM_DBG_INT_TIMER_TEST BIT(22) /* enable RKPM_TIMEOUT_WAKEUP_EN */ 82 #define RKPM_DBG_WOARKAROUND BIT(23) /* ignore, useless */ 83 #define RKPM_DBG_VAD_INT_OFF BIT(24) /* enable RKPM_VADOFF */ 84 #define RKPM_DBG_CLK_UNGATE BIT(25) /* enable all clks */ 85 #define RKPM_DBG_CLKOUT BIT(26) /* enable test_out clk output */ 86 #define RKPM_DBG_FSM_SOUT BIT(27) /* FSM state one pin out */ 87 #define RKPM_DBG_FSM_STATE BIT(28) /* FSM state multi pins out */ 88 #define RKPM_DBG_REG BIT(29) /* verbose regs */ 89 #define RKPM_DBG_VERBOSE BIT(30) /* verbose more message */ 90 #define RKPM_CONFIG_WAKEUP_END BIT(31) /* ignore, it's a placeholder */ 91 92 /* 93 * GPIOn/PWMn ignore global 1st reset, usually used for pwr_hold pin: 94 * rockchip,apios-suspend = <...>; 95 */ 96 #define GLB1RST_IGNORE_PWM0 BIT(23) /* pwm0 ignore global 1st reset */ 97 #define GLB1RST_IGNORE_PWM1 BIT(24) /* pwm1 ignore global 1st reset */ 98 #define GLB1RST_IGNORE_PWM2 BIT(25) /* pwm2 ignore global 1st reset */ 99 #define GLB1RST_IGNORE_GPIO0 BIT(26) /* gpio0 ignore global 1st reset */ 100 #define GLB1RST_IGNORE_GPIO1 BIT(27) /* gpio1 ignore global 1st reset */ 101 #define GLB1RST_IGNORE_GPIO2 BIT(28) /* gpio2 ignore global 1st reset */ 102 #define GLB1RST_IGNORE_GPIO3 BIT(29) /* gpio3 ignore global 1st reset */ 103 #define GLB1RST_IGNORE_GPIO4 BIT(30) /* gpio4 ignore global 1st reset */ 104 105 #endif 106