1*4882a593Smuzhiyun /* 2*4882a593Smuzhiyun * Header providing constants for Rockchip suspend bindings. 3*4882a593Smuzhiyun * 4*4882a593Smuzhiyun * Copyright (C) 2018, Fuzhou Rockchip Electronics Co., Ltd 5*4882a593Smuzhiyun * Author: Joseph Chen 6*4882a593Smuzhiyun * 7*4882a593Smuzhiyun * This program is free software; you can redistribute it and/or modify 8*4882a593Smuzhiyun * it under the terms of the GNU General Public License as published by 9*4882a593Smuzhiyun * the Free Software Foundation; either version 2 of the License, or 10*4882a593Smuzhiyun * (at your option) any later version. 11*4882a593Smuzhiyun * 12*4882a593Smuzhiyun * This program is distributed in the hope that it will be useful, 13*4882a593Smuzhiyun * but WITHOUT ANY WARRANTY; without even the implied warranty of 14*4882a593Smuzhiyun * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 15*4882a593Smuzhiyun * GNU General Public License for more details. 16*4882a593Smuzhiyun */ 17*4882a593Smuzhiyun #ifndef __DT_BINDINGS_RK3308_PM_H__ 18*4882a593Smuzhiyun #define __DT_BINDINGS_RK3308_PM_H__ 19*4882a593Smuzhiyun /******************************bits ops************************************/ 20*4882a593Smuzhiyun 21*4882a593Smuzhiyun #ifndef BIT 22*4882a593Smuzhiyun #define BIT(nr) (1 << (nr)) 23*4882a593Smuzhiyun #endif 24*4882a593Smuzhiyun 25*4882a593Smuzhiyun /* 26*4882a593Smuzhiyun * RK3308 system suspend mode configure definitions. 27*4882a593Smuzhiyun * 28*4882a593Smuzhiyun * Driver: 29*4882a593Smuzhiyun * These configures are pass to ATF by SMC in: 30*4882a593Smuzhiyun * drivers/soc/rockchip/rockchip_pm_config.c 31*4882a593Smuzhiyun * 32*4882a593Smuzhiyun * DTS: 33*4882a593Smuzhiyun * rockchip_suspend: rockchip-suspend { 34*4882a593Smuzhiyun * rockchip,sleep-mode-config = <...>; 35*4882a593Smuzhiyun * rockchip,wakeup-config = <...>; 36*4882a593Smuzhiyun * rockchip,apios-suspend = <...>; 37*4882a593Smuzhiyun * rockchip,pwm-regulator-config = <...>; 38*4882a593Smuzhiyun * }; 39*4882a593Smuzhiyun */ 40*4882a593Smuzhiyun 41*4882a593Smuzhiyun /* 42*4882a593Smuzhiyun * Suspend mode: 43*4882a593Smuzhiyun * rockchip,sleep-mode-config = <...>; 44*4882a593Smuzhiyun */ 45*4882a593Smuzhiyun #define RKPM_ARMOFF BIT(0) /* vdd_arm off */ 46*4882a593Smuzhiyun #define RKPM_VADOFF BIT(1) /* assume vad off, enter lowest system suspend */ 47*4882a593Smuzhiyun #define RKPM_PMU_HW_PLLS_PD BIT(3) /* disable PLLs by PMU hardware, recommend */ 48*4882a593Smuzhiyun #define RKPM_PMU_DIS_OSC BIT(4) /* disable 24M osc */ 49*4882a593Smuzhiyun #define RKPM_PMU_PMUALIVE_32K BIT(5) /* pvtm 32khz */ 50*4882a593Smuzhiyun #define RKPM_PMU_EXT_32K BIT(6) /* ext 32khz osc */ 51*4882a593Smuzhiyun #define RKPM_DDR_SREF_HARDWARE BIT(7) /* ddr enter self-refresh by PMU hardware, not recommend */ 52*4882a593Smuzhiyun #define RKPM_DDR_EXIT_SRPD_IDLE BIT(8) /* ddr exit sr/pd idle by ddr controller, not recommend */ 53*4882a593Smuzhiyun #define RKPM_PDM_CLK_OFF BIT(9) /* armoff with pdm clk off, not recommend */ 54*4882a593Smuzhiyun #define RKPM_PWM_VOLTAGE_DEFAULT BIT(10) /* pwm regulator default voltage (same with maskrom) */ 55*4882a593Smuzhiyun #define RKPM_PWM_VOLTAGE_DEFAULT_BS BIT(20) /* pwm regulator default voltage on 0.895v for RK3308BS chip */ 56*4882a593Smuzhiyun 57*4882a593Smuzhiyun /* 58*4882a593Smuzhiyun * Regulator mode: 59*4882a593Smuzhiyun * rockchip,pwm-regulator-config = <...>; 60*4882a593Smuzhiyun */ 61*4882a593Smuzhiyun #define RKPM_PWM_REGULATOR BIT(2) /* support pwm regulator */ 62*4882a593Smuzhiyun 63*4882a593Smuzhiyun /* 64*4882a593Smuzhiyun * Wakeup source: 65*4882a593Smuzhiyun * rockchip,wakeup-config = <...>; 66*4882a593Smuzhiyun */ 67*4882a593Smuzhiyun #define RKPM_ARM_PRE_WAKEUP_EN BIT(11) /* all interrupts can wakeup(gic doesn't filter these) */ 68*4882a593Smuzhiyun #define RKPM_ARM_GIC_WAKEUP_EN BIT(12) /* all interrupts can wakeup(gic filter these) */ 69*4882a593Smuzhiyun #define RKPM_SDMMC_WAKEUP_EN BIT(13) /* sdmmc can wakeup */ 70*4882a593Smuzhiyun #define RKPM_SDMMC_GRF_IRQ_WAKEUP_EN BIT(14) /* sdmmc grf irq can wakeup */ 71*4882a593Smuzhiyun #define RKPM_TIMER_WAKEUP_EN BIT(15) /* rk timers can wakeup */ 72*4882a593Smuzhiyun #define RKPM_USBDEV_WAKEUP_EN BIT(16) /* usbdev can wakeup */ 73*4882a593Smuzhiyun #define RKPM_TIMEOUT_WAKEUP_EN BIT(17) /* PMU timeout can wakeup, for self test */ 74*4882a593Smuzhiyun #define RKPM_GPIO0_WAKEUP_EN BIT(18) /* gpio0(only) can wakeup */ 75*4882a593Smuzhiyun #define RKPM_VAD_WAKEUP_EN BIT(19) /* vad can wakeup */ 76*4882a593Smuzhiyun 77*4882a593Smuzhiyun /* 78*4882a593Smuzhiyun * Debug control in system suspend: 79*4882a593Smuzhiyun * rockchip,sleep-mode-config = <...>; 80*4882a593Smuzhiyun */ 81*4882a593Smuzhiyun #define RKPM_DBG_INT_TIMER_TEST BIT(22) /* enable RKPM_TIMEOUT_WAKEUP_EN */ 82*4882a593Smuzhiyun #define RKPM_DBG_WOARKAROUND BIT(23) /* ignore, useless */ 83*4882a593Smuzhiyun #define RKPM_DBG_VAD_INT_OFF BIT(24) /* enable RKPM_VADOFF */ 84*4882a593Smuzhiyun #define RKPM_DBG_CLK_UNGATE BIT(25) /* enable all clks */ 85*4882a593Smuzhiyun #define RKPM_DBG_CLKOUT BIT(26) /* enable test_out clk output */ 86*4882a593Smuzhiyun #define RKPM_DBG_FSM_SOUT BIT(27) /* FSM state one pin out */ 87*4882a593Smuzhiyun #define RKPM_DBG_FSM_STATE BIT(28) /* FSM state multi pins out */ 88*4882a593Smuzhiyun #define RKPM_DBG_REG BIT(29) /* verbose regs */ 89*4882a593Smuzhiyun #define RKPM_DBG_VERBOSE BIT(30) /* verbose more message */ 90*4882a593Smuzhiyun #define RKPM_CONFIG_WAKEUP_END BIT(31) /* ignore, it's a placeholder */ 91*4882a593Smuzhiyun 92*4882a593Smuzhiyun /* 93*4882a593Smuzhiyun * GPIOn/PWMn ignore global 1st reset, usually used for pwr_hold pin: 94*4882a593Smuzhiyun * rockchip,apios-suspend = <...>; 95*4882a593Smuzhiyun */ 96*4882a593Smuzhiyun #define GLB1RST_IGNORE_PWM0 BIT(23) /* pwm0 ignore global 1st reset */ 97*4882a593Smuzhiyun #define GLB1RST_IGNORE_PWM1 BIT(24) /* pwm1 ignore global 1st reset */ 98*4882a593Smuzhiyun #define GLB1RST_IGNORE_PWM2 BIT(25) /* pwm2 ignore global 1st reset */ 99*4882a593Smuzhiyun #define GLB1RST_IGNORE_GPIO0 BIT(26) /* gpio0 ignore global 1st reset */ 100*4882a593Smuzhiyun #define GLB1RST_IGNORE_GPIO1 BIT(27) /* gpio1 ignore global 1st reset */ 101*4882a593Smuzhiyun #define GLB1RST_IGNORE_GPIO2 BIT(28) /* gpio2 ignore global 1st reset */ 102*4882a593Smuzhiyun #define GLB1RST_IGNORE_GPIO3 BIT(29) /* gpio3 ignore global 1st reset */ 103*4882a593Smuzhiyun #define GLB1RST_IGNORE_GPIO4 BIT(30) /* gpio4 ignore global 1st reset */ 104*4882a593Smuzhiyun 105*4882a593Smuzhiyun #endif 106